U.S. patent application number 09/855849 was filed with the patent office on 2002-01-03 for method for the formation of gate electrode of semiconductor device using a difference in polishing selection ratio between polymer and oxide film.
Invention is credited to Lee, Sang-Ick.
Application Number | 20020001914 09/855849 |
Document ID | / |
Family ID | 19669200 |
Filed Date | 2002-01-03 |
United States Patent
Application |
20020001914 |
Kind Code |
A1 |
Lee, Sang-Ick |
January 3, 2002 |
Method for the formation of gate electrode of semiconductor device
using a difference in polishing selection ratio between polymer and
oxide film
Abstract
A method for the formation of a gate electrode with a uniform
thickness in the semiconductor device by using a difference in
polishing selection ratio between a polymer and an oxide film. The
method includes steps of depositing a polymer layer on a
semiconductor substrate; selectively etching the polymer layer to
form a patterned polymer; forming an insulating oxide film for
planarization; applying a CMP process to the insulating oxide film;
removing the patterned polymer to define an opening with its bottom
exposed to the substrate; forming a gate insulating film on the
substrate within the opening; depositing an electrically conducting
film to bury the opening; applying the CMP process to the
electrically conducting film to allow it to remain only within the
opening; removing a portion of the electrically conducting film
formed within the opening by etching; depositing a mask nitride
film to bury the top of the electrically conducting film; and
applying the CMP process to the mask nitride film until the
insulating oxide film is exposed.
Inventors: |
Lee, Sang-Ick; (Ichon-shi,
KR) |
Correspondence
Address: |
LAW OFFICES OF
JACOBSON HOLMAN
PROFESSIONAL LIMITED LIABILITY COMPANY
400 SEVENTH STREET, N.W.
WASHINGTON
DC
20004
US
|
Family ID: |
19669200 |
Appl. No.: |
09/855849 |
Filed: |
May 16, 2001 |
Current U.S.
Class: |
438/401 ;
257/E21.304; 257/E21.444; 257/E21.621 |
Current CPC
Class: |
H01L 21/823437 20130101;
H01L 21/3212 20130101; H01L 29/66545 20130101 |
Class at
Publication: |
438/401 |
International
Class: |
H01L 021/76 |
Foreign Application Data
Date |
Code |
Application Number |
May 19, 2000 |
KR |
2000-26895 |
Claims
What is claimed is:
1. A method for the formation of a gate electrode of a
semiconductor device, comprising steps of: (a) depositing a polymer
layer on a semiconductor substrate; (b) selectively etching the
polymer layer to form a patterned polymer; (c) forming an
insulating oxide film for planarization on a structure obtained at
said step (b); (d) applying a chemical-mechanical polishing (CMP)
process to the insulating oxide film, with said patterned polymer
being used as a polishing stop layer; (e) removing the patterned
polymer to define an opening, a bottom of said opening being
defined by an exposed part of the semiconductor substrate; (f)
forming a gate insulating film on the exposed part of the
semiconductor substrate within the opening; (g) depositing an
electrically conducting film on a structure obtained at said step
(f) to bury the opening; (h) applying the CMP process to the
electrically conducting film to leave the electrically conducting
film remaining only within the opening, with said insulating oxide
film being used as a polishing stop layer; (i) removing a portion
of the electrically conducting film formed within the opening by
etching; (j) depositing a mask nitride film on a structure obtained
at said step (i) to bury the top of the electrically conducting
film; and (k) applying the CMP process to the mask nitride film
until the insulating oxide film is exposed.
2. The method of claim 1, further comprising after said step (a),
steps of: (a1) applying a baking process to a structure obtained at
said step (a); and (a2) applying a curing process to said
structure.
3. The method of claim 2, wherein the step (a1) includes the steps
of: (all) baking the structure at a temperature ranging from
90.degree. C. to 150.degree. C.; (a12) baking the structure at a
temperature ranging from 200.degree. C. to 250.degree. C.; and
(a13) baking the structure at a temperature ranging from
300.degree. C. to 350.degree. C.
4. The method of claim 2, wherein the step (a2) is performed in a
nitrogen gas ambient and includes steps of: (a21) curing the
structure at a temperature ranging from 400.degree. C. to
500.degree. C.; (a22) curing the structure at a temperature ranging
from 350.degree. C. to 450.degree. C.; and (a23) curing the
structure at a temperature ranging from 300.degree. C. to
400.degree. C.
5. The method of claim 1, further comprising after said step (a), a
step of forming a hard mask layer including a SiN, SiO.sub.2 and
SiON on the polymer layer.
6. The method of claim 1, further including after said step (b), a
step of forming an insulating film spacer at a sidewall of the
patterned polymer, and said step (e) includes defining an opening
with a sidewall of said opening exposed to the insulating film
spacer and a bottom of said opening exposed to the semiconductor
substrate.
7. The method of claim 6, wherein said step (d) of applying the CMP
process to the insulating oxide film is performed in a condition
that a slurry of SiO.sub.2, CeO.sub.2, Al.sub.2O.sub.3 or ZrO.sub.2
series with a size ranging from 10 nm to 500 nm is used, the slurry
has a hydrogen ion concentration (pH) ranging from 3 to 12 mol/L,
and a concentration of organic material in the slurry is in a range
of 0.01 wt % to 5wt % by weight.
8. The method of claim 7, wherein said step (e) of removing the
patterned polymer is performed using a plasma scheme using a mixed
gas of O.sub.2 and Ar, or O.sub.2 and N.sub.2, or a wet
etching.
9. The method of claim 6, wherein the electrically conducting film
includes: a barrier metal film, formed on the gate insulating film,
which is made of one of a Ti, TiN, TiAIN, TiSiN, TaN, WN and
TiSi.sub.2 material; and a metal film formed on the barrier metal
film, which is made of one of tungsten (W) and copper (Cu).
10. The method of claim 9, wherein said step (h) of applying the
CMP process to the electrically conducting film is performed using
a slurry in which at least one of silica and aluminum and a
hydrogen peroxide having a concentration ranging from 0.5 wt % to
10 wt % is included.
11. The method of claim 10, wherein said step (k) of applying the
CMP process to the mask nitride film is performed in a condition
that a hydrogen ion concentration (pH) of the slurry containing an
abrasive Of SiO.sub.2, CeO.sub.2, Al.sub.2O.sub.3 or ZrO.sub.2
series is in a range of 3 to 12 mol/L.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a semiconductor device and,
more particularly, to a method for the formation of a gate
electrode with a uniform thickness in the semiconductor device
through the use of a difference in polishing selection ratio
between a polymer and an oxide film.
DESCRIPTION OF THE PRIOR ART
[0002] There are shown in FIGS. 1A to 1E sectional views setting
forth a conventional gate formation method using a damascene
process.
[0003] The structure shown in FIG. 1A is obtained by steps of
depositing a pad oxide film 11 followed by a polysilicon film 12 on
a semiconductor substrate 10; selectively etching the polysilicon
film 12 and the pad oxide film 11 to pattern the polysilicon film
12 for acting as a dummy pattern; depositing an insulating film
such as a nitride film or an oxide film on top of the patterned
polysilicon film 12; etching the whole surface obtained so as to
form an insulating film spacer 13 at a sidewall of the patterned
polysilicon film 12; depositing an insulating oxide film 14 for
planarization on the polysilicon film 12 and the insulating film
spacer 13; and heat-treating the insulating oxide film 14.
[0004] FIG. 1B is a sectional view showing a structure obtained by
applying a chemical-mechanical polishing (CMP) process to the
insulating oxide film 14 using a slurry for oxide film until the
patterned polysilicon film 12 is exposed. If the
chemical-mechanical polishing is applied to the insulating oxide
film 14 using a typical oxide film slurry having a very small
polishing selection ratio between the polysilicon film 12 and the
insulating oxide film 14, when the patterned polysilicon film 12 is
exposed, a chemical-mechanical polishing unevenness depending on a
wafer region is induced, resulting in a position dependent
thickness of the patterned polysilicon film 12.
[0005] Then, the polysilicon film 12 and the pad oxide film 11 are
removed. As a result, the insulating film spacer 13 is exposed at
its side wall and an opening 100 with a wafer-region-dependent
depth is formed as shown in FIG. 1C.
[0006] FIG. 1D is a sectional view showing that a gate oxide film
15, a barrier metal film 16 and a tungsten film 17 are sequentially
buried within the opening 100, after which the chemical-mechanical
polishing process is applied to the tungsten film 17 until the
insulating oxide film 14 is exposed. The unevenness of the
chemical-mechanical polishing causes the thickness of the tungsten
film 17 buried within the opening 100 to be variable.
[0007] FIG. 1E is a sectional view showing a structure obtained by
etching a portion of the tungsten film 17 in the opening;
depositing a mask nitride film 18 on the remaining tungsten film;
and forming the gate electrode by polishing the mask nitride film
18 until the insulating oxide film 14 is exposed.
[0008] As shown in FIG. 1E, the elevation of the tungsten film 17
making the gate electrode is dependent upon the wafer region
because while performing the chemical-mechanical polishing process
on the insulating oxide film 14 using a typical slurry for oxide
film polishing, with the polysilicon film 12 buried within the
opening, an uneven polishing is applied to the polysilicon film 12,
resulting in the removal of the polysilicon film 12 but allowing
the tungsten film 17 buried within the opening to have an uneven
thickness along the wafer region.
[0009] As a result, the conventional damascene gate formation
method discussed above suffers from a drawback in that the
elevation of the gate is dependent upon the wafer region, rendering
electrical properties of the gate unstable.
[0010] To overcome the foregoing problem, a method is proposed in
which the thickness of the insulating film spacer and the oxide
film is increased, but this method creates unnecessary burden to
increase thickness of the spacer and film to be polished.
SUMMARY OF THE INVENTION
[0011] It is, therefore, a primary object of the present invention
to provide a method for the formation of a gate electrode with a
uniform thickness in the semiconductor device through the use of a
difference in polishing selection ratio between a polymer and an
oxide film.
[0012] In accordance with a preferred embodiment of the present
invention, there is provided a method for the formation of a gate
electrode of a semiconductor device, comprising steps of depositing
a polymer layer on a semiconductor substrate; selectively etching
the polymer layer to form a patterned polymer; forming an
insulating oxide film for planarization on a structure obtained at
the above step; applying a chemical-mechanical polishing (CMP)
process to the insulating oxide film, wherein the patterned polymer
is used as a polishing stop layer; removing the patterned polymer
to define an opening with its bottom defined by an exposed portion
of the semiconductor substrate; forming a gate insulating film on
the exposed semiconductor substrate within the opening; depositing
an electrically conducting film on a structure obtained at the
above step to bury the opening; applying the CMP process to the
electrically conducting film to allow the electrically conducting
film to remain only within the opening, wherein the insulating
oxide film is used as a polishing stop layer; removing a portion of
the electrically conducting film formed within the opening by
etching; depositing a mask nitride film on a structure obtained at
the above step to bury the top of the electrically conducting film;
and applying the CMP process to the mask nitride film until the
insulating oxide film is exposed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The above and other objects and features of the present
invention will become apparent from the following description of
the preferred embodiments given in conjunction with the
accompanying drawings, in which:
[0014] FIGS. 1A to 1E are sectional views setting forth a
conventional gate formation method using a damascene process;
and
[0015] FIGS. 2A to 2E are sectional views setting forth a method
for the formation of a gate electrode in accordance with a
preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0016] As shown in FIG. 2A, a pad oxide film 21 followed by a
polymer 22 are deposited on a semiconductor substrate 20.
[0017] The pad oxide film 21 with a thickness of 40 .ANG. to 100
.ANG. is formed using a low pressure chemical vapor deposition
(hereinafter referred to as LPCVD) or a plasma enhanced chemical
vapor deposition (hereinafter referred to as PECVD) under a
temperature ranging from 400.degree. C. to 1300.degree. C. The
polymer 22 is formed by a Silk (silicon low K polymer--K is
dielectric constant), Flare (fluorinated poly-aryl-ether) or BCB
(benzocyclobutene).
[0018] The preceding step is then followed by baking the structure
shown in FIG. 2A at a temperature ranging from 90.degree. C. to
350.degree. C. for more than one minute. The baking process
includes a sequence of temperatures ranging from 90.degree. C. to
150.degree. C., from 200.degree. C. to 250.degree. C., and from
300.degree. C. to 350.degree. C. After the baking process, a curing
process is applied at a temperature ranging from 300.degree. C. to
500.degree. C. for 30 to 60 minutes. The curing process includes a
sequence of temperatures ranging from 400.degree. C. to 500.degree.
C., from 350.degree. C. to 450.degree. C. and from 300.degree. C.
to 400.degree. C. During the curing process, a concentration of
oxygen should be set to be less than several hundred PPM. On the
one side, a hard mask layer including a SiN, SiO.sub.2 and SiON may
be formed on the polymer 22. In this case, the hard mask layer with
a thickness of 100 .ANG. to 1000 .ANG. is formed by the PECVD at a
temperature ranging from 200.degree. C. to 550.degree. C.
[0019] Subsequently, as shown in FIG. 2B, the pad oxide film 21 and
the polymer 22 are selectively etched to form a patterned polymer
functioning as a dummy pattern. In an ensuing step, an impurity is
ion-implanted within the semiconductor substrate 20 to form a
source-drain path (not shown). After that, an insulating film
including a nitride film or an oxide film is deposited on a
structure resulting from the above steps. Next, an etching is
applied to the whole surface to form an insulating film spacer 23
at a sidewall of the patterned polymer 22. In a subsequent step, a
source-drain (not shown) of high concentration is formed by the
impurity ion implantation process. Depositing an insulating oxide
film 24 for planarization on the whole structure and heat-treating
the insulating oxide film 14 then follow the preceding steps.
[0020] The nitride film or the oxide film with a thickness ranging
from 100 .ANG. to 1000 .ANG. is formed by using the LPCVD or PECVD
process under a temperature ranging from 300.degree. C. to
1300.degree. C. The insulating oxide film 24 is formed by any one
of a borophosphor silicate glass (BPSG), phosphor silicate glass
(PSG), fluorinated silicate glass (FSG), tetraethyl orthosilicate
(TEOS) or SiH4, each being formed by the PECVD process; or PSG or
undoped silicate glass (USG) each being formed by a plasma of high
density and advanced planarization layer (APL), at a thickness
ranging from 3000.quadrature. to 10000.quadrature.. After the
formation of the insulating oxide film 24, a heat treatment is
applied according to a film type at a temperature ranging from
300.degree. C. to 1000.degree. C.
[0021] In a subsequent step, the chemical-mechanical polishing
process is applied to the insulating oxide film 24 using the slurry
for oxide film polishing as shown in FIG. 2C. In this case, the
patterned polymer is used as a polishing stop layer.
[0022] A slurry of SiO.sub.2, CeO.sub.2, Al.sub.2O.sub.3 or
ZrO.sub.2 series, with a size ranging from 10 nm to 500 nm, is
utilized as the slurry for oxide film polishing in the
chemical-mechanical polishing process. The slurry has a hydrogen
ion concentration (pH) ranging from 3 to 12 mol/L, and a
concentration of organic material in the slurry should be included
in a range of 0.01 to 5 wt % by weight. The slurry for oxide film
polishing has a high polishing selection ratio of the oxide film to
the polymer 22, enhancing a uniformity of the chemical-mechanical
polishing.
[0023] The preceding step is then followed by removing the polymer
22 and the pad oxide film 21 as shown in FIG. 2D. As shown, an
opening 200 with its sidewall exposed to the insulating film spacer
23 and its bottom exposed to the semiconductor substrate 20 is
defined. The polymer 22 is removed by a plasma scheme using a mixed
gas of O.sub.2 and Ar or O.sub.2 and N.sub.2, or a wet etching.
[0024] As mentioned above, the uniform chemical-mechanical
polishing for the insulating oxide film 24 allows the opening 200
with a uniform depth to be defined on the wafer region.
[0025] Subsequently, as shown in FIG. 2E, a gate insulating film 25
made of a thermal oxide film, high temperature oxide film,
Al.sub.2O.sub.3 or Ta.sub.2O.sub.3, within a range of 40 .ANG. to
100 .ANG. in thickness, is formed within the opening 200. A barrier
metal film 26 is formed on the gate insulating film 25 by
depositing a Ti, TiN, TiAIN, TiSiN, TaN, WN or TiSi.sub.2 material
with a thickness ranging from 50 .ANG. to 800 .ANG. on the gate
insulating film 25, through the use of a physical vapor deposition
such as sputtering, a chemical vapor deposition or an
electroplating. Then, a metal film 27 to be used as a gate
electrode is formed on the barrier metal film 26 and the insulating
oxide film 24.
[0026] The metal film 27 is formed by depositing tungsten(W),
copper (Cu) and/or the like with a thickness ranging from 2000
.ANG. to 5000 .ANG. on the barrier metal film 26 using the physical
vapor deposition such as sputtering or the chemical vapor
deposition, at a normal temperature or 1000.degree. C. On the other
hand, after the formation of the barrier metal film 26, a heat
treatment may be selectively applied at a temperature ranging from
400.degree. C. to 800.degree. C. in a N.sub.2 ambient according to
a film type.
[0027] In an ensuing step, as shown in FIG. 2F, a
chemical-mechanical polishing process is applied to the metal film
27 to allow the metal film 27 to remain only within the opening
200. During the polishing, the insulating oxide film 24 is used as
a polishing stop layer.
[0028] In this case, an abrasive such as at least one of silica and
aluminum, and slurry with a hydrogen peroxide having a
concentration ranging from 0.5 wt % to 10 wt % may be used.
[0029] Next, as shown in FIG. 2G, a portion of the metal film 27
formed within the opening 200 is removed by etching, followed by a
mask nitride film 28 being deposited on the remaining metal film.
Next, a chemical-mechanical polishing process is applied to the
mask nitride film 28 until the insulating oxide film 24 is exposed,
resulting in the formation of the gate electrode.
[0030] The mask nitride film 28 with a thickness ranging from 200
.ANG. to 2000 .ANG. is deposited by the LPCVD or PECVD process,
under a temperature ranging from 400.degree. C. to 1300.degree. C.
During the polishing of the mask nitride film 28, a hydrogen ion
concentration (pH) of the slurry containing an abrasive of
SiO.sub.2, CeO.sub.2, Al.sub.2O.sub.3 or ZrO.sub.2 series should be
maintained in the range of 3 to 12 mol/L.
[0031] As demonstrated above, the present invention has the ability
to form a gate with a uniform elevation irrespective of a wafer
region. Furthermore, even though a chemical-mechanical polishing
process using a typical slurry for oxide film polishing is
utilized, the present invention has the capability of controlling a
polishing selection ratio between an oxide film and a dummy polymer
pattern to thereby form a gate (i.e., wordline) with a uniform
elevation, resulting in stabilized electrical properties of the
semiconductor device.
[0032] Although the preferred embodiments of the invention have
been disclosed for illustrative purposes, those skilled in the art
will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
spirit of the invention as disclosed in the accompanying
claims.
* * * * *