U.S. patent application number 09/934761 was filed with the patent office on 2002-01-03 for semiconductor memory device having silicon-on-insulator (soi) structure and method for fabricating thereof.
Invention is credited to Kim, Yun-Gi.
Application Number | 20020001913 09/934761 |
Document ID | / |
Family ID | 19537782 |
Filed Date | 2002-01-03 |
United States Patent
Application |
20020001913 |
Kind Code |
A1 |
Kim, Yun-Gi |
January 3, 2002 |
Semiconductor memory device having silicon-on-insulator (SOI)
structure and method for fabricating thereof
Abstract
A silicon on insulator transistor including a gate electrode, a
pair of source/drain regions and a channel area is electrically
connected to a conductor through an opening in an insulating layer
formed therebetween, through the channel area. The presence of the
conductor prevents irregular variation in threshold voltage and
reduces the sub-threshold leakage and thereby guarantees high
operating speed. A transistor including a pair of source/drain
regions and a channel area is formed on one surface of a
semiconductor substrate or processing wafer. A first insulating
layer is formed on the transistor and over the semiconductor
substrate/processing wafer. A handling wafer is bonded onto the
first insulating layer. The other surface of the semiconductor
substrate/processing wafer is ground and/or polished. A second
insulating layer is formed on the ground/polished semiconductor
substrate/processing wafer. A conductor is formed on the second
insulating layer and electrically connected to the channel area of
the transistor through the second insulating layer.
Inventors: |
Kim, Yun-Gi; (Wonjoo-shi,
KR) |
Correspondence
Address: |
Eugene M. Lee, Esq.
THE LAW OFFICE OF EUGENE M. LEE, P.L.L.C.
Suite 1200
2111 Wilson Boulevard
Arlington
VA
22201
US
|
Family ID: |
19537782 |
Appl. No.: |
09/934761 |
Filed: |
August 23, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09934761 |
Aug 23, 2001 |
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09320214 |
May 26, 1999 |
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6294806 |
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Current U.S.
Class: |
438/400 ;
257/E21.703; 257/E27.086; 257/E27.09; 257/E27.112 |
Current CPC
Class: |
H01L 21/84 20130101;
H01L 27/1203 20130101; H01L 27/10882 20130101; H01L 27/1082
20130101; H01L 29/78648 20130101; H01L 27/0214 20130101; H01L
27/10808 20130101; Y10S 438/928 20130101 |
Class at
Publication: |
438/400 |
International
Class: |
H01L 021/76 |
Foreign Application Data
Date |
Code |
Application Number |
May 27, 1998 |
KR |
98-19164 |
Claims
What is claimed is:
1. A method for fabricating a semiconductor device comprising:
providing a processing wafer having first and second surfaces
opposing each other; forming a device isolation layer in and on the
first surface of the processing wafer to define active and inactive
regions; forming a gate electrode structure being composed of a
gate oxide, a gate electrode and a pair of source/drain region on
the active region; forming a first insulating layer on the gate
electrode structure and on the first surface of the processing
wafer; bonding one surface of a handling wafer onto the first
insulating layer; and forming a second insulating layer on the
second surface of the processing wafer.
2. The method according to claim 1, further comprising forming a
conductor on the second insulating layer and in the second
insulating layer to be electrically connected to the processing
wafer underlying the gate electrode and between the pair of
source/drain region.
3. The method according to claim 1, further comprising forming a
second gate electrode on the second insulating layer and aligning
the second gate electrode over the gate electrode and parallel
thereto.
4. The method according to claim 2, wherein the conductor is
electrically connected to the gate electrode.
5. The method according to claim 2, wherein the conductor is
aligned over the gate electrode and parallel thereto.
6. The method according to claim 2, wherein the contact resistance
of the gate electrode is equal to that of the conductor.
7. The method according to claim 2, wherein one of the gate
electrode and conductor serves as a back gate electrode.
8. The method according to claim 3, wherein the gate electrode is
electrically connected to the second gate electrode.
9. The method according to claim 1, further comprising, before
bonding the two wafer, forming a capacitor on the first insulating
layer to be electrically connected to one of the pair of the
source/drain region, and forming an adhesion layer on the capacitor
and on the first insulating layer, wherein the one surface of the
handling wafer is bonded onto the processing wafer through the
adhesion layer.
10. The method according to claim 1, further comprising, grinding
and/or polishing the second surface of the processing wafer down to
a top surface of the device isolation layer to form a polished
surface, wherein the second insulating layer is formed on the
polished surface.
11. The method according to claim 2, wherein the conductor is made
of a material selected from the group consisting of a polysilicon,
the tungsten silicide, tungsten, metal and a combination
thereof.
12. The method according to claim 3, wherein the gate electrode is
made of a material selected from the group consisting of a
polysilicon, a tungsten silicide, tungsten, metal and a combination
thereof.
13. The method according to claim 3, wherein one of the gate
electrode and second gate electrode serves as a back gate
electrode.
14. The method according to claim 3, wherein the contact resistance
of the gate electrode is equal to that of the second gate
electrode.
15. A method for fabricating a semiconductor device comprising:
providing a processing wafer having first and second surfaces
opposing each other; forming a device isolation layer in the first
surface of the processing wafer to define active an inactive
regions; grinding and/or polishing the second surface of the
processing wafer down to a top surface of the device isolation
layer to form a polished surface; forming a first insulating layer
on the polished surface; forming a conductor on and in the first
insulating layer; forming a gate electrode structure being composed
of a gate oxide, a gate electrode and a pair of source/drain region
on the active region, wherein the active region between the pair of
the source/drain region and underlying the gate electrode is
electrically connected to the conductor; forming a second
insulating layer on the gate electrode structure and on the first
surface of the processing wafer; and bonding one surface of a
handling wafer onto the first insulating layer.
16. A SOI semiconductor device comprising: a semiconductor
substrate having first and second surfaces opposing each other, the
first surface having an active region; a first gate electrode
structure being composed of a gate oxide, a gate electrode and a
pair of source/drain region on the active region of first surface
of the substrate; a first insulating layer formed on the second
surface of the substrate; a second insulating layer formed on the
first gate electrode on the substrate; a third insulating layer
formed on the second insulating layer; and a handling wafer formed
on the third insulating layer.
17. The SOI semiconductor device according to claim 16, further
comprising a conductor pattern formed in and on the first
insulating layer and electrically connected to the active region
aligned over the first gate electrode and between the pair of the
source/drain region.
18. The SOI semiconductor device according to claim 16, further
comprising a second gate electrode formed in the first insulating
layer.
19. The SOI semiconductor device according to claim 17, wherein the
second gate electrode is parallel to the underlying first gate
electrode layer.
20. The SOI semiconductor device according to claim 16, further
comprising a capacitor formed on the third insulating layer and
electrically connected to the source/drain region, wherein the
processing wafer is bonded onto the fourth insulating layer.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a method of making a
semiconductor device, and more particularly to a semiconductor
memory cell fabricated on a silicon-on-insulator (hereinafter
referred to SOI) type substrate.
BACKGROUND OF THE INVENTION
[0002] Substrates useful in manufacturing semiconductor devices are
increasingly required to possess a higher degree of freedom when
designing a device to be fabricated thereon. Therefore, this trend
has drawn more attention to the substrates of so called SOI type,
which typically comprise a bonded wafer being structured such that
a thermally grown oxide layer is sandwiched between two silicon
wafers, at least one of the silicon wafers being mono-crystalline.
The bonded wafer may be used for making an electric device such as
a semiconductor device or, for example, a micro machine in one of
the other fields of application. A transistor built on the SOI has
an advantage of requiring low supply voltage and low operation
voltage due to reduced well and load resistance. In addition, the
SOI transistor exhibits high operation speed.
[0003] However, the SOI transistor has some inherent drawbacks. One
important shortcoming of these SOI transistors is the occurrence of
the floating body effect, or electrical floating. The electrical
floating of the transistor active region allows the unstable
characteristics of the transistor and generates reliability
concerns associated with transistor mis-operation and degradation
of the characteristics.
[0004] FIG. 1 schematically illustrates a DRAM device built on an
SOI. The DRAM device typically includes a reversed capacitor 20 and
word lines 14a and 14b, respectively formed on first insulating
layer 22a and second insulating layer 18 which are disposed over a
handling wafer 24 in this order. The reversed capacitor 20 is
connected to one of the source/drain regions 16 through the second
insulating layer 18. The other of the source/drain regions 16 is
connected to a bit line 28 at a selected portion while other areas
are insulated from the other source/drain regions 16 by a third
insulating layer 26 formed therebetween. An area underlying the
word line 14a and between the pair of the source/drain regions 16
is defined as a channel area. A fourth insulating layer 30 is
disposed over the bit line 28 and metal lines 30a and 30b are
formed on the fourth insulating layer 30.
[0005] As can be seen, the channel area is in the state of
electrical floating. Such a floating state of the channel area
allows an irregular variation of the threshold due to an
accumulation hole. Thus, there exists a need to develop a
semiconductor memory device having an SOI structure that does not
suffer from the drawbacks associated with electrical floating.
SUMMARY OF THE INVENTION
[0006] The present invention was made in view of the above problem,
and it is therefore a feature of the present invention to provide a
method for fabricating a DRAM device on an SOI type substrate
wherein a channel area of the transistor is electrically connected
to a conductor so as to suppress the floating body effect.
[0007] In accordance with a primary feature of the present
invention, there is provided a method of fabricating a
semiconductor device comprising providing a processing wafer having
first and second surfaces opposing each other, forming a device
isolation layer in and on the first surface of the processing wafer
to define active and inactive regions, forming a gate electrode
structure being composed of a gate oxide, a gate electrode and a
pair of source/drain region on the active region, forming a first
insulating layer on the gate electrode structure and on the first
surface of the processing wafer, bonding one surface of a handling
wafer onto the first insulating layer, and forming a second
insulating layer on the second surface of the processing wafer. A
conductor may be further formed on and in the second insulating
layer so as to be electrically connected to the processing wafer
underlying the gate electrode and between the pair of source/drain
region. A second gate electrode may also be formed on the second
insulating layer in alignment and parallel with and over the gate
electrode.
[0008] In accordance with another feature of the present invention,
there is provided a DRAM device on an SOI type substrate where the
conductor connected to the channel area is aligned over the gate
line and is parallel thereto. The conductor also is connected to
the overlying metal line at the terminal portion of the cell array
(i.e., around the sense amplifier). The accumulation hole caused by
the floating body effect of the transistor flows out to the ground
and the back-bias voltage (V.sub.bb) through the conductor
connected to the channel to thereby prevent the sub-threshold
voltage leakage and suppress an unacceptable variation in the
threshold voltage.
[0009] In accordance with yet another feature of the present
invention, a device isolation region is formed on a semiconductor
substrate or a processing wafer, and preferably the device
isolation region surrounds active regions in and on one surface of
the semiconductor substrate or processing wafer. A transistor
including a gate oxide layer, a gate electrode, a capping layer, a
pair of source/drain regions, and a channel area disposed between
the pair of source/drain regions can be formed on the selected
active region. A first insulating layer then may be formed on the
transistor and over the semiconductor substrate or processing
wafer. A capacitor then preferably is formed in a conventional
manner on the first insulating layer and electrically connected to
one of the source/drain region through the first insulating layer.
A second insulating layer may be formed on the first insulating
layer. A handling wafer then can be bonded onto the second
insulating layer. The other surface of the semiconductor substrate
or processing wafer preferably is ground and/or polished down to
the device isolation region so that a bonded SOI type substrate is
formed. A third insulating layer then can be formed on the polished
semiconductor surface/processing wafer. A contact preferably is
opened in the third insulating layer to the channel area of the
transistor. A conductive material then can be deposited on the
third insulating layer and in the contact opening and patterned to
form a conductor line. A fourth insulating layer can be formed on
the conductor line and over the third insulating layer. A bit line
then may be formed on the fourth insulating layer and electrically
connected to another source/drain region through selected fourth
insulating layer. A fifth insulating layer then may be formed over
the fourth insulating and a first metal line formed thereon.
[0010] According to another aspect of the present invention, the
conductor line can be connected to the underlying gate line. Due to
this connection between the gate line and the conductor line, the
dynamic threshold voltage (V.sub.t) is controlled. If the gate
current is zero (i.e., off current), channel current is submitted
to zero concurrently, and consequently, the sub-threshold leakage
is suppressed. On the other hand, if the gate current increases to
a predetermined voltage (i.e., on current), the channel voltage
also increases to that magnitude, so that V.sub.t of the channel
significantly decreases and increases motility.
[0011] According to another aspect of the present invention, after
formation of the third insulating layer, a second gate line can be
formed on the third insulating layer and parallel to the underlying
embedded gate line. The two gate lines then may be connected to
each other. One of the two gate electrodes serves as a backgate and
operates as described above.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The invention may be understood and its features will become
apparent to those skilled in the art by reference to the
accompanying drawings, wherein:
[0013] FIG. 1 is a cross-sectional view of a DRAM device fabricated
on SOI type substrate according to a prior art method;
[0014] FIG. 2A is a cross-sectional view of a semiconductor
substrate having a gate line and a capacitor according to a first
embodiment of the present invention;
[0015] FIG. 2B illustrates a process step subsequent to that shown
in FIG. 2A wherein an insulating layer is formed over the
capacitor;
[0016] FIG. 2C illustrates a process step subsequent to that shown
in FIG. 2B wherein a handling wafer is bonded onto the insulating
layer to thereby form an SOI type substrate;
[0017] FIG. 3A illustrates a process step subsequent to that shown
in FIG. 2C wherein a novel conductor line according to the
invention is formed;
[0018] FIG. 3B illustrates a process step subsequent to that shown
in FIG. 2C wherein a second gate line is formed is formed according
to a second embodiment of the present invention;
[0019] FIGS. 4A and 4B are top plan views of a SOI type substrate
according to a first embodiment of the present invention and
modifications thereof, respectively; and
[0020] FIG. 4C is a top plan view of a SOI type substrate according
to a second embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0021] Korean application no. 98-19164, filed May 27, 1998, is
hereby incorporated by reference as if fully set forth herein.
[0022] The invention may be understood and its objects will become
apparent to those skilled in the art by reference to the detailed
description of the preferred embodiments, which now will be
described in detail with reference to the accompanying
drawings.
[0023] A first embodiment of the present invention will be
described with reference to FIGS. 2A to 2C, 3A, 4A and 4B. FIG. 2A
represents a cross-sectional view showing schematically a
semiconductor substrate having already undergone certain process
steps according to this embodiment of the present invention. First,
a device isolation layer 112 is conventionally formed on one
surface of the semiconductor substrate 100 to define an active
region and inactive region. A transistor including a gate electrode
114a, a gate oxide (not shown), and source/drain regions 116 is
formed on the active region of the semiconductor substrate 100. The
formation of the transistor is conventional and their explanation
is omitted. Accordingly, skilled artisans are capable of
fabricating a transistor as shown in FIG. 2A using techniques known
in the art.
[0024] Insulating layer 118 then can be formed on the transistor
and the semiconductor substrate 100 in a conventional manner known
to those skilled in the art. Generally, a silicon dioxide layer is
preferred as the insulating layer 118. An opening then can be
formed in the first insulating layer 118 to one of the source/drain
regions 116 and a lower electrode of the capacitor can be deposited
in the opening and on the first insulating layer 118. A dielectric
film of the capacitor and a top electrode are deposited and
patterned to completely form the capacitor 120. A second insulating
layer 122 such as borophosphosilicate glass (BPSG) then can be
formed on the capacitor 120 and the first insulating layer 118.
This BPSG layer 122 typically is used as a glue layer for a SOI
type substrate.
[0025] Referring now to FIG. 2B, the BPSG layer 122 then is grinded
and polished for a SOI type substrate and subsequently bonded onto
the prepared handling wafer 124. The other surface of the
semiconductor substrate 100 (i.e., the surface opposing the
handling wafer 124) then can be planarized down to the device
isolation layer 112 as shown in FIG. 2C. The planarization process
preferably is accomplished by employing a chemical mechanical
polishing (CMP) technique. Those skilled in the art are capable of
using the CMP technique to polish, or planarize, substrate 100 down
to the device isolation layer 112.
[0026] The formation of the body contact conductor line is
described below with reference to FIG. 3A. Referring now to FIG.
3A, a third insulating layer 128a, preferably composed of an oxide
layer (most preferably a metal oxide layer) may be formed on the
planarized surface to a thickness of about 1,000.ANG.. An opening
then can be formed in the third insulating layer 128a to the
channel area corresponding the bulk region of the semiconductor
substrate between the source/drain regions 116. A conductive
material preferably is deposited in the opening and on the third
insulating layer 128a and pattered to form body contact conductor
linea 126a and 126b, respectively. The conductive line 126b is
formed overlapping and parallell to underlying gate electrode 114a.
In other words, an accumulation hole that may be caused by the
floating body effect is flowed to the ground or V.sub.bb to thereby
suppress the deduction of the breakdown voltage and sub-threshold
leakage. Furthermore, since the gate line and the capacitor are
embedded, there is no overlapping concern between the bit line (or
metal line) over the body contact conductor line and the gate line
(or capacitor). Therefore, the body contact conductor line can be
made of any suitable material, preferably those selected from
polysilicon, tungsten silicide, tungsten, or metal, and can be used
simultaneously for a resistance line of the peripheral circuit
region.
[0027] The next process step is the formation of a bit line 130. In
accordance with this process step, a fourth insulating layer 128b
can be s formed on the body contact conductor line 126b and the
third insulating layer 128a. An opening then can be formed in the
third and fourth insulating layers 128a and 128b, respectively, to
the other one of the source/drain regions 116. A bit line material
then can be deposited in the opening and on the fourth insulating
layer 128b to form the bit line 130. A fifth insulating layer 132
now can be formed on the fourth insulating layer 128b and metal
lines 134a and 134b formed thereon.
[0028] FIG. 4A illustrates schematically a top plan view of a SOI
type substrate after formation of the body contact conductor line
126 (126a and 126b) according to the first embodiment. As can be
seen, the body contact conductor line 126 is aligned over and
parallell to the underlying the gate electrode 114a which
intersects active regions 110. The body contact conductor line 126
is connected to the active regions 110 (more specifically to the
channel area) through the contact plug 126a. The body contact
conductor line 126 suppresses advantageously the floating body
effect of the transistor.
[0029] Alternatively, the gate electrode 114a and the body contact
conductor line 126b may be connected to each other through a
contact 135 and contact plug 136, as shown in FIG. 4B. As a result,
the body contact conductor line 126b serves as a backgate.
[0030] The body contact conductor line can be connected to the
ground or backbias voltage (V.sub.bb). If the gate voltage is zero
(i.e., off current), the channel area is also submitted to zero
voltage thereby suppressing the sub-threshold leakage. If the
predetermined voltage is applied to the gate (i.e., on current),
the channel area is also applied by the same magnitude voltage of
the gate thereby reducing the threshold voltage and increasing
carrier concentration.
[0031] A second embodiment of the present invention will be
described below with reference to FIGS. 3B and FIG. 4C. The same
parts functioning as the first embodiment are identified with the
same reference numerals and their explanation is briefly described.
After forming the SOI type substrate shown in FIG. 2C, a third
insulating layer 128c can be formed on the planarized SOI surface.
A second gate 126, so called backgate, then can be formed on the
third insulating layer 128c so as to overlap and be parallel to the
underlying first gate electrode 114a. The backgate 126 then can be
connected to the first gate electrode 114a. Herein, the second gate
126 has the same resistance as the first gate electrode 114a and
preferably is made of the same conductive material such as
polysilicon, tungsten silicide, tungsten and metal. The process
sequence of the first gate electrode and second back gate may be
reversed. Briefly, after defining active and inactive region by the
device isolation layer 112, a back gate may first be formed on the
active region of the semiconductor substrate. Several process step
then can be carried out as described above with reference to first
embodiment. The third insulating layer 128c then can be formed and
a gate subsequently formed on the third insulating layer 128c.
[0032] A fourth insulating layer 128d then can be formed on the
second backgate 126 and the third insulating layer 128c. The next
process sequences are similar to those described above with respect
to the first embodiment. The function of the back gate is already
explained in the first embodiment of the present invention.
[0033] FIG. 4C illustrates schematically a top plan view of a SOI
type substrate after formation of the second backgate 126 according
to the second embodiment of the present invention. As can be seen,
the second backgate 126 is connected to the first gate electrode
114a through the contact 135 and contact plug 136.
[0034] It will be recognized by those skilled in the art that the
innovative concepts disclosed in the present application can be
applied in a wide variety of contexts. Moreover, the preferred
implementation can be modified in a tremendous variety of ways.
Accordingly, it should be understood that the modification and
variations suggested below and above are merely illustrative. These
examples may help to show some of the scope of the inventive
concepts, but these examples do not exhaust the full scope of
variation in the disclosed novel concepts.
* * * * *