U.S. patent application number 09/318734 was filed with the patent office on 2002-01-03 for semiconductor memory having buried digit lines.
Invention is credited to TASAKA, KAZUHIRO.
Application Number | 20020000625 09/318734 |
Document ID | / |
Family ID | 15359167 |
Filed Date | 2002-01-03 |
United States Patent
Application |
20020000625 |
Kind Code |
A1 |
TASAKA, KAZUHIRO |
January 3, 2002 |
SEMICONDUCTOR MEMORY HAVING BURIED DIGIT LINES
Abstract
A semiconductor memory comprises a gate electrode formed on a
gate oxide film formed in each of active regions on a principal
surface of a semiconductor substrate, grooves formed in self
alignment with the gate electrode and to penetrate the inside of
the semiconductor substrate, a buried digit line formed of a
diffused layer which is formed at an inner surface of each of the
grooves and which is of a conductivity type opposite to that of the
semiconductor substrate, a CVD oxide film formed to cover the
surface of each of the grooves and at least a portion of a side
surface of the gate electrode, a BPSG film filled up in the
grooves, and a word line formed on the principal surface of the
semiconductor substrate to extend orthogonally to the grooves, and
constituting the gate electrode on the active region and
functioning as an interconnection layer on the grooves.
Inventors: |
TASAKA, KAZUHIRO; (TOKYO,
JP) |
Correspondence
Address: |
MCGINN & GIBB, PLLC
8321 OLD COURTHOUSE ROAD
SUITE 200
VIENNA
VA
22182-3817
US
|
Family ID: |
15359167 |
Appl. No.: |
09/318734 |
Filed: |
May 26, 1999 |
Current U.S.
Class: |
257/391 ;
257/E21.671; 257/E27.102 |
Current CPC
Class: |
H01L 27/112 20130101;
H01L 27/11253 20130101 |
Class at
Publication: |
257/391 |
International
Class: |
H01L 031/062; H01L
029/94; H01L 029/76 |
Foreign Application Data
Date |
Code |
Application Number |
May 26, 1998 |
JP |
10-144312 |
Claims
1. A semiconductor memory comprising a semiconductor substrate
having a principal surface, a gate electrode which is formed on a
gate insulator film formed in an active region on said principal
surface of said semiconductor substrate and which is formed of a
semiconductor layer and a conducting layer, grooves formed in self
alignment with said gate electrode and to penetrate the inside of
said semiconductor substrate, a buried digit line formed of a
diffused layer which is formed within each of said grooves and
which is of a conductivity type opposite to that of said
semiconductor substrate, a first insulating film covering a surface
of each of said grooves and at least a portion of a side surface of
said gate electrode, a second insulating film filled up in said
grooves and having a high reflow property, and a word line formed
on said principal surface of said semiconductor substrate to extend
orthogonally to said grooves, and constituting said gate electrode
on said active region and functioning as an interconnection layer
on said grooves.
2. A semiconductor memory claimed in claim 1 wherein said grooves
have a V-shape in a cross-section.
3. A semiconductor memory claimed in claim 1 wherein said first
insulating film has an etching rate smaller than that of said
second insulating film.
4. A semiconductor memory claimed in claim 1 wherein said
semiconductor layer is formed of a polysilicon film or an amorphous
silicon film.
5. A semiconductor memory claimed in claim 1 wherein said
conducting layer is formed of a refractory metal film.
6. A semiconductor memory claimed in claim 1 wherein said
conducting layer is formed of a polysilicon film or an amorphous
silicon film.
7. A method for fabricating a semiconductor memory, comprising the
steps of: forming a semiconductor layer on a gate insulator film
formed on a principal surface of a semiconductor substrate; forming
grooves to penetrate the inside of said semiconductor substrate in
buried digit line formation regions which locate an active region
between each pair of adjacent buried digit line formation regions;
introducing impurity of a conductivity type opposite to that of
said semiconductor substrate, into at least a surface of said
grooves in said semiconductor substrate; depositing a first
insulating film on said semiconductor substrate; depositing a
second insulating film having a high reflow property, to fill up
said grooves having said surface covered with said first insulating
film, and to planarize a surface of said semiconductor substrate;
removing said first insulating film and said second insulating film
to allow said first insulating film and said second insulating film
to remain only within said grooves; forming a conducting layer on
said semiconductor substrate; and selectively partially removing
said conducting layer and said semiconductor layer to form a word
line extending on said principal surface of said semiconductor
substrate orthogonally to said grooves, and constituting said gate
electrode on said active region and functioning as an
interconnection layer on said grooves.
8. A method claimed in claim 7 wherein said grooves have a V-shape
in a cross-section.
9. A method claimed in claim 7 wherein said grooves are formed by
performing an etching using a patterned photoresist film formed on
said semiconductor layer as a mask.
10. A method claimed in claim 7 wherein said grooves are formed by
forming on said semiconductor layer a third insulating film
different from said first insulating film and said second
insulating film, patterning said third insulating film, and
performing an etching using the patterned third insulating film as
a mask.
11. A method claimed in claim 7 wherein said first insulating film
has an etching rate smaller than that of said second insulating
film.
12. A method claimed in claim 7 wherein the step of introducing the
impurity of the conductivity type opposite to that of said
semiconductor substrate, into at least the surface of said grooves
in said semiconductor substrate, is carried out by a slant rotating
ion implantation.
13. A method claimed in claim 7 wherein said grooves are formed by
performing an etching using a patterned photoresist film formed on
said semiconductor layer as a mask, and wherein in the step of
introducing the impurity of the conductivity type opposite to that
of said semiconductor substrate, into at least the surface of said
grooves in said semiconductor substrate, said impurity is
introduced into said semiconductor layer.
14. A method claimed in claim 7 wherein said semiconductor layer is
formed of a polysilicon film or an amorphous silicon film.
15. A method claimed in claim 7 wherein when said semiconductor
layer is formed, impurity of the conductivity type opposite to that
of said semiconductor substrate is introduced into said
semiconductor layer.
16. A method claimed in claim 7 wherein said conducting layer is
formed of a refractory metal film.
17. A method claimed in claim 7 wherein said conducting layer is
formed of a polysilicon film or an amorphous silicon film.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor memory and
a method for fabricating the same, and more specifically to a
structure of a semiconductor memory such as a
large-storage-capacity NOR type mask ROM, having buried digit
lines, and a method for fabricating the same.
[0003] 2. Description of Related Art
[0004] Now, a prior art will be described with reference to FIGS. 3
and 4. FIG. 3 is a plan view for illustrating a general cell layout
in the NOR type mask ROM having buried digit lines. A plurality of
buried digit lines 8 and active regions 6 are alternately located.
A plurality of word lines 13 extend orthogonally to the buried
digit lines 8. A region surrounded by a dotted line in FIG. 3
corresponds to a unitary cell. In FIG. 3, "L" indicates a channel
length, and "W" indicates a channel width.
[0005] Next, a method in accordance with the prior art for
fabricating the NOR type mask ROM having buried digit lines will be
described with reference to FIGS. 4A to 4D, which are diagrammatic
sectional views taken along the line A-A in FIG. 3 for illustrating
the prior art method.
[0006] As shown in FIG. 4A, an oxide film 4 is formed on a P-type
silicon substrate 1, and a photoresist film 5 is formed on the
oxide film 4, and then patterned to have an opening at a region
which is positioned between each pair of adjacent active regions 6
and where a buried digit line is to be formed in future. Then, as
shown in FIG. 4B, N-type impurity, for example, arsenic, is
implanted into the substrate 1 using the patterned photoresist film
5 as a mask. As a result, buried digit lines 8 are formed. After
the photoresist film 5 and the oxide film 4 are removed, oxidation
is carried out so that a gate oxide film 2 is formed on the surface
of the substrate 1 as shown in FIG. 4C. Further, a polysilicon film
3 and a tungsten silicide film 11 are formed on the whole surface
as shown in FIG. 4D, and then, are selectively removed so that the
word line 13 constituted of a polycide gate electrode 12 formed of
the tungsten silicide film 11 and the polysilicon film 3, is formed
on the active region 6.
[0007] Incidentally, an example of the NOR type mask ROM is
disclosed by Japanese Patent Application Pre-examination
Publication No. JP-A-05-003303 (an English abstract of
JP-A-05-003303 is available and the content of the English abstract
is incorporated by reference in its entirety into this
application).
[0008] In the above mentioned NOR type mask ROM, a layer resistance
of the buried digit line is desired to be maintained even if the
cell size is reduced, from the viewpoint of a demand in a circuit
for ensuring a high speed operation margin. On the other hand, a
margin of the channel length in a cell transistor (Lmin) should be
ensured. For this purpose, it is desirable to reduce the dose of
the N-type impurity in order to suppress a lateral diffusion.
However, this results in an increased layer resistance of the
buried digit line. Namely, the maintaining of the layer resistance
of the buried digit line and the ensuring of the channel length
margin (Lmin) of the cell transistor are a tradeoff relation
against each other. In the prior art, therefore, it is difficult to
reduce the cell size while simultaneously realizing both of the
maintaining of the layer resistance of the buried digit line and
the ensuring of the channel length margin (Lmin) of the cell
transistor.
SUMMARY OF THE INVENTION
[0009] Accordingly, it is an object of the present invention to
provide a semiconductor memory having a buried digit line, which
has overcome the above mentioned problem of the prior art, and a
method for fabricating the same.
[0010] Another object of the present invention is to provide a
semiconductor memory having buried digit lines, which can reduce
the cell size while simultaneously realizing both of the
maintaining of the layer resistance of the buried digit line and
the ensuring of the channel length margin of the cell transistor,
and a method for fabricating the same.
[0011] The above and other objects of the present invention are
achieved in accordance with the present invention by a
semiconductor memory comprising a semiconductor substrate having a
principal surface, a gate electrode which is formed on a gate
insulator film formed in an active region on the principal surface
of the semiconductor substrate and which is formed of a
semiconductor layer and a conducting layer, grooves formed in self
alignment with the gate electrode and to penetrate the inside of
the semiconductor substrate, a buried digit line formed of a
diffused layer which is formed within each of the grooves and which
is of a conductivity type opposite to that of the semiconductor
substrate, a first insulating film covering a surface of each of
the grooves and at least a portion of a side surface of the gate
electrode, a second insulating film filled up in the grooves and
having a high reflow property, and a word line formed on the
principal surface of the semiconductor substrate to extend
orthogonally to the grooves, and constituting the gate electrode on
the active region and functioning as an interconnection layer on
the grooves.
[0012] According to another aspect of the present invention, there
is provided a method for fabricating a semiconductor memory,
comprising the steps of:
[0013] forming a semiconductor layer on a gate insulator film
formed on a principal surface of a semiconductor substrate;
[0014] forming grooves to penetrate the inside of the semiconductor
substrate in buried digit line formation regions which locate an
active region between each pair of adjacent buried digit line
formation regions;
[0015] introducing impurity of a conductivity type opposite to that
of the semiconductor substrate, into at least a surface of the
grooves in the semiconductor substrate;
[0016] depositing a first insulating film on the semiconductor
substrate;
[0017] depositing a second insulating film having a high reflow
property, to fill up the grooves having the surface covered with
the first insulating film, and to planarize a surface of the
semiconductor substrate;
[0018] removing the first insulating film and the second insulating
film to allow the first insulating film and the second insulating
film to remain only within the grooves;
[0019] forming a conducting layer on the semiconductor substrate;
and
[0020] selectively partially removing the conducting layer and the
semiconductor layer to form a word line extending on the principal
surface of the semiconductor substrate orthogonally to the grooves,
and constituting the gate electrode on the active region and
functioning as an interconnection layer on the grooves.
[0021] With the above mentioned arrangement, even if the cell size
is reduced, it is possible at least to maintain the layer
resistance of the buried digit line.
[0022] In addition, if the grooves are formed to have a V-shape in
a cross-section, even if the cell area is reduced, it is possible
to simultaneously realize at least the maintaining and preferably
the reducing of the layer resistance of the buried digit line, and
the ensuring of the gate length margin (Lmin) of the cell
transistor.
[0023] The grooves can be formed by performing an etching using a
patterned photoresist film formed on the semiconductor layer as a
mask, or alternatively by patterning an insulating film formed on
the semiconductor layer and performing an etching using the
patterned insulating film as a mask.
[0024] Preferably, the first insulating film covering a surface of
each of the grooves and at least the portion of the side surface of
the gate electrode, has an etching rate smaller than that of the
second insulating film having a high reflow property and filling up
the grooves.
[0025] In addition, the step of introducing the impurity of the
conductivity type opposite to that of the semiconductor substrate,
into at least the surface of the grooves in the semiconductor
substrate, can be carded out by a slant rotating ion
implantation.
[0026] Alternatively, the grooves are formed by performing an
etching using a patterned photoresist film formed on the
semiconductor layer as a mask, and in the step of introducing the
impurity of the conductivity type opposite to that of the
semiconductor substrate, into at least the surface of the grooves
in the semiconductor substrate, the impurity is introduced into the
semiconductor layer which was not doped the impurity to have the
conductivity type opposite to that of the semiconductor
substrate.
[0027] Furthermore, the semiconductor layer is formed of a
polysilicon film or an amorphous silicon film. The semiconductor
layer can be doped with impurity to have the conductivity type
opposite to that of the semiconductor substrate when the
semiconductor layer is formed, or alternatively, in a later step,
the semiconductor layer can be doped with impurity to have the
conductivity type opposite to that of the semiconductor
substrate.
[0028] In addition, the conducting layer can be formed of a
refractory metal film such as a tungsten silicide film, or
alternatively can be formed of a polysilicon film or an amorphous
silicon film.
[0029] The above and other objects, features and advantages of the
present invention will be apparent from the following description
of preferred embodiments of the invention with reference to the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIGS. 1A to 1G are diagrammatic sectional views of the NOR
type mask ROM having buried digit lines, for illustrating a first
embodiment of the method in accordance with the present invention
for fabricating the NOR type mask ROM;
[0031] FIGS. 2A to 2G are diagrammatic sectional views of the NOR
type mask ROM having buried digit lines, for illustrating a second
embodiment of the method in accordance with the present invention
for fabricating the NOR type mask ROM;
[0032] FIG. 3 is a plan view for illustrating a general cell layout
in the NOR type mask ROM having buried digit lines; and
[0033] FIGS. 4A to 4D are diagrammatic sectional views for
illustrating a method in accordance with the prior art for
fabricating the NOR type mask ROM having buried digit lines.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0034] In the following, embodiments of the present invention will
be described with reference to the accompanying drawings.
FIRST EMBODIMENT
[0035] FIGS 1A to 1G are diagrammatic sectional views for
illustrating a first embodiment of the method in accordance with
the present invention for fabricating the NOR type mask ROM having
buried digit lines, and FIG. 1G shows a sectional structure of the
NOR type mask ROM fabricated in accordance with that method, and
corresponds to a sectional view taken along the line A-A in FIG.
3.
[0036] As shown in FIG. 1G, the first embodiment of the NOR type
mask ROM in accordance with the present invention having buried
digit lines includes a gate electrode 12 which is located on a gate
oxide film 2 formed in an active region 6 on a principal surface of
a P-type silicon substrate 1 and which is formed of a polysilicon
film 3 and a tungsten silicide film 11. The NOR type mask ROM
further includes grooves 7 having a rectangular vertical
cross-sectional shape, formed to penetrate the inside of the P-type
silicon substrate in a self-alignment with the active regions 6 so
that each of the active regions 6 is confined between each pair of
adjacent grooves. In addition, the NOR type mask ROM includes a
buried digit line 8 formed of an N+ diffused layer formed at an
inner surface of each groove 7, a CVD (chemical vapor deposition)
oxide film 9 formed to cover the buried digit line 8 in each groove
7 and at least a portion of a side surface of the gate electrode
12, and a BPSG (borophosphosilicate glass) film 10 filled up in
each groove 7 and having an etching rate higher than that of the
CVD oxide film 9. Moreover, the NOR type mask ROM includes a word
line 13 which is orthogonal to the grooves 7 (namely, the buried
digit lines 8) and which is constituted of an interconnection layer
formed, on each active region, of a polycide gate electrode 12
composed of the polysilicon film 3 and the tungsten silicide film
11, and on each groove 7, of only the tungsten silicide film
11.
[0037] Now, a first embodiment of the method in accordance with the
present invention for fabricating the first embodiment of the NOR
type mask ROM in accordance with the present invention, will be
described with reference to FIGS. 1A to 1G.
[0038] As shown in FIG. 1A, the gate oxide film 2 having a
thickness of 0.005 .mu.m to 0.03 .mu.m, the polysilicon film 3
having a thickness of 0.1 .mu.m to 0.3 .mu.m, and an oxide film 4
having a thickness of 0.1 .mu.m to 0.34 .mu.m, are formed on the
principal surface of the P-type silicon substrate 1 in the named
order.
[0039] As shown in FIG. 1B, by using a patterned photoresist film 5
as a mask, the oxide film 4, the polysilicon film 3 and the gate
oxide film 2 are etched in the named order. After the photoresist
film 5 is removed, as shown in FIG. 1C, the P-type silicon
substrate 1 is etched using the patterned oxide film 4 as a mask,
so that the grooves 7 having a width of 0.2 .mu.m to 0.5 .mu.m and
having a rectangular vertical cross-sectional shape are formed in
buried digit line formation regions located and separated to put
one active region 6 between each pair of adjacent buried digit line
formation regions. After the polysilicon film 3 is formed, the
grooves 7 can be formed using the patterned photoresist film 5 as a
mask, without forming the oxide film 4.
[0040] Thereafter, as shown in FIG. 1D, an N-type impurity, for
example, arsenic, is implanted on the whole surface of the silicon
substrate 1 by a slant rotating ion implantation under an energy of
40 keV to 100 keV and a dose of 1.times.10.sup.14/cm.sup.2 to
6.times.10.sup.15/cm.sup.2, so that a buried digit line 8 is formed
at an inner surface of each groove 7.
[0041] As shown in FIG. 1E, the CVD oxide film 9 having a thickness
of 1.0 .mu.m to 0.3 .mu.m and the BPSG oxide film 10 having a
thickness of 0.2 .mu.m to 1.0 .mu.m, are formed on the P-type
silicon substrate 1 in the named order, and an annealing is carried
out for 5 minutes to 50 minutes in a nitrogen atmosphere of
800.degree. C. to 950.degree. C., so that the grooves 7 are filled
up with the BPSG film 10 and the surface of the substrate 1
(namely, the surface of the BPSG film 10) is planarized.
[0042] As shown in FIG. 1F, an etching-back is carried out by a dry
etching using the polysilicon film 3 as a stopper, so that the CVD
oxide film 9 and the BPSG oxide film 10 are left only within the
grooves 7. In this etching-back process, since the etch rate of the
CVD oxide film 9 is smaller than that of the BPSG oxide film 10,
even if the etching-back becomes an over-etching, the P-type
silicon substrate 1 is never exposed at the side surface of the
grooves 7.
[0043] As shown in FIG. 1G, the tungsten silicide film 11 is formed
on the whole surface. Thereafter, the tungsten silicide film 11 and
the polysilicon film 3 are selectively partially removed to form
the word lines 13 each of which extends on the surface of the
P-type, silicon substrate 1 orthogonally to the grooves 7 and each
of which is constituted of an interconnection layer formed, on each
active region 6, of the polycide gate electrode 12 composed of the
polysilicon film 3 and the tungsten silicide film 11, and on each
groove 7, of only the tungsten silicide film 11.
[0044] As mentioned above, in the first embodiment of the NOR type
mask ROM in accordance with the present invention, since the whole
of the inner surface of the groove 7 formed in the P-type silicon
substrate 1 can be used for the buried digit line, even if the cell
area is reduced, it is possible at least to maintain and preferably
to reduce the layer resistance of the buried digit lines,
differently from the prior art.
SECOND EMBODIMENT
[0045] FIGS. 2A to 2G are diagrammatic sectional views for
illustrating a second embodiment of the method in accordance with
the present invention for fabricating the NOR type mask ROM having
buried digit lines, and FIG. 2G shows a sectional structure of the
NOR type mask ROM fabricated in accordance with that method, and
corresponds to a sectional view taken along the line A-A in FIG.
3.
[0046] As shown in FIG. 2G, the second embodiment of the NOR type
mask ROM in accordance with the present invention having buried
digit lines includes a gate electrode 12 which is located on a gate
oxide film 2 formed in an active region 6 on a principal surface of
a P-type silicon substrate 1 and which is formed of a polysilicon
film 3 and a tungsten silicide film 11. The NOR type mask ROM
further includes grooves 7A having a triangular vertical
cross-sectional shape having a tapering bottom end (V-shaped
groove), formed to penetrate the inside of the P-type silicon
substrate in a self-alignment with the active regions 6 so that
each of the active regions 6 is confined between each pair of
adjacent grooves. In addition, the NOR type mask ROM includes a
buried digit line 8 formed of an N.sup.+ diffused layer formed at
an inner surface of each groove 7A, a CVD oxide film 9 formed to
cover the buried digit line 8 in each groove 7A and at least a
portion of a side surface of the gate electrode 12, and a BPSG film
10 filled up in each groove 7A and having an etching rate higher
than that of the CVD oxide film 9. Moreover, the NOR type mask ROM
includes a word line 13 which is orthogonal to the grooves 7A
(namely, the buried digit lines 8) and which is constituted of an
interconnection layer formed, on each active region, of a polycide
gate electrode 12 composed of the polysilicon film 3 and the
tungsten silicide film 11, and on each groove 7A, of only the
tungsten silicide film 11.
[0047] Now, a second embodiment of the method in accordance with
the present invention for fabricating the second embodiment of the
NOR type mask ROM in accordance with the present invention, will be
described with reference to FIGS. 2A to 2G.
[0048] As shown in FIG. 2A, the gate oxide film 2 having a
thickness of 0.005 .mu.m to 0.03 .mu.m, the polysilicon film 3
having a thickness of 0.1 .mu.m to 0.3 .mu.m, and an oxide film 4
having a thickness of 0.1 .mu.m to 0.3 .mu.m, are formed on the
principal surface of the P-type silicon substrate 1 in the named
order.
[0049] As shown in FIG. 2B, by using a patterned photoresist film 5
as a mask, the oxide film 4, the polysilicon film 3 and the gate
oxide film 2 are etched in the named order. After the photoresist
film 5 is removed, as shown in FIG. 2C, the P-type silicon
substrate 1 is etched using the patterned oxide film 4 as a mask,
so that the V-shaped grooves 7A having a width of 0.2 .mu.m to 0.5
.mu.m are formed in buried digit line formation regions located and
separated to put one active region 6 between each pair of adjacent
buried digit line formation regions. After the polysilicon film 3
is formed, the grooves 7A can be formed using the patterned
photoresist film 5 as a mask, without forming the oxide film 4,
similarly to the first embodiment.
[0050] Thereafter, as shown in FIG. 2D, an N-type impurity, for
example, arsenic, is implanted on the whole surface of the silicon
substrate 1 by an implantation at an implanting angle of 0 degree
under an energy of 40 keV to 100 keV and a dose of
1.times.10.sup.14/cm.sup.2 to 6.times.10.sup.15/cm.sup.2, so that a
buried digit line 8 is formed at an inner surface of each groove
7A.
[0051] As shown in FIG. 2E, the CVD oxide film 9 having a thickness
of 0.1 .mu.m to 0.3 .mu.m and the BPSG oxide film 10 having a
thickness of 0.2 .mu.m to 1.0 .mu.m, are formed on the P-type
silicon substrate 1 in the named order, and an annealing is carried
out for 5 minutes to 50 minutes in a nitrogen atmosphere of
800.degree. C. to 950.degree. C., so that the grooves 7A are filled
up with the BPSG film 10 and the surface of the substrate 1
(namely, the surface of the BPSG film 10) is planarized.
[0052] As shown in FIG. 2F, an etching-back is carried out by a dry
etching using the polysilicon film 3 as a stopper, so that the CVD
oxide film 9 and the BPSG oxide film 10 are left only within the
grooves 7A. In this etching-back process, since the etch rate of
the CVD oxide film 9 is smaller than that of the BPSG oxide film
10, even if the etching-back becomes an over-etching, the P-type
silicon substrate 1 is never exposed at the side surface of the
grooves 7A.
[0053] As shown in FIG. 2G, the tungsten silicide film 11 is formed
on the whole surface. Thereafter, the tungsten silicide film 11 and
the polysilicon film 3 are selectively partially removed to form
the word lines 13 each of which extends on the surface of the
P-type silicon substrate 1 orthogonally to the grooves 7A and each
of which is constituted of an interconnection layer formed, on each
active region 6, of the polycide gate electrode 12 composed of the
polysilicon film 3 and the tungsten silicide film 11, and on each
groove 7A, of only the tungsten silicide film 11.
[0054] As mentioned above, in the second embodiment of the NOR type
mask ROM in accordance with the present invention, the whole of the
inner surface of the groove 7A formed in the P-type silicon
substrate 1 can be used for the buried digit line. In addition,
since the groove 7A is a V-shape in a vertical cross-section, the
slant rotating ion implantation is no longer necessary in the
N-type impurity implantation for forming the buried digit line 8 at
the inner surface of the grooves 7, and also, the deeper the level
along the V-shaped groove becomes, a spacing between each pair of
adjacent buried digit lines becomes larger, so that it becomes
possible to suppress a punch-through at a deep position, which
cannot be controlled by the polycide gate electrode 12. Therefore,
even if the cell area is reduced, the second embodiment can
simultaneously realize at least the maintaining and preferably the
reducing of the layer resistance of the buried digit line, and the
ensuring of the gate length margin (Lmin) of the cell
transistor.
[0055] As mentioned above, the following advantages can be obtained
according to the present invention.
[0056] (1) The gate length margin (Lmin) of the cell transistor can
be ensured. The reason for this is that, since the groove is a
V-shape in a vertical cross-section, it is possible to avoid the
punch-trough between a source and a drain at a deep position.
[0057] (2) It is possible at least to maintain and preferably to
reduce the layer resistance of the buried digit line. The reason
for this is that the inner surface area of the groove can be
ensured and increased by adjusting the depth and the shape of the
groove.
[0058] (3) It is possible to suppress a seeping-out of the code
boron in a channel direction of the cell transistor, because the
cell transistors are isolated from one another by the grooves in a
channel direction.
[0059] (4) It is possible to reduce the capacitance of the word
line, because the capacitance of the word line is reduced by the
thickness of the insulator film corresponding to the depth of the
groove.
[0060] The invention has thus been shown and described with
reference to the specific embodiments. However, it should be noted
that the present invention is in no way limited to the details of
the illustrated structures but changes and modifications may be
made within the scope of the appended claims.
* * * * *