U.S. patent application number 08/902044 was filed with the patent office on 2001-12-27 for process for device fabrication.
Invention is credited to BEVK, JOZE.
Application Number | 20010055862 08/902044 |
Document ID | / |
Family ID | 26730601 |
Filed Date | 2001-12-27 |
United States Patent
Application |
20010055862 |
Kind Code |
A1 |
BEVK, JOZE |
December 27, 2001 |
PROCESS FOR DEVICE FABRICATION
Abstract
A process for device fabrication, comprising the steps of
forming a dielectric material region on a silicon substrate,
forming a first amorphous silicon or polysilicon region on the
dielectric material region, implanting one or more dopants in the
first amorphous silicon or polysilicon region, and, subsequent to
implanting the one or more dopants in the first amorphous silicon
or polysilicon region, forming a second amorphous silicon or
polysilicon region on the first amorphous silicon or polysilicon
region. Typically, a refractory metal silicide layer is formed over
the silicon, and such silicide is optionally formed by a salicide
process. The second silicon region makes it more difficult for the
implanted dopants to reach the silicide layer, and thereby reduces
undesirable lateral diffusion of dopants in the silicide and
accompanying cross-doping. The buried nature of the dopants in the
silicon further reduces the amount of lateral diffusion within the
silicon, regardless of the gate material. In addition, the benefits
of a relatively thin gate dielectric are realized. Further, the
reduced annealing times and temperatures necessary for dopant
drive-in and activation result in improved control of device
threshold voltage, on- and off-current, and channel and
source/drain dopant profiles.
Inventors: |
BEVK, JOZE; (SUMMIT,
NJ) |
Correspondence
Address: |
DOCKET ADMINISTRATOR
LUCENT TECHNOLOGIES INC RM 3C 512
600 MOUNTAIN AVENUE
P O BOX 636
MURRAY HILL
NJ
07974
|
Family ID: |
26730601 |
Appl. No.: |
08/902044 |
Filed: |
July 29, 1997 |
Current U.S.
Class: |
438/532 ;
257/E21.194; 257/E21.2; 257/E21.637; 438/592 |
Current CPC
Class: |
H01L 21/28061 20130101;
H01L 21/28176 20130101; H01L 21/28202 20130101; H01L 21/823842
20130101; H01L 29/518 20130101 |
Class at
Publication: |
438/532 ;
438/592 |
International
Class: |
H01L 021/425; H01L
021/3205; H01L 021/4763 |
Claims
What is claimed is:
1. A process for device fabrication, comprising the steps of:
forming a dielectric material region on a silicon substrate;
forming a first amorphous silicon or polysilicon region on the
dielectric material region; implanting one or more dopants in the
first amorphous silicon or polysilicon region; and subsequent to
implanting the one or more dopants, forming a second amorphous
silicon or polysilicon region on the first amorphous silicon or
polysilicon region.
2. The process of claim 1, wherein the implantation step comprises
implanting an n-type dopant in a first portion of the first
amorphous silicon or polysilicon region and implanting a p-type
dopant in a second portion of the first amorphous silicon or
polysilicon region.
3. The process of claim 2, wherein the first portion overlies a
p-type region of the silicon substrate and the second portion
overlies an n-type region of the silicon substrate.
4. The process of claim 1, wherein the first and second silicon
regions are amorphous silicon.
5. The process of claim 1, further comprising the step of forming a
refractory metal silicide on at least a portion of the second
amorphous silicon or polysilicon region.
6. The process of claim 5, further comprising the step of
introducing nitrogen into the refractory metal silicide.
7. The process of claim 6, wherein the nitrogen is ion implanted at
about 10 to about 50 keV and at a dose of about 1.times.10.sup.15
to about 2.times.10.sup.15 atoms/cm.sup.2.
8. The process of claim 1, further comprising the step of
performing an anneal subsequent to forming the second amorphous
silicon or polysilicon region.
9. The process of claim 8, wherein the anneal is performed at a
temperature of about 580 to about 650.degree. C., for about 1 to
about 5 hours.
10. The process of claim 1, wherein the first amorphous silicon or
polysilicon region is amorphous silicon and has a thickness of
about 300 to about 1000 .ANG..
11. The process of claim 1, wherein the second amorphous silicon or
polysilicon region is amorphous silicon and has a thickness of
about 200 to about 1000 .ANG..
12. The process of claim 2, wherein the n-type dopant is selected
from arsenic and phosphorus.
13. The process of claim 2, wherein the p-type dopant is boron.
14. The process of claim 5, wherein the refractory metal silicide
is selected from tungsten silicide, tantalum silicide, and cobalt
silicide.
15. The process of claim 12, wherein the n-type dopant is arsenic
and the arsenic is implanted by ion implantation at about 2 to
about 30 keV.
16. The process of claim 15, wherein the implantation is performed
at a dosage of about 1.5.times.10.sup.15 to about 5.times.10.sup.15
atoms/cm.sup.2.
17. The process of claim 12, wherein the n-type dopant is
phosphorus and the phosphorus is implanted by ion implantation at
about 1 to about 20 keV.
18. The process of claim 17, wherein the implantation is performed
at a dosage of about 3.times.10.sup.15 to about 8.times.10.sup.15
atoms/cm.sup.2.
19. The process of claim 13, wherein the boron is implanted by ion
implantation at about 0.25 to about 5 keV.
20. The process of claim 19, wherein the implantation is performed
at a dosage of about 1.5.times.10.sup.15 to about 4.times.10.sup.15
atoms/cm.sup.2.
21. The process of claim 19, wherein the implantation is performed
for a time of about 5 minutes or less.
22. The process of claim 1, further comprising a step of,
subsequent to forming the second amorphous silicon or polysilicon
region, performing a rapid thermal anneal at a temperature of about
900 to about 1050.degree. C. for a time of about 2 to about 10
seconds.
Description
[0001] This application claims priority of Provisional Application
Ser. No. ______, entitled Process for Device Fabrication, filed
Jul. 14, 1997.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention relates to fabrication of integrated
circuits.
[0004] 2. Discussion of the Related Art
[0005] A variety of applications utilize CMOS (Complimentary Metal
Oxide Semiconductor) integrated circuits. Many CMOS integrated
circuits contain a dual-gate structure, illustrated in part by FIG.
7. Typically, formation of a dual-gate structure begins by forming
a gate dielectric region 108 over a silicon substrate 100 having an
n-doped region 102 and a p-doped region 104. (A dielectric material
is an electrically insulating material, i.e., a material having a
resistivity of about 10.sup.6 ohm-cm or greater.) A field
dielectric 106 is also formed to isolate the oppositely-doped
regions of the device. A polysilicon region 110 is typically
deposited over the gate dielectric 108 and field dielectric 106.
The portion of the polysilicon 110 overlying the n-doped region 102
is provided with a p-type dopant such as boron or BF.sub.2, and the
portion of the polysilicon 110 overlying the p-doped region 104 is
provided with an n-type dopant such as phosphorus or arsenic. Such
dual-gate CMOS configurations typically contain a refractory metal
silicide layer 112 (or other metal layer) over the doped
polysilicon, the refractory metal silicide acting to lower
resistance in the gate structure and thereby improve device and
circuit performance.
[0006] However, n-type and p-type dopants tend to diffuse more
readily in refractory metal silicides than in polysilicon. Dopants
thus tend to diffuse, for example, from a region of the polysilicon
110 overlying doped silicon region 102 into the silicide layer 112,
laterally in the silicide layer 112, and then back into the
polysilicon 110 at a region overlying the oppositely-doped region
104. Thus, n-type dopants move into a p-doped polysilicon region
and vice versa. The phenomenon is referred to herein as
cross-doping. Diffusion of these cross-dopants into the area of the
polysilicon adjacent to the underlying gate dielectric causes
undesirable shifts in threshold voltage, an important parameter in
CMOS design and operation. Moreover, the problem of cross-doping is
becoming more severe as the industry moves toward smaller CMOS
devices, e.g., moving towards 0.25 .mu.m length devices, and even
more significantly toward 0.18 .mu.m and lower. The smaller the
devices, the larger the effect of cross-dopants on properties such
as threshold voltage, and the closer the devices, the less distance
the dopants have to laterally travel to interfere with adjacent
devices.
[0007] Problems are also created by the distribution of dopants in
the implanted regions of the polysilicon 110. Advantageously, the
implanted dopants in the final device are located near the
underlying gate dielectric 108. Typically, however, the majority of
dopants lie close to the top of the polysilicon 110, and an anneal
is used to diffuse the dopants toward the gate dielectric 108.
However, the anneal time and temperature required to diffuse the
dopants across this distance will often undesirably allow diffusion
of some of the dopants laterally within the polysilicon 110 into an
oppositely-doped region of the polysilicon 110, causing
cross-doping. This lateral diffusion within the polysilicon 110 is
a problem regardless of whether a silicide layer is present. This
mechanism of cross-doping is particularly problematic where half
the distance between the active regions of adjacent devices becomes
comparable to the thickness of the doped regions of the polysilicon
110. In addition, the use of thinner gate dielectric layers
improves device performance, but only where a relatively large
concentration of dopants, advantageously about 10.sup.20
dopants/cm.sup.3 or greater, is located adjacent to the gate
dielectric (resulting in what is known in the art as low
poly-depletion). If sufficient dopants are not located adjacent to
the dielectric layer, the use of a thinner gate dielectric will at
best only marginally improve device performance.
[0008] It is also possible for dopant distribution to cause
problems when forming a refractory metal silicide by a salicide
process. In a typical salicide process, a refractory metal is
deposited after formation of a polysilicon gate structure, a source
and drain, and silicon dioxide spacers. The device is heated to
react the metal with the silicon, thereby forming a refractory
metal silicide. Due to a low level of bonding between the
refractory metal and the silicon dioxide spacers, the silicide
typically does not form on the spacers, leading to what is
conventionally known as self-alignment of the silicide structure.
Growth of the silicide layer in such a salicide process is
detrimentally affected if too many dopants, or dopant-based
precipitates, are located in the top region of the polysilicon gate
structure, where the silicide is formed. In addition, because the
polysilicon region is typically thicker when using a salicide
process, the dopant diffusion distance to the gate dielectric is
often increased, thereby allowing encroachment of the underlying
channel region that often leads to shorts in the device.
[0009] For these reasons, a process that places dopants deep within
the polysilicon layer is desired. Such a deep implant is difficult
to attain, however. Typically, as mentioned above, the majority of
dopants will lie close to the top surface of the polysilicon
regions. It is difficult to implant dopants deeper in the
polysilicon without encountering undesirable effects. For example,
it is possible for dopants, particularly boron, to penetrate the
polysilicon during ion implantation and move into the underlying
silicon substrate, or to move along certain crystallographic
orientations of polysilicon--a phenomenon known as channeling.
(Both mechanisms are referred to herein generally as penetration.)
The presence of the boron in the channel region of the silicon
substrate detrimentally affects the threshold voltage. Thus,
implantation is performed at energies low enough to reduce
penetration. Yet, where lower implantation energies are used, the
concentration profile will often not be deep enough to avoid the
problems discussed above.
[0010] Thus, improved processes which address problems created by
cross-doping and by certain dopant concentration profiles,
particularly in smaller, dual-gate CMOS devices, are desired.
SUMMARY OF THE INVENTION
[0011] The process of the invention addresses problems of
cross-doping, and of undesirable dopant concentration profiles,
found in current CMOS fabrication processes, and is also applicable
to smaller devices. In an embodiment of the invention, devices are
prepared by forming a first, relatively thin (e.g., about 300-1000
.ANG.) amorphous silicon region over a gate dielectric material
region formed over n-type and p-type regions of a silicon
substrate. It is also possible to use polysilicon. (The term
amorphous indicates a lack of long-range order.)
[0012] An n-type dopant is implanted at a first portion of the
first amorphous silicon region, typically over the p-type region of
the substrate. The n-type dopant is advantageously implanted such
that substantially all of the dopant remains in the first amorphous
silicon region and does not penetrate into the underlying
dielectric region or the substrate. "Substantially all" indicates
that no more than about 0.001% of the implanted dopant penetrates
into the underlying dielectric layer or substrate during
implantation. This result is attained, for example, by use of a low
energy ion implantation method, e.g., implanting arsenic at 2-30
keV or phosphorus at 1-20 keV. A p-type dopant species is then
implanted at a second portion of the first amorphous silicon
region, typically over the n-type region of the substrate. Again,
it is advantageous for substantially all of the p-type dopant
species to remain in the first amorphous silicon region. It is
possible for this result to be similarly attained by use of low
energy ion implantation, e.g., implanting boron at 0.25-5 keV.
[0013] Once the desired dopants are implanted into the first
silicon region, a second amorphous silicon (or polysilicon) region
is formed over the first silicon region, in essence burying the
implanted dopants. Typically, a refractory metal silicide layer is
formed over the second amorphous silicon region. Devices are then
formed on the structure in accordance with conventional processing
techniques known to one skilled in the art. The creation of the
buried implant layer is significant in that the buried nature of
the dopants hinders cross-doping that occurs through the silicide.
For example, in order for such detrimental cross-doping to occur,
the dopant must diffuse from the p-doped region of the first
amorphous silicon region into and through the second amorphous
silicon region into the metal silicide layer, diffuse laterally
within the silicide layer to the area over the oppositely-doped
amorphous silicon region, diffuse back through the second amorphous
silicon region into the opposite-doped region of the first
amorphous silicon region, and move through the first amorphous
silicon region to an area along the underlying gate dielectric.
[0014] In addition, because the dopants are implanted in a
relatively thin layer formed on the gate dielectric, the diffusion
distance to the gate dielectric is relatively low. Thus, dopants
are able to diffuse to the area adjacent to the gate dielectric
without substantial lateral diffusion in the silicon or substantial
reduction in the channel. Similarly, the process of the invention
provides for a relatively high concentration of dopants at and near
the gate dielectric, thereby allowing advantageous use of a thin
gate dielectric. Furthermore, due to the buried nature of the
dopants, there is typically little interference by dopants with a
salicide process.
[0015] Advantageously, the process of the invention also includes a
subsequent rapid thermal anneal in which the wafer is heated to
about 900 to about 1050.degree. C. for a time of about 2 to about
10 seconds. (Rapid thermal anneal indicates a process that uses a
heat source such as high-powered quartz filaments, which provide a
fast increase in temperature, e.g., 100-200.degree. C./sec, and in
which the measured temperature is that of the silicon wafer.) The
rapid thermal anneal is useful in attaining a desirable
distribution of dopants in the doped regions of the device and in
helping to activate the dopants. (The term activate indicates that
the dopants become electrically active by moving to the proper
sites in the silicon lattice (substituting for silicon atoms as
opposed to being located interstitially within the silicon
lattice).) The short time of the rapid thermal anneal is desirable,
particularly for short length devices, because lateral diffusion in
both the gate and the channel region, as well as dopant diffusion
through the gate dielectric, is reduced.
[0016] Thus, the process of the invention, due to the buried nature
of the dopants, provides a relatively simple way of reducing
detrimental cross-doping, as well as providing a desirable dopant
distribution.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] FIGS. 1(a) to 1(d) reflect process steps in an embodiment of
the invention.
[0018] FIGS. 2-4 show dopant distribution profiles for arsenic,
boron, and phosphorus, respectively, implanted in an amorphous
silicon region in accordance with an embodiment of the process of
the invention.
[0019] FIGS. 5 and 6 show dopant distribution profiles for arsenic,
and boron and nitrogen, respectively, implanted in an amorphous
silicon region in accordance with an embodiment of the process of
the invention, where numerous processing steps were performed
subsequent to dopant implantation.
[0020] FIG. 7 illustrates a prior art process for forming a
dual-gate structure.
DETAILED DESCRIPTION OF THE INVENTION
[0021] The invention relates to a process for fabricating devices,
particularly dual-gate CMOS devices. General principles and
standard procedures for device fabrication are found, for example,
in Van Zant, "Microchip Fabrication," 3d Ed., McGraw-Hill, 1997. It
is expected that future processing technology will allow, for
example, use of thinner layers and lower implantation energies in
the process of the invention, and the concept of the invention is
applicable to such future improvements.
[0022] The process of the invention is illustrated by the
embodiment shown in FIGS. 1(a) through 1(d). Devices are fabricated
by obtaining or forming a semiconductor substrate 10 having an
n-type region 12 and a p-type region 14, as shown in FIG. 1(a). It
is possible for these regions to be formed in accordance with
standard processing techniques well known to one skilled in the
art, such as the twin tub process described in U.S. Pat. No.
4,435,596to Parillo et al., the disclosure of which is hereby
incorporated by reference. A field dielectric 16 is formed on the
substrate to separate the n-type region 12 and the p-type region
14, in accordance with standard processing techniques. Field
dielectric 16 constitutes, for example, a surface isolation (e.g.,
LOCOS--localized oxidation of silicon) or a trench isolation (e.g.,
STI--shallow trench isolation). Typically, the field dielectric 16
is LOCOS isolation and has a thickness of about 2000 to about 3000
.ANG..
[0023] A gate dielectric region 18, typically silicon dioxide, is
then formed over the portions of the n-type region 12 and p-type
region 14 not covered by the field dielectric 16. The gate
dielectric 18 is formed in accordance with standard processing
techniques and, when formed from silicon dioxide, is advantageously
about 15 to about 100 .ANG. thick. It is possible to consider the
combination of the field dielectric 16 and gate dielectric 18 as
constituting a dielectric material region. As also shown in FIG.
1(a), a first region of amorphous silicon 20 is then formed on the
field dielectric 16 and gate dielectric 18. It is also possible to
use polysilicon. Amorphous silicon is advantageous in that it
substantially reduces channeling and therefore allows use of
thinner layers. Advantageously, the amorphous region 20 has a
thickness of about 300 to about 1000 .ANG.. The region 20 is formed
in accordance with standard processing techniques known to one
skilled in the art, e.g., chemical vapor deposition, as discussed,
for example in Van Zant, supra, Chapter 12.
[0024] As shown in FIG. 1(b), a mask 30 is then formed over the
first amorphous silicon region 20, using standard lithographic
techniques known to one skilled in the art. The mask 30 selectively
exposes portions of the region 20 that overlay the p-type region 14
of the substrate 10. An n-type dopant 32 is implanted into the
exposed portions of the region 20. Suitable n-type dopants include
arsenic and phosphorus. The implantation is advantageously
performed by ion implantation at an energy that reduces
penetration. Advantageous implant energies for arsenic range from
about 2to about 30 keV, and for phosphorus from about 1 to about 20
keV. Useful dopant implant doses for arsenic range from about
1.5.times.10.sup.15 to about 5.times.10.sup.15 dopants/cm.sup.2,
and for phosphorus from about 3.times.10.sup.15 to about
8.times.10.sup.15 dopants/cm.sup.2. At these energies and doses,
implantation is typically performed for a time of a few seconds to
a few minutes (e.g., 5 minutes).
[0025] The mask 30 is then removed. Again using standard
lithographic techniques, a second mask 40, as shown in FIG. 1(c),
is formed over the first amorphous silicon region 20. The mask 40
selectively exposes portions of the region 20 that overlay the
n-type region 12 of the substrate 10. A p-type dopant 42 is
implanted into the exposed portions of the region 20. Suitable
p-type dopants include boron. The implantation of the p-type dopant
is also advantageously performed by ion implantation at an implant
energy that reduces penetration. Advantageously, the implantation
of boron is performed at about 0.25 to about 5 keV, and at dopant
implant doses of about 1.5.times.10.sup.15 to about
4.times.10.sup.15 dopants/cm.sup.2. At these energies and doses,
implantation is typically performed for a time of a few seconds to
a few minutes (e.g., 5 minutes). Boron typically requires more time
for implantation than n-type dopants.
[0026] The energy and dopant dose selected for both n-type and
p-type dopants depend in part on the thickness of the amorphous
silicon region 20. In general, it is possible to use higher implant
energies and doses with thicker layers without resulting in
unwanted penetration.
[0027] The mask 40 is then removed, and, as shown in FIG. 1(d), a
second amorphous silicon region 50 is formed over the now-implanted
first amorphous silicon region 20. It is also possible to use
polysilicon. Amorphous silicon is advantageous because diffusion of
dopants is generally slower in recrystallized amorphous silicon
than in deposited polysilicon. Advantageously, the second amorphous
region 50 has a thickness of about 200 to about 1000 .ANG.. The
second region 50 is formed in accordance with standard processing
techniques known to one skilled in the art, e.g., chemical vapor
deposition.
[0028] A refractory metal silicide layer 52 is optionally formed on
the second amorphous silicon region 50 by standard processing
techniques known to one skilled in the art, e.g., sputtering or
chemical vapor deposition. Examples of suitable refractory metal
silicides include tungsten silicide, tantalum silicide, and cobalt
silicide. Advantageously, the refractory metal silicide layer 52
has a thickness of about 800 to about 2000 .ANG.. It is also
advantageous for the process of the invention to include a step of
introducing nitrogen into the refractory metal silicide layer.
Where the nitrogen is ion implanted, the implantation
advantageously is performed at an energy of about 10-50 keV
(depending on the thickness), more advantageously 30 keV, and at a
dopant implant dose of about 1.times.10.sup.15 to about
2.times.10.sup.15 atoms/cm.sup.2. The nitrogen appears to trap
boron atoms in the silicide layer, and thus assists in reducing
lateral diffusion and cross-doping of boron.
[0029] It is also possible to form a silicide layer by a salicide
process. Metal layers other than refractory metal silicides are
also possible.
[0030] Advantageously, an anneal is performed after formation of
the second amorphous silicon region 50 to recrystallize the second
amorphous silicon region 50 and first amorphous silicon region 20,
i.e., transform the regions 50, 20 into polysilicon. It is possible
for the anneal to be performed after formation of the second
silicon region 50, after formation of the silicide layer 52, or
after a nitrogen implant of the silicide layer 52. The anneal is
advantageously performed at a temperature of about 580 to about
650.degree. C., for about 1 to about 5 hours, in a nitrogen
atmosphere. More advantageously, the anneal is performed at about
650.degree. C. for about 3 hours in a nitrogen atmosphere.
[0031] The resulting structure is then subjected to processing
steps to form gate stacks over the n-regions and p-regions of the
substrate, in accordance with standard procedures known to one
skilled in the art. Advantageously, such steps include a rapid
thermal anneal after formation of gate stacks. The rapid thermal
anneal is advantageously performed such that the wafer is raised to
a temperature of about 900 to about 1050.degree. C. for a time of
about 2 to about 10 seconds. More advantageously, the wafer is
raised to a temperature of 1000.degree. C. for 5 seconds. The rapid
thermal anneal is useful in attaining a desirable distribution of
dopants in the doped regions of the device and in helping to
activate the dopants.
[0032] Typical processing steps subsequent to formation and
implantation of refractory silicide layer 52 would include the
following:
[0033] Deposit of a gate hard mask. The mask is formed, for
example, from silicon oxide deposited by plasma-enhanced deposition
of tetraethyl orthosilicate (PETEOS), a nitride layer formed by
plasma-enhanced chemical vapor deposition (PECVD), or a spin-on
glass (SOG) layer;
[0034] Formation of a gate photoresist to allow selective etching
of the gate hard mask, etching of the hard mask, and removal of the
photoresist;
[0035] Etching of refractory silicide layer 52 and first and second
silicon regions 20, 50;
[0036] Formation of a photoresist to allow implantation of a
low-doped drain region (LDD), implanting of the LDD, and removal of
the photoresist;
[0037] Deposit of a dielectric, e.g., silicon oxide by PETEOS, for
gate spacer formation, anneal of the dielectric, and etch of the
spacers;
[0038] Formation of a photoresist to allow implantation of n-type
source and drain, implanting the n-type source and drain, and
removal of the photoresist;
[0039] Formation of a photoresist to allow implantation of p-type
source and drain, implanting the p-type source and drain, and
removal of the photoresist.
[0040] The rapid thermal anneal is advantageously performed
subsequent to implantation of the p-type source and drain. Where a
salicide process is used, the process is typically performed
subsequent to formation of the n-type and p-type source and drain,
and the rapid thermal anneal is typically performed prior to
depositing the refractory metal on the polysilicon gate
structure.
[0041] The invention will be further clarified by the following
examples, which are intended to be exemplary.
EXAMPLE 1
[0042] A silicon wafer was processed using conventional expedients,
well known to one skilled in the art, to form a silicon substrate
having lightly doped n-type and p-type regions. A 2000 .ANG. thick
LOCOS field dielectric region was grown on a selected portion of
the substrate by dry/wet/dry oxidation to electrically isolate the
n-type and p-type regions. A 60 .ANG. gate dielectric layer of
silicon oxynitride was formed on the portions of the substrate not
covered by the LOCOS region by thermal oxidation in N.sub.2O at
850.degree. C. A 500 .ANG. thick layer of amorphous silicon was
formed over the field and gate dielectric layers by low pressure
chemical vapor deposition. A layer of photoresist, in accordance
with standard practice, was formed on the silicon and structured to
expose portions of the silicon overlying the lightly doped p-type
region of the substrate. The exposed portions were then implanted
with arsenic at 8 keV and a dosage of 2.5.times.10.sup.15
atoms/cm.sup.2. The photoresist was removed, and a second
photoresist layer was formed to expose portions of the silicon
region overlying the lightly doped n-type region of the substrate.
The exposed portions were then implanted with boron at 2 keV and a
dosage of 2.times.10.sup.15 atoms/cm.sup.2. The implant profile of
arsenic, measured by SIMS (secondary ion mass spectroscopy), is
shown in FIG. 2, and the SIMS implant profile of boron is shown in
FIG. 3.
[0043] (The implant profile of phosphorus in place of arsenic in an
identical embodiment, implanted at 5 keV and a dosage of
4.times.10.sup.15 atoms/cm.sup.2, is shown in FIG. 4.)
EXAMPLE 2
[0044] A silicon wafer was processed according to the steps of
Example 1, using dopants of arsenic and boron. After implantation,
a second amorphous silicon region having a thickness of 500 .ANG.
was formed by low pressure chemical vapor deposition. An anneal was
then performed at 650.degree. C. for 3 hours in nitrogen atmosphere
to crystallize the amorphous silicon. After the anneal, a 1000
.ANG. tungsten silicide layer was formed on the second amorphous
silicon region by sputtering, and nitrogen was implanted into the
silicide at 30 keV and a dosage of 1.times.10.sup.15
atoms/cm.sup.2. In accordance with the standard processing steps
discussed above, gate stacks were formed. Specifically, a 1500
.ANG. silicon dioxide hard mask was formed on the silicide layer by
PETEOS; the hard mask was etched; the silicide and silicon regions
were etched; a low-doped drain region of arsenic was implanted; a
silicon dioxide layer was formed for gate spacers and the spacers
were etched; an anneal was performed at 750.degree. C. for 30
minutes in oxygen to densify the silicon dioxide spacers; n-type
drain and source were implanted; and p-type drain and source were
implanted. Then, a rapid thermal anneal of the wafer was performed,
the wafer being heated at 1000.degree. C. for 5 seconds by
high-powered quartz filaments. FIGS. 5 and 6 show the subsequent
SIMS profiles for the arsenic and boron dopants. FIG. 6 also shows
the nitrogen profile.
[0045] In FIG. 5, the implant peak for arsenic is visible in the
middle of the polysilicon region made up of both the first and
second amorphous silicon regions (which were transformed to
polysilicon during the 650.degree. C. anneal). Due to the
relatively short diffusion distance from the implant peak to the
polysilicon/gate oxide interface, the arsenic concentration at the
interface is desirably high (about
2.times.10.sup.20atoms/cm.sup.3). The arsenic concentration
decreases toward the tungsten silicide (WSi.sub.x) layer, in which
the concentration is about one order of magnitude less than at the
polysilicon/gate oxide interface. This lesser number of atoms in
the silicide is desirable in that lateral diffusion and associated
cross-doping by arsenic atoms will be reduced.
[0046] FIG. 6 shows a similar result. The boron concentration is
desirably high at the polysilicon/gate oxide interface, and
decreases toward the silicide layer. The boron concentration within
the tungsten silicide layer also appears to be relatively high. The
boron profile strongly corresponds to the nitrogen profile,
however, indicating that the nitrogen atoms trapped the boron atoms
in the silicide, thereby reducing lateral diffusion and
cross-doping by boron atoms.
[0047] The quantification of the dopant concentrations in FIGS. 5
and 6 are not accurate in the SiO.sub.2 layers.
[0048] Other embodiments of the invention will be apparent to those
skilled in the art from consideration of the specification and
practice of the invention disclosed herein.
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