U.S. patent application number 09/935474 was filed with the patent office on 2001-12-27 for semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (dram) circuitry.
Invention is credited to Lowrey, Tyler A., Pan, Pai-Hung, Tran, Luan C..
Application Number | 20010055860 09/935474 |
Document ID | / |
Family ID | 23528192 |
Filed Date | 2001-12-27 |
United States Patent
Application |
20010055860 |
Kind Code |
A1 |
Pan, Pai-Hung ; et
al. |
December 27, 2001 |
Semiconductor processing methods of forming contact openings,
methods of forming memory circuitry, methods of forming electrical
connections, and methods of forming dynamic random access memory
(DRAM) circuitry
Abstract
Methods of forming contact openings, memory circuitry, and
dynamic random access memory (DRAM) circuitry are described. In one
implementation, an array of word lines and bit lines are formed
over a substrate surface and separated by an intervening insulative
layer. Conductive portions of the bit lines are outwardly exposed
and a layer of material is formed over the substrate and the
exposed conductive portions of the bit lines. Selected portions of
the layer of material are removed along with portions of the
intervening layer sufficient to (a) expose selected areas of the
substrate surface and to (b) re-expose conductive portions of the
bit lines. Conductive material is subsequently formed to
electrically connect exposed substrate areas with associated
conductive portions of individual bit lines.
Inventors: |
Pan, Pai-Hung; (Boise,
ID) ; Tran, Luan C.; (Meridian, ID) ; Lowrey,
Tyler A.; (Sandpoint, ID) |
Correspondence
Address: |
WELLS ST JOHN ROBERTS GREGORY AND MATKIN
SUITE 1300
601 W FIRST AVENUE
SPOKANE
WA
992013828
|
Family ID: |
23528192 |
Appl. No.: |
09/935474 |
Filed: |
August 21, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09935474 |
Aug 21, 2001 |
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09848863 |
May 3, 2001 |
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09848863 |
May 3, 2001 |
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09765236 |
Jan 16, 2001 |
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09765236 |
Jan 16, 2001 |
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09387040 |
Aug 31, 1999 |
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Current U.S.
Class: |
438/520 ;
257/E21.295; 257/E21.507; 257/E21.59; 257/E21.649; 257/E21.657;
257/E21.658 |
Current CPC
Class: |
H01L 21/76897 20130101;
H01L 27/10888 20130101; H01L 21/76895 20130101; H01L 27/10855
20130101; H01L 21/32051 20130101; H01L 27/10885 20130101 |
Class at
Publication: |
438/520 |
International
Class: |
H01L 021/265 |
Claims
1. A semiconductor processing method of forming a contact opening
comprising: partially forming a first contact opening over a first
insulative material over a node location with which electrical
communication is desired; at least partially filling the contact
opening with a second insulative material; and etching a second
contact opening through the second insulative material and the
first insulative material.
2. The semiconductor processing method of claim 1, wherein the
etching outwardly exposes the substrate node location.
3. The semiconductor processing method of claim 1, wherein the
etching comprises selectively etching the second contact opening
relative to a different insulative material disposed within the
confines of the second contact opening.
4. The semiconductor processing method of claim 1, wherein the
first and second insulative materials are different.
5. The semiconductor processing method of claim 1, wherein the
etching comprises selectively etching the second contact opening
relative to a different insulative material which is disposed over
a conductive component within the second contact opening, the
second contact opening being self-aligned relative to the
conductive component.
6. A semiconductor processing method of forming memory circuitry
comprising: forming an array of word lines and bit lines over a
substrate surface and having a intervening insulative layer
therebetween; outwardly exposing conductive portions of the bit
lines; after the outwardly exposing, forming a layer of material
over the substrate and exposed conductive portions of the bit
lines; removing selected portions of the layer of material and the
intervening layer sufficient to (a) expose selected areas of the
substrate surface at least some of which defining bit line contact
areas with which electrical communication is desired, and (b)
re-expose said conductive portions of the bit lines; and after said
removing, forming conductive material to electrically connect
individual bit line contact areas and associated conductive
portions of individual bit lines.
7. The semiconductor processing method of claim 6, wherein the
outwardly exposing of the conductive portions of the bit lines
comprises masking over portions of the bit lines and etching
unmasked portions of the bit lines selectively relative to the
intervening insulative layer.
8. The semiconductor processing method of claim 6, wherein the
forming of the array of word lines and bit lines comprises: forming
a series of word lines over the substrate surface; forming an
insulative oxide layer over the word lines; planarizing the
insulative oxide layer, said insulative oxide layer defining said
intervening layer; and forming a series of bit lines over the
intervening insulative oxide layer.
9. The semiconductor processing method of claim 6, wherein: the
forming of the array of word lines and bit lines comprises: forming
a series of word lines over the substrate surface; forming an
insulative oxide layer over the word lines; planarizing the
insulative oxide layer, said insulative oxide layer defining said
intervening layer; and forming a series of bit lines over the
intervening insulative oxide layer; and the outwardly exposing
comprises: masking the bit lines with a masking layer having a
plurality of openings therein; etching bit line material through
the openings sufficiently to expose said conductive portions.
10. The semiconductor processing method of claim 6, wherein: the
forming of the array of word lines and bit lines comprises: forming
a series of word lines over the substrate surface; forming an
insulative oxide layer over the word lines; planarizing the
insulative oxide layer, said insulative oxide layer defining said
intervening layer; and forming a series of bit lines over the
intervening insulative oxide layer; the outwardly exposing
comprises: masking the bit lines with a masking layer having a
plurality of openings therein; and etching bit line material
through the openings sufficiently to expose said conductive
portions; and the forming of the layer of material over the
substrate comprises: forming a second insulative oxide layer over
the substrate; and planarizing said second insulative oxide
layer.
11. The semiconductor processing method of claim 6, wherein the
forming of the layer of material over the substrate comprises
forming an insulative oxide layer over the substrate and
planarizing said insulative oxide layer.
12. The semiconductor processing method of claim 6, wherein the
removing of the selected-portions of the layer of material and the
intervening layer comprises: masking over the individual word
lines; and etching the layer of material and the intervening layer
selective to word line material.
13. The semiconductor processing method of claim 6, wherein the
intervening layer separating the word lines and bit lines and the
layer of material which is formed over the substrate comprise
borophosphosilicate glass.
14. The semiconductor processing method of claim 6, wherein the
forming of the conductive material comprises: depositing
polysilicon over the bit line contact areas and the associated
conductive portion of the individual bit lines; and removing
polysilicon sufficient to isolate individual polysilicon plugs over
the bit line contact areas.
15. The semiconductor processing method of claim 6, wherein other
of the selected areas, which are exposed by the removing of the
selected portions of the layer of material, define capacitor
contact areas with which electrical communication with individual
capacitors is desired.
16. The semiconductor processing method of claim 15, wherein
forming of the conductive material to electrically connect
individual bit line contact areas and associated conductive
portions of individual bit lines also comprises forming said
conductive material over and in electrical communication with the
capacitor contact areas.
17. The semiconductor processing method of claim 16 further
comprising: forming insulative material over the conductive
material electrically connecting the individual bit line contact
areas and the associated conductive portions of the individual bit
lines; and forming a plurality of capacitors over the substrate,
individual capacitors being in electrical communication with
respective individual capacitor contact areas through the
conductive material formed thereover.
18. In a matrix of conductive lines formed over a substrate
comprising first and second- series of conductive lines, one series
being formed over another, an electrical connection method of
establishing electrical communication between at least some of the
lines and substrate node locations comprising: forming a masking
layer over the substrate defining a plurality of openings over an
uppermost of the series of lines; removing material of individual
lines of the uppermost series of lines and exposing conductive
material of the individual lines; after the removing of the
material of the individual lines, forming insulative material over
the substrate and the exposed conductive material; masking over the
substrate and defining mask openings over substrate node locations
with which electrical communication is desired; removing insulative
material through the mask openings and other substrate material
sufficient to expose both the conductive material of the individual
lines which was previously exposed and the substrate node locations
with which electrical communication is desired; and forming a
plurality of conductive interconnects over the substrate, the
interconnects establishing electrical communication between second
exposed conductive material of the individual lines and individual
respective substrate node locations.
19. The electrical connection method of claim 18, wherein: the
removing of the insulative material and the other substrate
material exposes other substrate node locations with which
electrical communication is desired, the other substrate node
locations being different from those substrate node locations which
are in electrical communication with the second exposed conductive
material through individual interconnects; and the forming of a
plurality of conductive interconnects also comprises forming
conductive material over the other substrate node locations.
20. The electrical connection method of claim 19 further
comprising: forming insulative material over the individual
interconnects; and after the forming of the insulative material,
forming a plurality of capacitors over the substrate and in
electrical communication with the conductive material formed over
the other substrate node locations.
21. The electrical connection method of claim 18, wherein the
matrix comprises a portion of a memory array and the first and
second series of conductive lines respectively comprise word lines
and bit lines of the memory array.
22. The electrical connection method of claim 21, wherein the
memory array comprises a DRAM array.
23. A semiconductor processing method of forming DRAM circuitry
comprising: forming an array of word lines and bit lines over a
substrate, the bit lines being formed over the word lines and atop
a first generally planarized insulative layer portions of which are
disposed between the word lines and bit lines; forming a masking
layer over the substrate having openings therein which expose
portions of the bit lines; selectively etching bit line material
through the openings relative to the insulative layer sufficient to
expose conductive portions of the bit lines; forming a second
insulative layer over the substrate and the exposed conductive
portions of the bit lines; etching a plurality of contact openings
through the first and second insulative layers sufficient to expose
underlying substrate areas and to reexpose the conductive portions
of the bit lines within some of the contact openings, the contact
openings defining bit line contact openings and capacitor contact
openings; and depositing conductive material within the contact
openings and in electrical communication with the exposed substrate
areas, some of said material establishing electrical communication
between the re-exposed conductive portions of the bit lines and
respective associated exposed substrate areas.
24. The semiconductor processing method of claim 23, wherein
etching of the bit line material comprises etching material from
both the top and sides of individual bit lines sufficient to expose
the conductive material.
25. The semiconductor processing method of claim 23, wherein
etching of the bit line material comprises conducting an angled
etch sufficient to expose conductive portions of the bit lines
along individual sidewalls thereof.
26. The semiconductor processing method of claim 23 further
comprising: forming insulative material over conductive material
within the bit line contact openings; and forming capacitors over
and in electrical communication with conductive material within the
capacitor contact openings.
27. A semiconductor processing method of forming a DRAM array
comprising: forming a plurality of conductive lines over a
substrate, at least some of which comprising word lines; forming a
first insulative layer over the substrate and word lines; forming a
plurality of bit lines over the first insulative layer, the word
lines and bit lines defining an array having substrate contact
areas with which electrical communication is desired, the substrate
contact areas comprising both bit line contact areas and capacitor
contact areas; exposing conductive portions of the bit lines;
forming a second insulative layer over the substrate and exposed
conductive portions of the bit lines; exposing bit line contact
areas, capacitor contact areas, and previously-exposed bit line
conductive portions through at least one of the first and second
insulative layers; forming conductive material over and in
respective electrical communication with exposed bit line contact
areas and capacitor contact areas, conductive material over the bit
line contact areas establishing electrical communication with the
previously-exposed bit line conductive portions; masking over the
conductive material formed over the bit line contact areas; and
forming a plurality of storage capacitors over the substrate,
individual capacitors being in electrical communication with
individual respective capacitor contact areas through the
respective conductive material formed thereover.
28. The semiconductor processing method of claim 27, wherein the
exposing of the conductive portions of the bit lines comprises
selectively etching material of the bit lines relative to the first
insulative material.
29. The semiconductor processing method of claim 27, wherein the
exposing of the conductive portions of the bit lines comprises not
exposing any word line material.
30. The semiconductor processing method of claim 27, wherein the
exposing of the conductive portions of the bit lines comprises
conducting an angled etch sufficient to expose sidewall material of
the bit lines.
31. The semiconductor processing method of claim 27, wherein the
exposing of the conductive portions of the bit lines comprises
etching bit line material from the top and sides of the individual
bit lines.
32. The semiconductor processing method of claim 27, wherein the
exposing of the conductive portions of the bit lines comprises
selectively etching bit line material from the top and sides of the
individual bit lines relative to the first insulative material.
33. The semiconductor processing method of claim 27 further
comprising planarizing the second insulative layer prior to
exposing the bit line contact areas, capacitor contact areas, and
bit line conductive portions.
34. The semiconductor processing method of claim 27, wherein the
exposing of the bit line contact areas, capacitor contact areas,
and bit line conductive portions comprises etching both the first
and second insulative layers selectively relative to both bit line
and word line material.
Description
TECHNICAL FIELD
[0001] This invention relates to semiconductor processing methods
of forming contact openings, methods of forming memory circuitry,
methods of forming electrical connections, and methods of forming
dynamic random access memory (DRAM) circuitry.
BACKGROUND OF THE INVENTION
[0002] Semiconductor processing typically involves a number of
processing steps including material deposition, masking with
masking layers, and etching to define integrated circuitry
structures. At each processing step there are risks that the
integrated circuitry being formed can be compromised. As the
complexity of integrated circuitry increases, so too can the
processing complexities and the risk that the formed circuitry will
be compromised. One of the factors that contributes to the risk of
compromised integrated circuitry is the number of masking steps
that are used in a particular processing flow. The more masking
steps, the more the likelihood is that a misalignment can occur.
Another problem which has implications insofar as device integrity
is concerned relates to conductive material undesirably remaining
behind over wafer areas. Such remnant material is sometimes
referred to as "stringers" and can cause device components to short
to one another. Accordingly, there is a need within the industry to
reduce the likelihood that these and other problems will affect the
integrated circuitry being formed.
[0003] This invention arose out of concerns associated with
improving the methods by which integrated circuitry is formed and
reducing the risks that the formed circuitry will be
compromised.
SUMMARY OF THE INVENTION
[0004] Methods of forming contact openings, memory circuitry, and
dynamic random access memory (DRAM) circuitry are described. In one
implementation, an array of word lines and bit lines are formed
over a substrate surface and separated by an intervening insulative
layer. Conductive portions of the bit lines are outwardly exposed
and a layer of material is formed over the substrate and the
exposed conductive portions of the bit lines. Selected portions of
the layer of material are removed along with portions of the
intervening layer sufficient to (a) expose selected areas of the
substrate surface and to (b) re-expose conductive portions of the
bit lines. Conductive material is subsequently formed to
electrically connect exposed substrate areas with associated
conductive portions of individual bit lines.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings.
[0006] FIG. 1 is a diagrammatic sectional view of a wafer fragment
in process, and an exemplary conductive line formed thereover.
[0007] FIG. 2 is a diagrammatic sectional view of a plurality of
conductive lines.
[0008] FIG. 3 is a view of the FIG. 2 conductive lines at a
different processing step.
[0009] FIG. 4 is a view of the FIG. 3 conductive lines at a
different processing step.
[0010] FIG. 5 is a top plan view of a semiconductor wafer
fragment.
[0011] FIG. 6 is a view of the FIG. 5 wafer fragment at a different
processing step.
[0012] FIG. 7 is a view of the FIG. 6 wafer fragment at a different
processing step.
[0013] FIG. 8 is a diagrammatic sectional view of the FIG. 7 wafer
fragment taken along line 8-8 in FIG. 7.
[0014] FIG. 9 is a diagrammatic side sectional view which is taken
along line 9-9 in FIG. 7.
[0015] FIG. 10 is a view of the FIG. 7 wafer fragment at a
different processing step.
[0016] FIG. 11 is a view of the FIG. 9 wafer fragment at a
different processing step.
[0017] FIG. 12 is a view of the FIG. 11 wafer fragment at a
different processing step.
[0018] FIG. 13 is a view of the FIG. 10 wafer fragment at a
different processing step.
[0019] FIG. 14 is a view of the FIG. 12 wafer fragment at a
different processing step.
[0020] FIG. 15 is a view of the FIG. 14 wafer fragment at a
different processing step.
[0021] FIG. 16 is a view of the FIG. 15 wafer fragment at a
different processing step.
[0022] FIG. 17 is a view of the FIG. 13 wafer fragment at a
different processing step.
[0023] FIG. 18 is a view which is taken along line 18-18 in FIG. 17
and illustrates a portion of conductive material which supports
capacitor structure.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0024] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0025] Referring to FIG. 1, a semiconductor wafer fragment is
indicated generally at 20 and comprises a semiconductive substrate
22. In the context of this document, the term "semiconductive
substrate" is defined to mean any construction comprising
semiconductive material, including, but not limited to, bulk
semiconductive materials such as a semiconductive wafer (either
alone or in assemblies comprising other materials thereon), and
semiconductive material layers (either alone or in assemblies
comprising other materials). The term "substrate" refers to any
supporting structure, including, but not limited to, the
semiconductive substrates described above.
[0026] An exemplary conductive line or gate is shown generally at
100. The illustrated conductive line and the description of the
formation of the various NMOS FETs and PMOS FETs which follow
constitute but one way of forming specific conductive lines.
Accordingly, other conductive lines and methods of forming the same
can be utilized in the context of the invention. Various aspects of
the invention are described in the context of memory circuitry, and
in particular, dynamic random access memory (DRAM) circuitry. Such
circuitry is typically formed over a wafer and can be categorized
as including array circuitry (i.e. circuitry formed within a memory
array) and peripheral circuitry (i.e. circuitry formed outside the
memory array and operably coupled therewith). Conductive lines,
such as line 100, can be formed to constitute both array circuitry
and peripheral circuitry. An exemplary conductive line construction
can comprise a conventional gate stack, e.g., a gate oxide layer
102, a polysilicon layer 104, and a tungsten silicide layer 106. A
dielectric cap 108 can be provided over the conductive material and
can be formed from suitable materials such as oxides, nitrides, and
the like. Following a patterning and etching step in which the
conductive lines are formed, a lightly doped drain (LDD) diffusion
step can take place to form lightly doped drain regions (not
specifically shown). Subsequently, a layer 110 comprising an oxide
material formed through decomposition of tetraethylorthosilicate
(TEOS) can be deposited to a thickness of around 600 Angstroms.
[0027] Referring to FIG. 2, three illustrative conductive lines are
shown generally at 112, 114, and 116. Line 112 comprises an NMOS
FET, line 114 comprises a PMOS FET, and line 116 comprises a
conductive line which is formed within the memory array. An
exemplary processing technique for forming NMOS FETs includes
forming photoresist over the substrate and exposing conductive
lines which are to constitute the gates of NMOS FETs. Accordingly
lines 114 and 116 would be covered with photoresist. Layer 110 is
subsequently etched to form sidewall spacers 118, 120. Source/drain
implants are then formed (not shown), i.e. by implanting arsenic or
boron. Subsequently, the resist is stripped, followed by formation
of an oxide layer 122 from decomposition of TEOS to a thickness of
around 100-200 Angstroms. Such layer can be formed over all of the
lines.
[0028] Referring to FIG. 3, PMOS FETs can be formed by depositing a
layer 124 of polysilicon (or nitride) to a thickness of around 500
Angstroms, forming photoresist (not shown) over conductive lines
112 and 116, and etching layers 124, 122, and 110 over line 114 to
form sidewall spacers 126, 128. Source/drain regions can be formed
through implantation of BF.sub.2 followed by an angled implantation
of phosphorous. Subsequently, the photoresist can be stripped.
[0029] Referring to FIG. 4, material of layers 124 and 122 can be
subsequently removed from over lines 112, 116, followed by
deposition of a layer 130 comprising oxide formed through
decomposition of TEOS, to a thickness of about 300 Angstroms. The
above description constitutes but one method for forming spacers
associated with the conductive lines.
[0030] The discussion now proceeds with reference to FIG. 5 wherein
substrate 22 is shown prior to formation of the above described
conductive lines. A plurality of isolation regions 24 are provided
and between which are defined a plurality of active areas 26.
Isolation regions 24 can be formed through known shallow trench
isolation (STI) or other techniques.
[0031] Referring to FIG. 6, a plurality of conductive lines 28 are
formed over substrate 22 and preferably comprise a series of word
lines for a memory array, such as a dynamic random access memory
(DRAM) array. The illustrated conductive lines 28 can correspond to
conductive line 116 described above, in connection with FIGS.
1-4.
[0032] Referring to FIGS. 7 and 8, a first insulative oxide layer
30 (FIG. 8) is formed over substrate 22 and word lines 28. An
exemplary and preferred material for layer 30 comprises
borophosphosilicate glass which can be deposited to a thickness of
between about 10,000 to 14,000 Angstroms. Layer 30 can be
subsequently reflowed and chemical mechanical polished to planarize
the layer. The planarization of layer 30 preferably terminates over
conductive lines 28.
[0033] A plurality of bit lines 32 are formed over planarized first
insulative layer 30. Exemplary bit lines 32 can comprise a layer of
polysilicon or a conductive barrier layer 34, a silicide or
refractive metal (e.g., W) layer 36, and a dielectric cap 38 formed
from suitable dielectric materials (including WN.sub.x, TiN.sub.x,
etc.) such as oxides, nitrides, and/or both. Such layers are
subsequently patterned into the individual bit lines shown in FIG.
7. Sidewall spacers are preferably provided over the bit lines and
can comprise an oxide formed through decomposition of TEOS, or a
suitable nitride deposited through low-pressure chemical vapor
deposition.
[0034] Collectively, bit lines 32 and word lines 28 comprise a
matrix (FIG. 7) which is formed over the substrate. In a preferred
embodiment, the matrix defines a memory array comprising a dynamic
random access memory (DRAM) array. Insulative oxide layer 30 (FIG.
8) defines an intervening layer which separates the word lines and
bit lines. For purposes of the ongoing discussion, word lines 28
define a first series of conductive lines, and bit lines 32 define
a second series of conductive lines which are disposed over the
first series of conductive lines. Within the array are defined a
plurality of substrate contact areas, i.e. source/drain diffusion
regions, with which electrical communication is desired. In a
preferred embodiment, substrate contact areas 33a (FIG. 7) comprise
bit line contact areas and substrate areas 33b comprise capacitor
contact areas.
[0035] Referring to FIGS. 9 and 10, a masking layer 40 is formed
over substrate 22 and patterned to define a plurality of openings
42 over, and expose portions of bit lines 32, which in this
example, constitute the uppermost conductive lines of the first and
second series of conductive lines. The openings also define an area
over the bit line contact areas 33a.
[0036] Referring to FIG. 11, unmasked insulative material of the
individual bit lines is removed to expose underlying conductive
material 36, 34. The insulative material is preferably etched,
selectively, relative to intervening insulative oxide layer 30.
Such constitutes exemplary partially forming of a first contact
opening which exposes conductive material of the individual bit
lines over insulative layer 30. The removing of the bit line
material can remove some of material 30. In one aspect, an angled
etch can be conducted to expose only sidewall portions of the
individual bit lines. In a preferred aspect, an anti-reflective
coating layer (not shown) can be deposited and over which the
illustrated masking layer 40 is formed. A reactive ion etch (RIE)
can be conducted which is highly selective to the underlying
insulative oxide layer 30. Such etch exposes the illustrated top
portion of bit lines 32, as well as sidewall portions thereof which
includes conductive material of both layers 34, 36. After the
exposing of the conductive portions of the bit lines, the
photoresist is stripped away.
[0037] Referring to FIG. 12, a layer of material 44 is formed over
substrate 22 and the exposed conductive portions of the individual
bit lines. Such material at least partially fills the contact
opening formed through the removal of the insulative portions of
the bit lines mentioned above. Preferably, layer 44 is a second
insulative oxide layer comprising borophosphosilicate glass. Layer
44 can be formed to a thickness of 8,000 to 10,000 Angstroms, and
thereafter reflowed and planarized, as by chemical mechanical
polishing which terminates on or over individual bit lines 32.
[0038] Referring to FIG. 13, a patterned masking layer 46 is formed
over substrate 22 and defines a plurality of openings 48 over the
substrate node locations with which electrical communication is
desired. In the illustrated example, such substrate node locations
include both the bit line contact areas 33a and the capacitor
contact areas 33b.
[0039] Referring to FIGS. 14 and 15, material from over substrate
22 is removed through masked openings 48 sufficiently to form
second contact openings which expose both the conductive material
of the individual bit lines which was previously exposed, and the
individual substrate node locations with which electrical
communication with the bit lines is desired. The removal of such
material also exposes node locations 33b (FIG. 13) over which
capacitors are to be formed. The first and second insulative oxide
layers 30 and 44 can be selectively etched relative to material
from which the bit lines and word lines are formed. Such etch forms
contact openings which are self-aligned relative to both the word
lines and the bit lines and defines bit line contact openings and
capacitor contact openings. Exemplary etch chemistries can include
gases such as CF.sub.4, CHF.sub.3, CH.sub.2F.sub.2, Ar, and
O.sub.2. Reactor power can be provided at around 700 Watts, with
pressures around 30 mTorr. Other exemplary processing can take
place as described in U.S. Pat. No. 5,286,344, which is
incorporated by reference herein.
[0040] Referring to FIG. 15, conductive material 50 is formed over
the substrate and within the bit line contact openings and the
capacitor contact openings. Accordingly, material 50 establishes
electrical communication or electrically connects individual bit
line contact areas 33a with their associated individual bit lines.
Such conductive material also provides material over the capacitor
contact areas which will ultimately form conductive plugs
therewithin. An exemplary and preferred material is polysilicon
which can be deposited and subsequently isolated within the
individual openings as by reactive ion etch or other suitable
isolation techniques. Such constitutes forming a plurality of
conductive interconnects which establish electrical communication
between the bit lines and the substrate node locations.
[0041] Referring to FIG. 16, insulative material 52 is formed over
substrate 22 and conductive material 50. In the illustrated
example, insulative material 52 comprises a first layer 54 and a
second layer 56. Materials can be selected for layers 54, 56 which
are selectively etchable relative to one another. As an example,
layer 54 can comprise an oxide formed through decomposition of TEOS
deposited to a thickness of 400 Angstroms, and layer 56 can
comprise a nitride layer formed to a thickness of 500 Angstroms.
Alternatively, layer 54 can comprise a nitride layer formed to a
thickness of 400 Angstroms, and layer 56 can comprise an oxide
layer formed through decomposition of TEOS to a thickness of 800
Angstroms.
[0042] Referring to FIGS. 16 and 17, a patterned masking layer 58
is formed over the substrate and preferably the conductive material
which is formed over the individual bit line contact areas 33a.
[0043] Referring to FIGS. 17 and 18, insulative material 52 is
removed from over capacitor contact areas 33b. Capacitors are
formed over and in electrical communication with conductive
material 50 which is formed within the capacitor contact openings
and in electrical communication with node locations 33b (FIG. 17).
For illustrative purposes only, the capacitors include a storage
node layer 60, a dielectric layer 62, and a cell plate layer 64.
Various known techniques and materials can be utilized in forming
the capacitors. In some embodiments, the storage node layer 60 is
formed from polysilicon presenting a roughened surface, such as
hemispherical grain polysilicon, as represented by the shading in
FIG. 18, in order to provide increased capacitance.
[0044] The above described method has advantages in that
polysilicon stringers (which can cause shorting) are reduced, if
not eliminated. Additionally, less masks are needed which reduces
processing complexity. The method also provides for self-aligned
contact openings to be etched at the same time, with the openings
being self-aligned to both the word lines and the bit lines.
[0045] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the doctrine of equivalents.
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