U.S. patent application number 09/886993 was filed with the patent office on 2001-12-27 for solid state imager.
Invention is credited to Miyagawa, Ryohei.
Application Number | 20010054713 09/886993 |
Document ID | / |
Family ID | 18690638 |
Filed Date | 2001-12-27 |
United States Patent
Application |
20010054713 |
Kind Code |
A1 |
Miyagawa, Ryohei |
December 27, 2001 |
Solid state imager
Abstract
A device region surrounded by a device isolation region has a
rectangular shape with a width in a direction in which a gate
electrode of a transfer gate extends. A signal accumulation region
of a photodiode is disposed on the entirety of that portion of the
device region, which is located on a source side of the gate
electrode of the transfer gate. A detection section having a width
in the direction in which the gate electrode extends is disposed on
that portion of the device region, which is located on a drain side
of the gate electrode of the transfer gate. The size of the
detection section is set to be as small as possible. Two edge
portions of the detection section, which are located in the
direction of extension of the gate electrode, are spaced apart from
the device isolation region.
Inventors: |
Miyagawa, Ryohei;
(Sagamihara-shi, JP) |
Correspondence
Address: |
OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT PC
FOURTH FLOOR
1755 JEFFERSON DAVIS HIGHWAY
ARLINGTON
VA
22202
US
|
Family ID: |
18690638 |
Appl. No.: |
09/886993 |
Filed: |
June 25, 2001 |
Current U.S.
Class: |
257/72 ; 257/258;
257/291; 257/292; 257/E27.132 |
Current CPC
Class: |
H01L 27/14609 20130101;
H01L 27/1463 20130101 |
Class at
Publication: |
257/72 ; 257/258;
257/291; 257/292 |
International
Class: |
H01L 029/04; H01L
031/036; H01L 029/80; H01L 031/112 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 26, 2000 |
JP |
2000-191321 |
Claims
What is claimed is:
1. A solid state imager comprising: a semiconductor substrate of a
first conductivity type; a device isolation region provided on the
semiconductor substrate; a photoelectric conversion element
disposed within a device region surrounded by the device isolation
region; and a transfer gate, provided within the device region, for
transferring a charge produced by the photoelectric conversion
element to a detection section, wherein said detection section is
an impurity region of a second conductivity type disposed within
the device region, and at least a portion of edge portions of the
detection section, which exclude an edge portion adjoining a
channel region of the transfer gate, is spaced apart from the
device isolation region.
2. The solid state imager according to claim 1, wherein the
transfer gate is a MOS transistor having a gate electrode extending
in one direction, and a channel width of the transfer gate is equal
to a width of the device region in said one direction.
3. The solid state imager according to claim 1, wherein the
transfer gate is a MOS transistor having a gate electrode extending
in one direction, and a width of the detection section in said one
direction is less than a width of the device region in said one
direction.
4. The solid state imager according to claim 1, wherein the
transfer gate is a MOS transistor having a gate electrode extending
in one direction, and a channel width of the transfer gate is
greater than a width of the detection section in said one
direction.
5. The solid state imager according to claim 1, wherein the
transfer gate is a MOS transistor having a gate electrode extending
in one direction, said photoelectric conversion element is disposed
on a source side of the gate electrode, and said detection section
is disposed on a drain side of the gate electrode.
6. The solid state imager according to claim 1, wherein the
transfer gate is a MOS transistor having a gate electrode extending
in one direction, said detection section is disposed at a central
portion of the channel region, and all edge portions of the
detection section are spaced apart from the device isolation
region.
7. The solid state imager according to claim 1, wherein the
transfer gate is a MOS transistor having a gate electrode extending
in one direction, said detection section is disposed at a central
portion of the channel region, and the edge portions of the
detection section in said one direction are spaced apart from the
device isolation region.
8. The solid state imager according to claim 1, wherein the
transfer gate is a MOS transistor having a gate electrode extending
in one direction, said detection section is disposed at an end
portion of the channel region, and a portion of the edge portions
of the detection section in said one direction is spaced apart from
the device isolation region.
9. The solid state imager according to claim 1, wherein the
transfer gate is a MOS transistor having a gate electrode extending
in one direction, said detection section is disposed to extend from
a central portion of the channel region to an end portion of the
channel region, and a portion of the edge portions of the detection
section in said one direction is spaced apart from the device
isolation region.
10. The solid state imager according to claim 1, wherein said
detection section is shared by said photoelectric conversion
element and another photoelectric conversion element.
11. The solid state imager according to claim 1, wherein said
photoelectric conversion element comprises the semiconductor
substrate and a signal accumulation region of the second
conductivity type formed in the semiconductor substrate.
12. The solid state imager according to claim 11, further
comprising a surface shield layer of the first conductivity type
disposed on the signal accumulation region.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2000-191321, filed Jun. 26, 2000, the entire contents of which are
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a device structure of a
pixel section of a solid state imager.
[0004] 2. Description of the Related Art
[0005] FIG. 1 shows a circuit structure of a pixel section of a
sense type solid state imager.
[0006] A pixel comprises a photodiode 21 for converting an optical
signal to an electric signal (charge); a transfer gate (MOS
transistor) 22 for transferring a charge of the photodiode 21 to a
detection section (detection node) D; a reset gate (MOS transistor)
23 for resetting the charge (potential) in the detection section D;
a sense gate (MOS transistor) 24 for amplifying the potential of
the detection section D; and a select gate (MOS transistor) 25 for
outputting a potential of a selected pixel.
[0007] A charge photoelectrically converted by the photodiode 21
and accumulated in a signal accumulation region over a
predetermined time period is transferred to the detection section D
via the transfer gate 22. The charge transferred to the detection
section D from the photodiode 21 varies the potential of the
detection section D. The sense gate 24 amplifies the variation
amount of the potential of the detection section D.
[0008] FIG. 2 is a plan view showing a prior-art device layout of a
photodiode and a transfer gate. FIG. 3 is a cross-sectional view
taken along line III-III in FIG. 2, and FIG. 4 is a cross-sectional
view taken along line IV-IV in FIG. 2.
[0009] A device isolation region 12 is provided on a p-type
semiconductor substrate (or p-type well region) 11. In this
example, the device isolation region 12 is formed of a field oxide
film by LOCOS (Local Oxidation of Silicon). Alternatively, the
device isolation region 12 may be formed of an oxide film having,
for example, an STI (Shallow Trench Isolation) structure.
[0010] A photodiode and a transfer gate are disposed in a device
region surrounded by the device isolation region 12.
[0011] In this example, the photodiode comprises the p-type
semiconductor substrate 11 and an n-type signal accumulation region
(impurity diffusion layer) 13 formed in the semiconductor substrate
11. The transfer gate comprises the n-type signal accumulation
region 13 and an n.sup.+detection section (detection node) 14, both
formed in the p-type semiconductor substrate 11, and a gate
electrode 15 formed on a channel region between the signal
accumulation region 13 and detection section 14.
[0012] The n-type signal accumulation region 13 functions as a
cathode of the photodiode and also as a source of the transfer
gate. The impurity density in the n-type signal accumulation region
13 is set at a lowest possible level in order to transfer all the
charge accumulated by photoelectric conversion in the signal
accumulation region 13 to the detection section 14. The detection
section 14 is connected to an amplifier circuit 17 (e.g. sense gate
24 in FIG. 1).
[0013] In the above-described sense type solid state imager, the
less the parasitic capacitance in the detection section 14, the
greater the signal potential that is obtained in the detection
section 14 relative to a predetermined charge amount accumulated in
the signal accumulation region 13. In other words, the less the
parasitic capacitance in the detection section 14, the greater the
photosensitivity of the image sensor.
[0014] It is thus desirable that the detection section 14 be
designed with a smallest possible size in order to decrease the
parasitic capacitance and to enhance the photosensitivity of the
image sensor. On the other hand, it is important that the signal
accumulation region 13 be designed with a greatest possible size in
order to receive as much as possible light and to generate as much
as possible charge by photoelectric conversion.
[0015] For these reasons, as shown in FIG. 2, the signal
accumulation region 13 of the pixel section of the prior-art solid
state imager has a large size, while the detection section 14 has a
small size.
[0016] As is shown in FIG. 2, in the prior-art solid state imager,
the size of the signal accumulation region 13 is increased as much
as possible, and the size of the detection section 14 is decreased
as much as possible.
[0017] The device region is surrounded by the device isolation
region 12, and the position and size of the device region are
determined by the device isolation region 12. In addition, in this
example, the positions and sizes of the signal accumulation region
13 and detection section 14 are also determined by the device
isolation region 12. In short, the edge portions (except portions
adjoining the channel region) of the signal accumulation region 13
and detection section 14 coincide with the edge portions of the
device isolation region 12.
[0018] However, the device region is formed of a semiconductor
(e.g. silicon) whereas the device isolation region 12 is formed of
an insulator (e.g. silicon oxide). The material of the device
region and that of the device isolation region 12 are different
and, as a matter of course, have different thermal expansion
coefficients.
[0019] Consequently, when heat is applied in a step of forming the
device isolation region 12 or in other steps, thermal stress may
occur and crystal defects may be caused in the semiconductor layer
(device region) near the device isolation region 12. The crystal
defects may lead to a leak current. Such a leak current varies the
potential of, in particular, the detection section 14. Thus, a
pseudo signal is produced by the leak current, and the stable
operation of the solid state imager cannot be ensured.
[0020] It is well known that in the photodiode as shown in FIGS.
2-4, a problem arises due to so-called KTC noise (K: Boltzmann's
constant; T: absolute temperature; C: capacitance of photodiode).
In order to prevent the KTC noise, a p.sup.+surface shield layer
may advantageously be formed on the n-type signal accumulation
region 13 so that the photodiode may have a buried structure.
[0021] Adopting the buried-type photodiode structure, the n-type
signal accumulation region 13 with a low impurity density can be
completely depleted and all the charge in the signal accumulation
region 13 can be completely transferred to the detection section
14. In brief, this structure is advantageous in inactivating a
surface defective level of the signal accumulation region 13,
suppressing a leak current and reducing KTC noise.
[0022] The depletion potential of the buried-type photodiode is
determined by a two-dimensional effect. Thus, the peripheral
portion of the signal accumulation region 13 has a lower depletion
potential than the central portion thereof. Accordingly, as the
size of the photodiode (the size of the signal accumulation region
13) decreases, the depletion potential for depleting the entirety
of the signal accumulation region 13 becomes lower and all the
charge may advantageously be transferred.
[0023] However, as mentioned above, the size of the signal
accumulation region 13 cannot be decreased in order to receive as
much as possible light and to generate as much as possible charge
by photoelectric conversion.
[0024] The same trade-off problem arises with the channel width of
the transfer gate (read gate). As is shown in FIG. 2, the channel
width W2 (equal to the dimension in one direction of the detection
section 14) of the transfer gate is normally set to be less than
the size W1 (i.e. the width in one direction) of the signal
accumulation region 13. The reason is that it is advantageous, as
mentioned above, to minimize the size of the detection section 14
and to maximize the size of the signal accumulation region 13,
thereby to receive as much as possible light and to enhance the
photosensitivity of the image sensor as high as possible.
[0025] If the channel width W2 of the transfer gate is decreased,
however, the width of the charge transfer path from the signal
accumulation region 13 to the detection section 14 narrows. As a
result, the read-out of the charge becomes difficult, and the
charge cannot completely be transferred.
[0026] This problem can be overcome if the channel width W2 of the
transfer gate is increased. In this case, however, the size of the
detection section 14 will inevitably be increased. In short, if the
channel width W2 of the transfer gate is increased in order to
completely transfer the charge, the size of the detection section
14 increases and the photosensitivity of the image sensor
deteriorates.
[0027] As has been described above, the first problem in the
prior-art solid state imager is as follows. Since all the edge
portions of the detection section, except the edge portion on the
channel region side, are in contact with the device isolation
region, crystal defects which may occur in the peripheral portion
of the device isolation region will cause a leak current in the
detection section. As a result, a pseudo signal may be
produced.
[0028] The second problem is as follows. In the prior-art solid
state imager, the size of the signal accumulation region of the
photodiode is maximized and the size of the detection section is
minimized in order to convert as much as possible light to charge
and to enhance the photosensitivity. In this case, however, the
channel width of the transfer gate is decreased and this is
disadvantageous for complete transfer of charge. Moreover, if the
channel width of the transfer gate is increased, the size of the
detection section increases and the photosensitivity decreases.
BRIEF SUMMARY OF THE INVENTION
[0029] An object of the present invention is to suppress a leak
current at a detection section due to crystal defects in a
peripheral portion of a device isolation region, and another object
of the invention is to increase a channel width without involving
an increase in size of a detection section, thereby achieving
complete transfer of charge and enhancement of photosensitivity at
the same time.
[0030] The present invention provides a solid state imager
comprising: a device isolation region provided on a semiconductor
substrate of a first conductivity type; a photoelectric conversion
element disposed within a device region surrounded by the device
isolation region; and a transfer gate, provided within the device
region, for transferring a charge produced by the photoelectric
conversion element to a detection section. The detection section is
an impurity region of a second conductivity type disposed within
the device region, and at least a portion of edge portions of the
detection section, which exclude an edge portion adjoining a
channel region of the transfer gate, is spaced apart from the
device isolation region.
[0031] Additional objects and advantages of the invention will be
set forth in the description which follows, and in part will be
obvious from the description, or may be learned by practice of the
invention. The objects and advantages of the invention may be
realized and obtained by means of the instrumentalities and
combinations particularly pointed out hereinafter.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0032] The accompanying drawings, which are incorporated in and
constitute a part of the specification, illustrate presently
embodiments of the invention, and together with the general
description given above and the detailed description of the
embodiments given below, serve to explain the principles of the
invention.
[0033] FIG. 1 is a circuit diagram showing a pixel of a
conventional solid state imager;
[0034] FIG. 2 is a plan view of a conventional solid state
imager;
[0035] FIG. 3 is a cross-sectional view taken along line III-III in
FIG. 2;
[0036] FIG. 4 is a cross-sectional view taken along line IV-IV in
FIG. 2;
[0037] FIG. 5 is a plan view showing a first embodiment of a solid
state imager according to the present invention;
[0038] FIG. 6 is a cross-sectional view taken along line VI-VI in
FIG. 5;
[0039] FIG. 7 is a cross-sectional view taken along line VII-VII in
FIG. 5;
[0040] FIG. 8 is a plan view showing a second embodiment of the
solid state imager according to the present invention;
[0041] FIG. 9 is a cross-sectional view taken along line IX-IX in
FIG. 8;
[0042] FIG. 10 is a cross-sectional view taken along line X-X in
FIG. 8;
[0043] FIG. 11 is a plan view showing a third embodiment of the
solid state imager according to the present invention;
[0044] FIG. 12 is a cross-sectional view taken along line XII-XII
in FIG. 11;
[0045] FIG. 13 is a cross-sectional view taken along line XIII-XIII
in FIG. 11;
[0046] FIG. 14 is a plan view showing a modification of the third
embodiment of the solid state imager according to the present
invention;
[0047] FIG. 15 is a cross-sectional view taken along line XV-XV in
FIG. 14;
[0048] FIG. 16 is a cross-sectional view taken along line XVI-XVI
in FIG. 14;
[0049] FIG. 17 is a cross-sectional view showing a device structure
of a buried-type photodiode;
[0050] FIG. 18 is a plan view showing a fourth embodiment of the
solid state imager according to the present invention;
[0051] FIG. 19 is a cross-sectional view taken along line XIX-XIX
in FIG. 18;
[0052] FIG. 20 is a cross-sectional view taken along line XX-XX in
FIG. 18; and
[0053] FIG. 21 is a circuit diagram showing an equivalent circuit
of the device shown in FIG. 18.
DETAILED DESCRIPTION OF THE INVENTION
[0054] A solid state imager of the present invention will be
described below in detail with reference to the accompanying
drawings.
[0055] First Embodiment
[0056] FIG. 5 shows a first embodiment of a solid state imager
according to the present invention. FIG. 6 is a cross-sectional
view taken along line VI-VI in FIG. 5, and FIG. 7 is a
cross-sectional view taken along line VII-VII in FIG. 5.
[0057] A device isolation region 12 is provided on a p-type
semiconductor substrate (or p-type well region) 11. In this
example, the device isolation region 12 is formed of a field oxide
film by LOCOS (Local Oxidation of Silicon). Alternatively, the
device isolation region 12 may be formed of an oxide film having,
for example, an STI (Shallow Trench Isolation) structure.
[0058] A photodiode and a transfer gate are disposed in a device
region surrounded by the device isolation region 12.
[0059] In this example, the photodiode comprises the p-type
semiconductor substrate 11 and an n-type signal accumulation region
(impurity diffusion layer) 13 formed in the semiconductor substrate
11. Alternatively, as shown in FIG. 17, a p.sup.+surface shield
layer 18 may be formed on the n-type signal accumulation region 13,
thereby constituting a buried-type photodiode. The transfer gate
comprises the n-type signal accumulation region 13 and an
n.sup.+detection section (detection node) 14, both formed in the
p-type semiconductor substrate 11, and a gate electrode 15 formed
on a channel region between the signal accumulation region 13 and
detection section 14.
[0060] The n-type signal accumulation region 13 functions as a
cathode of the photodiode and also as a source of the transfer
gate. The impurity density in the n-type signal accumulation region
13 is set at a lowest possible level in order to lower a depletion
potential and to transfer all the charge accumulated by
photoelectric conversion in the signal accumulation region 13 to
the detection section 14. The detection section 14 is connected to
an amplifier circuit 17 (e.g. sense gate 24 in FIG. 1).
[0061] A first feature of the device structure in this embodiment
is that two edge portions Li and L2 of the detection section 14,
which are located in a direction (corresponding to "one direction")
in which the gate electrode 15 of the transfer gate (MOS
transistor) extends, are spaced apart from the device isolation
region 12 (i.e. the edge portions Li and L2 are not in contact with
the device isolation region 12).
[0062] In this embodiment, the device region surrounded by the
device isolation region 12 has the same width Wi on both sides
(source side and drain side) of the gate electrode 15 of the select
gate. On the source side of the gate electrode 15, as in the prior
art, the signal accumulation region 13 of the photodiode is
disposed. On the other hand, the detection section 14 having a
smaller width W3 than the width Wi of the device region is disposed
on the drain side of the gate electrode 15. As a result, the edge
portions of the detection section 14, which are located in the
direction of extension of the gate electrode 15, are spaced apart
from the device isolation region 12.
[0063] Compared to the prior-art device, the device of this
embodiment is characterized in that at least one of the edge
portions of the detection section 14 which exclude the edge portion
adjoining the channel region (or a portion of edge portions of the
detection section 14 in a case where the detection section 14 is
not rectangular) is spaced apart from the device isolation region
12.
[0064] With this structure, the detection section 14 is free from
the effect of crystal defects occurring at the peripheral portion
of the device isolation region 12, and a leak current occurring at
the detection section can be suppressed. Accordingly, a pseudo
signal can be prevented and the stable operation of the solid state
imager is ensured.
[0065] In the present embodiment, the two edge portions L1 and L2
of the detection section 14, which are located in the direction in
which the gate electrode 15 extends, are spaced apart from the
device isolation region 12. In the present invention, however, it
should suffice if at least one of the edge portions of the
detection section 14 excluding the edge portion adjoining the
channel region (or at least a portion of edge portions of the
detection section 14 in a case where the detection section 14 is
not rectangular) is spaced apart from the device isolation region
12.
[0066] A second feature of the device structure in this embodiment
is that the channel width W2 of the transfer gate is greater than
the dimension (i.e. a width in one direction) W3 of the detection
section 14. For example, the channel width W2 of the transfer gate
is set to be equal to the dimension (i.e. a width in one direction)
W1 of the signal accumulation region 13 of the photodiode.
[0067] Specifically, in the prior-art device (see FIG. 2), since
the channel width W2 of the transfer gate is set to be equal to the
dimension of the detection section 14, the channel width W2 and the
dimension of the detection section 14 depend on each other and a
trade-off problem occurs between the charge transfer and the
photosensitivity. By contrast, according to the device of the
present embodiment, the channel width W2 can be freely set
irrespective of the dimension W3 of the detection section 14, and
such a trade-off problem is solved.
[0068] Therefore, according to the device structure of this
embodiment, the channel width W2 of the transfer gate can be set,
at maximum, at a value equal to the dimension W1 of the signal
accumulation region 13 of the photodiode, and all charge can be
transferred from the signal accumulation region 13 to the detection
section 14. Moreover, even if this structure is adopted, the
dimension W3 of the detection section 14 can be set to a minimum
and thus the photosensitivity of the image sensor cannot be
lowered.
[0069] Second Embodiment
[0070] A second embodiment of the present invention is a
modification of the device structure of the first embodiment. The
second embodiment is characterized in that all edge portions L1,
L2, L3 and L4 of the detection section 14 are spaced apart from the
device isolation region 12.
[0071] The device structure according to the second embodiment will
now be described in detail.
[0072] FIG. 8 shows the second embodiment of the solid state imager
according to the present invention. FIG. 9 is a cross-sectional
view taken along line IX-IX in FIG. 8, and FIG. 10 is a
cross-sectional view taken along line X-X in FIG. 8.
[0073] A device isolation region 12 is provided on a p-type
semiconductor substrate (or p-type well region) 11. In this
example, the device isolation region 12 is formed of a field oxide
film by LOCOS. Alternatively, the device isolation region 12 may be
formed of an oxide film having, for example, an STI structure.
[0074] A photodiode and a transfer gate are disposed in a device
region surrounded by the device isolation region 12.
[0075] The photodiode comprises the p-type semiconductor substrate
11 and an n-type signal accumulation region (impurity diffusion
layer) 13 formed in the semiconductor substrate 11. Alternatively,
as shown in FIG. 17, a p.sup.+surface shield layer 18 may be formed
on the n-type signal accumulation region 13, thereby constituting a
buried-type photodiode. The transfer gate comprises the n-type
signal accumulation region 13 and an n.sup.+detection section
(detection node) 14, both formed in the p-type semiconductor
substrate 11, and a gate electrode 15 formed on a channel region
between the signal accumulation region 13 and detection section
14.
[0076] The n-type signal accumulation region 13 functions as a
cathode of the photodiode and also as a source of the transfer
gate. The impurity density in the n-type signal accumulation region
13 is set at a lowest possible level in order to lower a depletion
potential and to transfer all the charge accumulated by
photoelectric conversion in the signal accumulation region 13 to
the detection section 14. The detection section 14 is connected to
an amplifier circuit 17 (e.g. sense gate 24 in FIG. 1).
[0077] A first feature of the device structure in this embodiment
is that all edge portions L1, L2, L3 and L4 of the detection
section 14 are spaced apart from the device isolation region 12
(i.e. the edge portions are not in contact with the device
isolation region 12).
[0078] Specifically, in this embodiment, the device region
surrounded by the device isolation region 12 has the same width W1
on both sides (source side and drain side) of the gate electrode 15
of the select gate. On the source side of the gate electrode 15, as
in the prior art, the signal accumulation region 13 of the
photodiode is disposed. On the other hand, the detection section 14
having a smaller width W3 than the width W1 of the device region is
disposed on the drain side of the gate electrode 15. In addition, a
width of as the detection section 14 in a direction (i.e. "the
other direction") perpendicular to a direction (i.e. "one
direction") in which the gate electrode 15 extends is less than a
dimension in the other direction between the edge portion of the
gate electrode 15 and the edge portion of the device isolation
region 12.
[0079] As a result, all the edge portions of the detection section
14 are spaced apart from the device isolation region 12.
[0080] With this structure, the detection section 14 is free from
the effect of crystal defects occurring at the peripheral portion
of the device isolation region 12, and a leak current occurring at
the detection section can be suppressed. Accordingly, a pseudo
signal can be prevented and the stable operation of the solid state
imager is ensured.
[0081] A second feature of the device structure in this embodiment
is that the channel width W2 of the transfer gate is greater than
the dimension (i.e. a width in "one direction") W3 of the detection
section 14. For example, the channel width W2 of the transfer gate
is set to be equal to the dimension (i.e. a width in "one
direction") W1 of the signal accumulation region 13 of the
photodiode.
[0082] Specifically, in the prior-art device (see FIG. 2), since
the channel width W2 of the transfer gate is set to be equal to the
dimension of the detection section 14, the channel width W2 and the
dimension of the detection section 14 depend on each other and a
trade-off problem occurs between the charge transfer and the
photosensitivity. By contrast, according to the device of the
present embodiment, the channel width W2 can be freely set
irrespective of the dimension W3 of the detection section 14, and
such a trade-off problem is solved.
[0083] Therefore, according to the device structure of this
embodiment, the channel width W2 of the transfer gate can be set,
at maximum, at a value equal to the dimension W1 of the signal
accumulation region 13 of the photodiode, and all charge can be
transferred from the signal accumulation region 13 to the detection
section 14. Moreover, even if this structure is adopted, the
dimension W3 of the detection section 14 can be set to a minimum
and thus the photosensitivity of the image sensor cannot be
lowered.
[0084] Third Embodiment
[0085] A third embodiment of the present invention is a
modification of the device structure of the first embodiment. The
third embodiment is characterized in that the detection section 14
is disposed at a corner of the rectangular device region, and at
least one of the edge portions of the detection section 14, which
exclude the edge portion adjoining the channel region, is spaced
apart from the device isolation region 12. Specifically, the edge
portion L1 of the two edge portions located in the direction of
extension of the gate electrode 15 is separated from the device
isolation region 12.
[0086] The device structure according to the present embodiment
will now be described in detail.
[0087] FIG. 11 shows the third embodiment of the solid state imager
according to the present invention. FIG. 12 is a cross-sectional
view taken along line XII-XII in FIG. 11, and FIG. 13 is a
cross-sectional view taken along line XIII-XIII in FIG. 11.
[0088] A device isolation region 12 is provided on a p-type
semiconductor substrate (or p-type well region) 11. In this
example, the device isolation region 12 is formed of a field oxide
film by LOCOS. Alternatively, the device isolation region 12 may be
formed of an oxide film having, for example, an STI structure.
[0089] A photodiode and a transfer gate are disposed in a device
region surrounded by the device isolation region 12.
[0090] The photodiode comprises the p-type semiconductor substrate
11 and an n-type signal accumulation region (impurity diffusion
layer) 13 formed in the semiconductor substrate 11. Alternatively,
as shown in FIG. 17, a p.sup.+surface shield layer 18 may be formed
on the n-type signal accumulation region 13, thereby constituting a
buried-type photodiode. The transfer gate comprises the n-type
signal accumulation region 13 and an n.sup.+detection section
(detection node) 14, both formed in the p-type semiconductor
substrate 11, and a gate electrode 15 formed on a channel region
between the signal accumulation region 13 and detection section
14.
[0091] The n-type signal accumulation region 13 functions as a
cathode of the photodiode and also as a source of the transfer
gate. The impurity density in the n-type signal accumulation region
13 is set at a lowest possible level in order to lower a depletion
potential and to transfer all the charge accumulated by
photoelectric conversion in the signal accumulation region 13 to
the detection section 14. The detection section 14 is connected to
an amplifier circuit 17 (e.g. sense gate 24 in FIG. 1).
[0092] A first feature of the device structure in this embodiment
is that at least one of the edge portions of the detection section
14 which exclude the edge portion adjoining the channel region (or
at least a portion of the edge portions of the detection section 14
in a case where the detection section 14 is not rectangular) is
spaced apart from the device isolation region 12. With this
structure, the detection section 14 is free from the effect of
crystal defects occurring at the peripheral portion of the device
isolation region 12, and a leak current occurring at the detection
section can be suppressed. Accordingly, a pseudo signal can be
prevented and the stable operation of the solid state imager is
ensured.
[0093] A second feature of the device structure in this embodiment
is that the channel width W2 of the transfer gate can be freely set
irrespective of the dimension W3 of the detection section 14. For
example, the dimension W3 of the detection section 14 can be
decreased as much as possible and the channel width W2 of the
transfer gate can be set at a value equal to the dimension W1 of
the signal accumulation region 13 of the photodiode. Accordingly,
charge can completely be transferred from the signal accumulation
region 13 to the detection section 14, and the photosensitivity of
the image sensor cannot be lowered.
[0094] A new problem arises with the device structure of the third
embodiment, in particular, in the case of the buried-type (or
complete-transfer-type) photodiode (see FIG. 17).
[0095] The depletion potential of the signal accumulation region 13
of the photodiode in a cross section taken along line A-A in FIG.
11 will be examined below. In normal cases, in a pixel section and
its peripheral portion of a solid state imager, electric force
lines spread to the device isolation region 12. As a result, the
depletion potential of the photodiode decreases due to a so-called
narrow channel effect.
[0096] For example, in the device shown in FIGS. 11 to 13, too, a
channel potential decreases due to a narrow channel effect in that
end portion ("end portion of channel region") of the channel region
just below the gate electrode 15 of the transfer gate, which is
located near the device isolation region 12. Consequently, in this
end portion of the channel region, the channel potential does not
reach a high depletion potential level at the central portion of
the photodiode, and charge cannot completely be transferred.
[0097] In order to solve this problem, there is an idea of applying
a higher potential to the gate electrode of the transfer gate. In
this case, however, a booster circuit needs to be added in order to
produce the high potential, or a sufficient gate breakdown voltage
cannot be maintained due to the high potential.
[0098] Thus, in order to solve the problem of the decrease in
depletion potential at the end portion of the channel region due to
the narrow channel effect, it is preferable to dispose the
detection section 14 at the central portion of the transfer gate
where the potential of the photodiode takes a maximum value, as in
the devices of the first and second embodiments.
[0099] It is possible to adopt a device structure as shown in FIGS.
14 to 16, which is a modification of the device structure shown in
FIGS. 11 to 13.
[0100] FIG. 14 is a plan view showing this modified device
structure according to the present invention. FIG. 15 is a
cross-sectional view taken along line XV-XV in FIG. 14, and FIG. 16
is a cross-sectional view taken along line XVI-XVI in FIG. 14.
[0101] In the device structure shown in FIGS. 14 to 16, the edge
portion Li of the detection section 14 is made closer to the edge
portion of the device isolation region 12, which is located in the
direction of extension of the gate electrode 15, so that the
detection section 14 may be disposed at the central portion (with
maximum potential) of the transfer gate. In this case, too, the
edge portion L1 of the detection section 14, of course, does not
come in contact with the device isolation region 12.
[0102] According to the device structure shown in FIGS. 14 to 16,
the size of the detection section 14 is somewhat increased.
However, since the detection section 14 is disposed at the central
portion of the transfer gate where the potential takes a maximum
value, the adverse effect of the narrow channel effect can be
suppressed to a minimum and the charge can completely be
transferred. Moreover, since the edge portion L1 of the detection
section 14 does not come in contact with the device isolation
region 12, the occurrence of a pseudo signal due to leak current
can be suppressed.
[0103] Fourth Embodiment
[0104] A fourth embodiment of the present invention is an
improvement of the device structure of the first embodiment. The
fourth embodiment is characterized in that one detection section is
provided for two photodiodes (photoelectric conversion sections),
and the size of the pixel is reduced. As regards the detection
section, like the first embodiment, two edge portions L1 and L2,
which are located in a direction (corresponding to "one direction")
in which gate electrodes of transfer gates extend, are spaced apart
from the device isolation region 12.
[0105] The device structure according to the present embodiment
will now be described in detail.
[0106] FIG. 18 shows the fourth embodiment of the solid state
imager according to the present invention. FIG. 19 is a
cross-sectional view taken along line XIX-XIX in FIG. 18, and FIG.
20 is a cross-sectional view taken along line XX-XX in FIG. 18.
[0107] A device isolation region 12 is provided on a p-type
semiconductor substrate (or p-type well region) 11. In this
example, the device isolation region 12 is formed of a field oxide
film by LOCOS. Alternatively, the device isolation region 12 may be
formed of an oxide film having, for example, an STI structure.
[0108] Two photodiodes (photoelectric conversion sections) and two
transfer gates are disposed in a device region surrounded by the
device isolation region 12.
[0109] The photodiodes are composed of the p-type semiconductor
substrate 11 and n-type signal accumulation regions (impurity
diffusion layers) 13A and 13B formed in the semiconductor substrate
11. Alternatively, as shown in FIG. 17, buried-type photodiodes may
be employed as the photodiodes. The transfer gates are composed of
the n-type signal accumulation regions 13A and 13B and an
n.sup.+detection section (detection node) 14, which are formed in
the p-type semiconductor substrate 11, and gate electrodes 15A and
15B formed on channel regions between the signal accumulation
regions 13A and 13B, on the one hand, and detection section 14, on
the other hand.
[0110] The n-type signal accumulation regions 13A and 13B function
as cathodes of the photodiodes and also as sources of the transfer
gates. The impurity density in each of the n-type signal
accumulation regions 13A and 13B is set at a lowest possible level
in order to lower a depletion potential and to transfer all the
charge accumulated by photoelectric conversion in the signal
accumulation region 13A, 13B to the detection section 14. The
detection section 14 is connected to an amplifier circuit 17 (e.g.
sense gate 24 in FIG. 1).
[0111] In the device structure of this embodiment, as shown in an
equivalent circuit diagram of FIG. 21, a photodiode 21A is
connected to a detection section (detection node) D via a transfer
gate 22A. Similarly, a photodiode 21B is connected to the detection
section (detection node) D via a transfer gate 22B.
[0112] A first feature of the device structure in this embodiment
is that two edge portions L1 and L2 of the detection section 14,
which are located in a direction (corresponding to "one direction")
in which the gate electrodes 15A and 15B of the transfer gates (MOS
transistors) extend, are spaced apart from the device isolation
region 12 (i.e. the edge portions L1 and L2 are not in contact with
the device isolation region 12).
[0113] In this embodiment, the device region surrounded by the
device isolation region 12 has the same width W1 on both sides
(source side and drain side) of the gate electrode 15A, 15B of the
select gate. On the source side of the gate electrode 15A, 15B, as
in the prior art, the signal accumulation region 13A, 13B of the
photodiode is disposed. On the other hand, the detection section 14
having a smaller width W3 than the width W1 of the device region is
disposed on the drain side of the gate electrode 15A, 15B. As a
result, the edge portions of the detection section 14, which are
located in the direction of extension of the gate electrode 15A,
15B, are spaced apart from the device isolation region 12.
[0114] With this device structure, the detection section 14 is free
from the effect of crystal defects occurring at the peripheral
portion of the device isolation region 12, and a leak current
occurring at the detection section can be suppressed. Accordingly,
a pseudo signal can be prevented and the stable operation of the
solid state imager is ensured.
[0115] A second feature of the device structure in this embodiment
is that the channel width W2 of each transfer gate is greater than
the dimension (i.e. a width in "one direction") W3 of the detection
section 14. For example, the channel width W2 is set to be equal to
the dimension (i.e. a width in "one direction") W1 of the signal
accumulation region 13A, 13B of each photodiode.
[0116] According to this device structure, the channel width W2 can
be freely set irrespective of the dimension W3 of the detection
section 14. Specifically, the channel width W2 of the transfer gate
can be set, at maximum, at a value equal to the dimension W1 of the
signal accumulation region 13A, 13B of the photodiode, and all
charge can be transferred from the signal accumulation region 13A,
13B to the detection section 14. Moreover, even if this structure
is adopted, the dimension W3 of the detection section 14 can be set
to a minimum and thus the photosensitivity of the image sensor
cannot be lowered.
Advantageous Effects of the Invention
[0117] As has been described above, according to the first feature
of the solid state imager of the present invention, at least one of
the edge portions of the detection section, which exclude the edge
portion adjoining the channel region, or at least a portion of the
edge portions of the detection section in a case where the
detection section is not rectangular, is spaced apart from the
device isolation region. With this structure, the detection section
is free from the effect of crystal defects occurring at the
peripheral portion of the device isolation region, and a leak
current occurring at the detection section can be suppressed.
Accordingly, a pseudo signal can be prevented and the stable
operation of the solid state imager is ensured.
[0118] According to the second feature of the solid state imager of
the present invention, the channel width can be freely set
irrespective of the dimension of the detection section. For
example, the channel width of the transfer gate is set to be equal
to the dimension (width in "one direction") of the signal
accumulation region of the photodiode. Accordingly, all charge can
be transferred from the signal accumulation region to the detection
section. Moreover, since the dimension of the detection section can
be set to a minimum irrespective of the channel width of the
transfer gate, the photosensitivity of the image sensor cannot be
lowered.
[0119] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *