U.S. patent application number 09/923725 was filed with the patent office on 2001-12-27 for method and apparatus for simulating standard test wafers.
Invention is credited to Goldspring, Gregory J., O'Donnell, Robert J..
Application Number | 20010054600 09/923725 |
Document ID | / |
Family ID | 23082161 |
Filed Date | 2001-12-27 |
United States Patent
Application |
20010054600 |
Kind Code |
A1 |
Goldspring, Gregory J. ; et
al. |
December 27, 2001 |
Method and apparatus for simulating standard test wafers
Abstract
A method and apparatus are provided for simulating a standard
wafer in semiconductor manufacturing equipment. The apparatus
includes a support layer suitable for being handled by the
semiconductor manufacturing equipment. Applied to the support layer
is a mixture including a process agent and a material. During use,
the present invention simulates a standard production wafer
including material similar to that in the mixture of the present
invention.
Inventors: |
Goldspring, Gregory J.;
(Alameda, CA) ; O'Donnell, Robert J.; (Fremont,
CA) |
Correspondence
Address: |
MARTINE & PENILLA, LLP
710 LAKEWAY DRIVE
SUITE 170
SUNNYVALE
CA
94085
US
|
Family ID: |
23082161 |
Appl. No.: |
09/923725 |
Filed: |
August 6, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09923725 |
Aug 6, 2001 |
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09282585 |
Mar 31, 1999 |
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6296778 |
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Current U.S.
Class: |
216/59 ; 216/75;
216/77; 216/78; 216/79 |
Current CPC
Class: |
H01L 22/34 20130101;
G03F 7/70616 20130101; Y10S 438/926 20130101 |
Class at
Publication: |
216/59 ; 216/79;
216/75; 216/77; 216/78 |
International
Class: |
G01L 021/30 |
Claims
What is claimed is:
1. An apparatus suitable for simulating a standard wafer in
semiconductor manufacturing equipment, comprising: a support layer
suitable for being handled by the semiconductor manufacturing
equipment; and a mixture including a process agent and a material,
the mixture being applied to the support layer, wherein the
apparatus simulates a wafer including the material and having the
process agent thereon.
2. The apparatus of claim 1, wherein the process agent is
photoresist.
3. The apparatus of claim 1, wherein the material is silicon and
the apparatus simulates a wafer including polysilicon.
4. The apparatus of claim 1, wherein the material is tungsten and
the apparatus simulates a wafer including tungsten.
5. The apparatus of claim 1, wherein the material is tungsten
silicide and the apparatus simulates a wafer including tungsten
silicide.
6. The apparatus of claim 1, wherein the material is titanium and
the apparatus simulates a wafer including titanium.
7. The apparatus of claim 1, wherein the material is titanium
nitride and the apparatus simulates a wafer including titanium
nitride.
8. The apparatus of claim 1, wherein the material is silicon
dioxide and the apparatus simulates a wafer including silicon
dioxide.
9. The apparatus of claim 1, wherein the material is aluminum and
the apparatus simulates a wafer including aluminum.
10. The apparatus of claim 1, wherein the material is platinum and
the apparatus simulates a wafer including platinum.
11. The apparatus of claim 1, wherein the material is ruthenium and
the apparatus simulates a wafer including ruthenium.
12. The apparatus of claim 1, wherein the material is ruthenium
oxide and the apparatus simulates a wafer including ruthenium
oxide.
13. The apparatus of claim 1, wherein the material is copper and
the apparatus simulates a wafer including copper.
14. The apparatus of claim 1, wherein the material is tantalum and
the apparatus simulates a wafer including tantalum.
15. The apparatus of claim 1, wherein the material is nickel and
the apparatus simulates a wafer including nickel.
16. The apparatus of claim 1, wherein the support layer is at least
one of a disc and a wafer.
17. The apparatus of claim 1, wherein the support layer includes at
least one of silicon, metal, plastic, and an oxide.
18. The apparatus of claim 1, wherein the material and the process
agent of the mixture are baked on the support layer.
19. The apparatus of claim 1, wherein a ratio between the material
to the process agent corresponds to an exposed area on the wafer to
be simulated.
20. A process for manufacturing an apparatus suitable for use in
simulating a standard wafer in semiconductor manufacturing
equipment, comprising: combining a process agent and a material;
and applying the combination of the process agent and the material
to a support layer to simulate a wafer including the material and
having the process agent thereon.
21. The process of claim 20, wherein the process agent is a
photoresist.
22. The process of claim 20, wherein the material is silicon
dioxide to simulate a wafer including polysilicon.
23. The process of claim 20, wherein the material is tungsten to
simulate a wafer including tungsten.
24. The process of claim 20, wherein the material is tungsten
silicide to simulate a wafer including tungsten silicide.
25. The process of claim 20, wherein the material is titanium to
simulate a wafer including titanium.
26. The process of claim 20, wherein the material is titanium
nitride to simulate a wafer including titanium nitride.
27. The process of claim 20, wherein the material is silicon
dioxide to simulate a wafer including silicon dioxide.
28. The process of claim 20, wherein the material is aluminum to
simulate a wafer including aluminum.
29. The process of claim 20, wherein the material is platinum to
simulate a wafer including platinum.
30. The process of claim 20, wherein the material is ruthenium to
simulate a wafer including ruthenium.
31. The process of claim 20, wherein the material is ruthenium
oxide to simulate a wafer including ruthenium oxide.
32. The process of claim 20, wherein the material is copper to
simulate a wafer including copper.
33. The process of claim 20, wherein the material is tantalum to
simulate a wafer including tantalum.
34. The process of claim 20, wherein the material is nickel to
simulate a wafer including nickel.
35. The process of claim 20, wherein the support layer is at least
one of a disc and a wafer.
36. The process of claim 20, wherein the support layer includes at
least one of silicon, metal, plastic, and an oxide.
37. The process of claim 20, comprising: baking the combination of
the material and the process agent onto the support layer.
38. The process of claim 20, comprising: selecting a ratio between
the material and the process agent that corresponds to an exposed
area on the wafer to be simulated.
39. The process of claim 38, comprising: mixing the process agent
and the material such that the combination is a mixture.
40. In a semiconductor plasma chamber, a method for simulating a
standard wafer using an apparatus composed of a combination of a
process agent and a material applied to a support layer, the method
comprising: placing the apparatus within the semiconductor plasma
chamber; etching the apparatus; and simulating the standard wafer
by simultaneously producing byproducts during the etching that are
similar to byproducts produced by the standard wafer.
41. The method of claim 40, wherein the process agent is
photoresist.
42. The method of claim 40, wherein the material is silicon dioxide
to simulate a wafer including polysilicon.
43. The method of claim 40, wherein the material is tungsten to
simulate a wafer including tungsten.
44. The method of claim 40, wherein the material is tungsten
silicide to simulate a wafer including tungsten silicide.
45. The method of claim 40, wherein the material is titanium to
simulate a wafer including titanium.
46. The method of claim 40, wherein the material is titanium
nitride to simulate a wafer including titanium nitride.
47. The method of claim 40, wherein the material is silicon dioxide
to simulate a wafer including silicon dioxide.
48. The method of claim 40, wherein the material is aluminum to
simulate a wafer including aluminum.
49. The method of claim 40, wherein the material is platinum to
simulate a wafer including platinum.
50. The method of claim 40, wherein the material is ruthenium to
simulate a wafer including ruthenium.
51. The method of claim 40, wherein the material is ruthenium oxide
to simulate a wafer including ruthenium oxide.
52. The method of claim 40, wherein the material is copper to
simulate a wafer including copper.
53. The method of claim 40, wherein the material is tantalum to
simulate a wafer including tantalum.
54. The method of claim 40, wherein the material is nickel to
simulate a wafer including nickel.
55. The method of claim 40, wherein the support layer is at least
one of a disc and a wafer.
56. The method of claim 40, wherein the support layer includes at
least one of silicon, metal, plastic, and an oxide.
57. The method of claim 40, wherein the material and the process
agent are baked on the support layer.
58. The method of claim 40, wherein a ratio between the material
and the process agent corresponds to an exposed area on the wafer
to be simulated.
59. An apparatus suitable for simulating a standard manufactured
device in manufacturing equipment, comprising: a support layer
suitable for being handled by the manufacturing equipment; and a
mixture including a process agent and a material, the mixture being
applied to the support layer, wherein the apparatus simulates a
manufactured device including the material and having the process
agent thereon.
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to semiconductor
test wafers and, more particularly, to a test wafer that
effectively simulates "patterned" standard test wafers and can be
produced at a reduced cost.
BACKGROUND OF THE INVENTION
[0002] In semiconductor fabrication, the necessary related
equipment must often be tested and conditioned prior to being used
to manufacture integrated circuits. Such testing and conditioning
improve the quality and reliability of the manufactured integrated
circuits by providing a preview of how the semiconductor
manufacturing equipment operates during various processes. For
example, "marathon experiments" are often conducted wherein a vast
number of wafers are placed in a plasma chamber and etched in a
conventional manner. Analysis of various device parameters and the
end product during such marathon experiments provides information
that is beneficial during the preparation for actual production of
integrated circuits. In particular, data regarding particle
emissions may be collected during the course of the marathon
experiments to anticipate particle failure during the manufacture
of integrated circuits.
[0003] To carryout such conditioning exercises and marathon
experiments on semiconductor manufacturing equipment such as plasma
chambers, standard test wafers are normally used in place of
standard production wafers. A cross-section of a standard
production wafer 10 and a standard test wafer 20 are shown in FIGS.
1 and 2, respectively. As shown, the standard test wafer 20
includes a wafer 22 including any type of materials thereon such as
aluminum and the like. This standard test wafer 20 further has a
layer of photoresist 24 thereon. By this structure, the standard
test wafer 20 simulates a pair of uppermost layers 26 of the
standard production wafer 10.
[0004] In order to properly simulate a standard production wafer
10, it is preferred that the photoresist 24 of the standard test
wafer 20 be "patterned." In other words, the resist is ideally
applied to the standard test wafer 20 to define a plurality of
vias, channels, etc. which in turn leave a percentage of the
standard test wafer 20 exposed as shown in FIG. 3.
[0005] Therefore, the use of standard test wafers 20 can be
expensive, especially when standard test wafers 20 have multiple
layers similar to standard production wafers 10. This cost often
fails to justify many conditioning exercises and marathon
experiments which, in turn, leads to reduced quality and
reliability during the subsequent processing of standard production
wafers 10.
[0006] One known prior art alternative to the use of such
"patterned" standard test wafers 20 is to alternate between
aluminum wafers and blanket photoresist wafers in a plasma chamber.
Such method, however, tends to be cumbersome and time consuming
since the aluminum and blanket photoresist wafers must be
alternated during use. Further, the aluminum wafers and blanket
photoresist wafers are not processed at the same time. As such, the
present method fails to effectively simulate the composition of
materials being deposited in the plasma chamber during the
processing of standard production wafers. This in turn gives rise
to detrimental ramifications in particle performance.
[0007] There is thus a need for a test wafer that effectively
simulates "patterned" standard test wafers and can be produced at a
reduced cost.
DISCLOSURE OF THE INVENTION
[0008] The present invention includes a method and apparatus for
simulating a standard wafer in semiconductor manufacturing
equipment. The present invention includes a support layer suitable
for being handled by the semiconductor manufacturing equipment.
Applied to the support layer is a mixture including a process agent
and a material. During use, the present invention simulates a
standard wafer including material similar to that in the mixture of
the present invention.
[0009] By this design, the present invention offers a
cost-effective substitution for standard test wafers. Moreover, the
present invention better simulates standard test wafers by ensuring
that byproducts are produced simultaneously. The ratio of
byproducts of the present invention may also be tailored to
simulate a specific percentages of area that is exposed through the
process agent on a standard test wafer. This is accomplished by
varying a volumetric ratio between the process agent and material
within the mixture.
[0010] These and other advantages of the present invention will
become apparent upon reading the following detailed description and
studying the various figures of the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The accompanying drawings, which are incorporated in and
constitute part of this specification, illustrate exemplary
embodiments of the invention and together with the description
serve to explain the principles of the invention.
[0012] Prior Art FIG. 1 is a vastly exaggerated cross-sectional
view of a standard production wafer of the prior art.
[0013] Prior Art FIG. 2 is a vastly exaggerated cross-sectional
view of a standard test wafer of the prior art.
[0014] Prior Art FIG. 3 is a top view of the standard test wafer of
Prior Art FIG. 2 with a detailed view of the "patterned"
photoresist.
[0015] FIG. 4 is a flowchart delineating the process for
manufacturing an apparatus suitable for use in simulating a
standard test wafer in semiconductor manufacturing equipment,
according to one embodiment of the present invention.
[0016] FIG. 5 is a vastly exaggerated cross-sectional view of the
apparatus of the present invention prior to etching.
[0017] FIG. 6 is a vastly exaggerated cross-sectional view of the
apparatus of the present invention after etching.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0018] Reference will now be made to the present preferred
embodiments of the invention, examples of which are illustrated in
the accompanying drawings.
[0019] Prior Art FIG. 1 shows a standard production wafer 10. Prior
Art FIGS. 2 and 3 illustrate a standard test wafer 20. As shown in
FIGS. 4-6, one embodiment of the present invention includes a
method and apparatus that is suitable for simulating the standard
test wafer 20 in semiconductor manufacturing equipment such as a
plasma chamber.
[0020] Turning to FIG. 5, a wafer 28 in accordance with one
embodiment of the present invention will now be described. The
wafer 28 includes a support layer 30 and a combination 29 of a
process agent 32 and at least one predetermined material 34. The.
support layer 30 may be constructed from any type of material
suitable for being handled by the semiconductor manufacturing
equipment. In various embodiments, the material 34 may include, but
is not limited to, silicon, an oxide, metal, plastic, any material
commonly known in the semiconductor arts, or any other material
capable of being handled by the semiconductor manufacturing
equipment. Further, in one embodiment, the support layer 30 may be
shaped in the form of a substantially planar disc or wafer having a
generally circular periphery. In the alternative, the support layer
30 may take the form of a flat panel, an optical substrate, or any
other type of support mechanism which is capable of supporting the
mixture.
[0021] The process agent 32 and the material 34 may take the form
of a mixture which is applied to the support layer 30. Further, the
process agent 32 may include a photoresist such as a deep-UV
photoresist or any components thereof, a polymer, or a resin such
as Novolac.TM. resin which is a component of a conventional I-line
photoresist. It should be noted, however, that the process agent 32
may include any type of suitable substance which is associated with
photolithography, etching or any other manufacturing process.
[0022] With respect to the material 34, the same may include any
substance for the purpose of simulating a standard test wafer 20
including the material 34. Depending on the application at hand,
the mixture need not be limited to only a single material 34. Table
1 shows a list of examples of potential materials 34 and the wafer
which each is designed to simulate. Such list is not to be deemed
as exhaustive and may include any type of material(s).
1 TABLE 1 Standard Wafer Type Appropriate Simulation Material
Aluminum Aluminum (Al) Polysilicon Silicon (Si) Tungsten
interconnect/etchback Tungsten (W) Tungsten Silicide Tungsten
Silicide (WSi.sub.2) Titanium Titanium (Ti) Titanium Nitride
Titanium Nitride (TiN) Silicon Dioxide Silicon Dioxide (SiO.sub.2)
Platinum Platinum (Pt) Ruthenium Ruthenium (Ru) Ruthenium Oxide
Ruthenium Oxide (RuO.sub.2) Copper Copper (Cu) Tantalum Tantalum
(Ta) Nickel Nickel (Ni)
[0023] The method associated with the construction of the apparatus
of the present invention will now be set forth with specific
reference to FIG. 4. As mentioned earlier, the material 34 and the
process agent 32 are combined to form the mixture. Note box 36 of
FIG. 4. In the case where the material is aluminum in a power form,
such powder may comprise of particulates with a size in the order
of 20 .mu.m. It should be understood, however, that the
particulates may have any microscopic or macroscopic size.
[0024] As will soon become apparent, a volumetric ratio between the
material 34 and the process agent 32 may be selected in order to
simulate a percentage of an area that is exposed through the
process agent 32 on a "patterned" standard test wafer 20. For
example, a 2:1 volumetric ratio between the material 34 and the
process agent 32 may simulate an exposed area A on the simulated
standard test wafer 20 while a 3:1 volumetric ratio between the
material 34 and the process agent 32 may simulate an exposed area
greater than A on the simulated standard test wafer 20. In various
alternate embodiments, other types of ratios may be employed for
partitioning the material 34 and the process agent 32 such as a
mass ratio, density ratio, etc.
[0025] Thereafter, the mixture is applied to the support layer 30,
as indicated by box 38 of FIG. 4. Application of the mixture may be
carried out in various ways including, but not limited to spraying,
spinning or brushing the mixture onto the support layer 30. While
applying the mixture to the support layer 30, any type of known
technique may be employed to prevent the accumulation of the
mixture adjacent the periphery of the support layer 30.
[0026] As indicated by box 40 of FIG. 4, the mixture is
subsequently baked at a temperature and for a period of time
sufficient to "cure" the process agent. In one embodiment, the
mixture may be baked at 120.degree.-130.degree. F. for 10-15
minutes. It should be noted that the baking may be carried out with
any effective means including a hot plate, oven or the like. After
baking, the present invention is then complete and ready to be used
in place of a standard test wafer 20 in a plasma chamber or the
like.
[0027] In use, the present invention is placed within the
semiconductor plasma chamber and is subsequently etched using
conventional processes and techniques. During etching, the present
invention produces byproducts and behaves in a manner similar to
the "patterned" standard test wafer 20 that is to be simulated. As
mentioned earlier, the process agent 32 on a "patterned" standard
test wafer 20 is distributed upon a predetermined percentage of the
surface area of the wafer. Accordingly, as the process agent 32 and
wafer are etched, byproducts from the process agent 32 and the
wafer are emitted simultaneously during the etching processes.
[0028] Similarly, during the etching of the present invention, the
mixture of the material 34 and process agent 32 are exposed
together as a combination, as shown in FIG. 6. As such, within the
plasma chamber the present invention appears as being no different
than a corresponding "patterned" standard test wafer 20. Therefore,
the present invention simulates the etching of a "patterned"
standard test wafer 20, but by a means that is vastly less
expensive in comparison.
[0029] In terms of cost effectiveness, the present invention
appears to offer a sizable reduction in cost with respect to
conditioning plasma chambers and running related marathon
experiments with "patterned" standard test wafers 20. As mentioned
earlier, marathon experiments are procedures wherein a vast number
of wafers are placed in the plasma chamber and etched in a
conventional manner for testing purposes. The reduction in cost
results from not only avoiding the use of expensive standard test
wafers 20, but also providing a test article that can be processed
for a greater amount of time.
[0030] For example, a standard test wafer 20 manufactured by
Sematech.TM. costs approximately $300.00 and can be etched for 1.3
RF minutes. This translates into a cost of $230.00/RF minute to use
such standard test wafer 20. In contrast, in one embodiment of the
present invention wherein aluminum powder is employed with a 1:2
volumetric ratio to a process agent such as photoresist, each unit
costs $6.70 and can be etched for 120 RF minutes. This results in a
cost of approximately $0.63/RF minute, less than 1% the cost
associated with processing the standard test wafer 20.
[0031] Although only a few embodiments of the present invention
have been described in detail herein, it should be understood that
the present invention may be embodied in many other specific forms
without departing from the spirit or scope of the invention.
Therefore, the present examples and embodiments are to be
considered as illustrative and not restrictive, and the invention
is not to be limited to the details given herein, but may be
modified within the scope of the appended claims.
* * * * *