U.S. patent application number 09/289859 was filed with the patent office on 2001-12-20 for method of fabricating vias.
Invention is credited to CHANG, SHIH-CHANH, WANG, CHEIN-CHENG.
Application Number | 20010053596 09/289859 |
Document ID | / |
Family ID | 21639928 |
Filed Date | 2001-12-20 |
United States Patent
Application |
20010053596 |
Kind Code |
A1 |
WANG, CHEIN-CHENG ; et
al. |
December 20, 2001 |
METHOD OF FABRICATING VIAS
Abstract
The present invention is a method of fabricating interconnects.
A semiconductor substrate having a dielectric layer is provided.
The dielectric layer has a via opening therein, which exposes the
semiconductor substrate. Next, the surfaces of the via opening is
covered with a conformal titanium layer formed by a sputtering
process. The surface of the conformal titanium layer is covered
with an Al--Si--Cu alloy layer formed by a sputtering process at a
temperature of about 0.degree. C. to 200.degree. C. Then, the
surface of the Al--Si--Cu alloy layer is covered with an Al--Cu
alloy layer formed by a sputtering process at a temperature of
about 380.degree. C. to 450.degree. C., which Al--Cu alloy layer
fills the via opening. The Al--Cu alloy layer, the Al--Si--Cu alloy
layer and the wetting layer on the dielectric layer are patterned
by photolithography and etching process.
Inventors: |
WANG, CHEIN-CHENG; (TAICHUNG
HSIEN, TW) ; CHANG, SHIH-CHANH; (HSINCHU,
TW) |
Correspondence
Address: |
MARTINE & PENILLA, LLP
710 LAKEWAY DRIVE
SUITE 170
SUNNYVALE
CA
94085
US
|
Family ID: |
21639928 |
Appl. No.: |
09/289859 |
Filed: |
April 12, 1999 |
Current U.S.
Class: |
438/597 ;
257/E21.584; 257/E21.585; 438/653; 438/654; 438/658; 438/687;
438/688 |
Current CPC
Class: |
Y10S 438/913 20130101;
H01L 21/76877 20130101; H01L 21/76843 20130101 |
Class at
Publication: |
438/597 ;
438/653; 438/654; 438/658; 438/687; 438/688 |
International
Class: |
H01L 021/44; H01L
021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 11, 1999 |
TW |
88103736 |
Claims
What is claimed is:
1. A method of fabricating an interconnect, comprising the steps
of: providing a semiconductor substrate having a conducting area;
forming a dielectric layer on the semiconductor substrate, the
dielectric layer having a via opening exposing the conducting area;
forming a conformal wetting layer on the via opening; forming an
Al--Si--Cu alloy layer on the conformal wetting layer by a
sputtering process at a substantially low temperature; and forming
an Al--Cu alloy layer on the Al--Si--Cu alloy layer to fill the via
opening by a sputtering process at a substantially high
temperature;
2. The method as claimed in claim 1, wherein the conformal wetting
layer comprises titanium formed by a sputtering process.
3. The method as claimed in claim 2, wherein the Al--Si--Cu alloy
layer is formed at a temperature of about 0.degree. C. to
200.degree. C.
4. The method as claimed in claim 3, wherein the Al--Si--Cu alloy
layer has a silicon weight percentage of about 0.5% to about 1% and
a copper weight percentage of about 0.4% to about 0.6%.
5. The method as claimed in claim 3, wherein the Al--Cu alloy layer
is formed at a temperature of about 380.degree. C. to about
450.degree. C.
6. The method as claimed in claim 5, wherein the Al--Cu alloy layer
has a copper weight percentage of about 0.4% to about 0.6%.
7. The method as claimed in claim 1, wherein the Al--Si--Cu alloy
layer is formed at a temperature of about 0.degree. C. to about
200.degree. C.
8. The method as claimed in claim 7, wherein the Al--Si--Cu alloy
layer has a silicon weight percentage of about 0.5% to about 1% and
a copper weight percentage of about 0.4% to about 0.6%.
9. The method as claimed in claim 7, wherein the Al--Cu alloy layer
is formed at a temperature of about 380.degree. C. to about
450.degree. C.
10. The method as claimed in claim 9, wherein the Al--Cu alloy
layer has a copper weight percentage of about 0.4% to about
0.6%.
11. The method as claimed in claim 1, wherein the Al--Cu alloy
layer is formed at a temperature of about 380.degree. C. to
450.degree. C.
12. The method as claimed in claim 1, wherein the Al--Cu alloy
layer has a copper weight percentage of about 0.4% to 0.6%.
13. The method as claimed in claim 1, more comprising the step of
defining the Al--Cu alloy layer, the Al--Si--Cu alloy layer, and
the conformal wetting layer on the dielectric layer.
14. A method of fabricating a contact, comprising the steps of:
providing a dielectric layer on the semiconductor substrate, the
dielectric layer having an opening exposing a part of the
semiconductor substrate; forming a titanium layer along a surface
profile of the opening; forming an Al--Si--Cu alloy layer on the
titanium layer at a first temperature; and forming an Al--Cu alloy
layer on the Al--Si--Cu alloy layer at a second temperature to fill
the opening completely; wherein the first temperature is lower than
the second temperature.
15. The method as claimed in claim 14, wherein the conformal
wetting layer comprises titanium formed by a sputtering
process.
16. The method as claimed in claim 15, wherein the Al--Si--Cu alloy
layer is formed at a temperature of about 0.degree. C. to about
200.degree. C.
17. The method as claimed in claim 16, wherein the Al--Cu alloy
layer is formed at a temperature of about 380.degree. C. to about
450.degree. C.
18. The method as claimed in claim 14, wherein the Al--Si--Cu alloy
layer is formed at a temperature of about 0.degree. C. to about
200.degree. C.
19. The method as claimed in claim 18, wherein the Al--Cu alloy
layer is formed at a temperature of about 380.degree. C. to about
450.degree. C.
20. The method as claimed in claim 14, wherein the Al--Cu alloy
layer is formed at a temperature of about 380.degree. C. to about
450.degree. C.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a method of fabricating an
integrated circuit, and particularly to a method of fabricating a
multilevel interconnect.
[0003] 2. Description of the Related Art
[0004] In integration circuit process for semiconductor devices,
the interconnects are provided between two devices for allowing
electrical connection between different devices or components.
Aluminum is one conducting material that has been widely used to
fabricating vias. The main reasons for the pervasiveness of
aluminum are its low resistivity and its good adhesion to silicon
oxides and silicon.
[0005] Referring to FIG. 1A, in the conventional process for
manufacturing vias using aluminum, a wetting layer 18 formed of
titanium is deposited in the via opening 16. An aluminum layer 20
is deposited by a sputtering process to fill the via opening 16.
The wetting layers 18 and the aluminum layer 20 left in the via
opening 16 form a via plug. The wetting layer 18 and the aluminum
layer 20 on the dielectric layer 14 are patterned by
photolithography process and an etch process, as shown in FIG.
1B.
[0006] In the above conventional process, the aluminum layer 20
formed by a sputtering process reacts with the titanium wetting
layer 18 to form byproduct AlTi.sub.3 during the aluminum
deposition step. Therefore, the step coverage of the aluminum layer
20 is affected and becomes poor. The via-filling process suffers
from the poor step coverage, and voids 30 are formed in the via
plug consequently. This affects the device reliability. In
addition, the vias formed of aluminum further suffers an
electromigration problem. More specifically, an annealing step is
performed after the sputter deposition of aluminum, so that the
aluminum is usually in poly-crystalline state. The aluminum atoms
move along the grain boundary in an electric field, and the
movement results in an open-circuit failure. This also affects
device reliability.
SUMMARY OF THE INVENTION
[0007] The invention provides a method of fabricating
interconnects. A semiconductor substrate having a dielectric layer
is provided. The dielectric layer has at least a via opening, and
the via opening expose a part of the semiconductor substrate. A
titanium layer is formed along a surface profile of the via
opening. The surface of the titanium layer is covered with an
Al--Si--Cu alloy layer formed by a sputtering process at a
substantially low temperature. The via openings are filled with an
Al--Cu alloy layer formed by a sputtering process at a
substantially high temperature, such that the Al--Cu alloy covers
the surface of the Al--Si--Cu alloy layer.
[0008] In one preferred embodiment of the method of the present
invention, the Al--Si--Cu alloy layer is formed at a temperature of
about 0.degree. C. to about 200.degree. C. The composition of the
Al--Si--Cu alloy layer has a silicon weight percentage of about
0.5% to about 1% and a copper weight percentage of about 0.4% to
about 0.6%. The Al--Cu composition of the Al--Si--Cu alloy layer
has a silicon weight percentage of about 0.5% to about 1% and a
copper weight percentage of about 0.4% to about 0.6%. The Al--Cu
alloy layer is formed at a temperature from about 380.degree. C. to
about 450.degree. C. The composition of the Al--Cu alloy layer has
a copper weight percentage of about 0.4% to about 0.6%. The
Al--Si--Cu alloy layer and the Al--Cu alloy layer comprise copper,
so that the electromigration can be inhibited. The Al--Si--Cu alloy
layer formed at a low temperature comprises silicon, so that the
formation of the byproduct AlTi.sub.3 from the reaction of aluminum
and titanium can be suppressed. Because of the byproduct is
suppressed from being formed, the Al--Si--Cu alloy layer thus
inheres continuity which results in a good step coverage. In
addition, the Al--Cu alloy layer is formed at a high temperature,
which prevents the precipitate of silicon during the sputtering
step of the Al--Cu alloy layer and avoids a silicon nodule after a
metal etching step in the following process. The Al--Si--Cu alloy
layer is between the Al--Cu alloy layer and the titanium layer, so
that aluminum of the Al--Cu alloy layer does not react with
titanium to produce AlTi.sub.3 byproducts. Thus, the step coverage
of the Al--Cu alloy layer is not affected, and the filling problem
can be suppressed. Therefore, the method of the present invention
can be used to improve the step coverage and to avoid forming voids
in the vias, so that the reliability of devices can be
increased.
[0009] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory only and are not restrictive of the invention, as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention. In the
drawings,
[0011] FIGS. 1A-1B are schematic, cross-sectional views
illustrating of a method of fabricating interconnection according
to prior art method; and
[0012] FIGS. 2A-2D are schematic, cross-sectional views
illustrating of a method of fabricating interconnection according
to preferred embodiment of the method according to the present
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0013] In the preferred embodiment of the method according to the
present invention, the process of fabricating a via is described.
However, it is to be understood that the invention is not limited
thereto. In fact, the method of the present invention can be
applied in the process of fabricating a contact.
[0014] Referring to FIG. 2A, a dielectric layer 104 is formed on a
semiconductor substrate 100 having a conducting area 102. In the
preferred embodiment of the method of the present invention, the
conducting area 102 comprises a patterned metal layer. The
conducting area 102 comprises a doping area or a gate when the
method is used to fabricate contacts. A material for suitable
forming the dielectric layer comprises, for example, silicon oxide,
phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG)
formed by chemical vapor deposition (CVD), or spin-on-glass formed
by spin coating. The dielectric layer 104 is planarized by, for
example, a chemical mechanical polishing process in order to
provide a smooth surface for subsequent processes.
[0015] Referring to FIG. 2B, photolithography and etching is
performed on the dielectric layer 104 in order to form a via
opening 106 therein, which exposes the conducting area 102 on the
semiconductor substrate 100. The opening 120 comprises a contact
opening when the method is used to fabricate contacts. The etching
process is performed by, for example, anisotropic etching, such as
a plasma process, with CF.sub.4, CHF.sub.3 or C.sub.2F.sub.6, and
C.sub.3F.sub.8 as gas sources. A conformal wetting layer 108 is
formed on the semiconductor substrate 100 to cover an upper surface
110 of the dielectric layer 104 and a surface of the via opening
106. A suitable material for forming the wetting layer 108
comprises, for example, a titanium layer with a thickness of about
1500 .ANG. to about 4000 .ANG.. The wetting layer 108 is formed by
for example, a sputtering process at an room temperature of about
20.degree. C. to about 30.degree. C.
[0016] Still referring to FIG. 2B, because the electromigration
resistance of aluminum is poor and in order to improve the step
coverage of filling the via opening 106 with metal, an Al--Si--Cu
alloy layer 112 is formed on the wetting layer 108 by a sputtering
process at a low temperature. Preferably, the Al--Si--Cu alloy
layer 112 is formed at a temperature of about 0.degree. C. to about
200.degree. C. The Al--Si--Cu alloy layer 112 has a silicon weight
percentage of about 0.5% to about 1% and a copper weight percentage
of about 0.4% to about 0.6%. The thickness of the Al--Si--Cu alloy
layer 112 is about 2000 .ANG. to about 3000 .ANG.. The Al--Si--Cu
alloy layer 112 comprises copper, so that the electromigration can
be inhibited. In addition, the Al--Si--Cu alloy layer 112 comprises
silicon, so that a byproduct, AlTi.sub.3, formed from the reaction
of aluminum and titanium can be suppressed. Because the byproduct
is suppressed from being produced, the Al--Si--Cu alloy layer 112
inheres continuity. The continuous Al--Si--Cu alloy layer provides
a good step coverage.
[0017] Referring to FIG. 2C, an Al--Cu alloy layer 114 is formed on
the Al--Si--Cu alloy layer 112 to fill the remaining space of the
via opening 106. Preferably, the Al--Si--Cu alloy layer 112 is
formed at a temperature of about 380.degree. C. to about
450.degree. C. and the Al--Si--Cu alloy layer 112 has a copper
weight percentage of about 0.4% to about 0.6%.
[0018] Typically, the Al--Si--Cu layer 112 is very thick when the
via is formed from of one Al--Si--Cu layer. If the Al--Si--Cu is
too thick, precipitate of silicon is formed during the sputtering
step of the Al--Si--Cu layer. The silicon precipitate is to be
removed with difficulty. Thus, the etching process of fabricating
the connection takes a long time, otherwise, the silicon residue of
the silicon precipitate makes a bridge between two wiring lines
formed in subsequent processes. However, when the etching back
process consumes a long time, the thickness loss of the dielectric
layer becomes serious. Therefore, in the present invention, the via
opening 106 is not only filled with Al--Si--Cu alloy layer 112.
That is, the via opening 106 is partially filled with the wetting
layer 108, partially filled with the Al--Si--Cu alloy layer 112
formed by sputtering at the low temperature, and partially filled
with the Al--Cu alloy 114. The Al--Si--Cu alloy layer 112 is so
thin that the formation and the growth of the silicon precipitates
are suppressed.
[0019] Furthermore, the Al--Si--Cu alloy layer 112 is formed
between the Al--Cu alloy layer 114 and the wetting layer 108, so
that aluminum in the Al--Cu alloy layer 114 does not react with the
wetting layer 108 formed of titanium to produce byproduct
AlTi.sub.3. Since the step coverage of the Al--Cu alloy layer 114
cannot be affected, the filling problem can be avoided.
[0020] Referring to FIG. 2D, photolithography and etching is
performed on the wetting layer 108, the Al--Si--Cu alloy layer 112,
and the Al--Cu alloy layer 114 over the dielectric layer 104 in
order to form a wiring line 118. The wetting layer 108, the
Al--Si--Cu alloy layer 112, and the Al--Cu alloy layer 114 form a
via plug 116.
[0021] Since the thickness of the Al--Si--Cu alloy layer 112 is
about 2000 .ANG. to about 3000 .ANG., the formation and the growth
of the silicon precipitates are suppressed. Therefore, it does not
take a longer time to remove the silicon precipitates during the
etching process of fabricating wiring lines. The time of the
etching back is short, so that the thickness of the dielectric
layer loss is prevented. In addition, the problem of residual
silicon nodules making a bridge between two wiring lines in
subsequent processes can be avoided.
[0022] In the method of the present invention, the wetting layer is
formed along a surface profile of the via opening. The Al--Si--Cu
alloy layer is formed on the wetting layer by a sputtering process
at a low temperature. The Al--Cu alloy layer fills the remaining
space of the via opening. The Al--Si--Cu alloy layer and the Al--Cu
alloy layer comprise copper, so that the electromigration can be
inhibited. The Al--Si--Cu alloy layer formed at a low temperature
comprises silicon, so that the formation of the byproduct
AlTi.sub.3 from the reaction of aluminum and titanium can be
suppressed. It can provide good step coverage because the
Al--Si--Cu alloy layer is continuous. The Al--Si--Cu alloy layer is
formed between the Al--Cu alloy layer and the wetting layer formed
from titanium, so that aluminum of the Al--Cu alloy layer does not
react with titanium to from AlTi.sub.3 byproducts. Thus, the step
coverage of the Al--Cu alloy layer is not affected, and the filling
problem can be suppressed. Therefore, the method of the present
invention can be used to suppress electromigration, to improve the
step coverage and to avoid voids be formed in the vias, so that the
reliability of devices can be increased.
[0023] Other embodiments of the invention will appear to those
skilled in the art from consideration of the specification and
practice of the invention disclosed herein. It is intended that the
specification and examples be considered as exemplary only, with a
true scope and spirit of the invention being indicated by the
following claims.
* * * * *