U.S. patent application number 09/778889 was filed with the patent office on 2001-12-20 for semiconductor device.
Invention is credited to Mori, Hirotaka.
Application Number | 20010053582 09/778889 |
Document ID | / |
Family ID | 18680553 |
Filed Date | 2001-12-20 |
United States Patent
Application |
20010053582 |
Kind Code |
A1 |
Mori, Hirotaka |
December 20, 2001 |
Semiconductor device
Abstract
This invention provides a semiconductor device having dual gate
wherein impurity implanted into one gate is prevented from reaching
the other gate and diffusing there. A wide gate separating region
is secured between a p.sup.+ gate 22 and an n.sup.+ gate 23. This
gate separating region is a non-doped polysilicone region in which
the impurity such as B, P, As is not implanted. The wide gate
separating region secures a wide gap between the p.sup.+ gate 22
and the n.sup.+ gate 23. Therefore, the probability that the
impurity existing in one gate may reach the other gate through the
gate electrode metal film 24 is extremely low. Consequently, the
characteristic of the semiconductor device is maintained in an
excellent condition.
Inventors: |
Mori, Hirotaka; (Tokyo,
JP) |
Correspondence
Address: |
JONES VOLENTINE, L.L.P.
Suite 150
12200 Sunrise Vally Drive
Reston
VA
20191
US
|
Family ID: |
18680553 |
Appl. No.: |
09/778889 |
Filed: |
February 8, 2001 |
Current U.S.
Class: |
438/369 ;
257/E21.637 |
Current CPC
Class: |
H01L 21/823842
20130101 |
Class at
Publication: |
438/369 |
International
Class: |
H01L 021/331 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 15, 2000 |
JP |
JP2000-179252 |
Claims
What is claimed is:
1. A semiconductor device comprising: a first gate region composed
of semiconductor containing a first impurity; a second gate region
composed of semiconductor containing a second impurity; and a gate
electrode film adjoining the first gate region and the second gate
region, wherein a length of the shortest path of plural paths
connecting the first gate region to the second gate region,
selected in the gate electrode film, is larger than a diffusion
distance of the first impurity and a diffusion distance of the
second impurity in the gate electrode film.
2. A semiconductor device according to claim 1 wherein the first
gate is composed of polysilicone doped with the first impurity, the
second gate is composed of polysilicone doped with the second
impurity, and the gate electrode film is composed of silicone
compound.
3. A semiconductor device according to claim 1 further comprising a
barrier film adjoining the first gate region and the second gate
region preventing diffusion of the first impurity and the second
impurity.
4. A semiconductor device according to claim 3 wherein all of
plural paths connecting the first gate region to the second gate
region, selected in the gate electrode film bypass the barrier
film.
5. A semiconductor device according to claim 3 wherein the first
gate is composed of polysilicone doped with the first impurity, the
second gate is composed of polysilicone doped with the second
impurity, and the gate electrode film is composed of silicone
compound.
6. A semiconductor device according to claim 5 wherein the barrier
film is composed of silicone compound.
7. A semiconductor device according to claim 6 wherein the barrier
film is composed of SiN film.
8. A semiconductor device according to claim 5 wherein the barrier
film has conductivity.
9. A semiconductor device according to claim 8 wherein the barrier
film is composed of WN film.
10. A semiconductor device according to claim 8 wherein the barrier
film is composed of TiN film.
11. A semiconductor device comprising: a first gate region composed
of semiconductor containing a first impurity; a second gate region
composed of semiconductor containing a second impurity; and a gate
electrode film adjoining the first gate region and the second gate
region, wherein the gate electrode film has a sectional area
smaller than a diameter of crystal grain of material composing the
gate electrode film locally in a region not adjoining the first
gate region and the second gate region.
12. A semiconductor device comprising: a first gate region composed
of semiconductor containing a first impurity; a second gate region
composed of semiconductor containing a second impurity; and a gate
electrode film adjoining the first gate region and the second gate
region, wherein the gate electrode film has plural pits in a region
not adjoining the first gate region and the second gate region and
a gap between a pit and the other pit nearest the pit is smaller
than a diameter of crystal grain of material composing the gate
electrode film.
13. A semiconductor device comprising: a first gate region composed
of semiconductor containing a first impurity; a second gate region
composed of semiconductor containing a second impurity; and a gate
electrode film adjoining the first gate region and the second gate
region, wherein the gate electrode film has a labyrinth portion for
bending plural paths connecting the first gate region to the second
gate region, selected in the gate electrode film.
14. A semiconductor device comprising: a first gate region composed
of semiconductor containing a first impurity; a second gate region
composed of semiconductor containing a second impurity; and a gate
electrode film adjoining the first gate region and the second gate
region, the semiconductor device further comprising an impurity
trap region for trapping the first impurity invading into the gate
electrode film from the first gate region and the second impurity
invading into the gate electrode film from the second gate
region.
15. A semiconductor device according to claim 14 wherein the
impurity trap region adjoins a bottom face of the gate electrode
film.
16. A semiconductor device according to claim 14 wherein the
impurity trap region adjoins a top face of the gate electrode
film.
17. A semiconductor device according to claim 14 wherein the
impurity trap region is formed of intrinsic semiconductor for
composing the first gate region before the first impurity is doped
or intrinsic semiconductor for composing the second gate region
before the second impurity is doped.
18. A semiconductor device comprising: a first gate region composed
of semiconductor containing a first impurity; a second gate region
composed of semiconductor containing a second impurity; and a gate
electrode film adjoining the first gate region and the second gate
region, wherein the gate electrode film has an impurity diffusion
preventing region for preventing diffusion of the first impurity
and the second impurity.
19. A semiconductor device according to claim 18 wherein the
impurity diffusion preventing region is formed by after material
for forming the gate electrode film is grown, implanting
predetermined ions into a region including a region not adjoining
the first gate region and the second gate region in the grown
film.
20. A semiconductor device according to claim 19 wherein the ion is
N.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a semiconductor device.
Prior Art
[0002] Generally, a gate portion of a semiconductor device having
dual gate is formed as follows.
[0003] First, B ion or BF.sub.2 ion is implanted into polysilicone
film so as to form p.sup.+ region and P or As ion is implanted so
as to form n.sup.+ region. At this time, a narrow linear region
(hereinafter referred to as gate separating region) in which no ion
is implanted is secured between the p.sup.+ region and n.sup.+
region to separate both the regions.
[0004] Next, for example, WSi.sub.2 (tungsten silicide) is grown on
the polysilicone film so as to form gate electrode metal film. The
gate electrode metal film is formed across the p.sup.+ region and
the n.sup.+ region.
[0005] Finally, the p.sup.+ region and n.sup.+ region function as
p.sup.+ gate and n.sup.+ gate respectively.
[0006] FIG. 2 is a sectional view showing manufacturing process of
a dual gate portion in a conventional semiconductor device. FIG. 3
is a perspective view of that dual gate portion.
[0007] As shown in FIG. 2(a), by implanting B or BF.sub.2 ion into
the polysilicone film 11 formed on the semiconductor substrate 10
such as silicone substrate, a p.sup.+ region 12 is formed, and by
implanting P or As ion, a n.sup.+ region 13 is formed. Next, as
shown in FIG. 2(b), a gate electrode metal film 14 is formed of,
for example, WSi.sub.2 over the p.sup.+ gate 12 and n.sup.+ gate
13.
[0008] As a result, as shown in FIG. 3, a semiconductor device
having dual gate is obtained in which the p.sup.+ region 12 and
n.sup.+ region 13 function as the p.sup.+ gate 12 and n.sup.+ gate
13.
[0009] However, the conventional semiconductor device has such a
fear that the impurity (for example, B or BF.sub.2) contained in
the p.sup.+ gate 12 diffuses into the n.sup.+ gate 13 through the
gate electrode metal film 14 or conversely the impurity (for
example P or As) contained in the n.sup.+ gate 13 diffuses into the
p.sup.+ gate 12 through the gate electrode metal film 14. If the
diffusion of the impurity from one region to the other region is
progressed, the characteristic of the semiconductor device is
deteriorated considerably.
[0010] FIG. 4 shows a path for the impurity implanted into each
gate region to pass through the gate electrode metal film 14 to
reach the other gate region in the conventional semiconductor
device.
[0011] Assuming that as shown in FIG. 4, the impurity moving from
the p.sup.+ gate 12 to the gate electrode metal film 14 reaches the
n.sup.+ gate 13 through the gate electrode metal film 14, the
moving distance of the impurity increases or decreases depending on
the width of the gate separating region. Likewise, assuming that
the impurity moving from the n.sup.+ gate 13 to the gate electrode
metal film 14 reaches the p.sup.+ gate 14 through the gate
electrode metal film 14, the moving distance of the impurity also
increases or decreases depending on the width of the gate
separating region.
[0012] The probability that the impurity moving from a gate to the
gate electrode metal film 14 may reach the other region increases
as the moving distance of the impurity in the gate electrode metal
film 14 decreases.
[0013] In this point, because the width of the gate separating
region in the conventional semiconductor device is small,
necessarily, the moving distance of the impurity in the gate
electrode metal film 14 is short. Therefore, in the conventional
semiconductor device, there is a fear that most of the impurity
such as B, BF.sub.2, P, As implanted into the p.sup.+ gate 12 and
n.sup.+ gate 13 may reach the other gate through the gate electrode
metal film 14 and diffuse there.
[0014] If each impurity implanted into the p.sup.+ gate 12 or
n.sup.+ gate 13 moves to the other region and diffuse there, the
physical property of the semiconductor composing the p.sup.+ gate
12 and n.sup.+ gate 13 changes, so that the electrical
characteristics of the semiconductor device deteriorate
remarkably.
SUMMARY OF THE INVENTION
[0015] The present invention has been achieved in views of the
above described problems and therefore, an object of the invention
is to provide a semiconductor device having dual gate wherein the
impurity implanted into a gate is prevented from reaching the other
gate and diffusing there.
[0016] To achieve the above object, according to a first aspect of
the invention, there is provided a semiconductor device comprising:
a first gate region composed of semiconductor containing a first
impurity; a second gate region composed of semiconductor containing
a second impurity; and a gate electrode film adjoining the first
gate region and the second gate region. In this semiconductor
device, a length of the shortest path of plural paths connecting
the first gate region to the second gate region, selected in the
gate electrode film, is longer than a diffusion distance of the
first impurity and a diffusion distance of the second impurity in
the gate electrode film.
[0017] With such a structure, the first impurity never reaches the
second gate region through the gate electrode metal film or the
second impurity never reaches the first gate region through the
gate electrode metal film.
[0018] According to a second aspect of the invention, there is
provided a semiconductor device comprising: a first gate region
composed of semiconductor containing a first impurity; a second
gate region composed of semiconductor containing a second impurity;
and a gate electrode film adjoining the first gate region and the
second gate region. In this semiconductor device, the gate
electrode film has a sectional area smaller than a diameter of
crystal grain of material composing the gate electrode film locally
in a region not adjoining the first gate region and the second gate
region.
[0019] With such a structure, the diffusion of the first impurity
and second impurity in the gate electrode film is limited
remarkably. In other words, the gate electrode film increases
so-called diffused resistance in the diffusion of the first
impurity and second impurity.
[0020] According to a third aspect of the invention, there is
provided a semiconductor device comprising: a first gate region
composed of semiconductor containing a first impurity; a second
gate region composed of semiconductor containing a second impurity;
and a gate electrode film adjoining the first gate region and the
second gate region. In this semiconductor device, the gate
electrode film has plural pits in a region not adjoining the first
gate region and the second gate region. Preferably, a gap between a
pit and the other pit nearest the pit is smaller than a diameter of
crystal grain of material composing the gate electrode film.
[0021] With such a structure, the diffusion of the first impurity
and second impurity in the gate electrode film is limited
remarkably between the respective pits.
[0022] According to a fourth aspect of the invention, there is
provided a semiconductor device comprising: a first gate region
composed of semiconductor containing a first impurity; a second
gate region composed of semiconductor containing a second impurity;
and a gate electrode film adjoining the first gate region and the
second gate region. In this semiconductor device, the gate
electrode film has a labyrinth portion for bending plural paths
connecting the first gate region to the second gate region,
selected in the gate electrode film.
[0023] With such a structure, even if the first impurity and second
impurity try to move to the second gate region and first gate
region respectively through the gate electrode film, they must move
at a long distance to pass through the labyrinth portion.
Therefore, the first impurity and second impurity move at a
diffusion distance possessed thereby before they reach the second
gate region and first gate region. Consequently, they cannot reach
the second gate region and first gate region.
[0024] According to a fifth aspect of the invention, there is
provided a semiconductor device comprising: a first gate region
composed of semiconductor containing a first impurity; a second
gate region composed of semiconductor containing a second impurity;
and a gate electrode film adjoining the first gate region and the
second gate region. This semiconductor device further comprises an
impurity trap region for trapping the first impurity invading into
the gate electrode film from the first gate region and the second
impurity invading into the gate electrode film from the second gate
region.
[0025] With such a structure, the first impurity and second
impurity diffusing in the gate electrode film are trapped by the
impurity trap region, so that they never reach the second gate
region or first gate region.
[0026] According to a sixth aspect of the invention, there is
provided a semiconductor device comprising: a first gate region
composed of semiconductor containing a first impurity; a second
gate region composed of semiconductor containing a second impurity;
and a gate electrode film adjoining the first gate region and the
second gate region. In this semiconductor device, the gate
electrode film has an impurity diffusion preventing region for
preventing diffusion of the first impurity and the second
impurity.
[0027] With such a structure, the first impurity and second
impurity diffusing in the gate electrode film is prevented from
diffusing further by the impurity diffusion preventing region.
Therefore, if the impurity diffusion preventing region is disposed
at an appropriate position in the gate electrode film, the first
impurity is prevented from reaching the second gate region and the
second impurity is prevented from reaching the first gate
region.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The above and other features of the invention and the
concomitant advantages will be better understood and appreciated by
persons skilled in the field to which the invention pertains in
view of the following description given in conjunction with the
accompanying drawings which illustrate preferred embodiments.
[0029] FIG. 1 is a sectional view of a dual gate in a semiconductor
device according to a first embodiment of the present
invention;
[0030] FIG. 2 is a sectional view showing manufacturing process of
the dual gate of a conventional semiconductor device;
[0031] FIG. 3 is a perspective view of the dual gate of the
conventional semiconductor device;
[0032] FIG. 4 is a sectional view showing a path for impurity
implanted into each gate region to reach the other gate region
through gate electrode metal film in the conventional semiconductor
device;
[0033] FIG. 5 is a sectional view showing passage of impurity
implanted in each gate region in the gate electrode metal film in
the semiconductor device according to the first embodiment of the
present invention;
[0034] FIG. 6 is a sectional view of the dual gate in the
semiconductor device according to a second embodiment of the
present invention;
[0035] FIG. 7 is a sectional view showing passage of impurity
implanted in each gate in the gate electrode metal film in the
semiconductor device according to the second embodiment of the
present invention;
[0036] FIG. 8 is a sectional view of the dual gate in the
semiconductor device according to a third embodiment of the present
invention;
[0037] FIG. 9 is a sectional view showing passage of impurity
implanted in each gate in the gate electrode metal film in the
semiconductor device according to the third embodiment of the
present invention;
[0038] FIG. 10 is a sectional view of the dual gate in the
semiconductor device according to a fourth embodiment of the
present invention;
[0039] FIG. 11 is a sectional view showing passage of impurity
implanted in each gate in the gate electrode metal film in the
semiconductor device according to the fourth embodiment of the
present invention;
[0040] FIG. 12 is a plan view of a gate electrode metal film of the
dual gate in the semiconductor device according to a fifth
embodiment of the present invention;
[0041] FIG. 13 is a plan view showing a grain boundary of the gate
electrode metal film in the semiconductor device according to a
fifth embodiment of the present invention;
[0042] FIG. 14 is a plan view of the gate electrode metal film of
the dual gate in the semiconductor device according to a sixth
embodiment of the present invention;
[0043] FIG. 15 is a plan view showing a grain boundary of the gate
electrode metal film in the semiconductor device according to the
sixth embodiment of the present invention;
[0044] FIG. 16 is a plan view of the gate electrode metal film of
the dual gate in the semiconductor device according to a seventh
embodiment of the present invention;
[0045] FIG. 17 is a perspective view of a dual gate portion in the
semiconductor device according to the seventh embodiment of the
present invention;
[0046] FIG. 18 is a plan view of the gate electrode metal film of
the dual gate in the semiconductor device according to en eighth
embodiment of the present invention;
[0047] FIG. 19 is a plan view showing passage of impurity implanted
in each gate in the gate electrode metal film in the semiconductor
device according to the eighth embodiment of the present
invention;
[0048] FIG. 20 is a plan view of the gate electrode metal film of
the dual gate in the semiconductor device according to a ninth
embodiment of the present invention;
[0049] FIG. 21 is a plan view showing passage of impurity implanted
in each gate in the gate electrode metal film in the semiconductor
device according to the ninth embodiment of the present
invention;
[0050] FIG. 22 is a sectional view of the dual gate portion in the
semiconductor device according to a tenth embodiment of the present
invention;
[0051] FIG. 23 is a sectional view showing passage of impurity
implanted in each gate in the gate electrode metal film in the
semiconductor device according to the tenth embodiment of the
present invention;
[0052] FIG. 24 is a sectional view of the dual gate portion in the
semiconductor device according to an eleventh embodiment of the
present invention; and
[0053] FIG. 25 is a sectional view showing passage of impurity
implanted in each gate in the gate electrode metal film in the
semiconductor device according to the eleventh embodiment of the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0054] Hereinafter, the preferred embodiments of the semiconductor
device of the present invention will be described in detail with
reference to the accompanying drawings. In a following description
and accompanying drawings, like reference numerals are attached to
components having substantially the same function and structure and
a description thereof is omitted.
[0055] First Embodiment
[0056] FIG. 1 indicates a sectional view of a dual gate in a
semiconductor device according to a first embodiment of the present
invention. FIG. 5 indicates a sectional view showing passage of
impurity implanted in each gate region in the gate electrode metal
film in the semiconductor device according to the first embodiment
of the present invention.
[0057] As shown in FIG. 1, the semiconductor device of this
embodiment of the present invention includes dual gate comprising
p.sup.+ gate 22 acting as a p type polysilicone gate, n.sup.+ gate
23 acting as a n type polysilicone gate and gate electrode metal
film 24.
[0058] The p.sup.+ region formed by implanting B or BF.sub.2 ion in
polysilicone film 21 formed on a semiconductor substrate 20 such as
silicone substrate functions as p.sup.+ gate 22. The n.sup.+ region
formed by implanting P or As ion into the polysilicone film 21
functions as n.sup.+ gate 23.
[0059] The gate electrode metal film 24 is formed by growing, for
example, WSi.sub.2 on the p.sup.+ region, n.sup.+ region and a gate
separating region 21 to be mentioned later. That is, the gate
electrode metal film 24 is formed over the p.sup.+ region and
n.sup.+ region across the gate separating region 21.
[0060] A wide gate separating region 21 is secured between the
p.sup.+ gate 22 and n.sup.+ gate 23. This gate separating region 21
is a non-doped polysilicone region in which such impurity as B, P,
As is not implanted. Because the wide gate separating region 21 is
provided, a gap between the p.sup.+ gate 22 and n.sup.+ gate 23 is
large. This gap, namely the width a of the gate separating region
21 is preferred to be more than 50 .mu.m.
[0061] If as shown in FIG. 5, such impurities as B, BF.sub.2, P and
As implanted in the p.sup.+ gate 22 and n.sup.+ gate 23 move to the
other gate, the impurities pass an assumed path in the gate
electrode metal film 24. However, because the gate separating
region 21 having the width a is formed between the p.sup.+ gate 22
and n.sup.+ gate 23, a distance necessary for the impurities to
move to the other gate in the gate electrode metal film 24 is
prolonged. Therefore, a probability that the impurities existing in
one gate reaches the other gate becomes very low. Particularly if
the shortest path for each impurity to pass to move from one gate
to the other gate in the gate electrode metal film 24 is longer
than a diffusion distance of each impurity in the gate electrode
metal film 24, the impurity existing in one gate never reaches the
other gate.
[0062] Further, the gate electrode metal film 24 is composed of
WSi.sub.2. The diffusion speed of the impurity in the WSi.sub.2
film is slow. Therefore, in the manufacturing process of the
semiconductor device, even if each impurity implanted in the
p.sup.+gate 22 and n.sup.+gate 23 is activated when the
semiconductor device is heated up to generally the highest heat
treatment temperature (about 1000.degree. C.), the quantity of the
impurity which reaches the other gate is very small.
[0063] Because according to the semiconductor device of this
embodiment, as described above, the width a of the gate separating
region 21 is large, the length of the gate electrode metal film 24
between the p.sup.+ gate 22 and n.sup.+ gate 23, which can be a
path for the impurity to pass, is increased. Thus, this prevents
the impurity implanted in one gate from reaching the other gate and
diffusing therein. Consequently, the characteristic of the
semiconductor device is maintained in an excellent condition.
[0064] Second Embodiment
[0065] The second embodiment of the present invention will be
described.
[0066] Meanwhile, a description of substantially the same structure
and manufacturing method as the first embodiment is omitted.
[0067] FIG. 6 shows a section of dual gate possessed by the
semiconductor device according to the second embodiment of the
present invention. FIG. 7 shows passage of the impurity implanted
in each gate region in the gate electrode metal film of the
semiconductor device according to the second embodiment of the
present invention.
[0068] The dual gate possessed by the semiconductor device of this
embodiment is formed as follows.
[0069] First, B or BF.sub.2 ion is implanted into polysilicone film
formed on a semiconductor substrate 40 such as silicone substrate
so as to form p.sup.+ region and then, P or As ion is implanted so
as to form n.sup.+ region. The p.sup.+ region formed here functions
as p.sup.+ date 42 and the n.sup.+ region functions as n.sup.+ gate
43.
[0070] A gate separating region 41 is secured between the
p.sup.+gate 42 and n.sup.+gate 43. This gate separating region 41
is a non-doped polysilicone region in which the impurity such as B,
P, As is not implanted.
[0071] Next, SiN film, which is an insulating film, is formed on an
entire surface of the polysilicone film by, for example, plasma CVD
method. The thickness of this SiN film is about 100 .ANG..
[0072] After that, the SiN film is patterned by photo etching. As
shown in FIG. 6, the patterned SiN film 44 covers a top of the gate
separating region 41, top of a region of the p.sup.+ gate 42
adjoining the gate separating region 41 and top of a region of the
n.sup.+ gate 43 adjoining the gate separating region 41.
[0073] Further, gate electrode metal film 45 is formed of, for
example, WSi.sub.2 on the top face of the p.sup.+ gate 42, n.sup.+
gate 43 and SiN film 44.
[0074] The SiN film 44 functions as a barrier for preventing the
impurity contained in each gate region from invading into the gate
electrode metal film 45.
[0075] When as shown in FIG. 7, the impurity such as B, P, As
implanted into the p.sup.+ gate 42 and n.sup.+ gate 43 moves to the
other gate, the impurity passes an assumed path in the gate
electrode metal film 45. At this time, an invasion position of the
impurity contained in each gate region into the gate electrode
metal film 45 is limited to a place far from the gate separating
region 41 by the barrier function of the SiN film 44. Thus, the
path for the impurity contained in the gate electrode metal film 45
to pass to move to the other gate is prolonged. Therefore, the
probability that the impurity existing in one gate reaches the
other gate is extremely low.
[0076] Because as described above, the semiconductor device of this
embodiment includes the SiN film 44, the impurity implanted into
one gate is prevented from reaching the other gate and from
diffusing there. Consequently, the characteristic of the
semiconductor device is maintained in an excellent condition.
[0077] Third Embodiment
[0078] The third embodiment of the present invention will be
described.
[0079] A description of substantially the same structure and
manufacturing method of the semiconductor device according to the
first and second embodiments is omitted.
[0080] FIG. 8 shows a section of dual gate possessed by the
semiconductor device according to the third embodiment of the
present invention. FIG. 9 shows passage of the impurity implanted
into each gate region in the gate electrode metal film of the
semiconductor device according to the third embodiment of the
present invention.
[0081] In the semiconductor device of this embodiment, the SiN film
44 of the semiconductor device of the second embodiment is replaced
with WN film 51.
[0082] As shown in FIG. 8, this WN film 51 covers top of the gate
separating region 41, top of a region of the p.sup.+ gate 42
adjoining the gate separating region 41 and top of a region of the
n.sup.+ gate 43 adjoining the gate separating region 41. The
thickness of the WN film 51 is about 100 .ANG..
[0083] Further, gate electrode metal film 52 is formed of, for
example, WSi.sub.2 on top face of the p.sup.+ gate 42, n.sup.+ gate
43 and WN film 51.
[0084] The WN film 51 functions as a barrier for preventing the
impurity contained in each gate from invading into the gate
electrode metal film 52.
[0085] When as shown in FIG. 9, the impurity such as B, P, As
implanted into the p.sup.+ gate 42 and n.sup.+ gate 43 moves to the
other gate, the impurity passes an assumed path in the gate
electrode metal film 52.
[0086] At this time, an invasion position of the impurity contained
in each gate region into the gate electrode metal film 52 is
limited to a place far from the gate separating region 41 by the
barrier function of the WN film 51. Thus, the path for the impurity
contained in the gate electrode metal film 52 to pass to move to
the other gate is prolonged. Therefore, the probability that the
impurity existing in one gate reaches the other gate is extremely
low.
[0087] Because as described above, the semiconductor device of this
embodiment includes the WN film 51, the impurity implanted into one
gate is prevented from reaching the other gate and diffusing there.
Consequently, the characteristic of the semiconductor device is
maintained in an excellent condition.
[0088] Further, the WN film 51 has conductivity. Therefore,
according to the semiconductor device of this embodiment, a gate
electrode having a lower electric resistance than the semiconductor
device of the second embodiment is obtained.
[0089] Fourth Embodiment
[0090] The fourth embodiment of the present invention will be
described.
[0091] A description of substantially the same structure and
manufacturing method of the semiconductor device according to the
first to third embodiments is omitted.
[0092] FIG. 10 shows a section of dual gate possessed by the
semiconductor device according to the fourth embodiment of the
present invention. FIG. 11 shows passage of the impurity implanted
into each gate region in the gate electrode metal film of the
semiconductor device according to the fourth embodiment of the
present invention.
[0093] In the semiconductor device of this embodiment, the SiN film
44 and WN film 51 of the semiconductor device of the second and
third embodiments are replaced with TiN film 61.
[0094] As shown in FIG. 10, this TiN film 61 covers top of the gate
separating region 41, top of a region of the p.sup.+ gate 42
adjoining the gate separating region 41 and top of a portion of the
n.sup.+ gate 43 adjoining the gate separating region 41. The
thickness of the TiN film 61 is about 100 .ANG..
[0095] Further, gate electrode metal film 62 is formed of, for
example, WSi2 on top face of the p.sup.+ gate 42, n.sup.+ gate 43
and TiN film 61.
[0096] The TiN film 61 functions as a barrier for preventing the
impurity contained in each gate region from invading into the gate
electrode metal film 62.
[0097] When as shown in FIG. 11, the impurity such as B, P, As
implanted into the p.sup.+ gate 42 and n.sup.+ gate 43 moves to the
other gate, the impurity passes an assumed path in the gate
electrode metal film 62.
[0098] At this time, an invasion position of the impurity contained
in each gate region into the gate electrode metal film 62 is
limited to a place far from the gate separating region 41 by the
barrier function of the TiN film 61. Thus, the path for the
impurity contained in the gate electrode metal film 62 to pass to
move to the other gate is prolonged. Therefore, the probability
that the impurity existing in one gate reaches the other gate is
extremely low.
[0099] Because as described above, the semiconductor device of this
embodiment includes the TiN film 61, the impurity implanted into
one gate is prevented from reaching the other gate and diffusing
there. Consequently, the characteristic of the semiconductor device
is maintained in an excellent condition.
[0100] Further, the TiN film 61 has conductivity. Therefore,
according to the semiconductor device of this embodiment, a gate
electrode having a lower electric resistance than the semiconductor
device of the second embodiment is obtained.
[0101] Further, because Ti has a high reactivity to Si, assuming
that composition of the TiN film 61 is Ti-rich, the TiN film 61
indicates a slight reaction to the polysilicone film in contact
with a bottom face of the TiN film 61 and gate electrode metal film
62 composed of WSi.sub.2 in contact with a top face thereof.
Therefore, adhesion between the polysilicone film, TiN film 61 and
gate electrode metal film 62 is intensified.
[0102] According to the semiconductor device of the third
embodiment, a supply of Si from the polysilicone film to the gate
electrode metal film 52 is prevented by the WN film 51. The gate
electrode metal film 62 in the semiconductor device of this
embodiment has a high adhesion to the polysilicone film and TiN
film 61 so that it is unlikely to peel off.
[0103] Fifth Embodiment
[0104] The fifth embodiment of the present invention will be
described.
[0105] A description of substantially the same structure and
manufacturing method of the semiconductor device according to the
first to fourth embodiment is omitted.
[0106] FIG. 12 is a plan view of the gate electrode metal film of
dual gate possessed by the semiconductor device according to the
fifth embodiment of the present invention. FIG. 13 shows grain
boundary of the gate electrode metal film in the semiconductor
device according to the fifth embodiment of the present
invention.
[0107] The gate electrode metal film is formed by growing, for
example, WSi.sub.2 over the p.sup.+ region, n.sup.+ region and gate
separating region between the p.sup.+ region and n.sup.+ region.
That is, the gate electrode metal film is formed over the p.sup.+
region and n.sup.+ region across the gate separating region.
[0108] As shown in FIG. 12, the gate electrode metal film is
patterned to a shape comprising three regions, namely, first gate
electrode metal region 71, second gate electrode metal region 72
and third gate electrode metal region 73 by photo etching.
[0109] The first gate electrode metal region 71 is located over the
p.sup.+ region, the second gate electrode metal region 72 is
located over the n.sup.+ region and the third gate electrode metal
region 73 is located on the gate separating region.
[0110] The width b of the third gate electrode metal region 73 is
smaller than the width of the first gate electrode metal region 71
and the width of the second gate electrode metal region 72. The
width of the third gate electrode metal region 73 is adjusted
locally to less than 0.05 .mu.m.
[0111] In the gate electrode metal film having such a structure,
the gain boundary of the WSi.sub.2 composing the first gate
electrode metal region 71, second gate electrode metal region 72
and third gate electrode metal region 73 is as shown in FIG.
13.
[0112] Usually, an average diameter (grain size) of crystal grain
of the WSi.sub.2 becomes 0.02 to 0.05 .mu.m by heat treatment in
the manufacturing process for the semiconductor device. For the
reason, in the third gate electrode metal region 73 in which the
width b is adjusted to less than 0.05 .mu.m, the grain boundary
line appears predominantly in the width direction. That is, the
WSi.sub.2 in the third gate electrode metal region 73 becomes
crystal structure in which the boundary line crosses the length
direction of the third gate electrode metal region 73 like bamboo
joint (hereinafter called bamboo structure).
[0113] When the impurity such as B, P, As implanted in the p.sup.+
gate and n.sup.+ gate moves in the gate electrode metal film, each
impurity moves along mainly the grain boundary of the
WSi.sub.2.
[0114] Consequently, the impurity invading from the p.sup.+ gate
into the first gate electrode metal film 71 cannot pass the third
gate electrode metal region 73 having the bamboo structure and it
does not reach the second gate electrode metal region 72 so that it
does not diffuse within the n.sup.+ gate.
[0115] The impurity invading into the second gate electrode metal
film 72 from the n.sup.+ gate cannot pass the third gate electrode
metal film 73 having the bamboo structure and it does not reach the
first gate electrode metal film 71 so that it does not diffuse
within the p.sup.+ gate.
[0116] According to the semiconductor device of this embodiment, as
described above, because the gate electrode metal film is provided
with the third gate electrode metal region 73 having such a small
width, the impurity implanted into one gate is prevented from
reaching the other gate and diffusing there. As a result, the
characteristic of the semiconductor device is maintained in an
excellent condition.
[0117] Sixth Embodiment
[0118] The sixth embodiment of the present invention will be
described.
[0119] A description of substantially the same structure and
manufacturing method of the semiconductor device according to the
first to fifth embodiment is omitted.
[0120] FIG. 14 is a plan view of the gate electrode metal film of
dual gate possessed by the semiconductor device according to the
sixth embodiment of the present invention. FIG. 15 shows grain
boundary of the gate electrode metal film in the semiconductor
device according to the sixth embodiment of the present
invention.
[0121] The gate electrode metal film is formed by growing, for
example, WSi.sub.2 over the p.sup.+ region, n.sup.+ region and gate
separating region between the p.sup.+ region and n.sup.+ region.
That is, the gate electrode metal film is formed over the p.sup.+
region and n.sup.+ region across the gate separating region.
[0122] As shown in FIG. 14, the gate electrode metal film is
comprised of three regions including the first gate electrode metal
film 81, the second gate electrode metal film 82 and the third gate
electrode metal film 84.
[0123] The first gate electrode metal region 81 is located over the
p.sup.+ region, the second gate electrode metal region 82 is
located over the n.sup.+ region and the third gate electrode metal
region 84 is located on the gate separating region.
[0124] The third gate electrode metal film 84 includes a plurality
of pits 83 formed by removing metal by photo etching.
[0125] A distance c between respective pits 84 is adjusted locally
to less than 0.05 .mu..
[0126] In the gate electrode metal film having such a structure,
the gain boundary of the WSi.sub.2 composing the first gate
electrode metal region 81, second gate electrode metal region 82
and third gate electrode metal region 84 is as shown in FIG.
15.
[0127] Usually, the average diameter of the crystal grain of the
WSi.sub.2 becomes about 0.02 to 0.05 .mu.m by heat treatment in the
manufacturing process for the semiconductor device. Thus, in the
third gate metal region 84 having a plurality of the pits 83 in
which the distance c is adjusted to less than 0.05 .mu.m, the
WSi.sub.2 is formed in the bamboo structure.
[0128] Consequently, the impurity invading from the p.sup.+ gate
into the first gate electrode metal film 81 cannot pass the third
gate electrode metal region 84 having the bamboo structure and it
does not reach the second gate electrode metal region 82 so that it
does not diffuse within the n.sup.+ gate.
[0129] The impurity invading into the second gate electrode metal
film 82 from the n.sup.+ gate cannot pass the third gate electrode
metal film 84 having the bamboo structure and it does not reach the
first gate electrode metal film 81 so that it does not diffuse
within the p.sup.+ gate.
[0130] According to the semiconductor device of this embodiment,
the third gate electrode metal region 84 having a plurality of the
pits 83 is provided on the gate electrode metal film. Therefore,
the impurity implanted into one gate is prevented from reaching the
other gate and diffusing there. Consequently, the characteristic of
the semiconductor device is maintained in an excellent
condition.
[0131] According to the semiconductor device of this embodiment,
the third gate electrode metal region 84 is capable of securing a
larger sectional area than the third gate electrode metal region 73
provided on the semiconductor device of the fifth embodiment.
[0132] Therefore, a rise of electric resistance between the first
gate electrode metal film 81 and the second gate electrode metal
film 82 is prevented thereby securing a gate electrode having a
smaller electric resistance.
[0133] Seventh Embodiment
[0134] The seventh embodiment of the present invention will be
described below.
[0135] Meanwhile, a description of substantially the same structure
and manufacturing method as the semiconductor device according to
the first to sixth embodiments is omitted.
[0136] FIG. 16 is a plan view of the gate electrode metal film of
dual gate possessed by the semiconductor device according to the
seventh embodiment of the present invention. FIG. 17 is a
perspective view of a dual gate portion in the semiconductor device
according to the seventh embodiment of the present invention.
[0137] The dual gate in the semiconductor device of this embodiment
is formed as follows.
[0138] First, the impurity is implanted into the polysilicone film
formed on the semiconductor substrate so as to form p.sup.+ gate 91
and n.sup.+ gate 92. A gate separating region 94 is secured between
p.sup.+ gate 91 and n.sup.+ gate 92. This gate separating region 94
is a non-doped polysilicone region in which no impurity is
implanted.
[0139] A gate electrode metal film 95 is formed over the p.sup.+
gate 91, n.sup.+ gate 92 and the gate separating region 94.
[0140] Next, the gate electrode metal film 95 and the polysilicone
film below it are patterned by photo etching. By this patterning,
as shown in FIGS. 16, 17, dual gate comprised of the gate electrode
metal film 95, p.sup.+ gate 91, n.sup.+ gate 92, gate separating
region 94 and two extended regions 93 integrated with the gate
separating region 94 is formed.
[0141] Each extended region 93 is a non-doped polysilicone region
in which no impurity is implanted like the gate separating region
94. Each extended region 93 is formed so as to be extended from the
gate separating region 94 in a direction perpendicular to a
direction in which the p.sup.+ gate 91, gate separating region 94
and n.sup.+ gate 92 are arranged continuously.
[0142] As described above, the semiconductor device according to
this embodiment has a substantially cross-like dual gate.
[0143] When the impurity contained in the p.sup.+ gate 91 and
n.sup.+ gate 92 moves to the other gate region through the gate
electrode metal film 95, most of the moving impurity is absorbed in
each extended region 93 as shown in FIG. 17. Therefore, the
probability that the impurity contained in one gate region may
reach the other gate region located at an opposite position is
extremely low.
[0144] As described above, because according to the semiconductor
device of this embodiment, the two extended regions 93 for
absorbing the impurity are provided between the p.sup.+ gate 91 and
n.sup.+ gate 92, the impurity implanted into one gate is prevented
from reaching the other gate and diffusing there. Consequently, the
characteristic of the semiconductor device is maintained in an
excellent condition.
[0145] Eighth Embodiment
[0146] The eighth embodiment of the present invention will be
described below.
[0147] Meanwhile, a description of substantially the same structure
and manufacturing method as the semiconductor device according to
the first to seventh embodiments is omitted.
[0148] FIG. 18 is a plan view of the gate electrode metal film of
dual gate possessed by the semiconductor device according to the
eighth embodiment of the present invention. FIG. 19 indicates
passage of the impurity implanted into each gate region in the gate
electrode metal film.
[0149] The dual gate in the semiconductor device of this embodiment
is formed as follows.
[0150] First, the impurity is implanted into the polysilicone film
formed on the semiconductor substrate so as to form a p.sup.+ gate
101 and a n.sup.+ gate 102. The p.sup.+ gate 101 and a n.sup.+ gate
102 are surrounded by the non-doped polysilicone region in which no
impurity is implanted. A gate separating region 104 is secured
between the p.sup.+ gate 101 and n.sup.+ gate 102. This gate
separating region 104 is also a non-doped polysilicone region in
which no impurity is implanted.
[0151] A gate electrode metal film is formed over the p.sup.+ gate
101, n.sup.+ gate 102 and the gate separating region 104.
[0152] Next, the gate electrode metal film and the polysilicone
film below it are patterned by photo etching. By this patterning,
as shown in FIG. 18, dual gate comprised of the gate electrode
metal film, p.sup.+ gate 101, n.sup.+ gate 102, gate separating
region 104 and plural extended regions 103 integrated is
formed.
[0153] Each extended region 103 is a non-doped polysilicone region
in which no impurity is implanted like the gate separating region
104. Each extended region 103 is formed so as to be extended from
the sides of the p.sup.+ gate 101 and n.sup.+ gate 102 in a
direction perpendicular to a direction in which the p.sup.+ gate
101, gate separating region 104 and n.sup.+ gate 102 are arranged
continuously.
[0154] The semiconductor device of this embodiment has a dual gate
shaped substantially in a centipede (or comb).
[0155] When the impurity contained in the p.sup.+ gate 101 and
n.sup.+ gate 102 moves to the other gate region through the gate
electrode metal film, most of the moving impurity is absorbed in
the plural extended region 103 as shown in FIG. 19. Therefore, the
probability that the impurity contained in one gate region may
reach the other gate region located at an opposite position is
extremely low.
[0156] As described above, because according to the semiconductor
device of this embodiment, the plural extended regions 103 for
absorbing the impurity are provided on the sides of the p.sup.+
gate 101 and n.sup.+ gate 102, the impurity implanted into one gate
is prevented from reaching the other gate and diffusing there.
Consequently, the characteristic of the semiconductor device is
maintained in an excellent condition.
[0157] Further, according to the semiconductor device of this
embodiment, a layout for each extended region 103 can be selected
arbitrarily thereby improving freedom of designing the gate
portion.
[0158] Ninth Embodiment
[0159] The ninth embodiment of the present invention will be
described below.
[0160] Meanwhile, a description of substantially the same structure
and manufacturing method as the semiconductor device according to
the first to eighth embodiments is omitted.
[0161] FIG. 20 is a plan view of the gate electrode metal film of
dual gate possessed by the semiconductor device according to the
ninth embodiment of the present invention. FIG. 21 indicates
passage of the impurity implanted into each gate region in the gate
electrode metal film.
[0162] The dual gate in the semiconductor device of this embodiment
is formed as follows.
[0163] First, the impurity is implanted into the polysilicone film
formed on the semiconductor substrate so as to form a p.sup.+ gate
111 and a n.sup.+ gate 112. A gate separating region 114 is secured
between the p.sup.+ gate 111 and n.sup.+ gate 112. This gate
separating region 114 is a non-doped polysilicone region in which
no impurity is implanted.
[0164] A gate electrode metal film is formed of the WSi.sub.2 over
the p.sup.+ gate 111, n.sup.+ gate 112 and the gate separating
region 114.
[0165] Next, the gate electrode metal film is patterned by photo
etching. As shown in FIG. 20, a plurality of cutout portions 113-1,
113-2 are formed on the gate electrode metal film by this
patterning. The respective cutout portions 113-1, 113-2 are located
over the p.sup.+ gate 111, n.sup.+ gate 112 and the gate separating
region 114. The plural cutout portions 113-1 are formed so as to be
extended inward from one outer edge of the gate electrode metal
film, while the plural cutout portions 113-2 are formed so as to be
extended inward from the other outer edge opposing the one outer
edge.
[0166] By provision of these cutout portions 113-1, 113-2, the gate
electrode metal film has labyrinth structure if viewed as a path
for the impurity to move.
[0167] A gap between the cutout portion 113-1 located above the
gate electrode metal film 114 and the cutout portion 113-2 is
preferred to be adjusted to less than 0.05.mu.m. As shown in FIG.
21, in a region 115 between the cutout portion 113-1 located above
the gate separating region 114 and the cutout portion 113-2, the
WSi.sub.2 composing the gate electrode metal film has the bamboo
structure.
[0168] Thus, according to the semiconductor device of this
embodiment, as same as the semiconductor device according to the
fifth and sixth embodiments, the impurity invading into the gate
electrode metal film from the p.sup.+ gate 111 cannot pass a region
115 of the gate electrode metal film having the bamboo structure,
so that it does not reach the n.sup.+ gate 112. The impurity
invading into the gate electrode metal film from the n.sup.+ gate
112 cannot pass the region 115 of the gate electrode metal film
having the bamboo structure either, so that it does not reach the
p.sup.+ gate 111.
[0169] Further, according to the semiconductor device of this
embodiment, as shown in FIG. 21, the gate electrode metal film has
the labyrinth structure, thereby preventing a linear motion of the
impurity in the gate electrode metal film. Thus, if the impurity
tries to move from one gate to the other gate, the moving distance
is prolonged, so that the probability that the impurity may reach
the other gate further decreases.
[0170] Tenth Embodiment
[0171] The tenth embodiment of the present invention will be
described below.
[0172] Meanwhile, a description of substantially the same structure
and manufacturing method as the semiconductor device according to
the first to ninth embodiments is omitted.
[0173] FIG. 22 shows a section of dual gate portion possessed by
the semiconductor device according to the tenth embodiment of the
present invention. FIG. 23 indicates passage of the impurity
implanted into each gate in the gate electrode metal film of the
semiconductor device of the tenth embodiment.
[0174] The dual gate in the semiconductor device of this embodiment
is formed as follows.
[0175] First, the impurity is implanted into the polysilicone film
formed on the semiconductor substrate 120 so as to form a p.sup.+
gate 121 and a n.sup.+ gate 122. A gate separating region is
secured between the p.sup.+ gate 121 and n.sup.+ gate 122. This
gate separating region is a non-doped polysilicone region in which
no impurity is implanted.
[0176] A gate electrode metal film 123 is formed over the p.sup.+
gate 121, n.sup.+ gate 122 and the gate separating region.
[0177] Next, non-doped silicone film is formed on the gate
electrode metal film 123 by CVD method. The thickness of this
silicone film is 0.02 to 0.1 .mu.m.
[0178] Then, the silicone film is patterned by photo etching. As
shown in FIG. 22, the silicone film 124 formed by this patterning
covers a region up to about 50 .mu.m inward of the p.sup.+ gate 121
from a boundary area between the p.sup.+ gate 121 and the gate
separating region and a region up to about 50 .mu.m inward of the
n.sup.+ gate 122 from a boundary area between the n.sup.+ gate 122
and the gate separating region as well as the gate separating
region.
[0179] When the impurity contained in the p.sup.+ gate 121 and
n.sup.+ gate 122 tries to move to the other gate region through the
gate electrode metal film, most of the moving impurity is absorbed
in the silicone film 124 as shown in FIG. 23. Therefore, the
probability that the impurity contained in one gate region may
reach the other gate region located at an opposite position is
extremely low.
[0180] As described above, because according to the semiconductor
device of this embodiment, the silicone film 124 is formed over the
gate electrode metal film 123 as a region for absorbing the
impurity, the impurity implanted into one gate is prevented from
reaching the other gate and diffusing there. Consequently, the
characteristic of the semiconductor device is maintained in an
excellent condition.
[0181] Eleventh Embodiment
[0182] The eleventh embodiment of the present invention will be
described below.
[0183] Meanwhile, a description of substantially the same structure
and manufacturing method as the semiconductor device according to
the first to tenth embodiments is omitted.
[0184] FIG. 24 shows a section of dual gate portion possessed by
the semiconductor device according to the eleventh embodiment of
the present invention. FIG. 25 indicates passage of the impurity
implanted into each gate in the gate electrode metal film of the
semiconductor device of the eleventh embodiment.
[0185] The dual gate in the semiconductor device of this embodiment
is formed as follows.
[0186] First, the impurity is implanted into the polysilicone film
formed on the semiconductor substrate 130 so as to form a p.sup.+
gate 131 and a n.sup.+ gate 132. A gate separating region is
secured between the p.sup.+ gate 131 and n.sup.+ gate 132. This
gate separating region is a non-doped polysilicone region in which
no impurity is implanted.
[0187] A gate electrode metal film 133 is formed over the p.sup.+
gate 131, n.sup.+ gate 132 and the gate separating region.
[0188] Next, as shown in FIG. 24, N ion is implanted into the gate
electrode metal film 133 so as to form a N doping region 134. This
N doping region 134 covers a region up to about 50 .mu.m inward of
the p.sup.+ gate 131 from a boundary area between the p.sup.+ gate
131 and the gate separating region and a region up to about 50
.mu.m inward of the p.sup.+ gate 132 from a boundary area between
the n.sup.+ gate 132 and the gate separating region as well as the
gate separating region.
[0189] When the impurity contained in the p.sup.+ gate 131 and
n.sup.+ gate 132 moves to the other gate region through the gate
electrode metal film 133, a diffuison of the impurity is prevented
by the N doping region 134 as shown in FIG. 25. Therefore, the
probability that the impurity contained in one gate region may
reach the other gate region located at an opposite position is
extremely low.
[0190] As described above, because according to the semiconductor
device of this embodiment, the N doping region 134 is formed in the
gate electrode metal film 123, the impurity implanted into one gate
is prevented from reaching the other gate and diffusing there.
Consequently, the characteristic of the semiconductor device is
maintained in an excellent condition.
[0191] The preferred embodiments of the present invention have been
described with reference to the accompanying drawings. However, the
present invention is not restricted to these embodiments. It is
apparent to those skilled in the art that the present invention may
be modified or corrected in various ways within a scope of
technical philosophy described in the claims of the present
invention and needless to say, they also belong to the technical
field of the present invention.
[0192] As described above, according to the present invention, a
first impurity contained in a first gate region is prevented from
reaching a second gate region through a gate electrode film and a
second impurity contained in a second gate region is prevented from
reaching the first gate region through the gate electrode film.
Thus, the characteristic of the semiconductor device is maintained
in an excellent condition.
* * * * *