U.S. patent application number 09/864406 was filed with the patent office on 2001-12-20 for memory system and programming method thereof.
This patent application is currently assigned to Sony Corporation. Invention is credited to Hashiguchi, Akihiko, Kosaka, Hideo, Okaue, Takumi.
Application Number | 20010053092 09/864406 |
Document ID | / |
Family ID | 18681785 |
Filed Date | 2001-12-20 |
United States Patent
Application |
20010053092 |
Kind Code |
A1 |
Kosaka, Hideo ; et
al. |
December 20, 2001 |
Memory system and programming method thereof
Abstract
A memory system and its programming method capable of reducing
programming time for each page versatility thereof is high, wherein
the memory cell array is constituted, by a MONOS-type (MNOS-type)
non-volatile memory or floating gate non-volatile memory in which a
source side channel hot electron injection that enables the memory
to write therein data by each divided unit (for instance, each 64
bytes=512 bits) is carried out, instead of the write operation
where writing is carried out collectively by each page unit (512
bytes). Further, there is provided an emulation circuit
successively storing programming data that constitutes the page of
a plurality of divided units, and a control circuit successively
reading the held divided unit data so as to write to the
non-volatile memory.
Inventors: |
Kosaka, Hideo; (Kanagawa,
JP) ; Hashiguchi, Akihiko; (Kanagawa, JP) ;
Okaue, Takumi; (Kanagawa, JP) |
Correspondence
Address: |
RADER FISHMAN & GRAUER PLLC
LION BUILDING
1233 20TH STREET N.W., SUITE 501
WASHINGTON
DC
20036
US
|
Assignee: |
Sony Corporation
|
Family ID: |
18681785 |
Appl. No.: |
09/864406 |
Filed: |
May 25, 2001 |
Current U.S.
Class: |
365/185.19 |
Current CPC
Class: |
G11C 16/0466 20130101;
G11C 16/10 20130101 |
Class at
Publication: |
365/185.19 |
International
Class: |
G11C 016/04 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 12, 2000 |
JP |
P2000-180761 |
Claims
What is claimed is:
1. A memory system in which a program is completed with a page as a
unit, comprising: an intermediate circuit successively holding
program data that forms said page in a division unit where the
program data are divided into a plurality of division units; a
memory cell array in which a plurality of memory cells each
including at least one memory transistor having a control gate
controlling a charge accumulating means and a charge quantity
accumulated in said charge accumulating means, and at least one
selection transistor having a shared channel formation region and
said memory transistor are arranged, and in which the plurality of
memory cells arranged in a direction of a word line are connected
in a cascade connection; word lines to which a gate of the
selection transistor of each memory cell cascade-connected in the
direction of said word line are commonly connected; and a control
circuit successively reading the divided unit data held in said
intermediate circuit when programming, electrically dividing said
memory cell array in every interval of a plurality of the memory
cells in response to said division unit in the direction of the
word line by driving the control gate of said memory transistor,
and writing said division unit data to said memory cell array by
parallel applying programming pulses to the control gates of the
memory transistors in a predetermined bit unit.
2. A memory system according to claim 1, wherein said control
circuit carries out an application of the programming pulse in
parallel, and continuously carries out the verification in all the
same bit unit.
3. A memory system according to claim 1, wherein the charge
accumulating means of said memory cell comprises an insulating film
including a nitride film.
4. A memory system according to claim 1, wherein said memory cell
includes a first memory transistor, a second memory transistor and
a selection transistor formed to have a common channel formation
region between said first memory transistor and said second memory
transistor, and the charge accumulating means of both said memory
transistor and said second memory transistor is included in the
insulating film including the nitride film, and the first memory
transistor of one memory cell and the second memory transistor of a
memory cell adjacent to said one memory,cell commonly having an
insulating film as the control gate and the charge accumulating
means.
5. A memory system in which a program is completed with a page as a
unit comprising: a plurality of divided circuits each having an
intermediate circuit successively holding programming data that
forms said page in a division unit where the program data is
divided into a plurality of division units, a memory cell array in
which a plurality of memory cells including at least one memory
transistor having a control gate controlling a charge accumulating
means and a charge quantity accumulated in said charge accumulating
means, and at least one selection transistor having a shared
channel formation region and said memory transistor are arranged,
and in which the plurality of memory cells arranged in the
direction of a word line are connected in a cascade connection; and
word lines to which a gate of the selection transistor of each
memory cell cascade-connected in the direction of said word line
are connected commonly; and a control circuit constituting pages in
such a way as to range over a plurality of divided circuits,
successively reading a divided unit data held in said intermediate
circuit when programming, electrically dividing said memory cell
array at intervals of a plurality of the memory cells corresponding
to said divided unit in the direction of the word line by driving
the control gate of said memory transistor of each divided circuit,
and writing said divided unit data to said memory cell array by
applying programming pulses in parallel to the control gate of the
memory transistor in a predetermined bit unit with ranging over the
plurality of divided circuits.
6. A memory system according to claim 5, wherein said control
circuit carries out the programming pulse application in parallel,
continuously carries out the verification in every the same bit
unit.
7. A memory system according to claim 5, wherein the charge
accumulating means of said memory cell comprises an insulating film
including a nitride film.
8. A memory system according to claim 5, wherein said memory cell
includes a first memory transistor, a second memory transistor and
a selection transistor formed to have a common channel formation
region between said first memory transistor and said second memory
transistor, and said charge accumulating means of both said memory
transistor and said second memory transistor is included in the
insulating film including the nitride film, and the first memory
transistor of one memory cell and the second memory transistor of a
memory cell adjacent to said one memory cell commonly having an
insulation film as the control gate and the charge accumulating
means.
9. A programming method for a memory system having a memory cell
array in which a plurality of memory cells each including at least
one memory transistor having a control gate controlling a charge
accumulating means and a charge quantity accumulated in said charge
accumulating means, and at least one selection transistor having a
shared channel formation region and said memory transistor are
arranged, and in which a plurality of memory cells arranged in a
direction of a word line are connected in a cascade connection, and
in which a programming is completed with a page as a unit,
comprising the steps of: successively holding programming data that
forms a page in a division unit where the program data is divided
into a plurality of division units; successively reading the held
divided unit data; electrically dividing said memory cell array in
every interval of a plurality of memory cells corresponding to said
divided unit in the direction of the word line by driving the
control gate of said memory transistor; and successively writing
said divided unit data to said memory cell array by carrying out
parallel programming pulse application to the control gate of the
memory transistor in a predetermined bit unit.
10. A programming method of the memory system according to claim 9,
wherein writing of the divided unit data is executed in such a way
as to carry out programming pulse application in parallel, and to
carry out the verification of the same bit unit continuously.
11. A programming method for a memory system having a plurality of
divided circuits each including a memory cell array in which a
plurality of memory cells each including at least one memory
transistor having a control gate controlling a charge accumulating
means and a charge quantity accumulated in said charge accumulating
means, and at least one selection transistor having a shared
channel formation region and said memory transistor are arranged,
and in which a plurality of memory cells arranged in the direction
of a word line are connected in a cascade connection, in which a
programming is completed with a page as a unit, comprising the
steps of: successively holding programming data that forms a page
in a division unit, where the program data is divided into a
plurality of division units; forming said page in such a way as to
range over a plurality of divided circuits; successively reading
the held divided unit data; electrically dividing said memory cell
array in every interval of a plurality of memory cells
corresponding to said divided unit in the direction of the word
line by driving the control gate of said memory transistor of each
said divided circuit; and successively writing said divided unit
data to said memory cell array by carrying out parallel programming
pulse application to the control gate of the memory transistor in a
predetermined bit unit ranging over a plurality of divided
circuits.
12. The programming method of the memory system according to claim
11, wherein writing of the divided unit data is executed in such a
way as to carry out programming pulse application in parallel, and
to carry out the verification of the same bit unit continuously.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a memory system and its
programming method using a non-volatile memory in which writing is
carried out by every page unit.
[0003] 2. Description of the Related Art
[0004] FIG. 21 is a block diagram illustrating configuration
example of a conventional memory system using an NAND type flash
memory array.
[0005] This memory system 1 has a control portion 2 and a memory
portion 3, as a main configuration component.
[0006] The control portion 2 has a page buffer 21, an error
correction circuit (ECC) 22, a write register (WR.Reg) 23, a read
register (RD.Reg.) 24, a command register (Command Reg.) 25, a
configuration ROM (Config ROM) 26, an external interface 27 for
performing serial (S)/parallel (P) conversion of write data from
the external portion and for performing parallel (P)/serial (S)
conversion of read data from the memory portion 3 to output to the
external portion, and a memory interface 28.
[0007] Further, the memory portion 3 has a memory cell array 32 in
which an NAND type flash memory array is arranged, a register 31
and a control circuit which is not illustrated.
[0008] Note, the data register 31 is constituted by a command
register, a data register and other register(s).
[0009] Programming (write) operation of this memory system will be
explained.
[0010] Conventionally, in a non-volatile memory such as an NAND
type flash memory, since programming (write) speed of a memory
itself is slow, for instance, as illustrated in FIG. 22A, the page
buffer 21 stores therein data once.
[0011] Next, as illustrated in FIG. 22B, data is transferred by
means of internal transfer from the page buffer 21 to the register
31 of the memory portion 3.
[0012] Then, as illustrated in FIG. 22C, finally, the processing is
made to execute collectively the programming of data for one page
(for instance, data for 512 bytes connected 1 word line), namely,
the programming of the memory cell array for one page data from the
register 31 is executed.
[0013] FIG. 23 is a schematic view illustrating programming timing
of the NAND type flash memory.
[0014] In the programming of the NAND type flash memory, as
illustrated in FIG. 23, a command (CMD) is input to the register 31
in the period t1, the input is made to execute an address (ADR) is
input to the register 31 in the subsequent period t2, and the data
for one page of 512 bytes is input to the register 31 in the
further subsequent period t3.
[0015] Then, writing is made to execute collectively data for one
page of 512 bytes input in the period t4 in accordance with the
input command and address.
[0016] As described above, in the conventional memory system, since
the NAND type flash memory that is capable of carrying out
collectively writing for each page is employed and writing is made
to execute collectively one page for data to be programmed by each
page, a total programming time required for input of command,
address and data, further actual programming is long (maximum
writing time of one page is up to about 1500 .mu.s), and thus it
may be difficult to apply to such the NAND type flash memory to a
memory system such as a memory card which requires high speed
operation.
SUMMARY OF THE INVENTION
[0017] An object of the present invention is to provide a memory
system and its programming method capable of shortening a
programming time for each page and applicable in a variety
systems.
[0018] In order to achieve the above-mentioned object, according to
a first aspect of the present invention, there is provided a memory
system in which a program is completed with a page as a unit,
comprising: an intermediate circuit successively holding program
data that forms the page in a division unit where the program data
is divided into a plurality of division units; a memory cell array
in which a plurality of memory cells each including at least one
memory transistor having a control gate controlling a charge
accumulating means and a charge quantity accumulated in the charge
accumulating means, and at least one selection transistor having a
shared channel formation region and the memory transistor are
arranged, and in which the plurality of memory cells arranged in a
direction of a word line are connected in a cascade connection;
word lines to which gates of the selection transistors of each
memory cell cascade-connected in the direction of the word line are
commonly connected; and a control circuit successively reading the
divided unit data held in the intermediate circuit when
programming, electrically dividing the memory cell array in every
interval of a plurality of the memory cells in response to the
division unit in the direction of the word line by driving the
control gate of the memory transistor, and writing the division
unit data to the memory cell array by parallel applying programming
pulses to the control gates of the memory transistors in a
predetermined bit unit.
[0019] In accordance with a second aspect of the present invention,
there is provided a-memory system in which a program is completed
with a page as a unit comprising: a plurality of divided circuits
each having an intermediate circuit successively holding
programming data that forming a page(s) in a division unit where
the program data is divided into a plurality of division units, a
memory cell array in which a plurality of memory cells including at
least one memory transistor having a control gate controlling a
charge accumulating means and a charge quantity accumulated in the
charge accumulating means, and at least one selection transistor
having a shared channel formation region and the memory transistor
are arranged, and in which the plurality of memory cells arranged
in the direction of a word line are connected in cascade
connection; and word lines to which a gate of the selection
transistor of each memory cell cascade-connected in the direction
of the word line are connected commonly; and a control circuit
constituting pages in such a way as to range over a plurality of
divided circuits, successively reading a divided unit data held in
the intermediate circuit when programming, electrically dividing
the memory cell array at intervals of a plurality of the memory
cells corresponding to the divided unit in the direction of the
word line by driving the control gate of the memory transistor of
each divided circuit, and writing the divided unit data to the
memory cell array by applying programming pulses in parallel to the
control gate of the memory transistor in a predetermined bit unit
with ranging over the plurality of divided circuits.
[0020] The control circuit may carry out an application of the
programming pulse application in parallel, and continuously carries
out the verification in all the same bit unit.
[0021] The charge accumulating means of the memory cell may include
an insulating film including a nitride film.
[0022] The memory cell may include a first memory transistor, a
second memory transistor and a selection transistor formed to have
a common channel formation region between the first memory
transistor and second memory transistor, and the charge
accumulating means of both the memory transistor and second memory
transistor is included in the insulating film including the nitride
film, and the first memory transistor of one memory cell and the
second memory transistor of a memory cell adjacent to the one
memory cell commonly having an insulating film as the control gate
and the charge accumulating means.
[0023] In accordance with a third aspect of the present invention,
there is provided a programming method for a memory system having a
memory cell array in which a plurality of memory cells each
including at least one memory transistor having a control gate
controlling a charge accumulating means and a charge quantity
accumulated in the charge accumulating means, and at least one
selection transistor having a shared channel formation region and
the memory transistor are arranged, and in which a plurality of
memory cells arranged in a direction of a word line are connected
in a cascade connection, and in which a programming is completed
with a page as a unit, comprising the steps of: successively
holding programming data that forms a page in a division unit where
the program data is divided into a plurality of division units;
successively reading the held divided unit data; electrically
dividing the memory cell array in every interval of a plurality of
memory cells corresponding to the divided unit in the direction of
the word line by driving the control gate of the memory transistor;
and successively writing the divided unit data to the memory cell
array by carrying out parallel programming pulse application to the
control gate of the memory transistor in a predetermined bit
unit.
[0024] According to a fourth aspect of the present invention, there
is provided a programming method for a memory system having a
plurality of divided circuits each including a memory cell array in
which a plurality of memory cells including at least one memory
transistor having a control gate controlling a charge accumulating
means and a charge quantity accumulated in the charge accumulating
means, and at least one selection-transistor having a shared
channel formation region and memory transistor are arranged, and in
which a plurality of memory cells arranged in the direction of a
word line are connected in a cascade connection, in which a
programming is completed with a page as a unit, comprising the
steps of: successively holding programming data that constitutes a
page in a division unit, where the program data is divided into a
plurality of division units; forming the page in such a way as to
range over a plurality of divided circuits; successively reading
the held divided unit data; electrically dividing the memory cell
array in every interval of a plurality of memory cells
corresponding to the divided unit in the direction of the word line
while driving the control gate of the memory transistor of each the
divided circuit; and successively writing the divided unit data to
the memory cell array by carrying out a parallel programming pulse
application to the control gate of the memory transistor in a
predetermined bit unit ranging over the plurality of divided
circuits.
[0025] In the present invention, the program data with a page as a
unit is held successively with a plurality of divided units that
constitute a page of the programming data. Then, simultaneous
programming pulse application is made to carry out, for instance,
against the bit units existing in every interval of several bits on
the word line, followed by carrying out the verification of the
same bit units continuously, thus writing is made to carry out in
every divided unit data.
[0026] Also, in the present invention, the page is constituted in
such a way as to ranging over a plurality of divided circuits, for
instance, in such a way as to range over a plurality of chips or a
plurality of mats, then for instance, simultaneous programming
pulse application is made to carry out against the bit units
existing in every intervals of several bits on the word line with
ranging over a plurality of chips or a plurality of mats, followed
by carrying out the verification of the same bit units
continuously, thus writing is made to carry out in every divided
unit data.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] These and other objects and features of the present
invention will become clearer from the following description of the
preferred embodiments given with reference to the accompanying
drawings, in which:
[0028] FIG. 1 is a block configuration view illustrating one
embodiment of a memory system according to the present
invention;
[0029] FIG. 2 is a block diagram illustrating configuration of a
main part of the memory portion according to the embodiment of the
present invention;
[0030] FIG. 3 is an equivalent circuit view illustrating the
control gate separation type memory cell array according to the
present embodiment;
[0031] FIG. 4 is a schematic portional view along the direction of
a word line of the control gate separation type memory cell array
according to the present embodiment;
[0032] FIG. 5 is a plan view of a part (one row of FIG. 2) of the
control gate separation type memory cell array according to the
present embodiment;
[0033] FIG. 6 is an equivalent circuit view illustrating the
control gate shared type memory cell array according to the present
embodiment;
[0034] FIG. 7 is a schematic portional view along the direction of
the word line of the control gate shared type memory cell array
according to the present embodiment;
[0035] FIG. 8 is a plan view of a part (one row of FIG. 2) of the
control gate shared type memory cell array according to the present
embodiment;
[0036] FIG. 9 is a view explaining source side injection;
[0037] FIG. 10 is a portional view illustrating concrete
configuration example of a MONOS type memory transistor;
[0038] FIG. 11 is a view illustrating programming condition to the
control gate separation type memory cell array;
[0039] FIG. 12 is a view illustrating programming condition to the
control gate shared type memory cell array;
[0040] FIG. 13 is a view illustrating the example of the number of
the programming pulse application to a bit on the word line;
[0041] FIG. 14 is a view illustrating configuration example of
programming cycle;
[0042] FIG. 15 is a view illustrating the number of programming
pulse application of one page according to a first programming
method;
[0043] FIG. 16 is a view illustrating the number of programming
pulse application of one page according to a second programming
method;
[0044] FIG. 17 is a view explaining page configuration where one
page is divided into 8 chips;
[0045] FIG. 18 is a view illustrating the number of programming
pulse application of one page according to a third programming
method;
[0046] FIGS. 19A and 19B are views illustrating the concept of
division of the memory cell array according to the present
embodiment;
[0047] FIG. 20 is a view explaining effects of the present
invention;
[0048] FIG. 21 is a block diagram illustrating configuration
example of the conventional memory system;
[0049] FIGS. 22A to 22C are views explaining about programming
(write) operation of the conventional memory system; and
[0050] FIG. 23 is an explaining view about programming time of the
conventional memory system
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0051] Below, preferred embodiments of the present invention will
be described with reference to the accompanying drawings.
[0052] FIG. 1 is a block configuration view illustrating a first
embodiment of a memory system according to the present
invention.
[0053] This memory system 100 has a control portion 110 and a
memory portion 120, as main configuration components.
[0054] The control portion 110 has an error correction circuit
(ECC) 111, a write register (WR.Reg) 112, a read register (RD.
Reg.) 113, a command register (Command Reg.) 114, a configuration
ROM (Config ROM) 115, an external interface 116 for performing
serial(S)/parallel (P) conversion of write data from the external
portion and for performing parallel(P)/serial(S) conversion of read
data from the memory portion 120 to output to the external portion,
and a memory interface 117.
[0055] Further, the memory portion 120 has a memory cell array 121
in which non-volatile memory cells are arranged, an intermediate
circuit (emulation circuit) 122 and a control circuit 123, as main
components.
[0056] This memory system 100 is different from the conventional
memory system explained with reference to FIG. 21, on the points
that the memory cell array is configured by a non-volatile memory
capable of writing therein data by each divided unit (for instance,
each 64 bytes=512 bits) other than collectively writing by each
page (512 bytes), the program data which constitutes each page are
successively held in a division unit divided a plurality of program
data, and the held division unit data are successively read and
stored. As a result, the circuit configuration of the present
memory system is different from the conventional circuit in that
the control portion 11 is not provided with the page buffer, and a
concrete circuit configuration of the memory portion 120 is
different therefrom.
[0057] The concrete circuit configuration of the memory portion 120
and the programming method according to the present embodiment of
the present invention will be described in detail bellow with
reference to accompanying drawings.
[0058] FIG. 2 is a block diagram illustrating a main configuration
of the memory portion 120 according to the embodiment of the
present invention.
[0059] This memory portion 120 has a row decoder 124, a column
decoder 125 and an input/output circuit 126, in addition to the
aforementioned the memory cell array 121, the emulation circuit 122
and the control circuit 123.
[0060] In FIG. 2, circuits for switching operating mode responsive
to the reception of enable signals of read, write or erase,
circuits for controlling operating timing on the basis of clock,
power-supply circuit, address buffer, and other circuit are not
illustrated.
[0061] Note, the input/output circuit 4 in FIG. 2 includes all the
circuits of the bit line side necessary for write or read, such as
a column selection circuit CS, a sense amplifier SA, a write
circuit WR, and an input/output buffer I/OBUF.
[0062] The emulation circuit 122 has a register 1221 for, for
example, command CMD and address ADR, and data registers 1222 and
1223. When programming, in the emulation circuit 122, the register
1221 stores the command CMD and the address ADR therein, register
1221 stores divided unit data (for example, 64 bytes=512 bits)
therein and the register 1223 stores collectively the division data
therein, these registers inform the storage to the control circuit
123, and the output of the data stored in the registers to the
input/output circuit 126 is carried out under the control of the
control circuit 123.
[0063] The control circuit 123, as described later, drives the
control gate of the memory transistor of the memory cell array 121,
electrically divides the memory cell array in the direction of the
word line in each plurality of memory cells corresponding to the
aforementioned divided unit in a parallel application of
programming pulses to the control gate of the memory transistor in
the predetermined bit unit, and successively writes the divided
unit data read out on the input/output circuit 126 to the memory
cell array. At this time, the control circuit 123 carries out the
parallel programming pulse application, and the verification of the
same bit unit continuously.
[0064] The row decoder 124 receives the address signal ADR, selects
all or any one of a plurality of the word lines WL arranged in the
memory cell array 121 in response to the received address signal
ADR, and changes voltages of the selected word lines WL
corresponding to read, write or erase to activate the same.
[0065] The column decoder 125 receives the address signal ADR,
controls a column selection circuit CS in the input/output circuit
126 in response to the received address signal ADR, and selects a
plurality of the bit lines BL arranged in the memory cell array
121, for instance, in every predetermined number of the bit
lines.
[0066] The column selection circuit CS connects all of the selected
bit lines to the sense amplifiers SA when reading, and connects all
of the selected bit lines to the write circuit WR when writing.
[0067] When reading, the data stored in the memory cell is detected
from the selected bit line BL by the sense amplifier SA through the
column selection circuit CS. The detected result is accumulated at
a predetermined address in the input/output buffer I/OBUF.
[0068] As described later, the reason of why of the data
accumulation is that the collectively read data in the present
embodiment are arranged discrete in every predetermined bits. When
all one line storage data becomes complete by plural number of
reads, the data are output to an external data bus or the like as
read data D.sub.out, for instance, in a predetermined word
unit.
[0069] Or, the discretely read data may not be buffered to handle
one line storage data itself, and output to the external data bus
or the like.
[0070] Further, when programming, the divided unit data D.sub.in
from the emulation circuit 122 is accumulated once in the
input/output buffer I/OBUF. Then, write of one line data is made to
execute into the memory cell while converting the bit line voltage
into threshold voltage of the memory transistor due to plural
numbers of write operation, with a plurality of the bit lines BL
discretely selected by the column selection circuit as a unit.
[0071] Or, when the divided unit data D.sub.in is sent as discrete
writing one line storage data, it is suitable to successively write
it in the memory cell array without buffering the input data.
[0072] As described later in detail, in the memory cell array 121
according to the present embodiment, there are provided the control
gate line CL and the bit line BL that make a pair as common lines
in the direction of the bit line. The control line CL is in one
case where one control line CL and one bit line BL exist, while in
other case two control lines CL and one bit line BL exist.
[0073] These control lines CL are connected to the control circuit
5.
[0074] The control circuit 123 receives control signal decoded at
the column decoder 125, followed by dividing memory cell line
connected to one word line electrically in accordance with the rule
established beforehand, further changing the divided portion.
[0075] Concretely, voltage of the control gate line CL to be the
divided portion is made to switch from initial voltage to
interrupting voltage, and when removing the divided portion,
voltage of the control gate line CL to be the divided portion is
made to switch from the interrupting voltage to the initial
voltage.
[0076] An example of construction of the memory cell array 121 will
be explained with reference to FIG. 3 to FIG. 8 below, then
programming operation according to the present embodiment will be
explained in detail.
[0077] One memory cell according to the present embodiment has a
configuration in which selection transistor ST is arranged between
two memory transistors MT1, MT2 having a charge accumulated layer
CAM. In structure, a selection gate (word line W1 in the drawing)
is arranged at the center portion between source-drain regions of
the one memory cell, and the charge accumulated layer CAM in which
charge accumulated quantity is controlled according to a voltage
applied to the control gate CG is arranged at the both sides of the
selection gate.
[0078] Further, in the memory cell array 121 according to the
present embodiment, the selection gate of the selection transistor
ST of respective memory cells MCij is connected to the word line
WL, both the source and drain regions are connected to the bit line
BL, the control gate line CL for controlling the charge accumulated
layer has an array structure arranged in parallel to the bit line
BL.
[0079] Further, in the present embodiment, a storage data in one
charge accumulated layer CAM is assumed as 1 bit. In the memory
cell according to the present embodiment, since one selection gate
stands opposite to two bits, a memory cell size per bit is
small.
[0080] Furthermore, the control gate CG and the word line WL are
formed of polysilicon or the like. The bit line BL is formed by an
n.sup.+ diffusion layer.
[0081] The memory cell array 121 according to the present
embodiment can adopt two kinds of array constructions in which one
is constituted in such a way as to separate the control gate from
that of the memory cell adjacent thereto in the direction of the
word line, while the other is constituted in such a way as to hold
the control gate in common that is adjacent thereto in the
direction of the word line. Concretely, the memory cell array 121
can adopt two kinds of array construction of control gate separated
type and control gate shared type.
[0082] The control gate separation memory cell array is illustrated
in FIG. 3 to FIG. 5.
[0083] FIG. 3 is an equivalent circuit view illustrating the
control gate separation memory cell array. FIG. 4 is a schematic
portional view in the direction of the word line of the control
gate separation memory cell array. FIG. 5 is a plan view of a part
(1 column of FIG. 3) of the control gate separation memory cell
array.
[0084] In the control gate separation memory cell array 121A, as
illustrated in FIG. 3, for instance, i.times.j pieces of memory
transistors MC11, MC12, . . . , MC21, MC22, . . . , Mcij are
arranged in a matrix manner.
[0085] In FIG. 3, for simplification of the illustration, 2 rows
and 4 columns (2.times.4) of 8 pieces of memory cells MC11, MC12,
MC13, MC14, MC21, MC22, MC23, and MC24 are only illustrated.
[0086] As illustrated in FIG. 3, respective memory cells MC11 to
MC24, as described above, adopt a configuration in which the
selection transistor ST is arranged in such a way as to share a
channel formation region between the first memory transistor MT1
and the second memory transistor MT2 with the charge accumulated
layer CAM.
[0087] The gates of the selection transistors ST of the memory
cells MC11 to MC14 thus arranged in the first row are connected
commonly to the word line WL1, and the gates of the selection
transistors ST of the memory cells MC21 to MC24 thus arranged in
the second row are connected commonly to the word line WL2.
[0088] Actually, as illustrated in FIG. 4, the gate of the
selection transistor ST is constituted by the word line WL.
[0089] Further, the control gate of each first memory transistor
MT1 of the memory cells MC11 and MC21 thus arranged in first column
is connected to common control gate line CLL1, and the control gate
of each second memory transistor MT2 is connected to common control
gate line CLR1.
[0090] Similarly, the control gate of each first memory transistor
MT1 of the memory cells MC12 and MC22 thus arranged in the second
column is connected to common control gate line CLL2, and the
control gate of each second memory transistor MT2 is connected to
common control gate line CLR2.
[0091] The control gate of each first memory transistor MT1 of the
memory cells MC13 and MC23 thus arranged in the third column is
connected to common control gate line CLL3, and the control gate of
each second memory transistor MT2 is connected to common control
gate line CLR3.
[0092] The control gate of each first memory transistor MT1 of the
memory cells MC14 and MC24 thus arranged in the fourth column is
connected to common control gate line CLL4, and the control gate of
each second memory transistor MT2 is connected to common control
gate line CLR4.
[0093] Further, as illustrated in FIG. 4, the sources of the
respective first and second memory transistors MT1, MT2 are
connected to the drain region of another memory transistor adjacent
to one side of the word line direction, and the drain of the
respective memory transistors are connected to the source of
another memory transistor adjacent to the other side of the word
line direction. These common source and drain are constituted by a
line shaped source-drain impurity region that connects another
drain in the direction of the bit line with connecting portion of
the drain.
[0094] The respective source-drain impurity regions formed in such
a manner, as illustrated in FIG. 5, come to parallel stripe shaped
pattern in the whole memory cell array.
[0095] In the present embodiment, these source-drain impurity
regions are employed as the bit lines BL1, BL2, BL3, . . . as they
are.
[0096] However, it is suitable that there are provided bit lines
BL1, BL2, BL3, . . . made of metal wiring layer on the upper layer
of respective source-drain impurity regions. In this case,
respective bit lines BL1, BL2, BL3, . . . are wired in the
direction of the bit line while making contact appropriately with
corresponding lower layer of the source-drain impurity region.
[0097] The control gate shared memory cell array is illustrated in
FIG. 6 to FIG. 8.
[0098] FIG. 6 is an equivalent circuit view illustrating the
control gate shared memory cell array. FIG. 7 is a schematic
portional view along the direction of the word line of the control
gate shared memory cell array. FIG. 8 is a plan view of a part
(first column of FIG. 6) of the control gate shared memory cell
array.
[0099] In the control gate shared memory cell array 121A, as
illustrated in FIG. 6 that is the same as the control gate
separation memory cell array 121A of FIG. 3, for instance,
i.times.j pieces of memory transistors MC11, MC12, . . . , MC21,
MC22, . . . , Mcij are arranged in a matrix shape.
[0100] In FIG. 6, for simplification of the illustration, 2 rows
and 4 columns (2.times.4) of 8 pieces of memory cells MC11, MC12,
MC13, MC14, MC21, MC22, MC23, and MC24 are only illustrated.
[0101] The control gate shared memory cell array 121B is different
from the control gate separation memory cell array in that the
first and the second memory transistors MT1 and MT2 of the
respective memory cells and the memory transistors MT2 and MT1 of
the adjacent memory cell have the control gate CG in common, and
the first and the second memory transistors MT1 and MT2 of the
memory cell connected in the same column are connected to common
control gate line CL.
[0102] Concretely, the control gates of the respective first memory
transistors MT1 of the memory cells MC11 and MC21 arranged in the
first column are connected to the control gate line CL0 common to
the control gate of the second memory transistor MT2 of not
illustrated memory cells MC10 and MC20 which are positioned in the
neighbor on the left in the drawing, and the control gates of the
respective second memory transistors MT2 of the memory cells MC11
and MC21 are connected to the control gate line CL1 common to the
control gate of the first memory transistor MT1 of the memory cells
MC12 and MC22 which are positioned in the neighbor on the right in
the drawing.
[0103] Similarly, the control gates of the respective second memory
transistors MT2 of the memory cells MC12 and MC22 are connected to
the control gate line CL2 common to the control gate of the first
memory transistor MT1 of the memory cells MC13 and MC23 which are
positioned in the neighbor on the right in the drawing.
[0104] The control gates of the respective second memory
transistors MT2 of the memory cells MC13 and MC23 are connected to
the control gate line CL3 common to the control gate of the first
memory transistor MT1 of the memory cells MC14 and MC24 which are
positioned in the neighbor on the right in the drawing.
[0105] The control gates of the respective second memory
transistors MT2 of the memory cells MC14 and MC24 are connected to
the control gate line CL4 common to the control gate of the first
memory transistor MT1 of the memory cells MC15 and MC25 which are
positioned in the neighbor on the right in the drawing.
[0106] Since another construction is the same as that of the
aforementioned control gate separation memory cell array, here, the
detailed explanation is omitted.
[0107] As to the charge accumulated layer CAM, in the case of the
control gate separated type, the charge accumulated layer CAM is a
floating gate (FG) or an insulating film including nitride film,
while in the case of the control gate shared type, the charge
accumulated layer CAM is an insulating film including nitride film
capable of carrying out discrete trap.
[0108] For instance, in the respective memory transistors MT1 and
MT2, in the case of MONOS-type, at the insulating film portion
directly under the control gate, a laminated construction of a
plurality of insulating films including boundary between the oxide
film and the nitride film.
[0109] Further, in the case of FG type or nano-crystal type, at
least a plurality of insulating films are formed at a portion
directly under the control gate, and single film shaped conductive
material or conductive material diffused in innumerable fine
diameter grain are embedded between the insulating films. Such the
conductive materials or boundary surface between the oxide film and
the nitride film and carrier trap within the nitride film function
as a charge accumulating means of the memory transistor.
[0110] Threshold voltage Vth of the memory transistor changes
according to charge accumulated quantity of the charge accumulating
means.
[0111] When writing is made to carry out by using channel hot
electron injection, the charge accumulated quantity varies
depending on electric field in a lateral direction applied to
channel that is turned ON when writing. The electric field in
lateral direction is determined according to bit line voltage.
Namely, the write data communicated to the memory cell as existence
of voltage establishment of the bit line is converted into
difference of the threshold voltage Vth when writing, thus being
stored in the memory cell.
[0112] When reading, the voltage by which the memory transistor
turns ON or OFF in compliance with logic of the storage data is
applied to the transistor gate through the word line under the
condition that the predetermined read drain voltage is applied
between both bit lines. According to this operation, only when the
memory transistor turns ON, current flows between both bit lines
through the channel, thus voltage of the bit line is changed. The
existence of change of the bit line voltage is made to read by
detecting it by the sense amplifier SA and so forth. Namely, when
reading, contrary to the writing, the storage data is inverted into
difference of the bit line voltage instead of the difference of the
threshold voltage Vth of the memory transistor, thus, it becomes
possible to communicate to the external portion.
[0113] Moreover, as the charge accumulated layer CAM, it is
desirable to employ that of a MONOS type (or a MNOS type). Its
reason will be described as follows.
[0114] In the MONOS non-volatile semiconductor memory transistor,
the carrier trap within the nitride film [Six Ny (0<x<1,
0<y<1)] which bears charge holding independently or the
carrier trap of boundary between top oxide film and nitride film
spreads discretely and spatially (namely, in the surface direction
and in the film width direction), accordingly, the charge holding
characteristic is dependent on the distribution regarding both of
energy and space of the charge captured by the carrier trap within
Six Ny film except for a tunnel insulating film thickness.
[0115] When leak current path occurs locally on this tunnel
insulating film, in the FG type, the charge holding characteristic
deteriorates easily because a great deal of charges leak while
passing through the leak path, contrary thereto, in the MONOS type,
the charge accumulating means exist spatially and discretely,
therefore, only local charges adjacent to the leak path leak
locally passing through the leak path, thus the charge holding
characteristic of the whole storage element is difficult to
deteriorate.
[0116] For that reason, in the MONOS type, the disadvantage of
deterioration of the charge holding characteristic regarding thin
film of the tunnel insulating film is not as serious as FG type.
Consequently, the MONOS type is superior than the FG type in
connection with scaling characteristic of the tunnel insulating
film in the fine memory transistor whose gate length is extremely
short.
[0117] Further, when the MONOS type is employed, if the charge is
injected locally to the distributed plane of the carrier trap
spread flatly, the charges are held without spreading flatly and in
the film thickness direction as the FG type.
[0118] The MONOS type is capable of operating in high speed when
giving consideration to the writing speed. For instance, it is
possible to apply source side injection type MONOS (NMOS)
transistor in which channel hot electron (CHE) is made to inject
from the source side.
[0119] This source side-channel hot electron injection, for
instance, as illustrated in FIG. 9, the selection gate SG is made
to arrange in the side of the control gate SG to be source side of
the memory transistor and the charge accumulated layer CAM.
[0120] Then, the high electric field is made to form in the
boundary region between the selection gate SG and the charge
accumulated layer CAM in such a way that high voltage is made to
apply to the control gate CG, while low voltage is made to apply to
the selection gate SG, followed by injecting channel hot electron
into the charge accumulated layer CAM in the arrow direction in the
drawing.
[0121] Injection efficiency thereof is higher than the ordinary
channel hot electron injection method in which channel hot electron
is injected at the drain side, accordingly, it is possible to
shorten the writing time.
[0122] Further, this source side-channel hot electron injection is
also applicable to the floating gate FG of the charge accumulated
layer or the MONOS (MNOS) memory transistor including nitride
film.
[0123] Furthermore, the MONOS (NMOS) memory transistor is capable
of writing binary information independently to the source side and
the drain side of the charge accumulated layer because the charge
can be made to inject to a part of the discrete trap due to the CHE
injection method. Accordingly, it is possible to write 2 bits per 1
memory cell.
[0124] In this case, for instance, 2 bits information is made to
write by the CHE injection while changing voltage application
direction between the source and the drain, while when reading,
predetermined voltage is made to apply between the source and the
drain in the reverse direction against the time of the writing,
which is so-called "reverse read" method. It is possible to read
surely the 2 bits information, even though accumulated charge
quantity is small caused by short writing time.
[0125] Accordingly, in the case of control shared type described
above, the MONOS (MNOS) memory transistor is appropriate.
[0126] FIG. 10 is a portional view illustrating concrete
construction example of the MONOS memory transistor.
[0127] As illustrated in FIG. 10, the memory transistor has a gate
electrode GT of the selection transistor ST connected to the word
line WL formed on the center portion of channel formation region of
semiconductor substrate W, a control gate CGL for the first memory
transistor provided at the both sides of the channel direction
while insulating to be separated from the gate electrode GT, and a
control gate CGR for the second memory transistor.
[0128] Further, in the memory transistor, gate insulating films
10a, 10b are formed between the control gates CGL, CGR and the bit
line BL or the channel formation region terminal portion
respectively.
[0129] The gate insulating film includes, for instance, a bottom
insulating film 11a, a nitride film 12a, top insulating film 13a.
Also, the gate insulating film 10b includes, for instance, a bottom
insulating film 11b, a nitride film 12b, a top insulating film
13b.
[0130] The gate electrode GT is embedded between two control gates
CGL, CGR separated spatially in both of the source side and the
drain side and the laminated pattern of the gate insulating films
10a, 10b through the insulating film 14.
[0131] Further, the gate electrode GT is connected to upper wiring
layer to be the word line WL which is not illustrated, thus being
connected commonly between memory cells in the word line
direction.
[0132] Thus, in the memory transistor, the selection MOS transistor
connected to the word line is formed at the center portion of the
channel formation region. The control gates CGL, CGR are arranged
through the gate insulating films 10a, 10b of ONO film type
including charge accumulating means at the upper portion of pocket
region PCT formed by oblique ion injection and diffusion layer (bit
line BL).
[0133] This combination between the selection gate GT and the
control gates CGL, CGR is fundamentally the same as the memory cell
of the source side injection type of the split gate
construction.
[0134] Further, it is suitable to use any one of silicon nitride
film exhibiting FN tunneling characteristic, silicon oxide nitride
film, or another dielectric film such as multi layer film, tantalum
oxide film and so forth as the bottom insulating film at the most
lowest layer of the gate insulating film.
[0135] For this reason, in the source side injection, energy
obstacle at the side of conduction band is reduced from 3.2 eV at
the case of oxide film, thus, injection efficiency of the hot
electron is improved.
[0136] Furthermore, the selection MOS transistor is employed for
carrying out the source side injection efficiently when writing.
Moreover, when erasing, even when the charge accumulating means is
over-erased, the selection MOS transistor accomplishes role for
holding the threshold voltage Vth constantly in the erase condition
of the memory transistor. For this reason, the threshold voltage of
this selection gate MOS transistor is established, for instance,
between 0.5 V and 1 V.
[0137] Next, a programming method for the memory cell array having
construction described above will be explained with reference to
the drawing.
[0138] FIG. 11 is a view illustrating a programming condition to
the control gate separation memory cell array. FIG. 12 is a view
illustrating programming condition to the control gate shared
memory cell array.
[0139] Further, here, there will be explained in the case where
programming is made to carry out to the second memory transistor at
the right hand side of the memory cell MC11.
[0140] The programming data is provided to the emulation circuit
122 through the external interface 126 of the controller portion
11, further, through the memory interface 127.
[0141] In the emulation circuit 122, the register 1221 stores
therein the command CMD and the address ADR, then if the register
1221 stores therein the unit data of the division data (for
instance, 64 bytes=512 bits), the register 1223 stores collectively
therein the division data. Then, storage of the divided unit data
is informed to the control circuit 123. The divided unit data Din
stored in the register 1223 is output to the input/output circuit
126 under the control of the control circuit 123 on the basis of
the above information.
[0142] In such a condition, the programming operation to the
control gate separation memory cell array will be explained with
reference to FIG. 11.
[0143] As to the control gate separated type, if the charge
accumulated layer is, for instance, the floating gate FG, voltage
of 0V is made to apply to the bit line BL0 at the source side,
voltage of 5V or 0V is made to apply to the bit line BL1 at the
drain side, low voltage of 1.5 V is made to apply to the word line
WL1 connected to the gate of the selection transistor, and high
voltage of 12 V is made to apply to the control gate line CLR1
connected to the control gate of the second memory transistor MT2
which is the select bit portion.
[0144] With respect to not selected left hand side bit portion (the
first memory transistor MT1) within the memory cell MC11, in order
to possess a role for communication so as to flow required channel
current regardless of kind of storage data of that part,
appropriate voltage Vcg1 is applied to the control gate line CLL1
connected to the control gate of the first memory transistor
MT1.
[0145] According to these bias conditions, the programming is
carried out to the second memory transistor MT2 of the memory cell
MC11 to be the select bit.
[0146] The memory cell MC12 adjacent to the selection memory cell
MC11, in order to avoid error writing caused by applied voltage to
the bit line BL1 at the drain side of the selection memory cell
MC11, voltage of the control gate line CLL2 connected to the
control gate of the first memory transistor MT1 and the control
gate line CLR2 connected to the control gate of the second memory
transistor MT2 is set to 0V to interrupt the channel current.
[0147] The aforementioned voltage for applying to the control gate
lines CLL, CLR is provided by the control circuit 123
selectively.
[0148] Here, the all threshold voltage of the transistor controlled
by the control gate is set to positive voltage regardless of kind
of the storage data.
[0149] Further, it is possible to carry out the same programming to
the bit within the memory cell 13 which is set apart one in the
direction of the word line of the select memory cell 11.
[0150] Furthermore, voltage of 0V is made to apply to the not
selected word line WL2 to interrupt the channel current.
[0151] Finally, in this control gate separation memory cell array
121A, with respect to the select word line, it is possible to carry
out programming per 4 bits.
[0152] Next, programming operation to the control gate shared
memory cell array will be explained with reference to FIG. 12.
[0153] As to the control gate separated type, if the charge
accumulated layer is the MONOS type including the nitride film,
voltage of 0V is made to apply to the bit line BL0 connected to the
source side, voltage of 5V or 0V is made to apply to the bit line
BL1 connected to the drain side, low voltage of 0.8V is made to
apply to the word line WL1 connected to the gate of the selection
transistor SG, and high voltage of 6 V is made to apply to the
control gate line CL1 connected to the control gate of the second
memory transistor MT2 which is the selection bit portion.
[0154] With respect to not selected left hand side bit portion (the
first memory transistor MT1) within the memory cell MC11, in order
to possess a role for communication so as to flow required channel
current regardless of kind of storage data of that part,
appropriate voltage Vcg2 is applied to the control gate line CL0
connected to the control gate of the first memory transistor
MT1.
[0155] According to these bias conditions, the programming is
carried out to the second memory transistor MT2 of the memory cell
MC11 to be the select bit.
[0156] The memory cell MC12 adjacent to the selection memory cell
MC11, in order to avoid error writing caused by applied voltage to
the bit line BL1 at the drain side of the selection memory cell
MC11, voltage of the control gate line CL2 connected to the control
gate of the second memory transistor MT2 is set to 0V to interrupt
the channel current.
[0157] Further, adjacent memory cell MC13 including the first
memory transistor MT1 which shares the control gate (CL2) with the
second memory transistor MT2 of the memory cell MC12, becomes non
selection.
[0158] Further, it is possible to carry out the same programming to
the bit within the memory cell 14 which is set apart two in the
direction of the word line of the select memory cell MC11.
[0159] Furthermore, voltage of 0V is made to apply to the not
selected word line WL2 to interrupt the channel current.
[0160] Finally, in this control gate shared memory cell array 121B,
with respect to the selection word line, it is possible to carry
out programming per 6 bits.
[0161] First Programming Method
[0162] Next, the number of programming pulse application is made to
set for the bit. Here, the bit of the word line unit is taken as a
page, on the supposition that page size is 512 bytes as described
above.
[0163] Logically, according to the above-described example, it is
possible to carry out the programming in every 4 bits or in every 6
bits in the direction of the word line. However, it is assumed that
the programming may be made to carry out in every 8 bits in order
to make it clearly understandable. Accordingly, with respect to 1
word line, the number of bits for carrying out the programming
simultaneously is 512 bit line BL (=512 bytes/8=64 bytes)
[0164] FIG. 13 is a view illustrating the number of times of
programming pulse application against the bit on the word line.
[0165] In the respective bits, the bit those voltage does not reach
to the write threshold voltage by one time of the pulse appears. In
the distribution of the whole 4096 bits (=512 bytes), a lot of bits
are 1 time, and decreasing extremely in accordance with the order
of 2 times, 3 times, 4 times.
[0166] The average number of times of the programming pulse
application is about 1.5 times per bit. The average number of times
of programming pulse application is 2 times per 512 bits of the
simultaneous programming unit. The average number of times of
programming pulse application is 4 times per page.
[0167] Here, with respect to 512 bits and 1 page, the number of
times becomes the greatest number of bit, therefore, the greater
becomes bit unit, the larger is the number of application.
[0168] One time of the programming cycle is separated largely into,
as illustrated in FIG. 14, the programming pulse application and
step of the verification, the total time of the two is set to 20
.mu.s.
[0169] When taking account of the programming time, actually, it is
necessary to take account of time necessary for loading program
information into column latch circuit existing ahead of the bit
line, however, here that time is ignored because it is short.
[0170] Here, the programming time for one page is made to
consider.
[0171] Concretely, the simultaneous programming pulse application
is made to carry out against 512 bits existing in every 8 bits in
the direction of the word line, subsequently, programming pulse
application is made to carry out against adjacent 512 bits
thereto.
[0172] 8 times repetition of this 512 bits simultaneous programming
step come to the programming pulse application corresponding to one
page (512 bytes). The verification for one page is made to carry
out continuously, after the programming pulse application for one
page (512 bytes).
[0173] Further, as the case condition of the verification, for
instance, in the case of the control gate separated type, voltage
of 1.5 V is made to apply to the control gate line CLR1 connected
to control gate of the memory transistor MT2 of the selection bit
of the selection memory cell MC11, voltage of 8V is made to apply
to the control gate line CLL1 connected to the control gate of the
memory transistor MT1 of the selection memory cell MC11, voltage of
1.5V is made to apply to the bit line BL0 at the source side, and
voltage of 0V is made to apply to the bit line BL1 at the drain
side.
[0174] This verification is necessary to carry out at intervals of
several bits in the direction of the word line in the same way as
the programming, thus it is assumed that the verification is made
to carry out in every 8 bits.
[0175] Also in the verification operation, 8 times repetition of
this 512 bits simultaneous the verification step come to the
verification corresponding to one page (512 bytes).
[0176] As described above, 4 times of the programming pulse
application are required for each page. Namely, the programming is
completed by carrying out 4 times of cycle of the programming pulse
application of one page unit and the verification.
[0177] FIG. 15 is a view illustrating the number of times of the
programming pulse application and the number of times of the
verification while picking out.
[0178] As illustrated in FIG. 15, finally, a pair of the
programming pulse application and the verification come to
programming cycle of total 32 times, therefore, the programming
time for one page comes to 640 .mu.s (20 .mu.s.times.32 times).
[0179] This programming time is improved in comparison with the
conventional maximum 1500 .mu.s of the memory system.
[0180] In case of the above-described example, the programming
speed is converted into 0.8 Mbyte/s (=512 byte/640 .mu.s).
[0181] The second and the third programming methods that realize
programming in which programming speed is further high speed more
than, for example, several MByte/s will be explained below.
[0182] Second Programming Method
[0183] Also, in this case, the bit of the word line unit is taken
as a page, on the supposition that page size is 512 bytes, thus the
programming time for 1 page is made to consider.
[0184] Concretely, the simultaneous programming pulse application
is made to carry out to, for instance, 512 bits existing in every 8
bits in the direction of the word line, continuously, the
verification of the same 512 bits is made to carry out.
[0185] For instance, as illustrated in FIG. 13, it is assumed that
the number of times of the programming pulse application of average
2 times per 512 bits is required. Namely, as for 512 bits unit, the
programming is completed in such a way as to carry out average 2
times of cycle of the continuous programming pulse application and
the verification.
[0186] Next, as for 512 bits of adjacent bit thereto, the
programming is completed in such a way as to carry out average 2
times of cycle of the continuous programming pulse application and
the verification. The programming of 1 page (512 bytes) is
completed in such a way as to repeat 8 times a step consisting of
average 2 cycles of the continuous programming pulse application
and the verification of 512 bits.
[0187] FIG. 16 is a view illustrating the number of times of the
programming pulse application and the number of times of the
verification while picking out.
[0188] As illustrated in FIG. 16, according to the second
programming method, finally, pair of the programming pulse and the
verification come to programming cycle of total 16 times,
therefore, the programming time for one page comes to 320 .mu.s (20
.mu.s.times.16 times).
[0189] In case of the above-described example, programming speed is
converted into 1.6 Mbyte/s (=512 Byte/320 .mu.s). This becomes 2
times the case of the first programming speed.
[0190] The reason causes difference of the number of times of the
programming pulse application.
[0191] There is a tendency that the larger the bit unit to which
the programming pulse is applied, the more becomes the number of
times of application. In the example of FIG. 13, the number of
times of application is average 2 times in every 512 bits, and
average 4 times for each page.
[0192] In the present second method, since 512 bits unit is
adopted, the number of programming application becomes 1/2 of 1
page, accordingly, the programming speed becomes 2 times of 1 page
unit.
[0193] This programming speed is suitable for a device which
requires value more than several Byte/s, for instance, a memory
card and so forth.
[0194] Third Programming Method
[0195] In the present third programming method, a page is made to
constitute by a plurality of divided circuits, such as, for
instance, a plurality of chips or a plurality of mats.
[0196] For instance, as illustrated in FIG. 17, a page having a
size of 512 bytes is made to constitute by 8 pieces of divided
circuits, such as, for instance, mats MM1 to MM8.
[0197] By such a constitution, the number of bit becomes 512 bits
for each mat, and the 512 bits is made to constitute, for instance,
as illustrated in FIG. 17, by the bits in every 8 bits in the
direction of the word line.
[0198] In this case, as for all 8 mats MM1 to MM8, the simultaneous
programming pulse application is made to carry out to 512 bits
existing in every 8 bits in the direction of the word line, and the
verification of the same 512 bits is made to carry out
continuously.
[0199] Four times of the number of times of the programming pulse
application for each page should be required, for instance,
regardless of the condition of extending over the mat.
[0200] Namely, as for the page unit, the programming is completed
in such a way as to carry out average four times of cycle of the
continuous programming pulse application and the verification.
[0201] Since 512 bits becomes 1 page while extending over 8 chips,
the programming for 1 page (512 bytes) is completed by only these
steps without shifting to adjacent bit.
[0202] In this case, the programming for 1 page is made to
consider.
[0203] FIG. 18 is a view illustrating the number of times of the
programming pulse application and the number of times of the
verification while picking them out.
[0204] As illustrated in FIG. 18, according to the third
programming method, finally, pair of the programming pulse and the
verification come to programming cycle of total 4 times, therefore,
the programming time for one page comes to 80 .mu.s (20
.mu.s.times.4 times).
[0205] In case of the above-described example, the programming
speed is converted into 6.4 Mbyte/s (=512 Byte/80 .mu.s). This
becomes 8 times the case of the first programming speed. This
becomes 4 times the case of the second programming speed.
[0206] According to the present third programming method, there is
an advantage that it becomes possible to reduce drastically the
programming time.
[0207] Further, in the explanation described-above, as for the
memory cell array 1, for instance, the simultaneous programming
pulse application is made to carry out against 512 bits existing in
every 8 bits in the direction of the word line. This is an equal
value that the parallel operation is made to carry out while
dividing the memory cell array into a plurality of mats.
[0208] FIG. 19A and 19B are views illustrating concept of division
of the memory cell array according to the present embodiment.
[0209] In FIG. 19A illustrates physical memory cell array 1, in the
drawing, serial numbers 1, 2, . . . , n, n+1, . . . , 2n, 2n+1, . .
. , j are added to the memory cell column.
[0210] Then, for instance, on the occasion of this programming, or
the read operation, or the erase operation, the control circuit 123
of FIG. 2 divides the memory transistor in the direction of the
word line into plural number, thus the memory cell array is divided
into integer n pieces more than 3 of the memory cell mats MM1, MM2,
. . . , MMn. The respective memory cell mats MM1, MM2, . . . , MMn
include cyclically dispersed memory cell column. Namely, the memory
cell mat MM1 includes memory cell columns 1, n+1, 2n+1, . . . , the
memory cell mat MM2 includes memory cell columns 2, n+2, 2n+2, . .
. , and the final memory cell mat MMn includes memory cell columns
n, 2n, . . . , j.
[0211] Then, in the present embodiment, it causes the memory
transistor within any one of the selected memory cell mat to be
executed parallel operation.
[0212] Thus, in the present invention, it is possible to set the
number of the memory cell mat n arbitrarily. Further, it is
possible to cope therewith in such a way that the number of the
control gate for impressing interrupting voltage continuously at
the divided portion is set to, for instance, (n-2) control
gates.
[0213] As described above, according to the present embodiment, the
memory cell array is made to constitute by a MONOS type (MNOS type)
non-volatile memory or a floating gate type non-volatile memory for
carrying out source side-channel hot electron injection capable of
writing data with divided unit (for instance, 64 byte=512 bits)
different from the case where write of page unit (512 bytes) is
carried out collectively, and there are provided the emulation
circuit 122 for holding successively the programming data which
constitutes a page in the condition of being divided into a
plurality of divided units and a control circuit 123 for reading
successively the divided unit data thus held to write. Accordingly,
it is possible, not only, to carry out write or read in parallel
against a plurality of memory transistors, but also, as illustrated
in FIG. 20, it is possible to scheme high speed programming
operation including the verification in comparison with the case
where writing for page is made to carry out collectively while
employing conventional NAND flash memory.
[0214] Further, according to the present embodiment, a page is made
to constitute in such a way as to range over a plurality of mats
(or chips), the simultaneous programming pulse application is made
to carry out against bit unit existing in every several bits on the
word line extending over a plurality of mats, and the verification
of the same bit unit is made to carry out continuously,
accordingly, it is possible, not only, to carry out write or read
in parallel to a plurality of memory transistors. But also, there
is an advantage that it is possible to realize a higher speed
programming operation including the verification.
[0215] Furthermore, in the present embodiment, the example is
explained in which the emulation circuit 122 is provided within the
memory portion 120. However, the present invention is not limited
by this case, it may be possible to dispose it in the controller
portion 110.
[0216] Moreover, the memory cell is made to constitute by the first
memory transistor MT1, the second memory transistor MT2, and the
selection transistor SG sharing channel formation-region therewith
between the first and second memory transistors MT1, MT2, and the
first memory transistor MT1, the second memory transistor MT2 are
made to constitute by the MONOS type (MNOS type) non-volatile
memory. Thereby, if a plurality of memory cells are connected in
cascade connection, the control gate can be shared between the
first memory transistor MT1 of the memory cell and the first memory
transistor belonging to adjacent memory cell thereto, thus it is
possible to reduce the number of the control gate line, further it
is possible to scheme more high integration.
[0217] As described above, according to the present invention,
write or read of data can be made to execute for a plurality of
memory transistors in parallel, thus it is possible to achieve a
high speed programming operation.
[0218] While the invention has been described with reference to
specific embodiments chosen for purpose of illustration, it should
be apparent that numerous modifications could be made thereto by
those skilled in the art without departing from the basic concept
and scope of the invention.
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