U.S. patent application number 09/879079 was filed with the patent office on 2001-12-20 for method for driving semiconductor memory.
Invention is credited to Kato, Yoshihisa, Shimada, Yasuhiro.
Application Number | 20010053087 09/879079 |
Document ID | / |
Family ID | 26594164 |
Filed Date | 2001-12-20 |
United States Patent
Application |
20010053087 |
Kind Code |
A1 |
Kato, Yoshihisa ; et
al. |
December 20, 2001 |
Method for driving semiconductor memory
Abstract
In a method for driving a semiconductor memory including a
ferroelectric capacitor for storing a multi-valued data in
accordance with a displacement of polarization of a ferroelectric
film and a detector connected to one of an upper electrode and a
lower electrode of the ferroelectric capacitor for detecting the
displacement of the polarization of the ferroelectric film, the
multi-valued data is read by detecting the displacement of the
polarization of the ferroelectric film by the detector under
application of a reading voltage to the other of the upper
electrode and the lower electrode of the ferroelectric capacitor,
and then, the reading voltage applied to the latter electrode is
removed. The reading voltage has such magnitude that the
displacement of the polarization of the ferroelectric film is
restored to that obtained before reading the multi-valued data by
removing the reading voltage.
Inventors: |
Kato, Yoshihisa; (Otsu-shi,
JP) ; Shimada, Yasuhiro; (Muko-shi, JP) |
Correspondence
Address: |
NIXON PEABODY, LLP
8180 GREENSBORO DRIVE
SUITE 800
MCLEAN
VA
22102
US
|
Family ID: |
26594164 |
Appl. No.: |
09/879079 |
Filed: |
June 13, 2001 |
Current U.S.
Class: |
365/149 |
Current CPC
Class: |
G11C 11/223 20130101;
G11C 11/22 20130101 |
Class at
Publication: |
365/149 |
International
Class: |
G11C 011/24 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 19, 2000 |
JP |
2000-182642 |
Sep 5, 2000 |
JP |
2000-268270 |
Claims
What is claimed is:
1. A method for driving a semiconductor memory including a
ferroelectric capacitor for storing a multi-valued data in
accordance with a displacement of polarization of a ferroelectric
film thereof and detection means connected to a first electrode
corresponding to one of an upper electrode and a lower electrode of
said ferroelectric capacitor for detecting the displacement of the
polarization of said ferroelectric film, comprising: a first step
of reading said multi-valued data by detecting the displacement of
the polarization of said ferroelectric film by said detection means
with a reading voltage applied to a second electrode corresponding
to the other of said upper electrode and said lower electrode of
said ferroelectric capacitor; and a second step of removing said
reading voltage applied to said second electrode, wherein said
reading voltage applied in the first step has such magnitude that
the displacement of the polarization of said ferroelectric film is
restored to that obtained before reading said multi-valued data by
removing said reading voltage in the second step.
2. The method for driving a semiconductor memory of claim 1,
further comprising, after the second step, a third step of making a
potential difference between said upper electrode and said lower
electrode of said ferroelectric capacitor zero.
3. The method for driving a semiconductor memory of claim 2,
wherein the third step includes a sub-step of applying a voltage
with polarity different from polarity of said reading voltage to
said first electrode before making said potential difference
zero.
4. The method for driving a semiconductor memory of claim 2,
wherein said semiconductor memory includes a switch for equalizing
the potentials of said first electrode and said second electrode of
said ferroelectric capacitor, and the third step includes a
sub-step of making said potential difference zero with said
switch.
5. The method for driving a semiconductor memory of claim 2,
wherein said semiconductor memory includes a switch for equalizing
the potentials of said first electrode of said ferroelectric
capacitor and potential, and the third step includes a sub-step of
applying a constant potential to said second electrode of said
ferroelectric capacitor and making said potential difference zero
with said switch.
6. The method for driving a semiconductor memory of claim 1,
wherein said reading voltage applied in the first step has such
magnitude that a voltage applied between said first electrode and
said second electrode of said ferroelectric capacitor when said
reading voltage is applied is smaller than a coercive voltage of
said ferroelectric capacitor.
7. The method for driving a semiconductor memory of claim 1,
wherein said detection means has a load capacitor, the first step
includes a sub-step of applying said reading voltage to both ends
of a series circuit composed of said ferroelectric capacitor and
said load capacitor, and said detection means detects the
displacement of the polarization of said ferroelectric film by
detecting a voltage applied to said load capacitor that is obtained
by dividing said reading voltage in accordance with a ratio between
the capacitance of said ferroelectric capacitor and the capacitance
of said load capacitor.
8. The method for driving a semiconductor memory of claim 1,
wherein said detection means includes a field effect transistor
formed on a substrate and having a gate electrode connected to said
first electrode of said ferroelectric capacitor, the first step
includes a sub-step of applying said reading voltage between said
second electrode of said ferroelectric capacitor and said
substrate, and said detection means detects the displacement of the
polarization of said ferroelectric film by detecting a current
flowing between a drain region and a source region of said field
effect transistor when a voltage obtained by dividing said reading
voltage in accordance with a ratio between the capacitance of said
ferroelectric capacitor and the gate capacitance of said field
effect transistor is applied to said gate electrode of said field
effect transistor.
9. A method for driving a semiconductor memory including a
plurality of successively connected ferroelectric capacitors each
storing a multi-valued data in accordance with the displacement of
polarization of a ferroelectric film thereof, a plurality of
selecting transistors respectively connected to said plurality of
ferroelectric capacitors for selecting one of said ferroelectric
capacitors for reading said multi-valued data, and detection means
connected to one end of said plurality of successively connected
ferroelectric capacitors for reading said multi-valued data by
detecting the displacement of the polarization of said
ferroelectric film included in one ferroelectric capacitor selected
by said selecting transistors, comprising: a first step of applying
a reading voltage to one of an upper electrode and a lower
electrode of each of said ferroelectric capacitors; and a second
step of removing said reading voltage applied to said one
electrode, wherein said reading voltage applied in the first step
has such magnitude that the displacement of the polarization of
said ferroelectric film is restored to that obtained before reading
said multi-valued data by removing said reading voltage in the
second step.
10. The method for driving a semiconductor memory of claim 9,
further comprising, after the second step, a third step of making a
potential difference between said upper electrode and said lower
electrode of said ferroelectric capacitor zero.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a method for driving a
semiconductor memory including a ferroelectric capacitor.
[0002] A first conventional example of a semiconductor memory
including a ferroelectric capacitor is composed of, as shown in
FIG. 15, a field effect transistor (hereinafter referred to as an
FET) 1 and a ferroelectric capacitor 2, and a bit line BL is
connected to a drain region 1a of the FET 1, an upper electrode of
the ferroelectric capacitor 2 is connected to a source region 1b of
the FET 1 and a word line WL is connected to a gate electrode 1c of
the FET 1.
[0003] The semiconductor memory of the first conventional example
employs the destructive read-out system in which a recorded data is
erased in reading the data. Therefore, a rewrite operation is
necessary to conduct after reading a data, and hence, an operation
for reversing the polarization direction of a ferroelectric film
(polarization reversing operation) should be carried out after
every data read operation.
[0004] Since a phenomenon of polarization fatigue occurs in a
ferroelectric film, the polarizing characteristic of the
ferroelectric film is largely degraded when the polarization
reversing operation is repeatedly carried out.
[0005] As a countermeasure, a semiconductor memory of a second
conventional example shown in FIG. 16 has been proposed. The
semiconductor memory of the second conventional example employs the
non-destructive read-out system in which a lower electrode 2b of a
ferroelectric capacitor 2 is connected to a gate electrode 1c of an
FET 1 so as to use the ferroelectric capacitor 2 for controlling
the gate potential of the FET 1. In FIG. 16, a reference numeral 3
denotes a substrate.
[0006] In writing a data in the semiconductor memory of the second
conventional example, a writing voltage is applied between an upper
electrode 2a of the ferroelectric capacitor 2 serving as a control
electrode and the substrate 3.
[0007] For example, when a data is written by applying a voltage
(control voltage) positive with respect to the substrate 3 to the
upper electrode 2a, downward polarization is caused in a
ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter,
even when the upper electrode 2a is grounded, positive charge
remains in a gate electrode 1c of the FET 1, and hence, the gate
electrode 1c has positive potential.
[0008] When the potential of the gate electrode 1c exceeds the
threshold voltage of the FET 1, the FET 1 is in an on-state.
Therefore, when a potential difference is caused between a drain
region 1a and a source region 1b of the FET 1, a current flows
between the drain region 1a and the source region 1b. Such a
logical state of the ferroelectric memory is defined, for example,
as "1".
[0009] On the other hand, when a voltage negative with respect to
the substrate 3 is applied to the upper electrode 2a of the
ferroelectric capacitor 2, upward polarization is caused in the
ferroelectric film 2c of the ferroelectric capacitor 2. Thereafter,
even when the upper electrode 2a is grounded, negative charge
remains in the gate electrode 1c of the FET 1, and hence, the gate
electrode 1c has negative potential. In this case, the potential of
the gate electrode 1c is always smaller than the threshold voltage
of the FET 1, and hence, the FET 1 is in an off-state. Therefore,
even when a potential difference is caused between the drain region
1a and the source region 1b, no current flows between the drain
region 1a and the source region 1b. Such a logical state of the
ferroelectric memory is defined, for example, as "0".
[0010] Even when the power supply to the ferroelectric capacitor 2
is shut off, namely, even when the voltage application to the upper
electrode 2a of the ferroelectric capacitor 2 is stopped, the
aforementioned logical states are retained, and thus, a nonvolatile
memory is realized. Specifically, when power is supplied again to
apply a voltage between the drain region 1a and the source region
1c after shutting off the power supply for a given period of time,
a current flows between the drain region 1a and the source region
1b if the logical state is "1", so that the data "1" can be read,
and no current flows between the drain region 1a and the source
region 1b if the logical state is "0", so that the data "0" can be
read.
[0011] In order to correctly retain a data while the power is being
shut off (which characteristic for retaining a data is designated
as a retention characteristic), it is necessary to always keep the
potential of the gate electrode 1c of the FET 1 to be higher than
the threshold voltage of the FET 1 when the data is "1" and to
always keep the potential of the gate electrode 1c of the FET 1 at
a negative voltage when the data While the power is being shut off,
the upper electrode 2a of the ferroelectric capacitor 2 and the
substrate 3 have ground potential, and hence, the potential of the
gate electrode 1c is isolated. Therefore, ideally, as shown in FIG.
17, a first intersection c between a hysteresis loop 4 obtained in
writing a data in the ferroelectric capacitor 2 and a gate
capacitance load line 7 of the FET 1 obtained when a bias voltage
is 0 V corresponds to the potential of the gate electrode 1c
obtained in storing a data "1", and a second intersection d between
the hysteresis loop 4 and the gate capacitance load line 7
corresponds to the potential of the gate electrode 1c obtained in
storing a data "0". In FIG. 17, the ordinate indicates charge Q
appearing in the upper electrode 2a (or the gate electrode 1c) and
the abscissa indicates a voltage V.
[0012] Actually, however, the ferroelectric capacitor 2 is not an
ideal insulator but has a resistance component, and hence, the
potential of the gate electrode 1c drops through the resistance
component. This potential drop is exponential and has a time
constant obtained by multiplying parallel combined capacitance of
the gate capacitance of the FET 1 and the capacitance of the
ferroelectric capacitor 2 by the resistance component of the
ferroelectric capacitor 2. The time constant is approximately
10.sup.4 seconds at most. Accordingly, the potential of the gate
electrode 1c is halved within several hours.
[0013] Since the potential of the gate electrode 1c is
approximately 1 V at the first intersection c as shown in FIG. 17,
when the potential is halved, the potential of the gate electrode
1c becomes approximately 0.5 V, which is lower than the threshold
voltage of the FET 1 (generally of approximately 0.7 V). As a
result, the FET 1 that should be in an on-state is turned off in a
short period of time.
[0014] In this manner, although the ferroelectric memory using the
ferroelectric capacitor for controlling the gate potential of the
FET has an advantage that a rewrite operation is not necessary
after a data read operation, it has the following problem: The gate
electrode of the FET obtains potential after writing a data, and
the ability for keeping the gate potential determines the retention
characteristic. Since the time constant until discharge of the
ferroelectric capacitor is short, the data retaining ability is
short, namely, the retention characteristic is not good.
SUMMARY OF THE INVENTION
[0015] In consideration of the aforementioned conventional problem,
an object of the invention is improving the retention
characteristic of a semiconductor memory including a ferroelectric
capacitor for storing a multi-valued data in accordance with a
displacement of polarization of a ferroelectric film.
[0016] In order to achieve the object, the first method of this
invention for driving a semiconductor memory including a
ferroelectric capacitor for storing a multi-valued data in
accordance with a displacement of polarization of a ferroelectric
film thereof and detection means connected to a first electrode
corresponding to one of an upper electrode and a lower electrode of
the ferroelectric capacitor for detecting the displacement of the
polarization of the ferroelectric film, comprises a first step of
reading the multi-valued data by detecting the displacement of the
polarization of the ferroelectric film by the detection means with
a reading voltage applied to a second electrode corresponding to
the other of the upper electrode and the lower electrode of the
ferroelectric capacitor; and a second step of removing the reading
voltage applied to the second electrode, and the reading voltage
applied in the first step has such magnitude that the displacement
of the polarization of the ferroelectric film is restored to that
obtained before reading the multi-valued data by eliminating the
reading voltage in the second step.
[0017] In the first method for driving a semiconductor memory of
this invention, the reading voltage applied in the first step has
such magnitude that the displacement of the polarization of the
ferroelectric film is restored to that obtained before reading the
multi-valued data by removing the reading voltage in the second
step. Therefore, in reading any multi-valued data stored in the
ferroelectric capacitor, the read data is not destroyed, and hence,
there is no need to carry out a data rewrite operation. Therefore,
there is no need to carry out an operation for changing the
polarization direction of the ferroelectric film (polarization
reversing operation) after every data read operation. Accordingly,
the ferroelectric film of the ferroelectric capacitor is minimally
degraded through polarization fatigue, resulting in largely
improving the read endurance characteristic of the semiconductor
memory.
[0018] The first method for driving a semiconductor memory
preferably further comprises, after the second step, a third step
of making a potential difference between the upper electrode and
the lower electrode of the ferroelectric capacitor zero.
[0019] When the potential difference between the upper electrode
and the lower electrode of the ferroelectric capacitor is made zero
after the second step, lowering of the potential difference through
a resistance component of the ferroelectric capacitor disappears,
resulting in improving the retention characteristic during the
power is shut-off.
[0020] When the first method for driving a semiconductor memory
comprises the third step of making the potential difference between
the upper electrode and the lower electrode of the ferroelectric
capacitor zero, the third step preferably includes a sub-step of
applying a voltage with polarity different from polarity of the
reading voltage to the first electrode before making the potential
difference zero.
[0021] In this case, even when a voltage is applied for partially
reversing the polarization of the ferroelectric film of the
ferroelectric capacitor in data read, the magnitude of the
polarization charge obtained after data read can be substantially
equal to the magnitude of the polarization charge obtained before
the data read. As a result, the disturb effect of the semiconductor
memory can be largely eliminated.
[0022] When the first method for driving a semiconductor memory
comprises the third step of making the potential difference between
the upper electrode and the lower electrode of the ferroelectric
capacitor zero, the semiconductor memory preferably includes a
switch for equalizing the potentials of the first electrode and the
second electrode of the ferroelectric capacitor, and the third step
preferably includes a sub-step of making the potential difference
zero with the switch.
[0023] In this manner, the potential difference between the upper
electrode and the lower electrode of the ferroelectric capacitor
can be easily and definitely made zero after the second step.
[0024] When the first method for driving a semiconductor memory
comprises the third step of making the potential difference between
the upper electrode and the lower electrode of the ferroelectric
capacitor zero, the semiconductor memory preferably includes a
switch for equalizing the potentials of the first electrode of the
ferroelectric capacitor and potential, and the third step
preferably includes a sub-step of applying a constant potential to
the second electrode of the ferroelectric capacitor and making the
potential difference zero with the switch.
[0025] In this manner, the potential difference between the upper
electrode and the lower electrode of the ferroelectric capacitor
can be easily and definitely made zero after the second step.
[0026] In the first method for driving a semiconductor memory, the
reading voltage applied in the first step preferably has such
magnitude that a voltage applied between the first electrode and
the second electrode of the ferroelectric capacitor when the
reading voltage is applied is smaller than a coercive voltage of
the ferroelectric capacitor.
[0027] In this manner, the displacement of the polarization of the
ferroelectric film can be definitely restored to that obtained
before reading the data when the reading voltage applied in the
first step is eliminated.
[0028] In the first method for driving a semiconductor memory, the
detection means preferably has a load capacitor, the first step
preferably includes a sub-step of applying the reading voltage to
both ends of a series circuit composed of the ferroelectric
capacitor and the load capacitor, and the detection means
preferably detects the displacement of the polarization of the
ferroelectric film by detecting a voltage applied to the load
capacitor that is obtained by dividing the reading voltage in
accordance with a ratio between the capacitance of the
ferroelectric capacitor and capacitance of the load capacitor.
[0029] In this manner, the reading voltage applied in the first
step is divided in accordance with the capacitance ratio between
the ferroelectric capacitor and the load capacitor. Therefore, the
voltage applied to the ferroelectric capacitor can be easily set to
such magnitude that the displacement of the polarization of the
ferroelectric film can be restored to that obtained before the data
read when the reading voltage is removed.
[0030] In the first method for driving a semiconductor memory, the
detection means preferably includes a field effect transistor
formed on a substrate and having a gate electrode connected to the
first electrode of the ferroelectric capacitor, the first step
preferably includes a sub-step of applying the reading voltage
between the second electrode of the ferroelectric capacitor and the
substrate, and the detection means preferably detects the
displacement of the polarization of the ferroelectric film by
detecting a current flowing between a drain region and a source
region of the field effect transistor when a voltage obtained by
dividing the reading voltage in accordance with a ratio between the
capacitance of the ferroelectric capacitor and the gate capacitance
of the field effect transistor is applied to the gate electrode of
the field effect transistor.
[0031] In this manner, the reading voltage applied in the first
step can be divided in accordance with the capacitance ratio
between the ferroelectric capacitor and the field effect
transistor. Therefore, the voltage applied to the ferroelectric
capacitor can be easily set to such magnitude that the displacement
of the polarization of the ferroelectric film can be restored to
that obtained before the data read when the reading voltage is
removed. Furthermore, the displacement of the polarization of the
ferroelectric film can be definitely detected by detecting the
current flowing between the drain region and the source region of
the field effect transistor.
[0032] The second method of this invention for driving a
semiconductor memory including a plurality of successively
connected ferroelectric capacitors each storing a multi-valued data
in accordance with a displacement of polarization of a
ferroelectric film thereof, a plurality of selecting transistors
respectively connected to the plurality of ferroelectric capacitors
for selecting the ferroelectric capacitors for reading the
multi-valued data, and detection means connected to one end of the
plurality of successively connected ferroelectric capacitors for
reading the multi-valued data by detecting the displacement of the
polarization of the ferroelectric film included in one
ferroelectric capacitor selected by the selecting transistors,
comprises a first step of applying a reading voltage to one of an
upper electrode and a lower electrode of each of the ferroelectric
capacitors; and a second step of removing the reading voltage
applied to the one electrode, and the reading voltage applied in
the first step has such magnitude that the displacement of the
polarization of the ferroelectric film is restored to that obtained
before reading the multi-valued data by removing the reading
voltage in the second step.
[0033] In the second method for driving a semiconductor memory of
this invention, even when any multi-valued data stored in the
ferroelectric capacitors is read, there is no need to carry out a
data rewrite operation similarly to the first driving method.
Accordingly, the ferroelectric film of the ferroelectric capacitor
is minimally degraded through the polarization fatigue, resulting
in largely improving the read endurance characteristic of the
semiconductor memory.
[0034] The second method for driving a semiconductor memory
preferably further comprises, after the second step, a third step
of making a potential difference between the upper electrode and
the lower electrode of the ferroelectric capacitor zero.
[0035] In this manner, lowering of the potential difference through
a resistance component of the ferroelectric capacitor disappears,
resulting in improving the retention characteristic during the
power is shut-off.
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] FIG. 1 is an equivalent circuit diagram of a memory cell
included in a semiconductor memory according to Embodiment 1 of the
invention;
[0037] FIG. 2 is an equivalent circuit diagram of a memory cell
array in which memory cells each included in the semiconductor
memory of Embodiment 1 are arranged in the form of a matrix;
[0038] FIG. 3 is a diagram for showing behavior of charge and
voltage in a read operation of the semiconductor memory of
Embodiment 1;
[0039] FIG. 4 is a diagram for showing behavior of charge and
voltage in a read operation of the semiconductor memory of
Embodiment 1;
[0040] FIG. 5 is an equivalent circuit diagram employed in the
semiconductor memory of Embodiment 1 for realizing a second method
for making a potential difference between an upper electrode and a
lower electrode of a ferroelectric capacitor zero after reading a
data;
[0041] FIG. 6 is an equivalent circuit diagram employed in the
semiconductor memory of Embodiment 1 for realizing a third method
for making a potential difference between the upper electrode and
the lower electrode of the ferroelectric capacitor zero after
reading a data;
[0042] FIG. 7 is an equivalent circuit diagram employed in the
semiconductor memory of Embodiment 1 for realizing a fourth method
for making a potential difference between the upper electrode and
the lower electrode of the ferroelectric capacitor zero after
reading a data;
[0043] FIG. 8 is an equivalent circuit diagram of a memory cell
included in a semiconductor memory according to Embodiment 2 of the
invention;
[0044] FIG. 9 is a diagram for showing behavior of charge and
voltage in a read operation of the semiconductor memory of
Embodiment 2;
[0045] FIGS. 10A and 10B are timing charts of a read operation of
the semiconductor memory of Embodiment 2, wherein FIG. 10A is a
timing chart employed when a data "1" is stored and FIG. 10B is a
timing chart employed when a data "0" is stored;
[0046] FIG. 11 is an equivalent circuit diagram for explaining an
evaluation test for the semiconductor memory of Embodiment 2;
[0047] FIG. 12 is a diagram for showing the relationship between
the number of read cycles and voltage resulting from the evaluation
test for the semiconductor memory of Embodiment 2;
[0048] FIG. 13 is a diagram for showing the relationship between
retention time and bit line voltage resulting from the evaluation
test for the semiconductor memory of Embodiment 2;
[0049] FIG. 14 is an equivalent circuit diagram of a memory cell
array of a semiconductor memory according to Embodiment 3 of the
invention;
[0050] FIG. 15 is an equivalent circuit diagram of a memory cell
included in a semiconductor memory according to a first
conventional example;
[0051] FIG. 16 is an equivalent circuit diagram of a memory cell
included in a semiconductor memory according to a second
conventional example; and
[0052] FIG. 17 is a diagram for showing behavior of charge and
voltage in a read operation of the semiconductor memory of the
second conventional example.
DETAILED DESCRIPTION OF THE INVENTION
[0053] Embodiment 1
[0054] A semiconductor memory and a method for driving the
semiconductor memory according to Embodiment 1 of the invention
will now be described with reference to FIGS. 1 through 4.
[0055] FIG. 1 shows an equivalent circuit of a memory cell included
in the semiconductor memory of Embodiment 1. The semiconductor
memory of this embodiment includes a reading FET 10 having a drain
region 11, a source region 12 and a gate electrode 13, a selecting
FET 20 having a drain region 21, a source region 22 and a gate
electrode 23, and a ferroelectric capacitor 30 having an upper
electrode 31, a lower electrode 32 and a ferroelectric film 33, and
the reading FET 10, the selecting FET 20 and the ferroelectric
capacitor 30 together form the memory cell.
[0056] The lower electrode 32 of the ferroelectric capacitor 30 is
connected to the gate electrode 13 of the reading FET 10 and the
source region 22 of the selecting FET 20. The upper electrode 31 of
the ferroelectric capacitor 30 is connected to the drain region 21
of the selecting FET 20 and a word line WL. The drain region 11 of
the reading FET 10 is connected to a bit line BL, the source region
12 of the reading FET 10 is connected to a plate line CP, and the
gate electrode 23 of the selecting FET 20 is connected to a control
line BS. In FIG. 1, a reference numeral 14 denotes a substrate
where the reading FET 10 is formed.
[0057] FIG. 2 shows an equivalent circuit of a memory cell array in
which a plurality of memory cells of FIG. 1 are arranged in the
form of a matrix.
[0058] As shown in FIG. 2, the upper electrodes 31 of the
ferroelectric capacitors 30 included in the memory cells on the
first row are connected to a first word line WL1, and the upper
electrodes 31 of the ferroelectric capacitors 30 included in the
memory cells on the second row are connected to a second word line
WL2. The drain regions 11 of the reading FETS 10 included in the
memory cells in the first column are connected to a first bit line
BL1, and the drain regions 11 of the reading FETs 10 included in
the memory cells in the second column are connected to a second bit
line BL2. The source regions 12 of the reading FETs 10 included in
the memory cells on the first row are connected to a first plate
line CP1, and the source regions 12 of the reading FETs 10 included
in the memory cells on the second row are connected to a second
plate line CP2. The gate electrodes 23 of the selecting FETs 20
included in the memory cells in the first column are connected to a
first control line BS1, and the gate electrodes 23 of the selecting
FETs 20 included in the memory cells in the second column are
connected to a second control line BS2.
[0059] Now, the method for driving the semiconductor memory of
Embodiment 1 will be described.
[0060] (Data Write Operation)
[0061] A write operation of the semiconductor memory of this
embodiment is carried out as follows:
[0062] With the gate potential of the reading FET 10 and the
substrate potential set to a ground voltage, a voltage 0 V is
applied to all the signal lines including the word line WL, the bit
line BL, the plate line CP and the control line BS. Thereafter, a
positive or negative writing voltage is applied to the word line
WL, so as to cause downward or upward polarization in the
ferroelectric film 33 of the ferroelectric capacitor 30. Herein, a
state where downward polarization is caused in the ferroelectric
film 33 is defined as a data "1" and a state where upward
polarization is caused in the ferroelectric film 33 is defined as a
data "0".
[0063] With reference to FIG. 3, the relationship between charge Q
(indicated by the ordinate) and voltage V (indicated by the
abscissa) in a write operation will now be described. In FIG. 3, a
reference numeral 4 denotes a hysteresis loop obtained in data
write, a reference numeral 5 denotes a first gate capacitance load
line obtained in writing a data "1", a reference numeral 6 denotes
a second gate capacitance load line obtained in writing a data "0",
and a reference numeral 7 denotes a third gate capacitance load
line obtained when a bias voltage is 0 V.
[0064] For example, when the potential of the word line WL is set
to 6 V, the magnitude of the polarization of the ferroelectric film
33 of the ferroelectric capacitor 30 corresponds to an upper end
point a on the hysteresis loop 4, and when the potential of the
word line WL is set to -6 V, the magnitude of the polarization of
the ferroelectric film of the ferroelectric capacitor 30
corresponds to a lower end point b on the hysteresis loop 4.
[0065] When a write operation is completed, the potential of the
word line WL is set to 0 V. Thus, in the case where a data "1"
(corresponding to downward polarization) is stored, the potential
of the gate electrode 13 of the reading FET 10 corresponds to a
first intersection c between the hysteresis loop 4 and the third
gate capacitance load line 7, which has positive potential. In the
case where a data "0" (corresponding to upward polarization) is
stored, the potential of the gate electrode 13 of the reading FET
10 corresponds to a second intersection d between the hysteresis
loop 4 and the third gate capacitance load line 7, which has
negative potential.
[0066] Under this condition, the potential of the control line BS
is increased to exceed the threshold voltage of the selecting FET
20, so as to turn on the selecting FET 20. Thus, the potential of
both the upper electrode 31 and the lower electrode 32 of the
ferroelectric capacitor 30 become 0 V. Therefore, in the case where
a data "1" is stored, the potential of the gate electrode 13 of the
reading FET 10 moves from the first intersection c to a first point
e on the ordinate, and in the case where a data floor is stored,
the potential of the gate electrode 13 of the reading FET 10 moves
from the second intersection d to a second point f on the
ordinate.
[0067] Thereafter, even when the potential of the control line BS
is set to 0 V so as to turn off the selecting FET 20, there is no
potential difference between the upper electrode 31 and the lower
electrode 32, and hence, the magnitude of the polarization of the
ferroelectric film 33 is retained.
[0068] (Data Read Operation)
[0069] A read operation of the semiconductor memory of this
embodiment is carried out as follows:
[0070] As described above, the selecting FET 20 is turned on after
a write operation, so as to set the potential of both the upper
electrode 31 and the lower electrode 32 of the ferroelectric
capacitor 30 to 0 V. Therefore, as shown in FIG. 3, in the case
where a data "1" is stored, the potential of the gate electrode 13
of the reading FET 10 moves from the first intersection c to the
first point e on the ordinate and in the case where a data "0" is
stored, the potential of the gate electrode 13 of the reading FET
10 moves from the second intersection d to the second point f on
the ordinate.
[0071] At this point, a voltage of, for example, 1.5 V is applied
to the word line WL of FIG. 1. In this manner, a potential
difference of 1.5 V is caused between the word line WL and the
substrate 14, and the potential difference is divided in accordance
with the capacitance of the ferroelectric capacitor 30 and the gate
capacitance of the reading FET 10. The dependency of the
capacitance of the ferroelectric capacitor 30 on voltage is varied
in accordance with the polarization direction of the ferroelectric
film 33, namely, whether the stored data is "1" or "0". This will
now e described with reference to FIG. 4.
[0072] In assuming a point for keeping the polarization to be he
origin and the gate capacitance to be a load line, a state where a
voltage of 1.5 V is applied to the word line WL is equivalent to
the load line crossing the voltage axis (abscissa) at a point of
1.5 V. This is equivalent to giving a fourth gate capacitance load
line 8 with respect to a data "1" and giving a fifth gate
capacitance load line 9 with respect to a data "0" as shown in FIG.
4.
[0073] When a voltage is applied to the word line WL, a voltage is
also applied to the ferroelectric capacitor 30. Therefore, in the
case where the word line WL has potential of 1.5 V, the
polarization is changed along a first curve A when the data is "1"
so as to be balanced at an intersection g between the first curve A
and the fourth gate capacitance load line 8, and the polarization
is changed along a second curve B when the data is "0" so as to be
balanced at an intersection h between the second curve B and the
fifth gate capacitance load line 9.
[0074] Intersections i, j and k determine the distribution of
potential in the respective polarized states. When the stored data
is "1", a voltage of approximately 0.7 V between the intersection i
and the intersection j is distributed as the gate potential of the
reading FET 10, and when the stored data is "0", a voltage of
approximately 0.9 V between the intersection i and the intersection
k is distributed as the gate potential of the reading FET 10.
[0075] Accordingly, when the threshold voltage of the reading FET
10 is set to 0.8 V corresponding to an intermediate value between
0.7 V and 0.9 V, the reading FET 10 is in an off-state in reading a
data "1" and is in an on-state in reading a data "0".
[0076] Therefore, when a potential difference is caused between the
plate line CP and the bit line BL of FIG. 1, no current flows
through the reading FET 10 when a data "1" is stored and a current
flows through the reading FET 10 when a data "0" is stored.
Accordingly, it can be determined whether the stored data is "1" or
"0" by detecting a current flowing through the reading FET 10 with
separately provided current detection means.
[0077] In this read operation, when the stored data is "1", the
voltage application to the word line WL enhances the polarization
but when the stored data is "0", the voltage application reverses
the polarization. Accordingly, when a voltage applied to the
ferroelectric capacitor exceeds the coercive voltage thereof, the
polarization is reversed. However, in this embodiment, the voltage
applied to the ferroelectric capacitor 30 when the stored data is
"0" is 0.6 V, which is lower than a point m corresponding to the
coercive voltage. Therefore, the polarization is not reversed and
there is no fear of change of a stored data.
[0078] Preferably, the voltage applied between the word line WL and
the substrate 14 is distributed between a voltage applied between
the upper electrode 31 and the lower electrode 32 of the
ferroelectric capacitor 30 and a voltage applied between the gate
electrode 13 of the reading FET 10 and the substrate 14 by
adjusting the capacitance of the ferroelectric capacitor 30 and the
gate capacitance of the reading FET 10, so that the voltage applied
to the ferroelectric capacitor 30 can be set to a value not
exceeding the coercive voltage of the ferroelectric capacitor 30,
namely, a value for not reversing the polarization.
[0079] In this embodiment, the voltage applied to the ferroelectric
capacitor 30 in a read operation is set to a value not exceeding
the coercive voltage of the ferroelectric capacitor, which does not
limit the invention. The voltage applied to the ferroelectric
capacitor 30 may have such magnitude that displacement of the
polarization of the ferroelectric film 33 is restored to that
obtained before reading a data by eliminating the reading voltage
applied to the ferroelectric capacitor 30.
[0080] In this manner, the polarization of the ferroelectric film
33 is not reversed when a read operation is carried out, and hence,
there is no need to carry out an operation for changing the
polarization (the polarization reversing operation) of the
ferroelectric film 33 after every data read. Accordingly,
polarization fatigue is minimally caused in the ferroelectric film
of the ferroelectric capacitor, which largely improves the read
endurance characteristic of the semiconductor memory.
[0081] (Operation after Data Read)
[0082] A first method for making a potential difference between the
upper electrode 31 and the lower electrode 32 of the ferroelectric
capacitor 30 zero after data read will now be described with
reference to FIG. 1.
[0083] First, the potential of the word line WL is set to 1.5 V so
as to read a data stored in the ferroelectric capacitor 30, and
then, the potential of the word line WL is lowered to 0 V.
[0084] Next, the potential of the control line BS is increased to
exceed the threshold voltage of the selecting FET 20, so as to turn
on the selecting FET 20. Thus, the upper electrode 31 and the lower
electrode 32 of the ferroelectric capacitor 30 are connected to
each other through the selecting FET 20, and hence, the potential
of both the upper electrode 31 and the lower electrode 32 become 0
V.
[0085] The polarization charge of the ferroelectric film 33
obtained after a read operation is substantially equal to the
polarization charge obtained before the read operation, and a
potential difference between the upper electrode 31 and the lower
electrode 32 of the ferroelectric capacitor 30 is zero.
Accordingly, lowering of the potential difference through a
resistance component of the ferroelectric capacitor 30 disappears.
This mechanism will be described in detail in Embodiment 2 with
reference to FIG. 9.
[0086] A second method for making a potential difference between
the upper electrode 31 and the lower electrode 32 of the
ferroelectric capacitor 30 zero after data read will now be
described with reference to FIG. 5.
[0087] FIG. 5 shows a circuit for realizing the second method for
making a potential difference between the upper electrode 31 and
the lower electrode 32 of the ferroelectric capacitor 30 zero. The
drain region 21 of the selecting FET 20 is connected between the
lower electrode 32 of the ferroelectric capacitor 30 and the gate
electrode 13 of the reading FET 10, and the source region 22 of the
selecting FET 20 is connected to the plate line CP.
[0088] First, the potential of the word line WL is set to 1.5 V so
as to read a data stored in the ferroelectric capacitor 30, and
then, the potential of the word line WL is lowered to 0 V. Thus,
the potential of the upper electrode 31 of the ferroelectric
capacitor 30 becomes 0 V.
[0089] Next, the potential of the control line BS is increased to
exceed the threshold voltage of the selecting FET 20, so as to turn
on the selecting FET 20. Thus, the lower electrode 32 of the
ferroelectric capacitor 30 and the plate line CP set to 0 V are
connected to each other through the selecting FET 20, and hence,
the potential of the lower electrode 32 also becomes 0 V.
[0090] A third method for making a potential difference between the
upper electrode 31 and the lower electrode 32 of the ferroelectric
capacitor 30 zero after data read will now be described with
reference to FIG. 6.
[0091] FIG. 6 shows a circuit for realizing the third method for
making a potential difference between the upper electrode 31 and
the lower electrode 32 of the ferroelectric capacitor 30 zero. The
drain region 21 of the selecting FET 20 is connected between the
lower electrode 32 of the ferroelectric capacitor 30 and the gate
electrode 13 of the reading FET 10, and the source region 22 of the
selecting FET 20 is connected to a ground line GND.
[0092] First, the potential of the word line WL is set to 1.5 V so
as to read a data stored in the ferroelectric capacitor 30, and
then, the potential of the word line WL is lowered to 0 V. Thus,
the potential of the upper electrode 31 of the ferroelectric
capacitor 30 becomes 0 V.
[0093] Next, the potential of the control line BS is increased to
exceed the threshold voltage of the selecting FET 20, so as to turn
on the selecting FET 20. Thus, the lower electrode 32 of the
ferroelectric capacitor 30 and the ground line GND are connected to
each other through the selecting FET 20, and hence, the potential
of the lower electrode 32 also becomes 0 V.
[0094] A fourth method for making a potential difference between
the upper electrode 31 and the lower electrode 32 of the
ferroelectric capacitor 30 zero after data read will now be
described with reference to FIG. 7.
[0095] FIG. 7 shows a circuit for realizing the fourth method for
making a potential difference between the upper electrode 31 and
the lower electrode 32 of the ferroelectric capacitor 30 zero. The
drain region 21 of the selecting FET 20 is connected between the
lower electrode 32 of the ferroelectric capacitor 30 and the gate
electrode 13 of the reading FET 10, and the source region 22 of the
selecting FET 20 is connected to the substrate 14 of the reading
FET 10.
[0096] First, the potential of the word line WL is set to 1.5 V so
as to read a data stored in the ferroelectric capacitor 30, and
then, the potential of the word line WL is lowered to 0 V. Thus,
the potential of the upper electrode 31 of the ferroelectric
capacitor 30 becomes 0 V.
[0097] Next, the potential of the control line BS is increased to
exceed the threshold voltage of the selecting FET 20, so as to turn
on the selecting FET 20. Thus, the lower electrode 32 of the
ferroelectric capacitor 30 and the substrate 14 of the reading FET
10 set to 0 V are connected to each other through the selecting FET
20, and hence, the potential of the lower electrode 32 also becomes
0 V.
[0098] Embodiment 2
[0099] A semiconductor memory and a method for driving the
semiconductor memory according to Embodiment 2 of the invention
will now be described with reference to FIGS. 8, 9, 10A and
10B.
[0100] FIG. 8 shows an equivalent circuit of a memory cell included
in the semiconductor memory of Embodiment 2. The semiconductor
memory of Embodiment 2 includes a reading FET (N-channel
transistor) 10 having a drain region 11, a source region 12 and a
gate electrode 13, a ferroelectric capacitor 30 having an upper
electrode 31, a lower electrode 32 and a ferroelectric film 30, a
first selecting FET (P-channel transistor) 40 having a drain region
41, a source region 42 and a gate electrode 43, and a second
selecting FET (P-channel transistor) 50 having a drain region 51, a
source region 52 and a gate electrode 53.
[0101] The upper electrode 31 of the ferroelectric capacitor 30 is
connected to the drain region 41 of the first selecting FET 40 and
a word line WL, and the lower electrode 32 of the ferroelectric
capacitor 30 is connected to the gate electrode 13 of the reading
FET 10, the source region 42 of the first selecting FET 40 and the
drain region 51 of the second selecting FET 50. The drain region 11
of the reading FET 10 is connected to a bit line BL, and the source
region 12 of the reading FET 10 is connected to the source region
52 of the second selecting FET 50 and a reset line RST. The gate
electrode 43 of the first selecting FET 40 is connected to a cell
selecting line BS, and the gate electrode 53 of the second
selecting FET 50 is connected to a read cell selecting line /RE.
Accordingly, the gate electrode 13 of the reading FET 10 is
connected to the reset line RST through the second selecting FET
50.
[0102] Now, the method for driving the semiconductor memory of this
embodiment will be described.
[0103] In the semiconductor memory of Embodiment 2, the read cell
selecting line /RE is always set to an L level (of, for example, 0
V) except in a read operation, and the second selecting FET 50 is
always in an on-state except in a read operation. Therefore, merely
in a read operation, charge flows from the ferroelectric capacitor
30 to the gate electrode 13 of the reading FET 10. Also, in
operations other than a read operation, the second selecting FET 50
connects the word line WL to the reset line RST through the first
selecting FET 40 as preparation for a write operation and an erase
operation.
[0104] (Data Write Operation)
[0105] In conducting a data write operation, the first selecting
FET 40 is first turned off by setting the cell selecting line BS to
an H level (of, for example, 5 V), so as to connect the upper
electrode 31 of the ferroelectric capacitor 30 to the word line WL
and to connect the lower electrode 32 of the ferroelectric
capacitor 30 to the reset line RST through the second selecting FET
50.
[0106] Thereafter, with the potential of the reset line RST kept at
an L level (of, for example, 0 V), the potential of the word line
WL is set to an H level so as to cause a positive potential
difference between the upper electrode 31 and the lower electrode
32 of the ferroelectric capacitor 30. Thus, downward polarization
is caused in the ferroelectric film 33 for storing a data "1".
[0107] Then, the potential of the word line WL is set to an L
level, so as to make the potential difference between the upper
electrode 31 and the lower electrode 32 of the ferroelectric
capacitor 30 zero.
[0108] (Data Erase Operation)
[0109] In conducting a data erase operation, the first selecting
FET 40 is turned off by setting the cell selecting line BS to an H
level, so as to connect the upper electrode 31 of the ferroelectric
capacitor 30 to the word line WL and to connect the lower electrode
32 of the ferroelectric capacitor 30 to the reset line RST through
the second selecting FET 50.
[0110] Thereafter, with the potential of the word line WL kept at
an L level, the potential of the reset line RST is increased to an
H level, so as to cause a negative potential difference between the
upper electrode 31 and the lower electrode 32 of the ferroelectric
capacitor 30. Thus, upward polarization is caused in the
ferroelectric film 33 for resetting the stored data to "0".
[0111] (Data Read Operation)
[0112] In conducting a data read operation, the first selecting FET
40 is turned off by setting the potential of the cell selecting
line BS to an H level. Then, the second selecting FET 50 is turned
off by setting the potential of the read cell selecting line /RS to
an H level, the potential the bit line BL is set to an H level and
the potential of the reset line RST is set to an L level. In this
manner, a potential difference is caused between the drain region
11 and the source region 12 of the reading FET 10, and voltage
change on the bit line BL obtained by applying a positive reading
voltage V.sub.RD to the word line WL is detected by a sense
amplifier (not shown) connected to the bit line BL. Thus, a data
stored in the ferroelectric capacitor 30 is read.
[0113] The capacitance of the ferroelectric capacitor 30 and the
gate capacitance of the reading FET 10 are set so that a
relationship of V.sub.R>V.sub.T>V.sub.S can hold among the
threshold voltage V.sub.T of the reading FET 10, a voltage V.sub.S
applied to the gate electrode 13 of the reading FET 10 when the
ferroelectric capacitor 30 stores a data "1", and a voltage V.sub.R
applied to the gate electrode 13 of the reading FET 10 hen the
ferroelectric capacitor 30 stores a data "0".
[0114] Now, read operations respectively conducted when the
ferroelectric capacitor 30 stores a data "1" and when it stores a
data "0" will be described with reference to FIGS. 8 and 9.
[0115] In FIG. 9, the ordinate indicates charge Q of polarization
kept in the ferroelectric film 33 of the ferroelectric capacitor
30, and the abscissa indicates voltage applied to a series circuit.
Also in FIG. 9, E denotes a gate capacitance load line of the
reading FET 10 obtained by applying the reading voltage V.sub.RD to
the word line WL when a data "1" is stored, F denotes a gate
capacitance load line of the reading FET 10 obtained by applying a
reading voltage of 0 V to the word line WL when a data "1" is
stored, G denotes a gate capacitance load line of the reading FET
10 obtained by applying the reading voltage V.sub.RD to the word
line WL when a data "0" is stored, and H denotes a gate capacitance
load line of the reading FET 10 obtained by applying a reading
voltage of 0 V to the word line WL when a data "0" is stored.
[0116] First, the potential of the substrate 14 where the reading
FET 10 is formed is set to an L level.
[0117] Next, in accordance with the aforementioned procedures of a
read operation, the upper electrode 31 of the ferroelectric
capacitor 30 is connected to the word line WL and the lower
electrode 32 of the ferroelectric capacitor 30 is connected to the
reset line RST. Thereafter, the second selecting FET 50 is turned
off by setting the potential of the read cell selecting line /RE to
an H level, the potential of the bit line BL is set to an H level
and the potential of the reset line RST is set to an L level.
[0118] Under this condition, when the positive reading voltage
V.sub.RD is applied to the word line WL, the reading voltage
V.sub.RD is applied to a series circuit composed of the
ferroelectric capacitor 30 and the reading FET 10 and present
between the word line WL and the substrate 14 of the reading FET 10
(hereinafter simply referred to as the series circuit).
[0119] <In Case where Data "1" is Stored>
[0120] In the case where the ferroelectric capacitor 30 stores a
data "1", the polarization charge kept in the ferroelectric film 33
is positioned on a point p. Thereafter, when the reading voltage
V.sub.RD is applied to the series circuit, the reading voltage
V.sub.RD is divided between a potential difference V.sub.S caused
between the gate electrode 13 of the reading FET 10 and the
substrate 14 (namely, a potential difference between points q and
r) and a potential difference V.sub.RD-V.sub.S caused between the
upper electrode 31 and the lower electrode 32 of the ferroelectric
capacitor 30 (namely, a potential difference between the points r
and p).
[0121] The position of the point r, namely, the potential
difference V.sub.S, depends upon the gate capacitance of the
reading FET 10, and the channel conductance of the reading FET 10
in reading a data "1" is determined in accordance with the
potential difference v.sub.S.
[0122] Accordingly, when a ratio between the capacitance of the
ferroelectric capacitor 30 and the gate capacitance of the reading
FET 10 (a capacitance ratio) is set so that a relationship of
V.sub.T>V.sub.S can hold between the threshold voltage V.sub.T
of the reading FET 10 and the potential difference V.sub.S, a
current flowing from the bit line BL set to an H level to the reset
line RST through the channel region of the reading FET 10 is
comparatively small. Therefore, potential drop on the bit line BL
is small.
[0123] The potential drop on the bit line BL is detected by a sense
amplifier connected to the bit line BL, and the detected value is
compared with a previously determined reference value. When the
detected value is not smaller than the reference value, it is
determined that a data "1" is stored.
[0124] <In Case where Data "0" is Stored>
[0125] In the case where the ferroelectric capacitor 30 stores a
data "0", the polarization charge kept in the ferroelectric film 33
is positioned on a point s. Thereafter, when the reading voltage
V.sub.RD is applied to the series circuit, the reading voltage
V.sub.RD is divided between a potential difference V.sub.R caused
between the gate electrode 13 of the reading FET 10 and the
substrate 14 (namely, a potential difference between points t and
u) and a potential difference V.sub.RD-V.sub.R caused between the
upper electrode 31 and the lower electrode 32 of the ferroelectric
capacitor 30 (namely, a potential difference between the points u
and s).
[0126] The position of the point u, namely, the potential
difference V.sub.R, depends upon the gate capacitance of the
reading FET 10, and the channel conductance of the reading FET 10
in reading a data "0" is determined in accordance with the
potential difference V.sub.R.
[0127] Accordingly, when the ratio between the capacitance of the
ferroelectric capacitor 30 and the gate capacitance of the reading
FET 10 (the capacitance ratio) is set so that a relationship of
V.sub.R>V.sub.T can hold between the threshold voltage V.sub.T
of the reading FET 10 and the potential difference V.sub.R, a
current flowing from the bit line BL set to an H level to the reset
line RST through the channel region of the reading FET 10 is
comparatively large. Therefore, the potential drop on the bit line
BL is large.
[0128] The potential drop on the bit line BL is detected by the
sense amplifier connected to the bit line BL, and the detected
value is compared with the previously determined reference value.
When the detected value is smaller than the reference value, it is
determined that a data "0" is stored.
[0129] In this manner, the voltage V.sub.S or V.sub.R applied to
the gate electrode 13 of the reading FET 10 in reading a data "1"
or a data "0" is determined depending upon the reading voltage
V.sub.RD applied to the word line WL, the capacitance of the
ferroelectric capacitor 30 and the gate capacitance of the reading
FET 10.
[0130] In general, the gate capacitance of the reading FET 10 may
be smaller than the capacitance of the ferroelectric capacitor 30
so as to select a capacitance ratio of, for example, 1:4.
[0131] Therefore, a voltage corresponding to merely 1/5 of the
reading voltage V.sub.RD is applied to the ferroelectric capacitor
30 in a read operation.
[0132] When the capacitance ratio is 1:4 and the reading voltage
V.sub.RD is 2.5 V, a voltage applied to the ferroelectric capacitor
30 is merely approximately 0.5 V, which is lower than a voltage
necessary for reversing polarization of the ferroelectric film 33
(namely, the coercive voltage) of the ferroelectric capacitor 30.
Accordingly, even when a data "0" is stored, namely, even when the
reading voltage is applied in a direction for reversing the
polarization of the ferroelectric film 33, the polarization of the
ferroelectric film 33 is not reversed, so that fatigue of the
ferroelectric film 33 through the polarization reverse can be
avoided.
[0133] In this manner, if the reading voltage V.sub.RD applied to
the word line WL, the capacitance of the ferroelectric capacitor 30
and the gate capacitance of the reading FET 10 are appropriately
selected, even when the reading voltage is applied in a direction
for reversing the polarization of the ferroelectric film 33
(namely, even when a data "0" is stored), the polarization is never
reversed but the absolute value of the polarization charge is
definitely reduced correspondingly to a potential difference
between the points s and u.
[0134] Therefore, at the ultimate stage of a read operation of this
embodiment, the potential of the word line WL is lowered from an H
level to an L level and the second selecting FET 50 is turned on by
setting the read cell selecting line /RE to an H level. Thus, a
potential difference between the upper electrode 31 and the lower
electrode 32 of the ferroelectric capacitor 30 is made zero.
[0135] When the second selecting FET 50 is turned on by setting the
read cell selecting line /RE to an H level before lowering the
potential of the word line WL from an H level to an L level, the
polarization charge of the ferroelectric film 33 of the
ferroelectric capacitor 30 is changed along the inside region of a
saturation hysteresis loop to reach a point v when the ultimate
stage of the read operation is completed. Accordingly, the
polarization charge obtained after data read is obviously smaller
than the polarization charge obtained before the data read.
[0136] When a data read operation by this driving method is
repeated, the absolute value of the polarization charge obtained in
reading a data "0" is gradually reduced to approximate to zero.
[0137] Therefore, in this embodiment, before making the potential
difference between the upper electrode 31 and the lower electrode
32 of the ferroelectric capacitor 30 zero by turning on the second
selecting FET 50, the potential of the word line WL is forcedly set
to an L level.
[0138] In this manner, although the polarization charge of the
ferroelectric film 33 of the ferroelectric capacitor 30 is changed
along the inside region of the saturation hysteresis loop, the gate
capacitance load line H of the reading FET 10 obtained when the
reading voltage applied to the word line WL is 0 V affects the
ferroelectric capacitor 30 so that the polarization charge of the
ferroelectric film 33 can cross the ordinate at the point s.
Specifically, a voltage in a reverse direction to the voltage
applied in data read (corresponding to a potential difference
between the points v and w) is applied to the ferroelectric
capacitor 30. Therefore, the polarization charge rapidly moves
through the points u and v to the point w.
[0139] The gradient of the gate capacitance load line (namely, the
gate capacitance) of the reading FET 10 is sufficiently smaller
than (and is approximately 1/4 of) the capacitance of the
ferroelectric capacitor 30, and therefore, the polarization charge
on the point w is substantially equal to the polarization charge on
the point s.
[0140] Therefore, even when the potential difference between the
upper electrode 31 and the lower electrode 32 of the ferroelectric
capacitor 30 is made 0 V by turning on the second selecting FET 50
by setting the potential of the read cell selecting line /RE to an
L level, the magnitude of the polarization charge of the
ferroelectric film 33 of the ferroelectric capacitor 30 storing a
data "0" is minimally different from the magnitude of the
polarization charge obtained before the data read.
[0141] Now, timing in a read operation will be described with
reference to FIGS. 10A and 10B. FIG. 10A shows a timing chart
employed when a data "1" is stored and FIG. 10B shows a timing
chart employed when a data "0" is stored.
[0142] <In Case where Data "1" is Stored>
[0143] First, at time t1, the potential of the read cell selecting
line /RE is set to an H level so as to turn off the second
selecting FET 50, and the potential of the bit line BL is set to an
H level. Also, the potential of the reset line RST is kept at an L
level.
[0144] Next, at time t2, when the potential of the word line L is
set to the reading voltage V.sub.RD, the reading voltage V.sub.RD
is applied to the series circuit present between the word line WL
and the substrate 14 of the reading FET 10. At this point, a
relationship of V.sub.F=V.sub.RD-V.sub.S holds wherein V.sub.F
indicates a voltage distributed to the ferroelectric capacitor 30
and V.sub.S indicates a voltage distributed to the reading FET
10.
[0145] Since the ratio between the capacitance of the ferroelectric
capacitor 30 and the gate capacitance of the reading FET 10 (the
capacitance ratio) is set so that the relationship of
V.sub.T>V.sub.S holds between the threshold voltage V.sub.T of
the reading FET 10 and the voltage V.sub.S distributed to the
reading FET 10, a current flowing from the bit line BL set to an H
level to the reset line RST through the channel region of the
reading FET 10 is comparatively small. Therefore, the voltage drop
on the bit line BL is small.
[0146] The voltage drop on the bit line BL is detected by the sense
amplifier connected to the bit line BL, so as to compare the
detected value with the previously set reference value. When the
detected value is not smaller than the reference value, it is
determined that a data "1" is stored.
[0147] Next, at time t3, when the potential of the word line WL is
lowered to an L level, the voltage V.sub.F distributed to the
ferroelectric capacitor 30 becomes zero.
[0148] Therefore, even when the potential of the read cell
selecting line /RE is lowered to an L level at time t4, the voltage
V.sub.F distributed to the ferroelectric capacitor 30 remains zero,
and hence, no change is caused in the polarization of the
ferroelectric film 33 of the ferroelectric capacitor 30.
[0149] <In Case where Data "0" is Stored>
[0150] First, at time t1, the potential of the read cell selecting
line /RE is set to an H level so as to turn off the second
selecting FET 50, and the potential of the bit line BL is set to an
H level. Also, the potential of the reset line RST is kept at an L
level.
[0151] Next, at time t2, when the reading voltage V.sub.RD is
applied to the word line WL, the reading voltage V.sub.RD is
applied to the series circuit present between the word line WL and
the substrate 14 of the reading FET 10. At this point, a
relationship of V.sub.F=V.sub.RD-V.sub.R holds wherein V.sub.F
indicates the voltage distributed to the ferroelectric capacitor 30
and V.sub.R indicates the voltage distributed to the reading FET
10.
[0152] Since the ratio between the capacitance of the ferroelectric
capacitor 30 and the gate capacitance of the reading FET 10 (the
capacitance ratio) is set so that the relationship of
V.sub.R>V.sub.T can hold between the threshold voltage V.sub.T
of the reading FET 10 and the voltage V.sub.R distributed to the
reading FET 10, a current flowing from the it line BL set to an H
level to the reset line RST through he channel region of the
reading FET 10 is comparatively large. Therefore, the voltage drop
on the bit line BL is large.
[0153] The voltage drop on the bit line BL is detected by the sense
amplifier connected to the bit line BL, so as to compare the
detected value with the previously set reference value. When the
detected value is smaller than the reference value, it is
determined that a data "0" is stored.
[0154] Next, at time t3, the potential of the word line WL is
forcedly returned to an L level, so as to apply a voltage with
polarity reverse to that of the reading voltage V.sub.RD between
the upper electrode 31 and the lower electrode 32 of the
ferroelectric capacitor 30.
[0155] Then, at time t4, the potential of the read cell selecting
line /RE is set to an L level, so as to make a voltage applied to
the ferroelectric capacitor 30 zero.
[0156] In this manner, in a time period between time t3 and time
t4, polarization corresponding to a data "0" is rewritten in the
ferroelectric film 33 of the ferroelectric capacitor 30.
[0157] Accordingly, the magnitude of the polarization of the
ferroelectric film 33 of the ferroelectric capacitor 30
corresponding to a data "0" is not changed between before and after
a read operation. As a result, a data "0" can be stably repeatedly
read out.
[0158] Now, the results of a test carried out for evaluating
Embodiment 2 will be described with reference to FIGS. 11, 12 and
13.
[0159] The evaluation test is carried out by detecting a voltage
V.sub.out of the drain region of the reading FET 10 with a voltage
of 5 V applied to the bit line BL connected to a resistance of 300
k.OMEGA. and with the reset line RST grounded as shown in FIG.
11.
[0160] FIG. 12 shows the relationship between the number of read
cycles (N) and the voltage V.sub.out. In both of the cases where a
data "1" is stored and where a data "0" is stored, the voltage
V.sub.out is not lowered when the number of read cycles is at least
10.sup.12.
[0161] FIG. 13 shows the relationship between the retention time
(h) and the voltage V.sub.out. In both of the cases where a data
"1" is stored and where a data "0" is stored, the voltage V.sub.out
is not lowered even when the retention time approximates to 1000
hours.
[0162] The reading FET 10 is an N-channel MOS transistor and the
first and second selecting FETs 40 and 50 are P-channel MOS
transistors in Embodiment 2. Instead, the reading FET 10 may be a
P-channel MOS transistor with N-channel transistors used as the
first and second selecting FETs 40 and 50. Alternatively, the
reading FET 10 and the first and second selecting FETs 40 and 50
may have the same channel type with the well region of the reading
FET 10 having a different conductivity type from the well regions
of the first and second selecting FETs 40 and 50.
[0163] Embodiment 3
[0164] A semiconductor memory and a method for driving the
semiconductor memory according to Embodiment 3 of the invention
will now be described with reference to FIG. 14.
[0165] As shown in FIG. 14, similarly to Embodiment 1, a plurality
of memory cells each including a ferroelectric capacitor 30 and a
selecting FET 20 connected to each other in parallel are serially
connected to one another, and a reading FET 10 is connected to one
end of each bit column including the plural serially connected
ferroelectric capacitors 30. Also, a plurality of bit column each
including the plural ferroelectric capacitors 30 are provided along
the row direction, so as to form a memory cell array.
[0166] The reading FET 10, the selecting FET 20 and the
ferroelectric capacitor 30 of Embodiment 3 have the same structures
as those of Embodiment 1.
[0167] As shown in FIG. 14, a first word line WL1 is connected to
the gate electrode of the selecting FET 20 included in each memory
cell on the first row, a second word line WL2 is connected to the
gate electrode of the selecting FET 20 included in each memory cell
on the second row, and a third word line WL3 and a fourth word line
WL4 are similarly connected.
[0168] The first bit column including the plural ferroelectric
capacitors 30 is connected to a first control line BS1 at one end
thereof and to the gate electrode of the reading FET 10 at the
other end thereof, and the drain region of the reading FET 10 is
connected to a first bit line BL1. Also, the second bit column
including the plural ferroelectric capacitors 30 is connected to a
second control line BS2 at one end thereof and to the gate
electrode of the reading FET 10 at the other end thereof, and the
drain region of the reading FET 10 is connected to a second bit
line BL2. Furthermore, the source regions of the reading FETs 10 of
the first and second columns are commonly connected to a plate line
CP.
[0169] In Embodiment 3, in selecting, for example, a memory cell on
the first row and in the first bit column connected to the first
control line BS1, the potential of the first word line WL1 is set
to an L level and the potential of the second through fourth word
lines WL2 through WL4 are set to an H level, so that the upper
electrodes and the lower electrodes of the ferroelectric capacitors
30 on the second through fourth rows are short-circuited. In this
manner, the ferroelectric capacitor 30 included in the memory cell
in the first bit column and on the first row is serially connected
to the reading FET 10 of the first bit column. This semiconductor
memory is thus equivalent to that of Embodiment 1.
[0170] Accordingly, a data write operation, a data read operation
and an operation after data read are carried out in the same manner
as in Embodiment 1, resulting in attaining the same effect as that
of Embodiment 1.
[0171] In each of Embodiments 1 through 3, change of the potential
of the gate electrode of the reading FET 10 depending upon whether
a stored data is "1" or "0" is utilized in a read operation so that
logical decision can be made on the basis of the modulation of the
reading FET 10. Instead, the gate voltage of the reading FET 10 may
be introduced to a sense amplifier so as to be compared with a
reference voltage or to amplify a voltage difference between the
gate voltage and a reference voltage for the logical decision.
* * * * *