U.S. patent application number 09/453215 was filed with the patent office on 2001-12-13 for method of forming a contact hole in a seminconductor device.
Invention is credited to LEE, SE-HYEONG, SHIN, JI-CHUL.
Application Number | 20010051425 09/453215 |
Document ID | / |
Family ID | 19562748 |
Filed Date | 2001-12-13 |
United States Patent
Application |
20010051425 |
Kind Code |
A1 |
LEE, SE-HYEONG ; et
al. |
December 13, 2001 |
METHOD OF FORMING A CONTACT HOLE IN A SEMINCONDUCTOR DEVICE
Abstract
A method of forming a contact hole for a semiconductor device,
and a method of forming a capacitor for a semiconductor device
using the same. An interlayer dielectric layer, a contact mask
material layer including of a material having a high etching
selectivity with respect to the interlayer dielectric layer, an
anti-reflection layer, and a photoresist layer, are formed on a
semiconductor substrate. A photoresist pattern is formed from the
photoresist layer to expose part of the anti-reflection layer. and
a flow process is performed on the photoresist pattern to expose
even a smaller amount of the anti-reflection layer. The
anti-reflection layer and the contact mask material layer are then
etched to expose part of the interlayer dielectric layer, and the
interlayer dielectric layer is etched to form a contact hole.
Inventors: |
LEE, SE-HYEONG;
(SUNGNAM-CITY, KR) ; SHIN, JI-CHUL; (SEOUL,
KR) |
Correspondence
Address: |
THE LAW OFFICES OF
EUGENE M. LEE, P.L.L.C.
2111 WILSON BOULEVARD
SUITE 1200
ARLINGTON
VA
22201
US
|
Family ID: |
19562748 |
Appl. No.: |
09/453215 |
Filed: |
December 3, 1999 |
Current U.S.
Class: |
438/639 ;
257/E21.252; 257/E21.257; 257/E21.578; 257/E21.649; 438/233 |
Current CPC
Class: |
H01L 21/31116 20130101;
H01L 27/10855 20130101; H01L 21/76804 20130101; H01L 21/31144
20130101 |
Class at
Publication: |
438/639 ;
438/233 |
International
Class: |
H01L 021/8238; H01L
021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 14, 1998 |
KR |
98-54877 |
Claims
What is claimed is:
1. A method of forming a contact hole for a semiconductor device,
comprising: stacking on each other in sequence an interlayer
dielectric layer, a contact mask material layer comprised of a
material having a high etching selectivity with respect to the
interlayer dielectric layer, an anti-reflection layer, and a
photoresist layer, on a semiconductor substrate; patterning the
photoresist layer to form a first photoresist pattern to expose a
part of a surface of the anti-reflection layer; performing a flow
process on the first photoresist pattern to produce a second
photoresist pattern which exposes a smaller amount of the surface
of the anti-reflection layer than the first photoresist pattern;
etching the anti-reflection layer and the contact mask material
layer using the second photoresist pattern as a mask to form an
anti-reflection layer pattern and a contact mask pattern exposing a
part of the surface of the interlayer dielectric layer; and etching
the interlayer dielectric layer using the second photoresist
pattern, the anti-reflection layer pattern, and the contact mask
pattern as an etch mask, to form the contact hole.
2. The method of claim 1, wherein the second photoresist pattern is
removed before etching the interlayer and after removing the
anti-reflection layer and contact mask layer.
3. The method of claim 1, wherein the contact mask material layer
comprises a conductive material.
4. The method of claim 2, wherein the contact mask material layer
comprises impurity-doped polysilicon.
5. The method of claim 3, wherein the thickness of the
impurity-doped polysilicon layer is between about 500 and about
2,000 .ANG..
6. The method of claim 3, wherein the anti-reflection layer
comprises silicon oxynitride.
7. The method of claim 5, wherein the thickness of the
anti-reflection layer is between about 200 and about 800 .ANG..
8. The method of claim 3, wherein etching the interlayer dielectric
layer comprises using C.sub.4F.sub.8 as an etching gas.
9. The method of claim 8, wherein the etching gas is supplied at a
flow rate of from 10 to 25 SCCM.
10. The method of claim 8, wherein etching the interlayer
dielectric layer comprises using C.sub.4F.sub.8 as an etching gas
and a gas mixture comprising carbon monoxide and argon gas as an
ambient gas.
11. The method of claim 10, wherein the carbon monoxide in the
ambient gas is supplied at a flow rate from about 150 to about 250
SCCM, the argon gas in the ambient gas is supplied at a flow rate
from about 200 to about 400 SCCM, an electric power of about 1,300
to about 2,000 W is supplied to the etching chamber, and an ambient
pressure of from about 20 to about 50 mTorr is maintained.
12. A method of forming a capacitor for a semiconductor device,
comprising: stacking in sequence on each other an interlayer
dielectric layer, a contact mask material layer comprised of a
material having a high etching selectivity with respect to the
interlayer dielectric layer, an anti-reflection layer, and a
photoresist layer, on a semiconductor substrate; patterning the
photoresist layer to form a first photoresist pattern to expose a
part of a surface of the anti-reflection layer; performing a flow
process on the first photoresist pattern to produce a second
photoresist pattern which exposes a smaller amount of the surface
of the anti-reflection layer than the first photoresist pattern;
etching the anti-reflection layer and the contact mask material
layer using the second photoresist pattern as a mask to form an
anti-reflection layer pattern and a contact mask pattern exposing a
part of a surface of the interlayer dielectric layer; etching the
interlayer dielectric layer using the second photoresist pattern,
the anti-reflection layer pattern, and the contact mask pattern as
an etch mask, to form a contact hole; removing the second
photoresist pattern; forming insulation spacers on sidewalls of the
contact hole; forming a conductive layer to fill the contact hole
and to cover an upper surface of the contact mask pattern; and
etching the conductive layer and the contact mask pattern to form a
storage node pattern.
13. The method of claim 12, wherein the second photoresist pattern
is removed before etching the interlayer and after removing the
anti-reflection layer and contact mask layer.
14. The method of claim 12, wherein the anti-reflection layer
pattern is removed before forming the insulation spacers and after
removing the second photoresist pattern.
15. The method of claim 12, wherein the anti-reflection layer
pattern is removed during the forming of the insulation
spacers.
16. The method of claim 12, wherein the contact mask material layer
comprises an impurity-doped polysilicon.
17. The method of claim 12, wherein the anti-reflection layer
comprises silicon oxynitride.
18. The method of claim 12, wherein etching the interlayer
dielectric layer comprises using C.sub.4F.sub.8 as an etching
gas.
19. The method of claim 18, wherein the etching gas is supplied at
a flow rate of from 10 to 25 SCCM.
20. The method of claim 18, wherein etching the interlayer
dielectric layer further comprises using a gas mixture comprising
carbon monoxide and argon gas as an ambient gas.
21. The method of claim 20, wherein the carbon monoxide in the
ambient gas is supplied at a flow rate from 150 to about 250 SCCM,
the argon gas in the ambient gas is supplied at a flow rate from
about 200 to about 400 SCCM, an electric power from about 1,300 to
about 2,000 W is supplied to the etching chamber, and an ambient
pressure from about 20 to about 50 mTorr is maintained.
22. The method of claim 16, wherein the insulation spacers comprise
a material selected from the group consisting of silicon nitride,
silicon oxynitride, and high temperature oxide.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method of forming a
contact hole and a capacitor for a semiconductor device, and more
particularly, to a method of forming a small contact hole through
an interlayer dielectric (ILD) layer having a small critical
dimension and a large step coverage, and a method of forming a
capacitor of a semiconductor device using the method.
[0003] 2. Description of the Related Art
[0004] With the increase in the level of integration of
semiconductor devices, the need for interconnection patterns having
a finer linewidth has increased. In the photolithography process
for forming such a fine contact pattern, first a photoresist
pattern having a critical dimension (CD) of about 200 nm can be
formed using deeply penetrating ultraviolet rays. Then, a
photoresist (PR) flow process is performed in order to form a
photoresist pattern having a finer linewidth than the previously
formed photoresist pattern. The thickness of the photoresist
pattern decreases as a result of the flow process and the width of
the contact hole exposing the underlayer becomes narrower, so that
a pattern of the desired fineness can be formed in subsequent
processing. According to this method, a wire pattern or a contact
pattern having a CD of around 130 nm can be obtained.
[0005] However, the PR flow process for achieving a fine linewidth
causes the following problems. A considerable part of the
photoresist pattern, the thickness of which has been decreased by
the flowing process, is etched when the layer under the photoresist
pattern (an ILD layer made of silicon oxide for example) is dry
etched. As a result, the desired shape of the mask pattern is lost.
If excessive etching is performed, a part or all of the photoresist
pattern may be removed from the top of the substrate, which may
result in enlarging the width of the opening at the top of the
contact holes more than desired. The sidewalls of the contact holes
become slanted with an increase in depth of the hole, so that the
width at the bottom of the contact hole is narrower than the width
of the opening at the top of the holes. If this phenomenon is
serious, the contact may have no opening at the bottom.
[0006] If there is no technical restriction on the thickness of the
photoresist layer, merely forming a thicker photoresist layer can
be one of the solutions for the above described problems. However,
since the resolution of the exposure apparatus depends on the
exposure light source used for the photolithography process, the
thickness of the photoresist cannot be arbitrarily selected. Also,
if excessive photoresist is deposited, the photoresist layer cannot
be completely removed by the subsequent ashing process and the
byproduct from the ashing process may refill the contact holes, so
that the underlayer is not exposed in the contact holes.
[0007] Other problems may also arise. A photoresist pattern having
a small CD is required to produce a small contact hole, but the
process margin may not be enough during the photolithography
process for such a purpose. Also, byproducts produced during the
development step (e.g., residues or bubbles of scummy byproduct)
may be deposited on the contact holes, so that the contact holes
are not opened.
[0008] Such problems are serious in third generation products such
as, for example, the 256 megabyte DRAM, a semiconductor device
having a 0.17 design rule which requires a fine contact having a CD
of 120 nm and a depth of 10,000 .ANG.. Thus, the problems described
above, e.g., that the upper part of the contact is much broader
than the lower part of the contact and that the contact hole is not
opened, must be solved in third generation products.
[0009] Hereinafter, a conventional method for forming a contact and
the problems thereof will be described with reference to the
appended drawings. FIG. 1 is a vertical sectional view of a
semiconductor device illustrating the formation of a photoresist
pattern. An ILD layer 15 and an anti-reflection layer 20 are
stacked in sequence on a semiconductor substrate 10, and then
photoresist is deposited to a predetermined thickness T1 on the top
surface of the resulting structure. A predetermined
photolithography process is performed on the deposited photoresist
to form a photoresist pattern 25 that exposes part of the layer
under the photoresist layer, the anti-reflection layer 20, by a
predetermined width W1. The anti-reflection layer 20 is for
preventing light irradiated onto the surface of the semiconductor
substrate from reflecting during the photolithography process
performed to obtain the photoresist pattern 25.
[0010] FIG. 2 is a vertical sectional view illustrating a
conventional photoresist flow process in which the width of the
opening in the photoresist pattern, through which the
anti-reflection layer is exposed, is reduced from W1 to W2. When
the photoresist flow process is performed, the original photoresist
pattern 25 (see FIG. 1) is deformed to a photoresist pattern 25a
having a reduced thickness T2 (smaller than the thickness T1 shown
in FIG. 1) and a reduced exposure width W2 (narrower than the width
W1 shown in FIG. 1).
[0011] FIG. 3 is a vertical sectional view showing a contact hole
passing through the ILD layer 15, formed by a conventional method.
Using the photoresist pattern 25a of FIG. 2 as a mask, etching is
performed to form a contact hole passing through the
anti-reflection layer 20 and the ILD layer 15. Then the material
layers 25a and 20 deposited on the ILD layer 15 are removed,
resulting in the structure of FIG. 3. It can be seen in FIG. 3 that
the lower width W.sub.b of the contact hole is narrower than the
upper width W.sub.t of the contact hole. This is due to the slanted
sidewalls of the contact hole. If the sidewalls slant too much, the
bottom of the contact hole which exposes the semiconductor
substrate or a lower interconnection level (not shown) may have no
opening at all.
[0012] The present invention is directed to overcoming or at least
reducing the effects of one or more of the problems set forth
above.
SUMMARY OF THE INVENTION
[0013] The present invention is directed to providing a method of
forming a contact hole and a capacitor in a semiconductor device
which reduces or avoids at least one of the above problems.
[0014] According to one aspect of the invention, there is provided
a method of forming a contact hole for a semiconductor device,
including stacking in sequence an interlayer dielectric (ILD)
layer, a contact mask material layer made of a material having a
high etching selectivity with respect to the ILD layer, an
anti-reflection layer, and a photoresist layer on a semiconductor
substrate. Then, the photoresist layer is patterned to form a first
photoresist pattern exposing a predetermined part of an upper
surface of the anti-reflection layer, and a flow process is
performed on the first photoresist pattern to produce a second
photoresist pattern, which exposes a smaller amount of the upper
surface of the anti-reflection layer than the first photoresist
pattern. Subsequently, the anti-reflection layer and the contact
mask material layer are etched using the second photoresist pattern
as a mask, to form an anti-reflection layer pattern and a contact
mask pattern exposing the upper surface of the interlayer
dielectric layer. The interlayer dielectric layer is then etched
using the second photoresist pattern, the anti-reflection layer
pattern, and the contact mask pattern as an etch mask, to form a
contact hole.
[0015] According to another aspect of the invention, there is
provided a method of forming a capacitor for a semiconductor
device, further including removing the second photoresist pattern
before etching the interlayer. The anti-reflection layer pattern
may be removed at this time or before the second photoresist
pattern is removed. Then, insulation spacers are formed on the
sidewalls of the contact mask pattern and the sidewalls of the
contact hole. If the anti-reflection layer pattern has not already
been removed, it may be removed from the contact mask pattern
during the etching process for forming the spacers to avoid the
need for an additional processing step. A conductive layer is
formed to fill the contact hole and to cover the upper surface of
the contact mask pattern, and the conductive layer and the contact
mask pattern are etched to form a storage node pattern. Then a
capacitor of a semiconductor device may be completed using
conventional methods.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above features and advantages of the present invention
will become more apparent by describing in detail preferred
embodiments thereof with reference to the attached drawings in
which:
[0017] FIGS. 1 through 3 are vertical sectional views for
illustrating a conventional method of forming a contact hole;
and
[0018] FIGS. 4 through 12 are vertical sectional views for
illustrating a method of forming a contact hole and a method of
forming a capacitor using the same method according to the present
invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0019] The present invention now will be described more fully with
reference to the accompanying drawings, in which preferred
embodiments of the invention are shown. This invention may,
however, be embodied in many different forms and should not be
construed as being limited to the embodiments set forth herein;
rather, these embodiments are provided so that this disclosure will
be thorough and complete, and will fully convey the concept of the
invention to those of ordinary skilled in the art. In the drawings,
the thicknesses of layers and regions are exaggerated for clarity.
It will also be understood that when a layer is referred to as
being "on" another layer or substrate, it can be directly on the
other layer or substrate, and one or more intervening layers may
also be present. Further, it will be understood that when a layer
13 referred to as being "under" another layer, it can be directly
under, and one or more intervening layers may also be present.
Korean application No. 98-54877 filed Dec. 14, 1998, is hereby
incorporated by reference as if fully set forth herein.
[0020] FIGS. 4 through 12 are vertical sectional views illustrating
a method of forming a contact hole according to a preferred
embodiment of the present invention. FIG. 4 illustrates the
formation of a photoresist pattern. An interlayer dielectric (ILD)
layer 115, a polysilicon layer 120 doped with impurities and used
as a contact mask, and an anti-reflection layer 125 are stacked in
sequence on a semiconductor substrate 110. The impurity-doped
polysilicon layer 120 is preferably comprised of a material having
a high etching selectivity with respect to the ILD layer 115.
[0021] A photoresist layer is then deposited on the top of the
resulting structure to a predetermined thickness T3. A
predetermined photolithography process is performed on the
deposited photoresist to form a photoresist pattern 130 that
exposes a predetermined part of the anti-reflection layer 125, the
layer under the deposited photoresist, by a predetermined width W3.
The anti-reflection layer 125 prevents formation of the photoresist
pattern with more than the desired linewidth caused by reflection
of the light irradiated onto the entire surface of the
semiconductor substrate during the photolithography process for
forming the photoresist pattern 130. Preferably, where the
impurity-doped polysilicon layer 120 is formed to a thickness of
500-2,000 .ANG., the anti-reflection layer 125 of silicon
oxynitride (SiON) is formed to a thickness of 200-800 .ANG..
[0022] FIG. 5 illustrates a photoresist flow process in which the
width of an opening of the photoresist pattern, exposing the
anti-reflection layer 125, is decreased from W3 to W4. As a result
of the photoresist flow process, the original photoresist pattern
130 (see FIG. 4) is deformed into a photoresist pattern 130a, the
thickness T4 and the exposure width W4 of which are both smaller
than the thickness T3 and the exposure width W3 of the original
photoresist pattern 130 shown in FIG. 4.
[0023] FIG. 6 illustrates the formation of a polysilicon layer
pattern to be used as a contact mask. Etching is performed using
the photoresist pattern 130a of FIG. 5 as an etch mask, resulting
in a pattern in which anti-reflection layer pattern 125a and
impurity-doped polysilicon layer pattern 120a are stacked, exposing
a predetermined part of the ILD layer 115. The properties of the
remaining photoresist pattern 130b are not different from that of
the photoresist pattern 130a of FIG. 5, except that the thickness
T5 of the photoresist pattern 130b may be less than the thickness
T4 of photoresist pattern 130a. Also, the exposure width W4 of the
opening of the stacked patterns 120a and 125a is shown as equal to
the width of the opening in the photoresist pattern 130b, but width
W4 actually may be wider or narrower than that of the photoresist
pattern 130b, depending on the etching process used.
[0024] FIG. 7 illustrates the formation of a contact hole using the
patterns 130c, 125a, and 120a stacked on the ILD layer 115 as an
etch mask. Here, the properties of the photoresist pattern 130c are
the same as those of the photoresist pattern 130b of FIG. 6, except
that, because the photoresist pattern 130c is the uppermost
pattern, the thickness T6 is reduced from the thickness T5 of FIG.
6 during the etching process.
[0025] There may be a semiconductor device formed on a part of the
semiconductor substrate 110, which is exposed through the contact
hole in the ILD layer 115a, and the contact hole can be filled with
a conductive material to make an electric connection with an upper
interconnection level not yet deposited. Here, the etching step for
forming the contact hole is preferably performed using a fluoride
gas containing carbon (C) and fluorine (F) as major components,
preferably C.sub.4F.sub.8, as an etching gas. Preferably
C.sub.4F.sub.8 is supplied to an etching chamber at a flow rate of
10-25 SCCM. Also, when etching is performed using C.sub.4F.sub.8 as
an etching gas, a gas mixture of carbon monoxide (CO) and argon
(Ar) is preferably used as an ambient gas. Preferably, CO of the
ambient gas is supplied to the etching chamber at a flow rate of
150-250 SCCM and Ar is supplied to the etching chamber at a flow
rate of 200-400 SCCM. Preferably, 1,300-2,000 W of electric power
is supplied to the etching chamber, and the internal pressure of
the etching chamber is maintained at 20-50 mTorr.
[0026] FIG. 8 illustrates the structure obtained by intentionally
removing the photoresist pattern 130c and the anti-reflection layer
pattern 125a of FIG. 7 from the top surface of the impurity-doped
polysilicon layer pattern 120a after the contact hole has been
formed as described with reference to FIG. 7. The photoresist
pattern 130c is preferably removed by ashing. Compared to FIG. 3,
it is clear that the upper width of the contact hole is nearly the
same as the lower width of the contact hole due to the steep
sidewalls of the contact hole, thus solving the problem of the
conventional method. The anti-reflection layer pattern 125a (see
FIG. 7) must be removed during a capacitor manufacturing process
for a semiconductor device. However, it is not necessary to remove
the anti-reflection layer pattern 125a immediately after the
photoresist layer pattern 130c is removed by ashing. Then, if the
anti-reflection layer pattern 125a of FIG. 7 can be removed
simultaneously in another subsequent process, the manufacturing
process of a semiconductor device can be simplified. This efficient
manufacturing process will be described in more detail later with
reference to FIG. 10.
[0027] FIGS. 9 and 10 are vertical sectional views illustrating the
formation of spacers that surround only the sidewalls of the
contact hole. Referring to FIG. 9, after the anti-reflection layer
pattern 125a formed on the impurity-doped polysilicon layer pattern
120a is removed as described with reference to FIG. 8, an
insulation layer 135 is formed completely surrounding the sidewalls
and bottom of the contact hole as well as the exposed top surface
of the impurity-doped polysilicon layer pattern 120a. The
insulation layer 135 is preferably formed of an insulating material
such as silicon nitride (SiN), silicon oxynitride (SiON), or high
temperature oxide (HTO).
[0028] Referring to FIG. 10, an etching process is performed on the
insulation layer 135 of FIG. 9 so that spacers 135a covering only
the sidewalls of the contact hole(i.e., only the sidewalls of the
impurity-doped polysilicon layer pattern 120b and the ILD layer
pattern 115a) are formed. Here, it is preferable to perform the
etching for forming the spacers 135a so that the spacers 135a can
insulate a storage node pattern 140a (see FIG. 12) from the
environment. Preferably, the insulation layer 135 of FIG. 9 is
anisotropically etched by a dry etching method. As described above,
if the anti-reflection layer pattern 125a of FIG. 7 is not removed
after forming the contact hole, the anti-reflection layer pattern
125a can be removed simultaneously during the etching performed to
form the spacers 135a. That is, an additional step for removing the
anti-reflection layer is not required, and there is the advantage
that the manufacturing process can be simplified.
[0029] FIGS. 11 and 12 are vertical sectional views illustrating
the formation of storage node patterns for a capacitor. Referring
to FIG. 11, a conductive layer 140 is formed on the entire surface
of the substrate 110 having the spacers 135a which are formed
through the steps illustrated with reference to FIGS. 9 and 10.
Here, the contact hole having the spacers 135a is refilled with the
conductive layer 140. The conductive layer 140 must contact the
upper surface of the semiconductor substrate 110 exposed through
the contact hole to make an electrical connection. Preferably, the
conductive layer 140 is formed of the same material used for the
impurity-doped polysilicon layer pattern 120b because this will
result in a better interface between the two layers. Thus, in
forming a capacitor, the formation of the storage node pattern
140a/120c can be simplified. However, if desired, the conductive
layer 140 may be formed from a different material from that used in
the polysilicon layer pattern 120b.
[0030] Referring to FIG. 12, patterning (i.e., etching) of the
conductive layer 140 and the polysilicon layer pattern 120b of FIG.
11 into the storage node pattern 140a/120c is performed, preferably
in the same chamber. The conductive layer 140 of FIG. 11 is changed
into the pattern 140a covering the area surrounding the contact
hole by the etching. The polysilicon layer pattern 120b of FIG. 11
formed under the conductive layer 140 is changed into the
polysilicon layer pattern 120c. Preferably, during the etching
process for forming the storage node pattern 140a/ 120c, the upper
surface of the ILD layer pattern 115a is exposed. In FIG. 12, the
total thickness T9 of the storage node pattern 140a/120c is
expressed as the sum of the thickness T8 of the conductive layer
pattern 140a and the thickness T7 of the polysilicon layer pattern
120c.
[0031] The reason that the polysilicon layer pattern 120c acts as a
part of the storage node pattern 140a/120c is that the polysilicon
layer pattern 120c is doped with impurities for conductivity. The
polysilicon layer pattern 120c of thickness T7, which was used for
another purpose (i.e., as an etch mask during the etching step for
forming a contact hole in the ILD layer 115a), can act as a part of
the storage node pattern 140a/120c of a capacitor. Thus, the
thickness of conductive layer 140 formed in the step illustrated in
FIG. 11 is reduced, thereby lowering the manufacturing cost and the
time required for the deposition of the conductive layer 140, and
increasing the manufacturing efficiency.
[0032] The method of forming a capacitor for a semiconductor device
according to the present invention requires subsequent steps, e.g.,
the steps of forming a dielectric layer and forming a plate node.
The subsequent steps can be performed using a conventional
technology without affecting the purpose, structure, and effect of
the present invention. Also, it is obvious that the method of
forming a contact for a semiconductor device and the method of
forming a capacitor for a semiconductor device according to the
present invention can be applied directly or indirectly to other
steps during the manufacture of a semiconductor device. In
particular, the method of the present invention may be applied to
the step of forming a plug that goes through an interposed material
layer and connects a higher interconnection level and a lower
interconnection level to achieve a plurality of connections.
[0033] As described above, when a contact which is fine enough to
satisfy the need for a highly integrated semiconductor device is
formed by the method according to the present invention, the
problems of the conventional method can be reduced or avoided.
These problems include the broadening of a contact hole at the
upper part, contact failure where a contact hole is filled with
byproducts produced during the photoresist ashing process, and
difficulty in selection of a photoresist etch mask required to form
a contact hole passing through a thick ILD layer. Thus, the present
invention can contribute directly toward more highly integrated
semiconductor devices. Also, the material layer used as a
photoresist etch mask to form the contact hole is not removed and
can be used as a part of another element to be formed later, so
that the cost is reduced and the manufacturing efficiency is
improved.
* * * * *