U.S. patent application number 09/876396 was filed with the patent office on 2001-12-13 for semiconductor device.
This patent application is currently assigned to NEC Corporation. Invention is credited to Kariyazaki, Syuuichi.
Application Number | 20010050423 09/876396 |
Document ID | / |
Family ID | 18674125 |
Filed Date | 2001-12-13 |
United States Patent
Application |
20010050423 |
Kind Code |
A1 |
Kariyazaki, Syuuichi |
December 13, 2001 |
Semiconductor device
Abstract
A semiconductor device including: a semiconductor member having
thereon a plurality of interconnect pads: and a mounting member
having a plurality of electrode terminals electrically and
mechanically connected to the respective interconnect pads for
mounting the semiconductor chip on the mounting member, the
electrode terminals forming a plurality of I/O cells each having
part of the electrode terminals, the part of electrode terminals
including signal terminals, the I/O cells forming a first group of
the I/O cells and a second group of I/O cells disposed on an inner
position of the mounting member with respect to the first group.
The higher integration of the semiconductor device having the
higher performances can be realized because the interconnect lines
can be drawn to the outer periphery of the chip from the
interconnect pads corresponding to each of the I/O cells when the
chip is miniaturized or the number of the ball electrodes is
increased.
Inventors: |
Kariyazaki, Syuuichi;
(Tokyo, JP) |
Correspondence
Address: |
Paul J. Esatto, Jr.
Scully, Scott, Murphy & Presser
400 Garden City Plaza
Garden City
NY
11530
US
|
Assignee: |
NEC Corporation
Tokyo
JP
|
Family ID: |
18674125 |
Appl. No.: |
09/876396 |
Filed: |
June 7, 2001 |
Current U.S.
Class: |
257/678 ;
257/E23.069; 257/E23.07 |
Current CPC
Class: |
H01L 2924/00014
20130101; H01L 2224/16225 20130101; H01L 2924/16195 20130101; H01L
2924/3011 20130101; H01L 2224/73253 20130101; H01L 23/49816
20130101; H01L 23/49838 20130101; H01L 2924/15311 20130101; H01L
2224/05571 20130101; H01L 2224/73204 20130101; H01L 2224/32225
20130101; H01L 2224/05573 20130101; H01L 2224/73204 20130101; H01L
2224/16225 20130101; H01L 2224/32225 20130101; H01L 2924/00
20130101; H01L 2924/15311 20130101; H01L 2224/73204 20130101; H01L
2224/16225 20130101; H01L 2224/32225 20130101; H01L 2924/00
20130101; H01L 2924/00014 20130101; H01L 2224/05599 20130101; H01L
2224/73204 20130101; H01L 2224/16225 20130101; H01L 2224/32225
20130101; H01L 2924/00012 20130101; H01L 2924/15311 20130101; H01L
2224/73204 20130101; H01L 2224/16225 20130101; H01L 2224/32225
20130101; H01L 2924/00012 20130101 |
Class at
Publication: |
257/678 |
International
Class: |
H01L 023/02 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 8, 2000 |
JP |
2000-171594 |
Claims
What is claimed is:
1. A semiconductor device comprising: a semiconductor member having
thereon a plurality of interconnect pads: and a mounting member
having a plurality of electrode terminals electrically and
mechanically connected to the respective interconnect pads for
mounting the semiconductor chip on the mounting member, the
electrode terminals forming a plurality of I/O cells each having
part of the electrode terminals, the part of electrode terminals
including signal terminals, the I/O cells forming a first group of
the I/O cells and a second group of I/O cells disposed on an inner
position of the mounting member with respect to the first
group.
2. The semiconductor device as defined in claim 1, wherein the
semiconductor member is a semiconductor chip, the electrode
terminals are internal electrodes disposed on a bottom surface of
the semiconductor chip, and the mounting member is a package
substrate used for packaging thereon the semiconductor chip.
3. The semiconductor device as defined in claim 1, wherein the
mounting member is a semiconductor package mounting a semiconductor
chip on a packaging substrate, the electrode terminals are ball
electrodes disposed on a bottom surface of the packaging substrate,
and the substrate is a mounting substrate for forming a specified
circuit by mounting the semiconductor package thereon.
4. The semiconductor device as defined in claim 1, wherein the I/O
cell includes only the electrode terminals for signals or the
electrode terminals for signals, power and ground intermingled
among one another.
5. The semiconductor device as defined in claim 4, wherein the I/O
cell includes peripherals.
6. The semiconductor device as defined in claim 1, wherein an
interconnect line is connected to the interconnect pad, and the
interconnect lines connected to the interconnect pad of the at
least one of the I/O cells are formed in a single interconnect
layer.
7. The semiconductor device as defined in claim 6, wherein the
substrate includes the interconnect pad and the interconnect line
electrically connected to the interconnect pad in the single
interconnect layer formed on the surface of the substrate.
8. The semiconductor device as defined in claim 7, wherein the
interconnect lines connected to the I/O cells located on inner
positions extend between the I/O cells located on the outer
periphery.
9. The semiconductor device as defined in claim 6, wherein the
interconnect pads and the interconnect lines electrically connected
to the interconnect pads are formed as a multi-layered interconnect
layer in the substrate.
10. The semiconductor device as defined in claim 9, wherein at
least one of the first group and the second group includes an outer
group and an inner group disposed on the inner position of the
mounting member with respect to the outer group.
11. The semiconductor device as defined in claim 10, wherein the
interconnect lines connected to the interconnect pads corresponding
to the first I/O cells and the interconnect lines connected to the
interconnect pads corresponding to the second I/O cells are formed
in different interconnect layers.
Description
BACKGROUND OF THE INVENTION
[0001] (a) Field of the Invention
[0002] The present invention relates to an area-array semiconductor
device having arranged external electrode terminals on the bottom
surface of a chip or the bottom surface of a package, and more in
detail to the semiconductor device having a reduced size of the
chip or the package and to increase the number of the external
electrode terminals.
[0003] (b) Description of the Related Art
[0004] With the higher integration of a semiconductor device, the
number of external electrode terminals for externally and
electrically connecting a chip or a package mounting the chip is
increased. On the other hand, the miniaturization of the chip or
the package is advanced to reduce the size of the pitch between the
terminals of internal electrode terminals. Accordingly, the pitch
of the interconnect pads formed on a packaging substrate or a
mounting board for packaging the chip thereon is also reduced, and
the reduced pitch makes it difficult to arrange the interconnects
on the packaging substrate or mounting board. As a result, the
miniaturization of the chip and the package is hardly realized.
[0005] A semiconductor device 101 as shown in FIG. 1 is an example
of forming internal electrode terminals on the bottom surface of a
chip 103 which is mounted on a packaging substrate 102. A plenty of
ball electrodes 131 acting as external electrode terminals are
arranged on the bottom surface of the chip 103 in a BGA (ball grid
array) arrangement. The packaging substrate 102 includes, on the
top surface thereof, interconnect pads 121 corresponding to the
ball electrodes 131 of the chip 103 and interconnect lines 122 for
connecting the respective interconnect pads 121. On the bottom
surface of the packaging substrate 102 are arranged packaging ball
electrodes 124 connected to the interconnect pads 121 and the
interconnect lines 122 through intermediary of via-plugs 123. The
chip 103 is mounted over the packaging substrate 102 and covered
and sealed with resin 105, and the ball electrodes 131 of the chip
103 are connected to the interconnect pads 121 by soldering. The
semiconductor device 101 is mounted on a substrate 104, and the
packaging ball electrodes 124 are connected to interconnects pads
141 formed on the top surface of the substrate 104.
[0006] The interconnect pads 121 arranged on the packaging
substrate 102 surface as shown in FIG. 2 are substantially
identical with the ball electrodes 131 formed on the bottom surface
of the chip 103 with respect to their arrangements. The
conventional interconnect pad arrangement has so-called peripherals
including a signal line terminal (S-terminal), a power source
terminal (V-terminal) and a ground terminal (G-terminal) arranged
on a single line and disposed in a region corresponding to the
outer peripheral of the chip 103. As shown in FIG. 2, the
respective interconnect pads 121 including the S-terminal, the
V-terminal and the G-terminal are arranged in the shape of a
lattice by keeping specified intervals. Each of interconnect lines
122 is connected to each of the interconnect pads 121, and extends
toward the outer region of the chip. The interconnect lines 122
connected to the interconnect pads 121 existing in the inner part
outwardly extend between the interconnect pads 121 existing in the
outer part, and the front end of the interconnect line 122 is
electrically connected to the packaging ball electrodes 124 on the
bottom surface of the packaging substrate 102 through intermediary
of the via-plugs 123 as shown in FIG. 1.
[0007] However, in the arrangement of the above interconnect pads,
due to the density of the interconnect pads 121 and the
interconnect lines 122 as shown in FIG. 3, the number of the
interconnect lines 122 extending from the inner interconnect pads
121 is restricted because the diameter of the interconnect pad 121
is generally larger than the width of the interconnect lines 122
and the interval of the adjacent lines.
[0008] When the interconnect pads 121 having a diameter of 100
.mu.m are arranged at a pitch of 250 .mu.m, only two interconnect
lines 122 can be drawn when the line width of the interconnect
lines 122 is 30 .mu.m and the line interval is 30 .mu.m. In other
words, only 12 interconnect lines 122 can be arranged in an area
having a width of 1 mm in the above structure of the interconnect
pads 121, and the density of the interconnect lines is 12 lines/mm.
When the number of the interconnect pads is increased to increase
the number of the interconnect lines, the pitch of the interconnect
pads is required to be larger than 250 .mu.m as described above or
the chip size is required to be larger, thereby hardly realizing
the miniaturization of the chip and the packaging substrate because
the larger area is necessary to arrange the interconnect pads
[0009] In order to solve such a problem, JP-A-10(1998)-116859
describes a technique in which interconnects pads for a standard
power and a standard current which do not receive nor supply
signals are disposed inside a package (chip) and the interconnects
pads are connected to external connecting terminals just below the
chip. In the configuration, since the interconnect pad which does
not receive nor supply signals is not required to be connected to
the interconnect line, the interconnect line to be arranged among
the interconnect pads is unnecessary, thereby reducing the interval
between the adjacent interconnect pads. As a result, the number of
the interconnect pads can be increased and the miniaturization of
the chip can be attained.
[0010] JP-A-9(1997)-69568 describes a technique in which an
input-output buffer is disposed in an open region occurring in an
inner circuit block-disposing area by not distinguishing an
input-output buffer disposing area from the inner circuit
block-disposing area in order to realize the configuration which
effectively utilizes the open area occurring in the inner circuit
blocks without deteriorating the fundamental algorism of a tool for
automatically disposing interconnects when the input-output buffer
and the inner circuit block are disposed on the chip. When the
technique is applied on the chip or the package, at least the
freedom of the disposition with respect to the disposition of the
interconnect pads is elevated to effectively implement the
miniaturization.
[0011] However, in the former publication, the number of the
interconnect pads which do not receive nor supply signals is
assumed not to be small. Accordingly, the technique cannot be
applied when the number of the interconnect pads of this kind is
small and most part of interconnect pads are required to be
connected to interconnect lines. If the technique is applied to
part of the interconnect pads, the number of the interconnect lines
externally drawn is restricted.
[0012] In the latter publication, the number of the input-output
buffers depends on the open area occurring among the inner circuit
blocks, and when the open areas are concentrated, it is uncertain
that the interconnect lines are drawn from the input-output buffers
Accordingly, the interconnect pads must be designed for every floor
plan to increase a period of time. When the drawing-out of the
interconnect lines is hardly attained, the effective means for
responding thereto does not exist.
[0013] In the above technique, the interconnect line formed on the
packaging substrate is assumed to be a single layer. When the
interconnect line formed on the packaging substrate is made to be a
multi-layered structure having two or more layers, the structure
increases the freedom of arranging the interconnect lines to assist
to solve the above problem. However, the multi-layered structure
may make the interconnect lines of the upper layer and the lower
layer crossed with each other to hardly perform the impedance
matching among the interconnect lines, thereby affecting larger
adverse effects on the semiconductor device.
SUMMARY OF THE INVENTION
[0014] In view of the foregoing, an object of the present invention
is to provide a semiconductor device in which a chip or a package
is miniaturized and the number of terminals of external connection
terminals is increased.
[0015] Thus, the present invention provides a semiconductor device
including: a semiconductor member having thereon a plurality of
interconnect pads: and a mounting member having a plurality of
electrode terminals electrically and mechanically connected to the
respective interconnect pads for mounting the semiconductor chip on
the mounting member, the electrode terminals forming a plurality of
I/O cells each having part of the electrode terminals, the part of
electrode terminals including signal terminals, the I/O cells
forming a first group of the I/O cells and a second group of I/O
cells disposed on an inner position of the mounting member with
respect to the first group.
[0016] In accordance with the present invention, the higher
integration of the semiconductor device having the higher
performances can be realized because the interconnect lines can be
drawn to the outer periphery of the chip from the interconnect pads
corresponding to each of the I/O cells when the chip is
miniaturized or the number of the ball electrodes is increased.
[0017] Since the interconnect pads and the interconnect lines
corresponding to the I/O cell is made by the single conductive
film, the interconnect lines connected to the single I/O cell are
not crossed in the vertical direction to easily perform the
impedance matching on each of the interconnect lines.
[0018] The above and other objects, features and advantages of the
present invention will be more apparent from the following
description.
BRIEF DESCRIPTION OF DRAWINGS
[0019] FIG. 1 is a sectional view showing a conventional
semiconductor device.
[0020] FIG. 2 is a schematic view showing interconnect pads and
interconnect lines arranged on a packaging substrate of the
conventional semiconductor device and an enlarged view showing a
part of the arrangement.
[0021] FIG. 3 is a schematic view showing the density of the
conventional interconnect pads and interconnect lines.
[0022] FIG. 4 is a vertical sectional view showing a semiconductor
device in accordance with a first embodiment of the present
invention and an enlarged view thereof.
[0023] FIG. 5 is a schematic view showing interconnect pads and
interconnect lines arranged on a packaging substrate of the first
embodiment.
[0024] FIG. 6 is a schematic view showing the density of the
interconnect pads and the interconnect lines of FIG. 5.
[0025] FIG. 7 is a vertical sectional view showing a semiconductor
device in accordance with a second embodiment and an enlarged view
thereof.
[0026] FIG. 8 is a schematic view showing interconnect pads and
interconnect lines arranged on a packaging substrate of the second
embodiment.
[0027] FIGS. 9A to 9C are a schematic views showing first modified
examples of ball electrodes and the interconnect pads of the second
embodiment.
[0028] FIGS. 10A to 10D are schematic views showing second modified
examples of the ball electrodes and the interconnect pads of the
second embodiment.
[0029] FIGS. 11A to 11D are schematic views showing third modified
examples of the ball electrodes and the interconnect pads of the
second embodiment.
[0030] FIGS. 12A to 12D are schematic views showing fourth modified
examples of the ball electrodes and the interconnect pads of the
second embodiment.
[0031] FIG. 13 is a flow chart sequentially showing steps for
fabricating the semiconductor device of the present invention.
PREFERRED EMBODIMENTS OF THE INVENTION
[0032] Then, the configuration of a semiconductor device of a first
embodiment will be described referring to FIG. 4.
[0033] A semiconductor device 11 includes a packaging substrate 12
and a chip 13 mounted thereon. The packaging substrate 12 is formed
by a dielectric plate material and includes, on the top surface
thereof, a plenty of interconnect pads 21 and interconnect lines 22
formed by etching a conductive film made of copper The interconnect
pads 21 and the interconnect lines 22 are connected to for mounting
ball electrodes 24 on the bottom surface of the packaging substrate
12 through intermediary of via-plugs 23 formed through the
packaging substrate 12. A flame-like spacer 25 is fixed to the
periphery of the top surface of the packaging substrate 12 by using
an adhesive agent, and accommodates the chip in the region
surrounded the spacer 25. A covering plate 27 is fixed on the
spacer 25 by using another adhesive agent 26 to seal the chip
13.
[0034] The chip 13 is formed by a semiconductor substrate such as
silicon, and various elements such as a transistor not shown in the
drawing are formed on the bottom main surface of the chip 13 and
are covered with a protective dielectric film such as a passivation
film. On the surface of the protective dielectric film or on the
bottom surface of the chip are formed and arranged ball electrodes
31 made of solder, connected to the above elements, acting as
internal electrodes. The ball electrodes 31 are soldered to the
interconnect pads 21 formed on the packaging substrate 12 to mount
the chip 13 on the packaging substrate 12 in a face-down manner,
and the elements in the chip 13 are electrically connected to the
ball electrodes 24 on the bottom surface of the packaging substrate
12 through intermediary of the ball electrodes 31 and the
interconnect pads 21. The chip 13 is sealed is sealing resin
28.
[0035] In the first embodiment, the semiconductor device 11 is
mounted on a mounting substrate 14. A specified interconnect
pattern is formed on a dielectric substrate by using a conductive
film to prepare the mounting substrate 14. The interconnect pattern
includes interconnects pads 41 connected to the ball electrodes 24
of the semiconductor device 11 and interconnect lines, not shown in
the drawings, for connecting the interconnect pads 41 among one
another on the mounting substrate 14 or the interconnect pad 41
with interconnect lines not shown in the drawings for connecting
the interconnect pad 41 to an external circuit.
[0036] An example of configuration will be described, referring to
FIG. 5, in which the ball electrodes 31 are formed and arranged on
the bottom surface of the chip 13 of the semiconductor device 11
and interconnect pads 21 are formed and arranged on the top surface
of the packaging substrate 12 corresponding to the ball electrodes
31.
[0037] The interconnect pads 21 formed on the top surface of the
packaging substrate 12 shown in FIG. 5 are disposed corresponding
to the ball electrodes 31 on the bottom surface of the chip 13. The
ball electrodes 31 on the bottom surface of the chip 13 are
arranged in the shape of a lattice and the interconnect pads 21 are
also arranged in the shape of the lattice corresponding to the ball
electrodes 31. The specified number of the ball electrodes 31 and
the interconnect pads 21 are grouped as a single I/O cell as shown
in FIG. 5 in which only the interconnect pads 21 are shown, and
these are arranged as the I/O cell unit. In the embodiment, the
plenty of the interconnect pads 21 are divided such that the single
I/O cell includes an array of 4.times.3 interconnect pads 21. The
I/O cell is, for example, a single group including a single unit
having one or more input-output buffers formed in the chip 13 and
an S-terminal (signal line terminal), a V-terminal (power source
terminal) and a G-terminal (ground terminal) connected to the
input-output buffers, or the single I/O cell may include only the
S-terminal. However, the number of the terminals and the
arrangement are not restricted to the above, and an I/O cell having
an arbitrary array can be formed.
[0038] Among the grouped I/O cells, part of the I/O cells (CELL-A)
are disposed on the periphery of the chip 13 similarly to the
conventional chip, and the remaining cells (CELL-B) are internally
disposed from the above I/O cells (CELL-A) at a specified interval.
In this case, the adjacent I/O cells (CELL-A) disposed on the
periphery have a specified space therebetween. In the first
embodiment, if the additional space exists between the adjacent I/O
cells (CELL-A), peripherals (PL) conventionally used are also
disposed on the chip. The peripherals are present in the open space
in the 4.times.3 array.
[0039] As shown in FIG. 6, two outer peripheral I/O cells (CELL-A)
on the chip 13 are disposed with a specified interval along the
periphery, and one inner I/O cell (CELL-B) is disposed in a space
opposing to the location between the two outer peripheral. I/O
cells (CELL-A). Similarly to the preceding example, the
interconnect lines 22a are connected to each of the interconnect
pads 21a of the two outer peripheral I/O cells (CELL-A), and are
drawn between the interconnect pads 21a to regions external to the
chip 13. On the other hand, the interconnect lines 22b are
connected to each of the interconnect pads 21b of the inner
peripheral I/O cell (CELL-B), and are drawn similarly to the
preceding example in the region of the peripheral I/O cell
(CELL-B), and are bundled at a specified interval, at a region out
of the inner peripheral I/O cell (CELL-B), to be drawn between the
outer peripheral I/O cells (CELL-A) to regions external to the chip
13.
[0040] In the structure of the interconnect pads 21 and the
interconnect lines 22 on the packaging substrate 12, the density of
arranging the interconnect lines 21a at the I/O cells (CELL-A)
arranged on the outer periphery of the chip 13 is substantially
same as the density of the conventional device shown in FIG. 3.
However, the density of arranging the interconnect lines 21b
connected to the interconnect pad 21b of the I/O cells (CELL-B)
arranged inside of the chip 13 can be increased because of the
absence of the interconnect pads.
[0041] When the line width of the interconnect lines connected to
the 12 interconnect pads 21 is 30 .mu.m and the line interval is 30
.mu.m as shown in FIG. 6, the dimension of arranging the 12 bundled
interconnect lines 22i is 750 .mu.m. The number of the interconnect
lines 22 in the region having a size of 2 mm along the outer
periphery of the chip is 27 calculated by adding the number of the
interconnect lines 22a of the outer peripheral I/O cells (CELL-A)
to the number of the interconnect lines 22b of the inner I/O cells
(CELL-B). The density of the interconnect lines 22 is 13.5 lines/mm
in the embodiment, and is increased compared with conventional
density of 12 lines/mm shown in FIG. 3.
[0042] Thereby, even when the size of the chip 13 is reduced for
miniaturization or the numbers of the ball electrodes 31 and the
interconnect pads 21 are increased with the chip 13 having the same
size, the higher integration of the semiconductor device having the
higher performances can be realized by dividing the ball electrodes
31 disposed on the chip 13 and the interconnect pads arranged on
the packaging substrate 12 into the plurality of the I/O cells and
disposing part of the I/O cells at the outer periphery of the chip
13 and the remaining I/O cells at the corresponding inner sections
of the chip 13 because the drawing-out of the interconnect lines 22
to the peripheral outer regions of the chip on the top surface of
the packaging substrate 12 is possible.
[0043] Especially, as shown in FIG. 6, since the interconnect lines
of the other I/O cells do not pass through the I/O cells (CELL-B)
disposed on the inner section of the chip, the I/O cells (CELL-B)
may be formed endlessly or annually to enable the arrangement of
the extremely larger number of the ball electrodes 31 and the
interconnect pads 21. An interval may exist between the I/O cells
(CELL-B) disposed on the inner section. The ball electrodes 31 and
the interconnect pads 21 of the outer peripheral I/O cells (CELL-A)
may be freely disposed so long as the spaces through which the
interconnect lines 22 of the I/O cells (CELL-B) disposed on the
inner section pass may be secured, thereby promoting the higher
integration of the semiconductor device having the higher
performances. The I/O cells can be freely disposed in the regions
of the chip so long as the above requisites are satisfied to
increase the freedom of the chip design and the package design.
[0044] Since the interconnect pads 21 and the interconnect lines 22
in the embodiment are made by the conductive film having the single
layer, the interconnect lines connected to the single I/O cell are
not crossed in the vertical direction to easily perform the
impedance matching on each of the interconnect lines. Especially,
when the interconnect pads and the interconnect lines corresponding
to the plurality of the input-output buffers are intermingled in
the single I/O cell, the proper impedance matching is possible by
preventing the mutual intervention between the interconnect lines
of each of the input-output buffers.
[0045] A second embodiment of the present invention is shown in
FIG. 7 in which the same numerals as those of the first embodiment
designate the same elements. A semiconductor device 11 includes a
packaging substrate 12A and a chip 13 mounted thereon. The
packaging substrate 12A includes a central core layer 211
sandwiched between a pair of buildup layers 212, 213, and a plenty
of interconnect pads 21 made of a conductive film are formed on the
top buildup layer 212. The interconnect pads 21 are connected to
the interconnect lines in each of the multi-layers of the top
buildup layer 212, further connected to the bottom buildup layer
213 through intermediary of via plugs, and still further connected
to ball electrodes 24 formed on the bottom surface of the bottom
buildup layer 213 or the bottom surface of the packaging substrate
12A.
[0046] Each of the buildup layers is multi-layered, and the top
buildup layer 212 includes five interconnect layers in which a
first layer includes the interconnect pads 21 and a GND layer, a
third layer includes a GND layer 3G and a VDD layer 3V, and a fifth
layer includes a GND layer 5G and a VDD layer 5V connected to the
via plugs of the above core layer. A second layer and a fourth
layer are formed as independent interconnect lines 22a, 22b for
signals. In the second embodiment the interconnect lines formed in
the single layer in the first embodiment are divided into the first
to fifth interconnect layers 201 to 205. Especially, the
interconnect lines connected to the interconnect pad 21 acting as
the S-terminal (signal terminal) can be drawn as the interconnect
lines 22 of the second and fourth layers separately from the
others.
[0047] In view of the increased number of layers (two-layered) of
the interconnect lines 22a, 22b, as schematically shown in FIG. 8,
the grouped I/O cell in the arrangement of the interconnect pads 21
as well as the ball electrodes 31 of the chip 13 can be divided
into a first I/O cell (CELL-1) and a second I/O cell (CELL-2). Part
of the first I/O cell (CELL-1) or I/O cells (CELL-1A) are disposed
on the outer peripheral region of the chip 13, and the remaining
I/O cells (CELL-1B) are disposed on the inner sections of the chip
13. Intervals are secured between the first I/O cells (CELL-1A)
remaining on the outer periphery for passing the interconnect lines
22 drawn from the inner I/O cells (CELL-1B). In FIG. 8, the first
I/O cells (CELL-1) disposed on the outer periphery are alternately
disposed on outer sections (CELL-1A) and inner parts (CELL-1B) in
the outer periphery. The second I/O cells (CELL-2) are disposed on
the sections inside of the other I/O cells (CELL-1), and part of
the second I/O cell (CELL-2) or I/O cells (CELL-2B) are disposed
inside of the remaining I/O cells (CELL-2A) and intervals are
secured between the outer second I/O cells (CELL-2A) for passing
the interconnect lines drawn from the inner second I/O cells
(CELL-2B). In FIG. 8, similarly to the first I/O cells (CELL-1),
the second I/O cells (CELL-2) are alternately disposed on outer
sections (CELL-2A) and inner parts (CELL-2B).
[0048] Referring again to FIG. 7, the interconnect line 22-1
connected to the interconnect pad 21-1 of the first I/O cell
(CELL-1) is connected in its outer region to the second
interconnect layer 202 of the top buildup layer 212 and drawn to
the outer region by the second interconnect layer 202. The
interconnect line 22-2 connected to the interconnect pad 21-2 of
the second I/O cell (CELL-2) is connected in the area between its
outer region and the first I/O cell (CELL-1) to the fourth
interconnect layer 204 of the top buildup layer 212 and drawn to
the outer region by the fourth interconnect layer 204. Accordingly,
the interconnect line 22-2 connected to the second I/O cell
(CELL-2) is never drawn to the outer region through the first I/O
cells (CELL-1). The interconnect lines 202, 204 of the second and
the fourth layers are connected to the via plugs 23 of the core
layer 211 at specified positions and further connected to the ball
electrodes 24 on the bottom surface of the packaging substrate 12A
through intermediary of the bottom buildup layer 213.
[0049] The configuration of the interconnect pads 21 and the
interconnect lines 22 on the top surface of the packaging substrate
12A obtained in this manner is similar to that shown in FIG. 6 for
each of the first I/O cell (CELL-1) and the second I/O cell
(CELL-2), and enables to elevate the density of the interconnect
pads 21 and the interconnect lines 22 of the first I/O cell
(CELL-1) and the second I/O cell (CELL-2). Since the first I/O cell
(CELL-1) and the second I/O cell (CELL-2) are double-disposed in
the second embodiment, the density almost twice that of the first
embodiment can be obtained. Thereby, even when the chip is
miniaturized or the numbers of the ball electrodes and the
interconnect pads are increased, the higher integration of the
semiconductor device having the higher performances can be realized
by drawing the interconnect lines of each of the I/O cells.
[0050] Since the interconnect lines 22-1 of the first I/O cell
(CELL-1) is drawn by the second interconnect layer 202 and the
interconnect lines 22-2 of the second I/O cell (CELL-2) is drawn by
the fourth interconnect layer 204 in the second embodiment, the
interconnect lines connected to the respective I/O cells are drawn
to the single interconnect layer and are not crossed in the
vertical direction to easily perform the impedance matching on each
of the interconnect lines. Especially, when the interconnect pads
and the interconnect lines corresponding to the plurality of the
input-output buffers are intermingled in the single I/O cell, the
proper impedance matching is possible by preventing the mutual
intervention between the interconnect lines of each of the
input-output buffers similarly to the first embodiment.
[0051] Modified first examples of arranging the first I/O cell
(CELL-1) and the second I/O cell (CELL-2) in the second embodiment
are shown in FIGS. 9A to 9C. In FIG. 9A, only for the first I/O
cell (CELL-1), the outer I/O cell (CELL-1A) and the inner I/O cell
(CELL-1B) are disposed. In FIG. 9B, only for the second I/O cell
(CELL-2), the outer I/O cell (CELL-2A) and the inner I/O cell
(CELL-2B) are disposed. As shown in FIG. 9C, each of the first I/O
cell (CELL-1) and the second I/O cell (CELL-2) may be disposed in a
single row.
[0052] Modified second examples of arranging the I/O cells in the
second embodiment are shown in FIGS. 10A to 10D in which either of
the first I/O cell (CELL-1) and the second I/O cell (CELL-2) is not
the I/O cell but the conventional peripherals. In FIG. 10A, the
outer peripheral section is formed by peripherals PL and the inner
section is formed by the second I/O cell (CELL-2). In FIG. 10B, the
inner second I/O cell (CELL-2) of FIG. 10A is formed by the outer
I/O cell (CELL-2A) and the inner I/O cell (CELL-2B). In FIG. 10C,
the outer peripheral section is formed by the first I/O cell
(CELL-1) and the inner section is formed by the peripherals PL. In
FIG. 10D, the outer first I/O cell (CELL-1) of FIG. 10C is formed
by the outer I/O cell (CELL-1A) and the inner I/O cell
(CELL-1B).
[0053] As shown in FIGS. 11A to 11D corresponding to FIGS. 10A to
10D, respectively, part of the first I/O cell (CELL-1) or the
second I/O cell (CELL-2) is formed by the peripherals PL to
intermingle the I/O cells and the peripherals PL. Similarly, as
shown in FIGS. 12A to 12D, part of the first I/O cells (CELL-1A,
CELL-1B) or the second I/O cells (CELL-2A, CELL-2B) formed by the
inner I/O cells and the outer I/O cells may be formed by the
peripherals PL In either case, the higher integration of the
semiconductor device having the higher performances can be realized
compared with the conventional configuration as shown in FIG. 2
because the ball electrodes and the number of the interconnect pads
can be increased.
[0054] The method of disposing the ball electrodes 31 and the
interconnect pads 21 as the I/O cells are substantially same for
the semiconductor devices of the first and the second embodiments.
The method for disposing the semiconductor device in the first
embodiment will be described referring to a flow chart shown in
FIG. 13.
[0055] At first, a template having I/O cells and peripherals to be
disposed on a chip along the outer periphery of the chip is
fabricated (S101). Then, the judgment is conducted whether or not
the numbers of the balls electrodes and the interconnect pads of
the I/O cell and the peripherals, and the number of required
terminals reach to specified values (S102). When the numbers reach
to the required values, the judgment is conducted whether or not
the request for disposing I/O cells at the center of the chip
(S103). In absence of the request, the disposal is finished (S104).
In present of the request for disposing the I/O cells at the center
of the chip, the cell is moved in accordance with a floor plan
(S105). When the movement is possible, the disposal is finished
(S104). When the movement is impossible, the step (S105) is again
executed after the floor plan and the I/O cells are modified. When
the movement is also impossible after the repetition of the
processes, a following step (S108) is initiated.
[0056] On the other hand, when the number of the terminals does not
reach to the required number in the step (S102), the number of the
I/O cells disposed on the inner sections of the chip is calculated
(S107) for increasing the number to the required one. Then, another
new template having a reduced interval between the I/O cells is
fabricated (S108). Then, the I/O cell is moved in accordance with a
floor plan (S109). When the movement of all the I/O cells is
possible, the disposal is finished (S104) because the I/O cells can
be disposed on the outer periphery and on the inner section of the
chip. When at least one of the I/O cells cannot move, the step
(S109) is again executed after a further template having a reduced
interval between the I/O cells is fabricated (S110). Or, depending
on necessity, the step (S109) is again executed after the
modification of the floor plan and the I/O cells. When the disposal
of all the I/O cells is not finished after the plurality of the
re-executions, the disposal is recognized to be failed, and the
procedures are started from the first step (S101) after the chip is
enlarged or the number of the interconnects is increased.
[0057] In the second embodiment, a process of diving the I/O cell
into the first I/O cell and the second I/O cell is inserted between
the steps (S107) and (S108), and the processes are conducted on and
after the step (S108) for each of the I/O cells.
[0058] In the method described above, after the I/O cell is formed
by grouping the S-terminal, the V-terminal and the G-terminal, the
method of disposing the interconnect pads of the I/O cell and
drawing the interconnect lines connected to the interconnect pads
is determined in advance. Thereby, the propriety of drawing the
interconnect lines at the time of preparing the floor plan can be
easily judged to advantageously reduce a length of processing time
(TAT). The method can be easily customized for every kind of the
semiconductor devices by suitably using the I/O cells having
different usages after the usages of each of the I/O cells are
stored as information.
[0059] Although the array of 4.times.3 is exemplified as the
arrangement of the I/O cells in the previous embodiments, the I/O
cells can be arranged in an array having an arbitrary number.
Depending on cases, the I/O cell may be formed by disposing the
plurality of the conventional peripherals.
[0060] Although the examples are described for applying the
configuration of the present invention to the ball electrodes 31
formed on the bottom surface of the chip 13 and the interconnect
pads 21 and the interconnect lines 22 on the packaging substrate
12, 12A in the preceding embodiments, the present invention may be
also applied to the ball electrodes 24 of the semiconductor device
11 and the interconnect pads 41 and the interconnect lines on the
mounting substrate 14. The ball electrodes 24 on the bottom surface
of the packaging substrate 12, 12A and the interconnect pads 41 on
the top surface of the mounting substrate 14 are disposed as the
I/O cells to increase the density of the ball electrodes 24 and the
interconnect pads 41 to achieve the miniaturization of the chip and
further to increase the number of the terminals, the higher
integration of the semiconductor device having the higher
performances can be realized. When the configuration of the second
embodiment is applied, the mounting substrate 14 is
multi-layered.
[0061] Since the above embodiment is described only for examples,
the present invention is not limited to the above embodiment and
various modifications or alterations can be easily made therefrom
by those skilled in the art without departing from the scope of the
present invention.
* * * * *