U.S. patent application number 09/197567 was filed with the patent office on 2001-12-13 for method of manufacturing a rom device that includes ion implantation through an insulating layer.
Invention is credited to ARITA, HIDENORI, MIYATA, KAZUAKI.
Application Number | 20010050405 09/197567 |
Document ID | / |
Family ID | 15839222 |
Filed Date | 2001-12-13 |
United States Patent
Application |
20010050405 |
Kind Code |
A1 |
ARITA, HIDENORI ; et
al. |
December 13, 2001 |
METHOD OF MANUFACTURING A ROM DEVICE THAT INCLUDES ION IMPLANTATION
THROUGH AN INSULATING LAYER
Abstract
The semiconductor device is provided with an element isolating
region disposed in a matrix to define a channel region on a
semiconductor substrate, gate interconnection layers extending in a
direction and disposed at predetermined intervals from each other
above element isolating region, and aluminum interconnection layers
extending in a direction intersecting gate interconnection layers
and disposed at predetermined intervals from each other, aluminum
interconnection layer being disposed above element isolating
region. Thus, it becomes possible to provide a semiconductor device
and a method of manufacturing thereof which enable the reduction in
time required for the final manufacturing steps of the
semiconductor device after the ROM specifications are
determined.
Inventors: |
ARITA, HIDENORI; (HYOGO,
JP) ; MIYATA, KAZUAKI; (HYOGO, JP) |
Correspondence
Address: |
MCDERMOTT WILL & EMERY
600 13TH STREET, N.W.
WASHINGTON
DC
20005-3096
US
|
Family ID: |
15839222 |
Appl. No.: |
09/197567 |
Filed: |
November 23, 1998 |
Current U.S.
Class: |
257/510 ;
257/E21.627; 257/E21.672; 257/E23.019; 257/E27.102 |
Current CPC
Class: |
H01L 2924/00 20130101;
H01L 27/112 20130101; H01L 27/1126 20130101; H01L 21/823475
20130101; H01L 23/485 20130101; H01L 2924/0002 20130101; H01L
2924/0002 20130101 |
Class at
Publication: |
257/510 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 15, 1998 |
JP |
10-166873(P) |
Claims
What is claimed is:
1. A semiconductor device, comprising: an element isolating region
disposed in a matrix for defining an active region on a
semiconductor substrate; first conductive layers extending in a
direction and disposed at predetermined intervals from each other
above said element isolating region; and second conductive layers
extending in a direction intersecting said first conductive layers
and disposed at predetermined intervals from each other above said
first conductive layers, said second conductive layers being
disposed above said element isolating region.
2. The semiconductor device according to claim 1, wherein said
active region forms source/drain regions and a channel region, each
of said first conductive layers forming a gate interconnection
layer, each of said second conductive layers forming an aluminum
interconnection layer, said source/drain regions, channel region,
gate interconnection layer, and aluminum interconnection layer
together forming an ROM transistor.
3. A method of manufacturing a semiconductor device, comprising the
steps of: forming an element isolating region in a matrix to define
an active region on a semiconductor substrate; forming a first
conductive layer at a given location of said active region defined
by said element isolating region with an insulating film
therebetween; introducing a first impurity into said semiconductor
substrate using said first conductive layer as a mask to form an
impurity diffusion region; covering said impurity diffusion region
and said first conductive layer to form an interlayer insulating
film having a contact hole reaching said impurity diffusion region;
forming a resist film covering said contact hole and leaving
exposed a region corresponding to said active region below said
first conductive layer; introducing a second impurity into said
active region using said resist film as a mask to adjust impurity
concentration in said active region below said first conductive
layer; removing said resist film and thereafter forming on said
interlayer insulating film a second conductive layer connecting
electrically to said impurity diffusion region at a contact hole;
and forming a surface protection layer to cover said second
conductive layer.
4. The method of manufacturing a semiconductor device according to
claim 3, wherein said insulating film is a silicon oxide film
having a thickness of 100 .ANG. to 300 .ANG. formed by thermal
oxidation, said first conductive layer having a film thickness of
2000 .ANG. to 6000 .ANG. and having a two-layered structure
including a polycrystalline silicon layer formed by the CVD method
and a tungsten silicide layer formed by sputtering, said interlayer
insulating film having a thickness of 0.41 .mu.m to 1.2 .mu.m,
being made of at least one of TEOS and BPSG, and being formed by
the CVD method, said second impurity being introduced at an
acceleration voltage of 400 keV to 1000 keV.
5. A method of manufacturing a semiconductor device comprising the
steps of: forming an element isolating region in a matrix to define
an active region on a semiconductor substrate; forming a first
conductive layer at a given location of said active region defined
by said element isolating region with an insulating film
therebetween; introducing a first impurity into said semiconductor
substrate using said first conductive layer as a mask to form an
impurity diffusion region; covering said impurity diffusion region
and said first conductive layer to form an interlayer insulating
film having a contact hole reaching said impurity diffusion region;
forming on said interlayer insulating film a second conductive
layer extending above said element isolating region and connecting
electrically to said impurity diffusion region at a contact hole;
forming a surface protection layer covering said interlayer
insulating film and said second conductive layer; forming on said
surface protection layer a resist film leaving exposed a region
corresponding to said active region below said first conductive
layer; and introducing a second impurity into said active region
using said resist film as a mask to adjust impurity concentration
in said active region below said first conductive layer.
6. The method of manufacturing a semiconductor device according to
claim 5, wherein said insulating film is a silicon oxide film
having a thickness of 100 .ANG. to 300 .ANG. formed by thermal
oxidation, said first conductive layer having a film thickness of
2000 .ANG. to 6000 .ANG. and having a two-layered structure
including a polycrystalline silicon layer formed by the CVD method
and a tungsten silicide layer formed by sputtering, said interlayer
insulating film having a film thickness of 0.4 .mu.m to 1.2 .mu.m,
being made of at least one of TEOS and BPSG, and being formed by
the CVD method, said surface protection layer being a nitride film
with a thickness of 0.5 .mu.m to 1.0 .mu.m, said second impurity
being introduced at an acceleration voltage of 1000 keV to 2000
keV.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device and
a method of manufacturing the device, and more specifically to the
improvements in the pattern configuration of an ROM region of a
semiconductor device incorporating an ROM (Read Only Memory) and to
a method of manufacturing the device.
[0003] 2. Description of the Background Art
[0004] In general, in manufacturing a semiconductor device
incorporating an ROM formed using photolithography and
ion-implantation techniques, the specifications of the ROM vary
according to the needs of the customers. Consequently, since all
semiconductor devices employ masks of identical specifications,
during the manufacturing steps of the semiconductor device
incorporating an ROM, the same manufacturing steps are adopted as
far as the step preceding the forming step of an ROM region. As a
result, the structures of the semiconductor devices at this
unfinished stage are identical, and in this unfinished condition
the semiconductor devices are stored for the time being.
[0005] Then, after the specifications of an ROM are determined
based on the order placed by the customer, the manufacturing steps
for the unfinished semiconductor device are resumed, an ROM region
is patterned according to the ROM specifications, and the final
manufacturing steps are carried out.
[0006] Referring now to FIG. 14, the planar pattern structure of an
ROM region in the conventional semiconductor device will be
described.
[0007] Element isolating regions 12 are disposed regularly at
predetermined intervals in the X and Y directions, and gate
interconnection layers 13 extending in the Y direction are disposed
at predetermined intervals in the X direction.
[0008] Aluminum interconnection layers 10 extending in the X
direction are disposed at predetermined intervals in the Y
direction in regions between element isolating regions 12. A
plurality of contact holes 9 are provided in aluminum
interconnection layer 10 to provide electrical connection to active
regions on a semiconductor substrate 1. A channel region 14 of an
ROM transistor is formed on semiconductor substrate 1 where gate
interconnection layer 13 and aluminum interconnection layer 10
intersect.
[0009] Referring now to FIGS. 15-19, the manufacturing steps of an
ROM transistor formed in the ROM region having the above-mentioned
structure will be described below.
[0010] Referring first to FIG. 15, element isolating region 12 as
shown in FIG. 14 is formed in a matrix using the LOCOS (Local
Oxidation of Silicon) method to define an active region in a given
region on the surface of silicon semiconductor substrate 1.
[0011] Next, a silicon oxide film 2 having a thickness of 100 .ANG.
to 300 .ANG. is formed by thermal oxidation on the surface of
silicon semiconductor substrate 1. Thereafter, a polycrystalline
silicon layer 3 having a film thickness of 1000 .ANG. to 3000 .ANG.
is formed on oxide film 2 using the CVD (Chemical Vapor Deposition)
method. Then, on polycrystalline silicon layer 3, a tungsten
silicide layer 4 having a film thickness of 1000 .ANG. to 3000
.ANG. is formed by sputtering.
[0012] Thereafter, silicon oxide film 2, polycrystalline silicon
layer 3, and tungsten silicide layer 4 are patterned using
photolithography and etching techniques. Thus, gate interconnection
layer 13 including oxide film 2, polycrystalline silicon layer 3,
and tungsten silicide layer 4 is completed.
[0013] Next, referring to FIG. 16, using as a mask the gate
interconnection layer 13 including oxide film 2, polycrystalline
silicon layer 3, and tungsten silicide layer 4, an n-type impurity
such as As is implanted with a dosage of 1.times.10.sup.15/cm.sup.2
to 1.times.10.sup.16/cm.sup.2 at an implantation energy of 30 keV
to 60 keV into semiconductor substrate 1. Then, the impurity
implanted into semiconductor substrate 1 is diffused thermally, and
n+ type impurity diffusion regions 5 which later become
source/drain regions of an ROM transistor is completed.
[0014] Referring now to FIG. 17, a resist film 7 of a predetermined
pattern is formed selectively on n+ type impurity diffusion region
5. Thereafter, in order to determine the threshold voltage (Vth) of
the ROM transistor, p-type impurity ions 8 such as boron are
implanted into channel region 14 at an acceleration voltage, for
example at approximately 200 keV, which penetrates oxide film 2,
polycrystalline silicon layer 3, and tungsten silicide layer 4.
[0015] Referring now to FIG. 18, resist film 7 is removed, and
then, semiconductor substrate 1 is heat-treated to activate p-type
impurity ions 8. Thereafter, an interlayer insulating film 6 having
a thickness of 0.4 .mu.m to 1.2 .mu.m and being formed of TEOS
(Tetra Ethyle Ortho Silicate) and/or BPSG (Boro Phospho Silicate
Glass) is formed by the CVD method so as to cover tungsten silicide
layer 4 and n+ type impurity diffusion region 5. Then, contact hole
9 reaching n+ type impurity diffusion region 5 is formed
selectively in interlayer insulating film 6 by etching.
[0016] Referring now to FIG. 19, aluminum interconnection layer 10
having a film thickness of 0.6 .mu.m to 1.0 .mu.m is formed by
sputtering, and thereafter, a surface protection film 11 such as a
nitride film having a film thickness of 0.5 .mu.m to 1.0 .mu.m is
formed by the CVD method. From the above-described steps, the ROM
transistor is formed with its threshold voltage (Vth) set at a
predetermined level.
[0017] The patterned structure of the aforementioned conventional
ROM transistor, however, is as shown in FIG. 14 in which aluminum
interconnection layer 10 crosses channel region 14 where impurity
ions are implanted to determine the threshold voltage (Vth) of the
ROM transistor.
[0018] Thus, the manufacturing steps are interrupted after forming
n+ type impurity diffusion regions 5 which later become the
source/drain regions of the ROM transistor shown in FIG. 16, and
the final manufacturing steps shown in FIGS. 17-19 are performed
after the ROM specifications are determined based on the order
placed by the customer.
[0019] As a result, due to the long manufacturing period required
for the final manufacturing steps shown in FIGS. 17-19 after the
ROM specifications are determined, it has been a problem that too
much time was required from the time of order to the time when the
products are supplied to the customer.
SUMMARY OF THE INVENTION
[0020] An object of the present invention is to provide a
semiconductor device and a method of manufacturing the device which
shortens the manufacturing period required for the final
manufacturing steps of a semiconductor device after the ROM
specifications are determined.
[0021] A semiconductor device according to the present invention is
provided with an element isolating region disposed in a matrix for
defining an active region on a semiconductor substrate, first
conductive layers extending in a direction and disposed at
predetermined intervals from each other above the element isolating
region, and second conductive layers extending in a direction
intersecting the first conductive layers and disposed at
predetermined intervals from each other above the first conductive
layers. The second conductive layer, also, is disposed above the
element isolating region.
[0022] Moreover, preferably in the above-mentioned semiconductor
device, the active region forms source/drain regions and a channel
region, the first conductive layer forms a gate interconnection
layer, the second conductive layer forms an aluminum
interconnection layer, and the source/drain regions, the channel
region, the gate interconnection layer, and the aluminum
interconnection layer together form an ROM transistor.
[0023] In accordance with one aspect of the method of manufacturing
a semiconductor device according to the present invention, the
method includes the steps of forming an element isolating region in
a matrix to define an active region on a semiconductor substrate,
forming a first conductive layer at a given location of the active
region defined by the element isolating region with an insulating
film therebetween, introducing a first impurity into the
semiconductor substrate using the first conductive layer as a mask
to form an impurity diffusion region, covering the impurity
diffusion region and the first conductive layer to form an
interlayer insulating film having a contact hole reaching to the
impurity diffusion region, forming on the interlayer insulating
film a second conductive layer extending above the element
isolating region and connecting electrically to the impurity
diffusion region at a contact hole, forming a surface protection
layer covering the interlayer insulating film and the second
conductive layer, forming on the surface protection layer a resist
film leaving exposed a region corresponding to the active region
below the first conductive layer, and introducing a second impurity
into the active region using the resist film as a mask to adjust
the concentration of impurity in the active region below the first
conductive layer.
[0024] In the above-mentioned semiconductor device and the method
of manufacturing the device, the second conductive layer is formed
extending above the element isolating region. Therefore, only the
first conductive layer, the interlayer insulating film, and the
surface protection layer exist above the active region which forms
a channel region. Consequently, it is possible to adjust the
concentration of the impurity in the active region below the first
conductive layer after the surface protection layer is formed.
[0025] In the aforementioned semiconductor device, the insulating
film is preferably a silicon oxide film having a thickness of 100
.ANG. to 300 .ANG. formed by thermal oxidation. The first
conductive layer has a film thickness of 2000 .ANG. to 6000 .ANG.
and has a two-layered structure including a polycrystalline silicon
layer formed by the CVD method and a tungsten silicide layer formed
by sputtering. The interlayer insulating film has a thickness of
0.4 .mu.m to 1.2 .mu.m, is made of at least one of TEOS and BPSG,
and is formed by the CVD method. The surface protection layer is a
nitride film with a thickness of 0.5 .mu.m to 1.0 .mu.m. The second
impurity is introduced at an acceleration voltage of 1000 keV to
2000 keV.
[0026] Thus, the introduction of the second impurity into the
active region is ensured using the resist film as a mask.
[0027] Next, in accordance with another aspect of the method of
manufacturing a semiconductor device according to the present
invention, the method includes the steps of forming an element
isolating region in a matrix to define an active region on a
semiconductor substrate, forming a first conductive layer at a
given location of the active region defined by the element
isolating region with an insulating film therebetween, introducing
a first impurity into the semiconductor substrate using the first
conductive layer as a mask to form an impurity diffusion region,
covering the impurity diffusion region and the first conductive
layer to form an interlayer insulating film having a contact hole
leading to the impurity diffusion region, forming a resist film
covering the contact hole and leaving exposed a region
corresponding to the active region below the first conductive
layer, introducing a second impurity into the active region using
the resist film as a mask to adjust the concentration of impurity
in the active region below the first conductive layer, removing the
resist film and thereafter forming on the interlayer insulating
film a second conductive layer connecting electrically to the
impurity diffusion region at a contact hole, and forming a surface
protection layer covering the second conductive layer.
[0028] According to the method of manufacturing the semiconductor
device described above, the concentration of the impurity in the
active region below the first conductive layer can be adjusted
after the interlayer insulating film is formed.
[0029] In the aforementioned semiconductor device, the insulating
film is preferably a silicon oxide film having a thickness of 100
.ANG. to 300 .ANG. formed by thermal oxidation. The first
conductive layer has a film thickness of 2000 .ANG. to 6000 .ANG.
and has a two-layered structure including a polycrystalline silicon
layer formed by the CVD method and a tungsten silicide layer formed
by sputtering. The interlayer insulating film has a film thickness
of 0.4 .mu.m to 1.2 .mu.m, is made of at least one of TEOS and
BPSG, and is formed by the CVD method. The second impurity is
introduced at an acceleration voltage of 400 keV to 1000 keV.
[0030] Thus, the introduction of the second impurity into the
active region is ensured using the resist film as a mask.
[0031] The foregoing and other objects, features, aspects and
advantages of the present invention will become more apparent from
the following detailed description of the present invention when
taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0032] FIG. 1 is a plan view of the ROM region of the semiconductor
device according to the first embodiment of the present
invention.
[0033] FIG. 2 is a cross sectional view taken along the line A-A in
FIG. 1.
[0034] FIGS. 3-7 are cross sectional views representing the first
to fifth steps of the method of manufacturing the semiconductor
device in accordance with the first embodiment of the
invention.
[0035] FIG. 8 is a plan view of the ROM region of the semiconductor
device in accordance with the second embodiment of the
invention.
[0036] FIG. 9 is a cross sectional view taken along the line A-A in
FIG. 8.
[0037] FIGS. 10-13 are cross sectional views representing the first
to fourth steps of the method of manufacturing the semiconductor
device in accordance with the second embodiment of the
invention.
[0038] FIG. 14 is a plan view of the ROM region of the conventional
semiconductor device.
[0039] FIGS. 15-19 are cross sectional views representing the first
to fifth steps of the method of manufacturing a conventional
semiconductor device.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0040] The semiconductor device in accordance with the embodiments
of the present invention and the method of manufacturing the device
will be described below with reference to the drawings.
[0041] First Embodiment
[0042] The semiconductor device and the method of manufacturing the
device according to this embodiment will be described with
reference to FIGS. 1-7.
[0043] First, referring to FIG. 1, the planar pattern structure of
an ROM region of a semiconductor, device will be described. Element
isolating regions 12 formed of an oxide film or the like are
disposed regularly at predetermined intervals in the X and Y
directions. Gate interconnection layers 13 serving as first
interconnection layers extending in the Y direction at a line width
of 0.5 .mu.m to 1.5 .mu.m are disposed at predetermined intervals
in the X direction.
[0044] In regions between element isolating regions 12, aluminum
interconnection layers 10 serving as second interconnection layers
extending in the X direction at a line width of 0.8 .mu.m to 2.0
.mu.m are disposed at predetermined intervals in the Y direction. A
plurality of contact holes 9 are provided at given locations in
aluminum interconnection layer 10 to establish electrical
connection with active regions on semiconductor substrate 1.
[0045] Channel region 14 of an ROM transistor formed of an active
region is formed on semiconductor substrate 1 where gate
interconnection layer 13 and aluminum interconnection layer 10
intersect.
[0046] Referring now to FIG. 2, the cross sectional structure taken
along the line A-A in FIG. 1 is described below. Gate
interconnection layer 13 having a predetermined shape and including
oxide film 2, polycrystalline silicon layer 3, and tungsten
silicide layer 4 is formed on semiconductor substrate 1.
[0047] From the surface down to a predetermined depth of
semiconductor substrate 1, n+ type impurity diffusion regions 5 are
formed with gate interconnection layer 13 in between. Channel
region 14 is formed in a region between n+ type impurity diffusion
regions 5 below gate interconnection layer 13. Gate interconnection
layer 13, a pair of n+ type impurity diffusion regions 5, and
channel region 14 together form an ROM transistor.
[0048] Interlayer insulating film 6 is formed so as to cover gate
interconnection layer 13 and n+ type impurity diffusion region 5.
Contact hole 9 reaching n+ type impurity diffusion region 5 is
provided in the interlayer insulating film 6.
[0049] Owing to this contact hole 9, aluminum interconnection layer
10 and n+ type impurity diffusion region 5 are connected
electrically. Further, surface protection film 11 is formed on
aluminum interconnection layer 10.
[0050] Next, the manufacturing steps of an ROM transistor formed in
the ROM region having the aforementioned structure will be
described with reference to FIGS. 3-7.
[0051] Referring first to FIG. 3, element isolating region 12 as
shown in FIG. 1 is formed in a matrix using the LOCOS method to
define an active region in a given region on the surface of silicon
semiconductor substrate 1.
[0052] Next, an oxide film 2 having a thickness of 100 .ANG. to 300
.ANG. is formed by thermal oxidation on the surface of silicon
semiconductor substrate 1. Thereafter, a polycrystalline silicon
layer 3 having a film thickness of 1000 .ANG. to 3000 .ANG. is
formed on oxide film 2 using the CVD method. Then, on
polycrystalline silicon layer 3, a tungsten silicide layer 4 having
a film thickness of 1000 .ANG. to 3000 .ANG. is formed by
sputtering.
[0053] Thereafter, oxide film 2, polycrystalline silicon layer 3,
and tungsten silicide layer 4 are patterned using photolithography
and etching techniques. Thus, gate interconnection layer 13
including oxide film 2, polycrystalline silicon layer 3, and
tungsten silicide layer 4 is completed.
[0054] Next, referring to FIG. 4, using gate interconnection layer
13 as a mask, an n-type impurity such as As is implanted with a
dosage of 1.times.10.sup.15/cm.sup.2 to 1.times.10.sup.16/cm.sup.2
at an implantation energy of 30 keV to 60 keV into semiconductor
substrate 1. Then, the impurity implanted into semiconductor
substrate 1 is diffused thermally, and n+ type impurity diffusion
regions 5 which later become source/drain regions of an ROM
transistor is completed.
[0055] Referring now to FIG. 5, an interlayer insulating film 6
having a thickness of 0.4 .mu.m to 1.2 .mu.m and being formed of
TEOS and/or BPSG is formed by the CVD method so as to cover gate
interconnection layer 13 and n+ type impurity diffusion region 5.
Then, contact hole 9 reaching n+ type impurity diffusion region 5
is formed selectively in interlayer insulating film 6 by
etching.
[0056] Referring now to FIG. 6, resist film 7 having a thickness of
approximately 3.5 .mu.m is formed covering a predetermined region
on the surface of interlayer insulating film 6 and contact hole 9.
Thereafter, in order to determine the threshold voltage (Vth) of
the ROM transistor, p-type impurity ions 8 such as boron are
implanted into channel region 14 at an acceleration voltage, for
example at 400 keV to 1000 keV, which penetrates oxide film 2,
polycrystalline silicon layer 3, and tungsten suicide layer 4 but
not resist film 7.
[0057] Referring now to FIG. 7, resist film 7 is removed, and then,
semiconductor substrate 1 is heat-treated to activate p-type
impurity ions 8. Thereafter, aluminum interconnection layer 10
having a film thickness of 0.6 .mu.m to 1.0 .mu.m is formed by
sputtering, and thereafter, a surface protection film 11 such as a
nitride film having a thickness of 0.5 .mu.m to 1.0 .mu.m is formed
by the CVD method.
[0058] From the above-described steps, the ROM transistor is formed
with its threshold voltage (Vth) set at a predetermined level.
[0059] With the method of manufacturing an ROM transistor in
accordance with the above-described embodiment, it becomes possible
to shorten the time required between the time when the order from
the customer is received and the time when the products are
supplied to the customer, since the impurity implantation step to
set the threshold voltage (Vth) of the ROM transistor is performed
after contact hole 9 is formed in interlayer insulating film 6
without modifying the planar pattern structure of a conventional
ROM transistor.
[0060] Second Embodiment
[0061] The semiconductor device and the method of manufacturing the
device according to this embodiment will be described with
reference to FIGS. 8-13.
[0062] First, referring to FIG. 8, the planar pattern structure of
an ROM region of a semiconductor device will be described. Element
isolating regions 12 are disposed regularly at predetermined
intervals in the X and Y directions. Gate interconnection layers 13
extending in the X direction at a line width of 0.5 .mu.m to 1.5
.mu.m are disposed at predetermined intervals in the Y
direction.
[0063] Aluminum interconnection layers 10 extending in the Y
direction at a line width of 0.8 .mu.m to 2.0 .mu.m are disposed at
predetermined intervals in the X direction above element isolating
regions 12. In regions between element isolating regions 12, a
plurality of contact holes 9 are provided at given locations in
aluminum interconnection layer 10 to establish electrical
connection with active regions on semiconductor substrate 1.
[0064] Channel region 14 of an ROM transistor is formed on
semiconductor substrate 1 where gate interconnection layer 13 and
aluminum interconnection layer 10 intersect.
[0065] Referring now to FIG. 9, the cross sectional structure taken
along the line A-A in FIG. 8 is described below. Gate
interconnection layer 13 having a predetermined shape and including
oxide film 2, polycrystalline silicon layer 3, and tungsten suicide
layer 4 is formed on semiconductor substrate 1.
[0066] From the surface down to a predetermined depth of
semiconductor substrate 1, n+ type impurity diffusion regions 5 are
formed with gate interconnection layer 13 in between. Channel
region 14 is formed in a region between n+ type impurity diffusion
regions 5 below gate interconnection layer 13. Gate interconnection
layer 13, a pair of n+ type impurity diffusion regions 5, and
channel region 14 together form an ROM transistor.
[0067] Interlayer insulating film 6 is formed so as to cover gate
interconnection layer 13 and n+ type impurity diffusion region 5.
Contact hole 9 reaching n+ type impurity diffusion region 5 is
provided in the interlayer insulating film 6.
[0068] Owing to this contact hole 9, aluminum interconnection layer
10 and n+ type impurity diffusion region 5 are connected
electrically. Further, surface protection film 11 is formed on
aluminum interconnection layer 10 and interlayer insulating film
6.
[0069] Next, the manufacturing steps of an ROM transistor formed in
the ROM region having the aforementioned structure will be
described with reference to FIGS. 10-13. Further, the step of
forming gate interconnection layer 13 including oxide film 2,
polycrystalline silicon layer 3, and tungsten silicide layer 4 and
the step of forming n+ type impurity diffusion region 5, interlayer
insulating film 6, and contact hole 9, being the same as the steps
of FIG. 3-5 illustrated in relation to the first embodiment, will
not be repeated here.
[0070] Referring to FIG. 10, aluminum interconnection layer 10
having a film thickness of 0.6 .mu.m to 1.0 .mu.m is formed by
sputtering to provide electrical connection to n+ type impurity
diffusion region 5 at contact hole 9. At this time, aluminum
interconnection layer 10 is formed only above n+ type impurity
diffusion region 5 and patterned so as not to cover channel region
14.
[0071] Referring now to FIG. 11, surface protection film 11 such as
a nitride film having a thickness of 0.5 .mu.m to 1.0 .mu.m is
formed by the CVD method to cover interlayer insulating film 6 and
aluminum interconnection layer 10.
[0072] Referring now to FIG. 12, resist film 7 having a thickness
of approximately 3.5 .mu.m to 5.0 .mu.m is formed in a
predetermined region on the surface of surface protection film 11.
Thereafter, in order to determine the threshold voltage (Vth) of
the ROM transistor, p-type impurity ions 8 such as boron are
implanted into channel region 14 at an acceleration voltage, for
example at 1000 keV to 2000 keV, which penetrates surface
protection film 11, interlayer insulating film 6, tungsten silicide
layer 4, polycrystalline silicon layer 3, and oxide film 2 but not
resist film 7.
[0073] Thereafter, as in FIG. 13, resist film 7 is removed, and in
order to activate p-type impurity ions 8, aluminum interconnection
layer 10 is heat-treated at a temperature high enough yet not as
high as to cause the melting of aluminum interconnection layer
10.
[0074] From the above-described steps, an ROM transistor set at a
predetermined threshold voltage (Vth) is formed.
[0075] In the ROM transistor structure and the method of
manufacturing thereof according to the aforementioned embodiment,
since aluminum interconnection layer 10 is disposed above the
element isolating region, aluminum interconnection layer does not
run through above channel region 14 of the ROM transistor. As a
result, the impurity implantation step for setting the threshold
voltage (Vth) for the ROM transistor may be performed after surface
protection film 11 is formed. Thus, a significant reduction in time
required from the time of order by the customer to the time of
supplying the products to the customer becomes possible.
[0076] Further, in each of the above-mentioned embodiments, the
described ion implantation method to determine the threshold
voltage (Vth) of an ROM transistor is the so-called channel-cut
method where the threshold voltage (Vth) is raised by the
implantation of p-type impurity ions 8 into channel region 14. The
same effect, however, may be achieved using the so-called depletion
method where the threshold voltage (Vth) is lowered by n-type
impurity ion implantation.
[0077] Although the present invention has been described and
illustrated in detail, it is clearly understood that the same is by
way of illustration and example only and is not to be taken by way
of limitation, the spirit and scope of the present invention being
limited only by the terms of the appended claims.
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