U.S. patent application number 09/815011 was filed with the patent office on 2001-12-13 for semiconductor device and method for fabricating the same.
This patent application is currently assigned to Fujitsu Limited. Invention is credited to Nakamura, Shunji.
Application Number | 20010050392 09/815011 |
Document ID | / |
Family ID | 18662753 |
Filed Date | 2001-12-13 |
United States Patent
Application |
20010050392 |
Kind Code |
A1 |
Nakamura, Shunji |
December 13, 2001 |
Semiconductor device and method for fabricating the same
Abstract
The method for fabricating the semiconductor device comprises
the steps of: forming an insulation film 56 above a substrate 10;
forming an opening 60 in the insulation film 56 down to the
substrate 10; forming a plate electrode 62 on at least a side wall
of the opening 60; removing the insulation film 56 to form an
opening 68 having a side wall surrounded by a plate electrode 62;
forming a capacitor dielectric film 70 on at least a side wall of
the opening 68; and forming a storage electrode 72 on the capacitor
dielectric film 70. Whereby electric characteristics between the
electrode, etc. in the below structure and the storage electrode
are prevented from deterioration in high-temperature thermal
processing in the step of forming the capacitor dielectric
film.
Inventors: |
Nakamura, Shunji; (Kawasaki,
JP) |
Correspondence
Address: |
ARMSTRONG,WESTERMAN, HATTORI,
MCLELAND & NAUGHTON, LLP
1725 K STREET, NW, SUITE 1000
WASHINGTON
DC
20006
US
|
Assignee: |
Fujitsu Limited
Kawasaki
JP
|
Family ID: |
18662753 |
Appl. No.: |
09/815011 |
Filed: |
March 23, 2001 |
Current U.S.
Class: |
257/309 ;
257/306; 257/E21.019; 257/E21.648; 257/E21.66; 438/253;
438/396 |
Current CPC
Class: |
H01L 27/10894 20130101;
H01L 28/91 20130101; H01L 27/10852 20130101 |
Class at
Publication: |
257/309 ;
257/306; 438/253; 438/396 |
International
Class: |
H01L 027/108; H01L
021/8242 |
Foreign Application Data
Date |
Code |
Application Number |
May 29, 2000 |
JP |
2000-158258/2000 |
Claims
What is claimed is:
1. A method for fabricating a semiconductor device comprising the
steps of: forming a first insulation film above a substrate;
forming a first opening in the first insulation film down to the
substrate; forming a plate electrode on at least a side wall of the
first opening; removing the first insulation film to form a second
opening having a side wall surrounded by the plate electrode;
forming a capacitor dielectric film on at least the side wall of
the second opening; and forming a storage electrode on the
capacitor dielectric film formed on the side wall of the second
opening.
2. A method for fabricating a semiconductor device according to
claim 1, in which the substrate includes a lower electrode; and an
etching stopper film formed on the lower electrode, and which
further comprises, between the step of forming the capacitor
dielectric film and the step of forming the storage electrode, the
steps of: performing a thermal treatment for sufficiently
crystallizing the capacitor dielectric film or supplementing oxygen
defects in the capacitor dielectric film; and removing the etching
stopper film in the second opening to expose the lower electrode in
the second opening.
3. A method for fabricating a semiconductor device according to
claim 1, in which the substrate includes a lower electrode; a
second insulation film formed on the lower electrode; and an
etching stopper film formed on the second insulation film, and
which further comprises, between the step of forming the capacitor
dielectric film and the step of forming the storage electrode, the
steps of: performing a thermal treatment for sufficiently
crystallizing the capacitor dielectric film or supplementing oxygen
defects in the capacitor dielectric film; and removing the etching
stopper film and the second insulation film in the second opening
to expose the lower electrode in the second opening.
4. A method for fabricating a semiconductor device according to
claim 2, wherein in the step of removing the etching stopper film,
the etching stopper film is removed, making an opening width of the
etching stopper film in the second opening smaller than a width of
the second opening along extension of a bit line.
5. A method for fabricating a semiconductor device according to
claim 3, wherein in the step of removing the etching stopper film
and the second insulation film, the etching stopper film and the
second insulation film are removed, making an opening width of the
etching stopper film and the second insulation film in the second
opening smaller than a width of the second opening along extension
of a bit line.
6. A method for fabricating a semiconductor device according to
claim 4, wherein the plate electrode having the side wall inversely
tapered is formed, and the etching stopper film is removed with the
plate electrode as a mask, whereby the opening width of the etching
stopper film is made smaller than the width of the second opening
along extension of the bit line.
7. A method for fabricating a semiconductor device according to
claim 5, wherein the plate electrode having the side wall inversely
tapered is formed, and the etching stopper film and the second
insulation film are removed with the plate electrode as a mask,
whereby the opening width of the etching stopper film and the
second insulation film is made smaller than the width of the second
opening along extension of the bit line.
8. A method for fabricating a semiconductor device according to
claim 4, wherein the etching stopper film is removed with, as a
mask, a resist film having an opening width along extension of the
bit line which is smaller than the width of the second opening
along extension of the bit line, whereby the opening width of the
etching stopper film is made smaller than the width of the second
opening along extension of the bit line.
9. A method for fabricating a semiconductor device according to
claim 5, wherein the etching stopper film and the second insulation
film are removed with, as a mask, a resist film having an opening
width along extension of the bit line which is smaller than the
width of the second opening along extension of the bit line,
whereby the opening width of the etching stopper film and the
second insulation film is made smaller than the width of the second
opening along extension of the bit line.
10. A method for fabricating a semiconductor device according to
claim 1, wherein in the step of forming the first opening, the
first opening having the side wall forward tapered is formed,
whereby the plate electrode having a side wall inversely tapered
and the storage electrode having a side wall forward tapered are
formed.
11. A method for fabricating the semiconductor device according to
claim 1, wherein in the step of forming the first insulation film,
the first insulation film is formed in a memory cell region and a
peripheral circuit region, and in the step for removing the first
insulation film, the first insulation film in the memory cell
region is selectively removed.
12. A semiconductor device comprising: a storage electrode having a
side wall forward tapered; a capacitor dielectric film formed on
the side wall of the storage electrode; and a plate electrode
formed on the side wall of the storage electrode interposing the
capacitor dielectric film therebetween, the plate electrode having
a side wall inversely tapered.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a semiconductor device
fabrication technique, more specifically a semiconductor device
having DRAM-type memory elements, and a method for fabricating the
same.
[0002] A DRAM is a semiconductor memory device which can be formed
of memory cells each having one transistor and one capacitor.
Various structures and fabrication methods have been conventionally
studied for semiconductor memory devices of higher density and
higher integration. Especially a structure of the capacitors of
DRAM much influences the integration, and it is significant how to
ensure a required storage capacitance without preventing higher
integration of the device.
[0003] A conventional method for fabricating a DRAM-type
semiconductor device will be explained with reference to FIGS.
32A-32B, 33A-33B, 34A-34B, and 35A-35B. FIGS. 32A-32B, 33A-33B,
34A-34B, and 35A-35B are sectional views of the semiconductor
device in the steps of the method for fabricating the same.
[0004] First, in the same way as in the usual method for
fabricating a MOS transistor, a memory cell transistor including a
gate electrode 102 and source/drain diffused layers 104, 106, and a
peripheral circuit transistor including a gate electrode 108 and a
source/drain diffused layer 110 are formed on a silicon substrate
100.
[0005] Next, a bit line 114 and an interconnection layer 116 are
formed on an inter-layer insulation film 118 covering the memory
cell transistor and the peripheral circuit transistor, electrically
connected respectively to the source/drain diffused layer 104
through a plug 112, and to the gate electrode 108 or to the
source/drain diffused layer 110.
[0006] Then, an inter-layer insulation film 120 is formed on the
inter-layer insulation film 118, on which the bit line 114 and the
interconnection layer 116 are formed.
[0007] Next, a plug 124 is buried in the inter-layer insulation
films 120, 118, electrically connected to the source/drain diffused
layer 106 through a plug 122 (FIG. 32A).
[0008] Then, on the inter-layer insulation film 120 with the plug
124 buried in, an etching stopper film 126 of a silicon nitride
film, an inter-layer insulation film 128 of a silicon oxide film,
and a mask film 130 of an amorphous silicon film are formed by,
e.g., CVD method.
[0009] Then, the mask film 130, the inter-layer insulation film 128
and the etching stopper film 126 are patterned by the lithography
and etching to form an opening 132 which arrives at the plug 124
(FIG. 32B).
[0010] A conducting film 134, such as a Ru (Ruthenium) film, SRO
(SrRuO.sub.3) film or others, is formed on the entire surface by,
e.g., CVD method.
[0011] Then, a silicon oxide film 136 is deposited on the entire
surface by, e.g., CVD method and etched back by, e.g., CMP method
or dry etching to fill the opening 132 with the conducting film 134
formed in by the silicon oxide film 136 (FIG. 33A).
[0012] Next, the surfaces of the conducting film 134, the silicon
oxide film 136 and mask film 130 are uniformly retreated by CMP
method or dry etching until the inter-layer insulation film 128 is
exposed. Thus, a cylindrical storage electrode 138 of the
conducting film 134 is formed in the opening 132 (FIG. 33B).
[0013] Then, the silicon oxide film 136 and the inter-layer
insulation film 128 are selectively etched with the etching stopper
film 126 as a stopper to expose the inside and outside walls of the
storage electrode (FIG. 34A).
[0014] Then, a dielectric film of, e.g., Ta.sub.2O.sub.5 film or
BST film on the entire surface by, e.g., CVD method to form a
capacitor dielectric film 140 of the dielectric film, covering the
storage electrode 138.
[0015] Next, annealing is performed to sufficiently crystallize the
capacitor dielectric film 140, and thermal oxidation is performed
to supplement oxygen defects in the capacitor dielectric film 140
(FIG. 34B). Conditions for the thermal processing are different
depending on dielectric materials forming the capacitor dielectric
film 140, but the processing at a high temperature of
500-850.degree. C. is necessary.
[0016] Next, a conducting film, such as an Ru film or SRO film, is
deposited on the entire surface by, e.g., CVD method and patterned
to form a plate electrode 142 of the conducting film, covering the
storage electrode 138 interposing the capacitor dielectric film 140
therebetween (FIG. 35A).
[0017] Thus, a capacitor including the storage electrode 138, the
capacitor dielectric film 140 and the plate electrode 142 and
connected electrically to the source/drain diffused layer 106 of
the memory cell transistor is formed.
[0018] Next, a silicon oxide film is deposited on the entire
surface by, e.g., CVD method to form an inter-layer insulation film
144 of the silicon oxide film.
[0019] Next, as required, an interconnection layer 146 and an
interconnection layer 148 are formed, connected respectively to the
plate electrode 142 and to the interconnection layer 116 (FIG.
35B).
[0020] Thus, a DRAM comprising memory cells each including one
transistor and one capacitor is fabricated.
[0021] As described above, in the conventional semiconductor device
fabrication method, crystallization of the capacitor dielectric
film 140 is improved for higher dielectric constant, or for low
leak current, high-temperature thermal processing is performed
after the capacitor dielectric film 140 has been formed.
[0022] However, such thermal processing can improve film quality of
the capacitor dielectric film 140, but on the other hand
deteriorate electric characteristics between the storage electrode
138 and the plug 124.
[0023] In a case, for example, that the plug 124 is formed of doped
polycrystalline silicon, a silicide layer formed in the contact
region between the storage electrode 138 and the plug 124
aggregate, reducing a contact area, with a result of increase of
the contact resistance. Often a dopant of the plug 124 is absorbed
by the silicide layer, forming a region of a lower dopant
concentration on the upper end of the plug 124, with a result of
higher contact resistance.
[0024] In a case that the thermal processing in an oxidizing
atmosphere is necessary, when the plug 124 is formed of doped
polycrystalline silicon, or a metal, such as W (tungsten), the
contact region of the plug 124 is oxidized, with a result of
increased contact resistance.
[0025] In order to suppress such contact resistance increase, it is
considered that a barrier metal, as of a TiN film, is formed on the
top of the plug 124, but the step of forming the barrier metal must
be added. Fabrication cost increase is inevitable. Depending on
kinds of the storage electrode 138 and the capacitor dielectric
film 140, oxidizing ability in the thermal processing is too high
to select a suitable barrier metal for preventing the
oxidation.
[0026] In the thermal processing, materials forming the plug 124
are diffused in the storage electrode 138 to deteriorate
compatibility between the storage electrode 138 and the capacitor
dielectric film 140, often with a result of decreased breakdown
voltage and increased capacitor leak current.
[0027] The above-described problems will be solved by lowering
crystallization annealing temperature and the thermal processing
temperature for the capacitor dielectric film 140. However, the
thermal processing at low temperatures is not sufficient for the
crystallization and supplement of oxygen defects, with results of
decreased dielectric constants of the capacitor dielectric film 140
or increased leak current. The crystallization annealing and
thermal oxidation for the capacitor dielectric film 140 will have
to be performed at higher temperature as the capacitor dielectric
film 140 is thinner. Accordingly, also for further micronization of
semiconductor devices it is required to prohibit the influence of
the thermal processing.
SUMMARY OF THE INVENTION
[0028] An object of the present invention is to provide a
semiconductor device and a method for fabricating the semiconductor
device which can prohibit electric characteristic deterioration
between the storage electrodes and the lower electrodes, etc.
connected to the storage electrodes in the steps of crystallization
annealing and oxidizing the capacitor dielectric film.
[0029] According to one aspect of the present invention, there is
provided a method for fabricating a semiconductor device comprising
the steps of: forming a first insulation film above a substrate;
forming a first opening in the first insulation film down to the
substrate; forming a plate electrode on at least a side wall of the
first opening; removing the first insulation film to form a second
opening having a side wall surrounded by the plate electrode;
forming a capacitor dielectric film on at least the side wall of
the second opening; and forming a storage electrode on the
capacitor dielectric film formed on the side wall of the second
opening.
[0030] According to another aspect of the present invention, there
is provided a semiconductor device comprising: a storage electrode
having a side wall forward tapered; a capacitor dielectric film
formed on the side wall of the storage electrode; and a plate
electrode formed on the side wall of the storage electrode
interposing the capacitor dielectric film therebetween, the plate
electrode having a side wall inversely tapered.
[0031] According to the present invention, insulation film is
formed on a substrate, a first opening is formed in the insulation
film down to the substrate, a plate electrode is formed on at least
the side wall of the first opening, the first insulation film is
removed to form a second opening having the side wall surrounded by
the plate electrode, a capacitor dielectric film is formed on at
least the side wall of the second opening, and a storage electrode
is formed on the side wall of the second opening through the
capacitor dielectric film, whereby electric characteristics between
the electrode, etc. in the below structure and the storage
electrode are prevented from deterioration in high-temperature
thermal processing in the step of forming the capacitor dielectric
film.
[0032] The thermal processing can be performed without taking into
consideration electric characteristics between the lower electrode
and the storage electrode, whereby the thermal processing can be
performed under conditions which are optimum for the capacitor
dielectric film, and the capacitor dielectric film can have higher
dielectric constant and higher film quality.
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] FIGS. 1A-1D and 2A-2D are sectional views of the
semiconductor device in the steps of the method for fabricating the
same, which explain the principle of the present invention.
[0034] FIG. 3A is a diagrammatic sectional view of the
semiconductor device according to a first embodiment of the present
invention, which shows a structure thereof.
[0035] FIG. 3B is a plan view of the semiconductor device according
to the first embodiment of the present invention, which shows a
structure thereof.
[0036] FIGS. 4A-4E, 5A-5C, 6A-6B, 7A-7B, and 8A-8B are sectional
views of the semiconductor device according to the first embodiment
of the present invention in the steps of the method for fabricating
the same, which show the method.
[0037] FIG. 9 is a view of one example of patterns of a photoresist
film used in the method for fabricating the semiconductor device
according to the first embodiment of the present invention.
[0038] FIG. 10 is a diagrammatic sectional view of the
semiconductor device according to a second embodiment of the
present invention, which shows a structure thereof.
[0039] FIGS. 11A-11C and 12A-12B are sectional views of the
semiconductor device according to the second embodiment of the
present invention in the steps of the method for fabricating the
same, which show the method.
[0040] FIG. 13 is a diagrammatic sectional view of the
semiconductor device according to a third embodiment of the present
invention, which shows a structure thereof.
[0041] FIGS. 14A-14B, 15A-15B, 16A-16B, and 17A-17B are sectional
views of the semiconductor device according to the third embodiment
of the present invention in the steps of the method for fabricating
the same, which show the method.
[0042] FIG. 18 is a view of one example of patterns of the
photoresist film used in the method for fabricating the
semiconductor device according to the third embodiment of the
present invention.
[0043] FIG. 19 is a diagrammatic sectional view of the
semiconductor device according to a fourth embodiment of the
present invention, which shows a structure thereof.
[0044] FIGS. 20A-20B and 21A-21B are sectional views of the
semiconductor device according to the fourth embodiment of the
present invention in the steps of the method for fabricating the
same, which show the method.
[0045] FIG. 22 is a diagrammatic sectional view of the
semiconductor device according to a fifth embodiment of the present
invention, which shows a structure thereof.
[0046] FIGS. 23A-23B, 24A-24B, and 25A-25B are sectional views of
the semiconductor device according to the fifth embodiment of the
present invention in the steps of the method for fabricating the
same, which show the method.
[0047] FIG. 26 is a diagrammatic sectional view of the
semiconductor device according to a sixth embodiment of the present
invention, which shows a structure thereof.
[0048] FIGS. 27A-27B, 28A-28B, and 29A-29B are sectional views of
the semiconductor device according to the sixth embodiment of the
present invention in the steps of the method for fabricating the
same, which show the method.
[0049] FIGS. 30A-30B and 31A-31B are views of examples of patterns
of the photoresist film used in the method for fabricating the
semiconductor device according to a modifications of the
embodiments of the present invention.
[0050] FIGS. 32A-32B, 33A-33B, 34A-34B, and 35A-35B are sectional
views of the conventional semiconductor device in the steps of the
method for fabricating the same, which shows the method.
DETAILED DESCRIPTION OF THE INVENTION
[0051] [A Principle Of The Invention]
[0052] The principle of the present invention will be explained
with reference to FIGS. 1A-1D and 2A-2D. FIGS. 1A-1D and 2A-2D are
sectional views of the semiconductor device according to the
present invention in the steps of the method for fabricating the
same, which explain the principle.
[0053] The present invention is characterized mainly in that a
capacitor dielectric film is formed after a plate electrode has
been formed, and then a storage electrode is formed.
[0054] The principle of the present invention will be explained by
means of an example that a storage electrode 72 electrically
connected to a plug 52, a capacitor dielectric film 70 and a plate
electrode 62 are formed on a base structure with the plug 52 buried
in an inter-layer insulation film 48.
[0055] First, an etching stopper film 54 of, e.g., a silicon
nitride film, and an inter-layer insulation film 56 of, e.g., a
silicon oxide film are formed on an inter-layer insulation film 48
with a plug 52 buried in (FIG. 1A).
[0056] Next, the inter-layer insulation film 56 is patterned to
form an opening 60 in the inter-layer insulation film 56. At this
time, the inter-layer insulation film 56 is etched with the etching
stopper film 54 as a stopper. The opening 60 is formed in a region
for a plate electrode 62 is to be formed (FIG. 1B). In FIG. 1B,
parts of two openings 60 are shown.
[0057] Next, a conducting film is buried in the opening 60 to form
a plate electrode 62 of the conducting film (FIG. 1C). The plate
electrode 62 may be formed by depositing the conducting film and
patterning the same, but as will be described later, the process of
burying the conducting film in the inter-layer insulation film 56
to form the plate electrode 62 has a significant merit of
facilitating the fabrication of the semiconductor device while
global flatness is maintained.
[0058] Next, the top of the plate electrode 62 is a little
retreated, and then a silicon nitride film 64, for example, having
etching characteristics different from those of the inter-layer
insulation film 56 is buried in the opening 60 on the plate
electrode 62 (FIG. 1D).
[0059] Then, the inter-layer insulation film 56 is removed
selectively with respective to the silicon nitride film 64, the
plate electrode 62 and the etching stopper film 54 to form an
opening 68 (FIG. 2A).
[0060] Next, a dielectric film is deposited and etched back to form
a capacitor dielectric film 70 of the dielectric film on the inside
wall of the opening 68.
[0061] Then, thermal processing for crystallizing the capacitor
dielectric film 70 or supplementing oxygen defects thereof is
performed (FIG. 2B). At this time, the plug 52, the upper surface
of which is covered by the etching stopper film 54 of the silicon
nitride film, is not oxidized. Neither aggregation of a silicide
layer formed between 52 and a storage electrode 72, nor transition
of the dopant takes place between the two takes place because the
storage electrode 72 is not formed yet.
[0062] Next, the etching stopper film 54 in the opening 68 is
selectively removed to expose the plug 52 in the opening 68 (FIG.
2C).
[0063] Then, a conducting film is buried in the opening 68 to form
the storage electrode 72 of the conducting film, electrically
connected to the plug 52 (FIG. 2D).
[0064] In fabricating the semiconductor device in such process, the
thermal processing for crystallizing the capacitor dielectric film
70 or supplementing oxygen defects thereof is not performed after
the plug 52 and the storage electrode 72 have been connected to
each other, whereby electric characteristics, etc. between the plug
52 and the storage electrode 72 are prevented from being
deteriorated by the thermal processing. The plug 52, which has been
already covered by the time of the thermal processing, is not
oxidized. Accordingly, the thermal processing for crystallizing the
capacitor dielectric film 70 or supplementing oxygen defects
thereof can be performed under conditions suitable for the
capacitor dielectric film 70 without considering electric
characteristics between the plug 52 and the storage electrode 72.
Thus, the capacitor dielectric film 70 having high dielectric
constant and little leak current can be easily formed.
[0065] The semiconductor device fabrication method shown in FIGS.
1A-1D and 2A-2D requires the etching step of FIG. 2C for removing
the etching stopper film 54, and there is a risk that the capacitor
dielectric film 70 might have plasma damage. However, the capacitor
dielectric film 70 is free from serious damage because the
capacitor dielectric film 70 is parallel with a direction of
movement of the ions. The capacitor dielectric film 70 is a little
damaged by ion implantation and charge-up, but such damages can be
removed by thermal processing at relatively low temperatures of
about 400-450.degree. C.
[0066] In order to make the dielectric film 70 invulnerable to such
damage it is very effective that the inter-layer insulation film 56
is patterned to inversely taper the side wall of the opening 60 in
the step of FIG. 1B, so that the opening 68 has a diameter
increased toward the plug 52.
[0067] In the specification, "inversely tapered" means that the
bottom surface and the side wall of the opening form an acute
angle, and "forward tapered" means that the bottom surface and the
side wall of the opening form an obtuse angle. When "inversely
tapered" and "forward tapered" are used for an electrode,
"inversely tapered" means that the bottom surface and the side wall
of the electrode form an acute angle, and "forward tapered" means
that the bottom surface and the side wall of the electrode form an
obtuse angle.
[0068] In a case that the thermal processing is not performed in an
oxidizing atmosphere, the thermal processing for crystallizing the
capacitor dielectric film 70 may be performed after the etching
stopper film 54 in the opening 68 is removed, and the plug 52 is
exposed. The thermal processing for the crystallization may be
performed after the capacitor dielectric film 70 is deposited,
following the removal of the etching stopper film 54 in the opening
68.
[0069] The present invention is applicable not only to connecting
the storage electrode 72 to the plug 52, but also to connecting the
storage electrode 72 to plugs lower of the plug 52 or the silicon
substrate. It is not essential that the opening is completely
buried by the storage electrode 72 and the plate electrode 62.
[0070] [A First Embodiment]
[0071] The semiconductor device and the method for fabricating the
same according to a first embodiment of the present invention will
be explained with reference to FIGS. 3A-3B, 4A-4E, 5A-5C, 6A-6B,
7A-7B, 8A-8B, and 9.
[0072] FIGS. 3A and 3B are views of the semiconductor device
according to the present embodiment, which shows a structure
thereof. FIGS. 4A-4E, 5A-5C, 6A-6B, 7A-7B, and 8A-8B are sectional
views of the semiconductor device according to the present
embodiment in the steps of the method for fabricating the same,
which show the method. FIG. 9 is a view of an example of patterns
of the photoresist film used in the method for fabricating the
semiconductor device according to the present embodiment.
[0073] First, the structure of the semiconductor device according
to the present embodiment will be explained with reference to FIGS.
3A and 3B. FIG. 3A is a diagrammatic sectional view of the
semiconductor device according to the present embodiment, which
shows the structure thereof. FIG. 3B is a plan view of a memory
cell region corresponding to the region on the left side of FIG. 3A
and has a scale different from FIG. 3A.
[0074] A device isolation film 12 defining device regions 14, 16 is
formed on a silicon substrate 10. A memory cell transistor
comprising a gate electrode 20 and source/drain diffused layers 26,
28 and a peripheral circuit transistor comprising a gate electrode
22 and a source/drain diffused layer 30 are formed respectively in
the device regions 14, 16. An inter-layer insulation films 32, 42
are formed on the silicon substrate 10 with the memory cell
transistor and the peripheral circuit transistor formed on. On the
inter-layer insulation film 42 there are formed a bit line 44
connected to the source/drain diffused layer 26 through a plug 38,
and an interconnection layer 46 connected to the gate electrode 22
or the source/drain diffused layer 30. An inter-layer insulation
film 48 is formed on the inter-layer insulation film 42 with the
bit line 44 and the interconnection layer 46 formed on. A
pillar-shaped storage electrode 72 is formed on the inter-layer
insulation film 48, connected to the source/drain diffused layer 28
through a plug 52 and a plug 40. A plate electrode 62 is buried
between the storage electrodes 72 interposing a capacitor
dielectric film 70 therebetween. A silicon nitride film 64 is
formed on the plate electrode 62. On the inter-layer insulation
film 48 of the peripheral circuit region, a silicon nitride film 54
and an inter-layer insulation film 62 are formed. An
interconnection layer 74 is formed on the silicon nitride film 54,
connected to the plate electrode 62. An interconnection layer 76 is
formed on the inter-layer insulation film 56, connected to the gate
electrode 22 or the source/drain diffused layer 30 through the
interconnection layer 46.
[0075] The semiconductor device of such DRAM-type according to the
present embodiment is characterized mainly in that the storage
electrode 72 has the side wall forward tapered, and the plate
electrode 62 has the side wall inversely tapered. This structure is
attributed to the fabrication method characteristic of the present
invention, and enables the capacitor dielectric film 70 to have
improved film quality, and can make a parasitic capacitance between
the bit line 44 and the storage electrode 72 small.
[0076] Next, the method for fabricating the semiconductor device
according to the present embodiment will be explained with
reference to FIGS. 4A-4E, 5A-5C, 6A-6B, 7A-7B, 8A-8B and 9. The
sectional views of the memory cell region in FIGS. 4A-4E, 5A-5C,
6A-6B, 7A-7B and 8A-8B are along the line A-A' in FIG. 3B unless
especially described.
[0077] First, the device isolation film 12 is formed on the primary
surface of a semiconductor substrate 10 by, e.g., STI (Shallow
Trench Isolation) technique to define the device regions 14, 16.
Here, the device region 14 indicates an active region of a memory
cell region constituting a memory cell transistor, and the device
region 16 indicates an active region of a peripheral circuit region
constituting a peripheral circuit transistor.
[0078] Next, a gate insulation film (not shown) is formed of a
silicon oxide film on the device regions 14, 16 by, e.g., thermal
oxidation.
[0079] Then, a polycrystalline silicon film and a silicon nitride
film are sequentially deposited on the entire surface by, e.g., CVD
method, and the laid films are patterned to form the gate
electrodes 20, 22 having the upper surfaces covered by the silicon
nitride film 18. Here, the gate electrode 20 is the gate electrode
of the memory cell transistor, and the gate electrode 22 is the
gate electrode of the peripheral circuit transistor.
[0080] Next, with the gate electrode 20 as a mask, ions are
implanted into the silicon substrate 10 to form the source/drain
diffused layers 26, 28 in the silicon substrate 10 on both sides of
the gate electrode 20. With the gate electrode 22 as a mask, ions
are implanted into the silicon substrate 10 to form an LDD region
or an extension region in the silicon substrate 10 on both sides of
the gate electrode 22.
[0081] Then, a silicon nitride film or a silicon oxide film is
deposited on the entire surface by, e.g., CVD method and is etched
back to form a sidewall insulation film 24 on the side walls of the
gate electrodes 20, 22 and the silicon nitride film 18.
[0082] Next, with the gate electrode 22 and the sidewall insulation
film 24 as a mask, ions are implanted into the silicon substrate 10
to form the source/drain diffused layer 30 in the silicon substrate
10 on both sides of the gate electrode 22.
[0083] Thus, the memory cell transistor comprising the gate
electrode 20 and the source/drain diffused layers 26, 28 formed in
the silicon substrate 10 on both sides of the gate electrode 20 is
formed in the device region 14, and the peripheral circuit
transistor comprising the gate electrode 22 and the source/drain
diffused layer 30 formed in the silicon substrate 10 on both sides
of the gate electrode 22 is formed in the device region 16 (FIG.
4A).
[0084] Then, a silicon oxide film is deposited on the entire
surface by, e.g., CVD method, and the surface of the silicon oxide
film is polished by CMP (Chemical Mechanical Polishing) or other
means until the silicon nitride film 18 is exposed, to form the
inter-layer insulation film 32 having the surface planarized.
[0085] Next, by the lithography and etching, the contact hole 34
and the contact hole 36 are formed in the inter-layer insulation
film 32 respectively down to the source/drain diffused layer 26 and
down to the source/drain diffused layer 28 (FIG. 4B).
[0086] Then, the plugs 38, 40 are buried in the contact holes 34,
36 opened in the inter-layer insulation film 32 (FIG. 4C). For
example, a polycrystalline silicon film is deposited by CVD method
and etched back to be left only in the contact holes 34, 36, and is
doped by ion implantation to be made low resistivity. The plugs 38,
40 of the doped polycrystalline silicon are formed. The plugs 38,
40 are positioned in the same plane in FIG. 4C, but actually are
often positioned in different planes.
[0087] Next, a 50-100 nm-thick silicon oxide film is deposited on
the entire surface by, e.g., CVD method to form the inter-layer
insulation film 42 of the silicon oxide film.
[0088] Next, the contact hole formed in the inter-layer insulation
film 42 down to the plug 38, the contact hole formed in the
inter-layer insulation film 42 and the silicon nitride film 18 down
to the gate electrode 22, and he contact hole formed in the
inter-layer insulation film 42, 32 down to the source/drain
diffused layer 30 are formed by the lithography and etching (FIG.
4D).
[0089] In FIG. 4D, for the convenience of the explanation, the
contact holes arrive at the plug 38 formed in the inter-layer
insulation film 42. Actually, however, the contact holes are not
positioned in the same plane along the plug 38 and the plug 40. The
structure upper of the inter-layer insulation film 42 including the
inter-layer insulation film 42 in FIG. 4D is along the sectional
view along the line B-B' in FIG. 3B.
[0090] Then, a TiN (titanium nitride) film, a W (tungsten) film and
a silicon nitride film are sequentially deposited on the entire
surface by CVD method and are patterned to form the bit line 44
having the upper surface covered by the silicon nitride film 47 and
connected to the source/drain diffused layer 26 through the plug
38, and an interconnection layer 46 having the upper surface
covered by the silicon nitride film 47 and connected to the gate
electrode 22 or the source/drain diffused layer 30 (FIG. 4E).
[0091] In FIG. 4E, for the convenience of the explanation, the bit
line 44 is described in the shown section, but actually is
positioned in plane different from that where the plug 40 is
positioned, as same as the contact holes formed in the inter-layer
insulation film 42. The structure upper of the inter-layer
insulation film 42 including the inter-layer insulation film 42 in
FIG. 4E is the section along the line B-B' in FIG. 3B.
[0092] Then, a silicon nitride film is deposited on the entire
surface by, CVD method, and is etched back to form a sidewall
insulation film (not shown) on the side walls of the bit line 44
and the silicon nitride film 47.
[0093] Next, a silicon oxide film is deposited on the entire
surface by, e.g., CVD method, and the surface of the silicon oxide
film is polished until the silicon nitride film 47 is exposed to
form the inter-layer insulation film 48 having the surface
planarized.
[0094] A contact hole 50 is formed in the inter-layer insulation
films 48, 42 down to the plug 40 by the lithography and etching
(FIG. 5A). The contact hole 50 is opened by self-alignment with the
silicon nitride film 47 formed on the bit line 44 and the sidewall
insulation film (not shown) formed on the side wall of the bit line
44. In FIG. 5A and the followers, the bit line 44 is indicated by
the dotted line, because the bit line 44 does not appear in the
shown section.
[0095] Next, the plug 52 is buried in the contact hole 50 opened in
the inter-layer insulation films 42, 48 (FIG. 5B). For example, a
Ti (titanium) film, a TiN film and a W film are sequentially
deposited by CVD method, and the W film and TiN film are left in
the contact hole 50 by CMP method or etching back to form the plug
52. For the convenience of the explanation, the plug 52 and the bit
line 44 are shown in the same plane, but actually the plug 52 and
the bit line 44 are positioned in different planes from each other
and are electrically insulated from each other by the inter-layer
insulation films 42, 48, etc.
[0096] Next, an about 50-200 nm-thick silicon nitride film is
formed on the inter-layer insulation film 48 by, e.g., CVD method
to form the etching stopper film 54 of the silicon nitride
film.
[0097] Then, a silicon oxide film is deposited on the etching
stopper film 54 by, e.g., CVD method to form the inter-layer
insulation film 56 of the silicon oxide film. A thickness of the
inter-layer insulation film 56 is suitably set in accordance with a
required capacitance. For example, when a design rule (half a pitch
between the word lines and between the bit lines) is 0.13 .mu.m, a
capacitance of 1 cell is 30 fF, and a thickness of the capacitor
dielectric film is 1.2 nm, a thickness of the inter-layer
insulation film 56 is 0.8-0.9 .mu.m.
[0098] Next, an amorphous silicon film is deposited on the
inter-layer insulation film 56 by, e.g., CVD method to form a mask
film 58 of the amorphous silicon film. The mask film 58 is formed
in consideration of a case that a photoresist film may not provide
by itself sufficient masking in etching the thick inter-layer
insulation film 56. The mask film may not be essentially formed
when the photoresist film has sufficient resistance.
[0099] Then, the mask film 58 and the inter-layer insulation film
56 are patterned by the lithography and etching to form an opening
60 down to the etching stopper film 54 (FIG. 5C). The opening 60
will be filled with the plate electrode 62 in a later step and is
formed in a mesh as shown in FIG. 9.
[0100] At this time, with the etching stopper film 54 below as an
etching stopper, the mask film 58 and the inter-layer insulation
film 56 are etched such that the opening 60 can have the side wall
forward tapered. The side wall of the opening 60 can be forward
tapered by anisotropic etching which uses C.sub.4F.sub.8 gas, CO
gas and Ar and is stopped by the etching stopper film 54.
[0101] Next, the photoresist film (not shown) used in forming the
opening 60 is removed by, e.g., plasma ashing, and the mask film 58
of the amorphous silicon film is removed by, e.g., dry etching.
[0102] Then, a conducting film to be the plate electrode is
deposited on the entire surface by, e.g., CVD method, and the
conducting film on the inter-layer insulation film 56 is
selectively removed by CMP method or etching back to form the
mesh-shaped plate electrode 62 of the conducting film and buried in
the opening 60. At this time, the conducting film is over-etched
until the surface of the plate electrode 62 is lower than the
surface of the inter-layer insulation film 56 by about 100-300 nm
(FIG. 6A). The over-etching is for decreasing leak current between
the plate electrode 62 and the storage electrode 72, which is
formed later. A thickness of the inter-layer insulation film
described above must be set in consideration of an amount of the
over-etching. The over-etching is not essential.
[0103] A material of the conducting film forming the plate
electrode 62 is suitably selected in accordance with compatibility
with the capacitor dielectric film, which is to be formed later.
For example, when the capacitor dielectric film is a dielectric
film as of Ta.sub.2O.sub.5, the plate electrode 62 can be formed of
Ru (ruthenium), WN (tungsten nitride) or others. When the capacitor
dielectric film is a dielectric film as of BST, the plate electrode
62 can be formed of Pt (platinum), Ru, SRO(SrRuO.sub.3) or others.
When the capacitor dielectric film is a dielectric film as of ON
(SiO.sub.2/SiN) or others, the plate electrode 62 can be formed of
doped polycrystalline silicon or others. When the capacitor
dielectric film is a dielectric film as of PZT, the plate electrode
62 can be formed of Pt or others. In the present embodiment, the
capacitor dielectric film is Ta.sub.2O.sub.5 film or BST film, and
the plate electrode 62 is formed of Ru.
[0104] The side wall of the thus formed plate electrode 62 is
inversely tapered, contouring the shape of the side wall of the
opening 60.
[0105] In the present embodiment, the plate electrode 62 is buried
in the opening 60 formed in the inter-layer insulation film 56 for
the prevention of the occurrence of a global step between the
peripheral circuit region and the memory cell region. The
inter-layer insulation film 56 is left in the peripheral circuit
region by a height which is substantially the same as the plate
electrode 62 (or including the silicon nitride film 64 to be later
formed), whereby the following steps can be carried out with the
surface of the substrate kept substantially flat. This is very
effective in planarization steps and lithography steps in which
depth of focus is important.
[0106] Then, a 200-500 nm-thick silicon nitride film is deposited
on the entire surface by, e.g., CVD method, and the silicon nitride
film on the inter-layer insulation film 56 is selectively removed
by CMP or etching back to bury the silicon nitride film 64 in the
opening 60 on the plate electrode 62 (FIG. 6B). The step of burying
the silicon nitride film 64 is not essential. In the absence of
this step, disadvantageously leak current tends to occur at the
upper ends of the storage electrode and the plate electrode between
the two, but advantageously the fabrication process can be
shortened.
[0107] Here, the insulation film buried on the plate electrode 62
is not essentially silicon nitride film. However, considering that
the insulation film is used as a mask for removing the inter-layer
insulation film 56 in a later step, it is preferable that the
insulation film has etching characteristics different from those of
the inter-layer insulation film 56.
[0108] Then, a photoresist film 66 covering the peripheral circuit
region but exposing the memory cell region is formed by the
lithography. The photoresist film 66 is laid with the edge
positioned on the plate electrode 62 as shown in FIG. 9.
[0109] Next, with the photoresist film 66 and the silicon nitride
film 64 as a mask, and the etching stopper film 54 as an etching
stopper, the inter-layer insulation film 56 is selectively etched.
Thus, a pillar-shaped opening 68 for the storage electrode 72 to be
formed in is formed in the region of the memory cell region where
the inter-layer insulation film 56 has been removed.
[0110] This etching can be anisotropic etching, such as RIE or
others. However, wet etching using, e.g., an HF-based aqueous
solution is preferable in consideration that the insulation film is
unnecessarily left on the side wall of the opening due to the
inverse taper of the plate electrode 62, the plate electrode 62 is
damaged by the ions, etc. It is also possible to perform
isotropically etching, such as wet etching or others after the
anisotropic etching, such as RIE or others for the purpose of
removing unnecessary insulation film left on the side wall of the
plate electrode 62.
[0111] Next, after the photoresist film 66 is removed, a 10-30
nm-thick Ta.sub.2O.sub.5 or BST film is deposited on the entire
surface by, e.g., CVD method to form the capacitor dielectric film
70 of the Ta.sub.2O.sub.5 or BST film.
[0112] Then, the capacitor dielectric film 70 is anisotropically
etched to be left selectively on the side wall of the opening 68
(FIG. 7A).
[0113] Then, thermal treatment is performed to sufficiently
crystallize the capacitor dielectric film 70 and supplement oxygen
defects in the film. The thermal treatment is performed for the
capacitor dielectric film 70 of Ta.sub.2O.sub.5 film, e.g., in a
dry oxygen atmosphere, at a 650-750.degree. C. thermal processing
temperature and for 30 minutes of the thermal processing. For the
capacitor dielectric film 70 of BST, the thermal processing is
performed, e.g., in a dry oxygen atmosphere, at a 500-700.degree.
C. thermal processing temperature and for about 30 minutes of the
thermal processing.
[0114] At this time, the plug 52, which is covered by the etching
stopper film 54 of silicon nitride film known as an oxidation mask,
is kept from the oxidation. The storage electrode 72 has not been
formed yet, and electric characteristics between the plug 52 and
the storage electrode 72 are not deteriorated. Accordingly, the
high temperature and long time thermal processing required for the
crystallization and oxidation of the capacitor dielectric film 70
is allowed to be performed suitably in accordance with requirements
of the capacitor dielectric film 70.
[0115] Then, the etching stopper film 54 exposed in the opening 68
is selectively removed by anisotropically etching, such as RIE or
others to expose the plug 52 in the opening 68 (FIG. 7B). In this
etching, the capacitor dielectric film 70 is exposed to the etching
environments but is free from serious damages because the capacitor
dielectric film 70 is arranged in parallel with the direction of
movement of the ions. The capacitor dielectric film 70 is a little
damaged by the ion application and charge up, but the damage can be
removed by relatively low-temperature thermal processing of
400-500.degree. C.
[0116] In the present embodiment, the plate electrode 62 has the
side wall inversely tapered, whereby plasma damage incorporated in
the capacitor dielectric film 70 can be reduced in comparison with
that in the case that the plate electrode 62 has the side wall made
vertical or forward tapered.
[0117] The plate electrode 62 has the side wall inversely tapered,
whereby additionally advantageously an opening width of the etching
stopper film 54 along the bit line can be smaller than an opening
width of the opening 68 along the bit line. That is, the parasitic
capacitance between the bit line 44 and the storage electrode 72
can be lowered.
[0118] At the same time that the etching stopper film 54 is etched,
the silicon nitride film 64 on the plate electrode 62 is etched.
However, the etching stopper film 54, a film thickness (about 20
nm) of which is sufficiently thinner than a film thickness (100-300
nm) of the silicon nitride film 64, can be removed, leaving the
silicon nitride film 64.
[0119] Then, a 50-300 nm-thick Ru film is deposited on the entire
surface by, e.g., CVD method, and the Ru film on the inter-layer
insulation film 56 is selectively removed by CMP method or etching
back to form in the opening 68 the capacitor electrode 72 of the Ru
film electrically connected to the source/drain diffused layer 28
through the plug 52. A material of the storage electrode 72 is
suitably selected in accordance with compatibility with the
capacitor dielectric film 70, as in the case of the plate
electrode.
[0120] Next, as required, the interconnection layer 74 is formed,
connected to the plate electrode 62; the interconnection layer 76
is formed, connected to the interconnection layer 46; etc.
[0121] Thus, a DRAM comprising memory cells including one
transistor and one capacitor can be fabricated.
[0122] When a semiconductor device having an about 0.2 .mu.m-.phi.
contact area between the plug 52 and the storage electrode 72 was
fabricated by the above-described fabrication process, a contact
resistance was about 10 .OMEGA./contact. On the other hand, when
the contact structure was formed by the conventional semiconductor
device fabrication process in which the storage electrode was
formed in advance, a contact resistance was about 1
M.OMEGA./contact. Thus, it is evident that the method for
fabricating the semiconductor device according to the present
invention is much superior.
[0123] As described above, according to the present embodiment, the
capacitor dielectric film 70 is formed after the plate electrode 58
has been formed, and then the storage electrode 72 connected to the
plug 52, whereby electric characteristics between the plug 52 and
the storage electrode 72 are not deteriorated by the
high-temperature thermal processing in the step of forming the
capacitor dielectric film 70.
[0124] The inter-layer insulation film 56 is left as it is in the
peripheral circuit region, whereby the formation of the capacitor
does not impair the surface flatness. Accordingly, the surface can
be easily planarized in comparison with the conventional method in
which a thick insulation film is formed and then the surface is
planarized. The problem of depth of focus can be mitigated, which
facilitates micronized patterning. There is no problem of impairing
interconnection reliability at a step.
[0125] [A Second Embodiment]
[0126] The semiconductor device and the method for fabricating the
same according to a second embodiment of the present invention will
be explained with reference to FIGS. 10, 11A-11C and 12A-12B. The
same members of the present embodiment as those of the
semiconductor device and the method for fabricating the same
according to the first embodiment are represented by the same
reference numbers not to repeat or to simplify their
explanation.
[0127] FIG. 10 is a diagrammatic sectional view of the
semiconductor device according to the present embodiment, which
show a structure thereof. FIGS. 11A-11C and 12A-12B are sectional
views of the semiconductor device in the steps of the method for
fabricating the semiconductor device, which show the method.
[0128] As shown in FIG. 10, the semiconductor device according to
the present embodiment is basically the same as the semiconductor
device according to the first embodiment shown in FIG. 3. The
semiconductor device according to the present embodiment is
characterized in that the storage electrode 72 is connected
directly to the plug 40 without the plug 52 interposed
therebetween. The semiconductor device has such structure, whereby
a number of its fabrication steps can be small, and its fabrication
cost can be low.
[0129] Next, the method for fabricating the semiconductor device
according to the present embodiment will be explained with
reference to FIGS. 11A-11C and 12A-12B.
[0130] First, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment shown in FIGS. 4A to 4E, a memory cell transistor, a
peripheral circuit transistor, a bit line 44, an interconnection
layer 46, etc. are formed.
[0131] Next, a silicon oxide film is deposited on the entire
surface by, e.g., CVD method, and the surface of the silicon oxide
film is polished by CMP method to form an inter-layer insulation
film 48 of the silicon oxide film and having the surface planarized
(FIG. 11A).
[0132] Then, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment, an etching stopper film 54, an inter-layer insulation
film 56, a plate electrode 62 and a capacitor dielectric film 70
are formed (FIG. 11B).
[0133] Next, thermal treatment is performed for sufficiently
crystallizing a capacitor dielectric film 70 and supplementing
oxygen defects in the film. At this time, a plug 40 is covered by
an etching stopper film 54 of silicon nitride film known as an
oxidation mask, etc., and the surface of the plug 40 is not
oxidized. The storage electrode 72 has not yet been formed, and
electrical characteristics between the plug 40 and the storage
electrode 72 are not deteriorated.
[0134] Then, the etching stopper film exposed in a opening 68 is
selectively removed by anisotropically etching, such as RIE or
others (FIG. 11C).
[0135] Then, the inter-layer insulation films 48, 42 exposed in the
opening 68 are selectively removed by anisotropically etching such
as RIE or others. Thus, the plug 40 connected to a source/drain
diffused layer 28 is exposed in the opening 68 (FIG. 12A).
[0136] Here, the inter-layer insulation films 48, 42 can be etched
by self-alignment with the silicon nitride film 47 formed on the
bit line 44, and a sidewall insulation film of the silicon nitride
film formed on the side wall of the bit line 44. Accordingly, the
bit line 44 is not exposed in the opening 68.
[0137] The plate electrode 62 has the side wall inversely tapered,
and a width of the opening formed in the inter-layer insulation
films 48, 42 can be smaller than an opening width of the opening
68, whereby a parasitic capacitance between the bit line 44 and the
storage electrode 72 can be small.
[0138] Next, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment shown in FIGS. 8A and 8B, the storage electrode 72 and
the interconnection layers 74 are formed. Thus, a DRAM comprising
memory cells each including one transistor and one capacitor can be
fabricated (FIG. 12B).
[0139] As described above, according to the present embodiment,
also in forming the storage electrode 72 so as to function also as
the plug 52 of the first embodiment, deterioration of electric
characteristics between the plug 40 and the storage electrode 72 by
the high-temperature thermal processing in forming the capacitor
dielectric film 70 can be prevented.
[0140] In the present embodiment, the storage electrode 72 is
connected to the source/drain diffused layer 28 through the plug
40. However, the storage electrode 72 may be connected directly to
the source/drain diffused layer 28, and in this case, the present
invention is significant in that oxidation of the surface of the
silicon substrate 10, and aggregation of a silicide layer formed
between the storage electrode 72 and the silicon substrate 10 are
suppressed in the high-temperature thermal processing for forming
the capacitor dielectric film 70. The storage electrode 72 is
connected directly to the silicon substrate 10 by further etching
the inter-layer insulation film 32 below the inter-layer insulation
film 42 in the step of FIG. 12A.
[0141] In the semiconductor device according to the present
embodiment, the plug 40 of doped polycrystalline silicon and the
storage electrode 72 of the metal directly contact each other, and
there is a risk that the plug 40 and the storage electrode 72 may
react with each other in a later thermal processing to form an
eutectic alloy. Accordingly, it is also preferable to form in
advance on the upper surface of the plug 40 a barrier metal for
preventing the eutectic reaction, and in this case, the barrier
metal of, e.g., TiN/Ti may be formed on the upper surface of the
plug 40 immediately after the plug 40 has been formed.
[0142] The barrier metal may be formed thin by sputtering after the
step of FIG. 12A. In this case, sputtered particles are not easily
deposited on the side wall of the opening 68, which is inversely
tapered, and can be deposited selectively on the plug 40. This
method is effective when the barrier metal and the capacitor
dielectric film 70 have poor compatibility with each other.
[0143] The barrier metal of TiON film may be formed on the entire
surface by CVD method. This is effective in a case that the
capacitor dielectric film 70 is formed of Ti.sub.2O.sub.5 film
because TiON film has good compatibility with Ti.sub.2O.sub.5
film.
[0144] [A Third Embodiment]
[0145] The semiconductor device according to a third embodiment of
the present invention and the method for fabricating the
semiconductor device will be explained with reference to FIGS. 13,
14A-14B, 15A-15B, 16A-16B, 17A-17B, and 18. The same members of the
present embodiment as those of the semiconductor device and the
method for fabricating the same according to the first and the
second embodiments are represented by the same reference numbers
not to repeat or to simplify their explanation.
[0146] FIG. 13 is a diagrammatic sectional view of the
semiconductor device according to the third embodiment of the
present invention, which shows the structure thereof. FIGS.
14A-14B, 15A-15B, 16A-16B, and 17A-17B are sectional views of the
semiconductor device according to the present embodiment in the
steps of the method for fabricating the same, which show the
method. FIG. 18 is a view of an example of patterns of the
photoresist film used in the method for fabricating the
semiconductor device according to the present embodiment.
[0147] As shown in FIG. 13, the semiconductor device according to
the present embodiment is basically the same as the semiconductor
device according to the second embodiment. The semiconductor device
according to the present embodiment is characterized in that a
width of the contact part of a storage electrode 72 is smaller than
an opening width of an opening 68 with the storage electrode 72
buried in. A width of the contact part of the storage electrode 72
along the extension of a bit line 44 is reduced, whereby a
parasitic capacitance between the bit line 44 and the storage
electrode 72 can be small, and a storage capacitance required by
the capacitor can be accordingly small. Accordingly, a merit is
that the storage electrode 72 can have a height reduced. The
storage electrode 72 can be low, which facilitates the process of
forming an opening in an inter-layer insulation film 56.
[0148] Next, the method for fabricating the semiconductor device
according to the present embodiment will be explained with
reference to FIGS. 14A-14B, 15A-15B, 16A-16B, and 17A-17B.
[0149] First, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment shown in FIGS. 4A to 4E and FIG. 5C, a memory cell
transistor, a peripheral circuit transistor, a bit line 44, an
interconnection layer 46, an etching stopper film 54, an
inter-layer insulation film 56, a mask film 58, an opening 60, etc.
are formed. The plug 52 is not formed, as is not in the second
embodiment (FIG. 14A)
[0150] Then, in the same way as in, e.g., the method for
fabricating the semiconductor device according to the first
embodiment shown in FIGS. 6A and 6B, a plate electrode 62 buried in
the opening 60, and a silicon nitride film 64 covering the upper
surface of the plate electrode 62 are formed (FIG. 14B)
[0151] Next, a photoresist film 66 is formed on the inter-layer
insulation film 56 and the silicon nitride film 64 by the
lithography (FIG. 15A).
[0152] The photoresist film 66 has the pattern exemplified in FIG.
18. The photoresist film 66 has a pattern which exposes at least a
part of the inter-layer insulation film 56 in a memory cell region
and has a width of an opening along extension of the bit line 44 is
sufficiently smaller than a width of the inter-layer insulation
film 56. For parasitic capacitance reduction it is preferable that
an opening width along extension of the bit line is about 1/3 of a
width of the storage electrode along extension of the storage
electrode 72. A pattern for forming such opening can be a stripe
pattern in which, as exemplified in FIG. 18, narrow stripes are
extended perpendicularly to the direction of extension of the bit
line 44.
[0153] Then, the inter-layer insulation film 56 is selectively
etched with the photoresist film 66 as a mask selectively with
respect to the plate electrode 62, the silicon nitride film 64 and
the etching stopper film 54 to form the opening 68 (FIG. 15B). At
this time, the inter-layer insulation film 56 is etched under
conditions for wet etching using an HF-based aqueous solution or
others, which isotropically advance the etching to be thereby
selectively removed.
[0154] Next, with the photoresist film 66 as a mask, the etching
stopper film 54 exposed in the opening 68 is selectively removed by
anisotropically etching, such as RIE or others (FIG. 16A). The
etching stopper film 54 is etched with the photoresist film 66 as a
mask, whereby an open width of the etching stopper film 54 along
extension of the bit line 44 can be made substantially equal to an
open width of the photoresist film 66. The etching stopper film 54
can be selectively removed by, e.g., anisotropic etching using
CF.sub.4 gas and C.sub.2H.sub.4 gas.
[0155] Then, after the photoresist film 66 has been removed, a
10-30 nm-thick Ta.sub.2O.sub.5 film or BST film is deposited on the
entire surface by, e.g., CVD method to form the capacitor
dielectric film 70 of Ta.sub.2O.sub.5 or BST.
[0156] Next, the capacitor dielectric film 70 is anisotropically
etched to be left selectively on the side wall of the opening 68
(FIG. 16B).
[0157] Next, thermal treatment follows for sufficiently
crystallizing the capacitor dielectric film 70 and supplementing
oxygen defects of the film. At this time, the plug 40, which is not
exposed, is not oxidized by the thermal treatment, or contact
characteristics of the plug 40 with the storage electrode 72, which
is to be formed in a later step are not deteriorated.
[0158] Next, with the silicon nitride film 64 and the etching
stopper film 54 as a mask, the inter-layer insulation films 48, 42
are selectively removed by anisotropically etching, such as RIE or
others to expose the plug 40 in the opening 68 (FIG. 17A). The
inter-layer insulation films 48, 42 are etched with the etching
stopper film 54 as a mask, whereby an open width of the inter-layer
insulation films 48, 42 along extension of the bit line 44 can be
made substantially equal to an open width of the photoresist film
66.
[0159] Then, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment shown in FIGS. 8A and 8B, the storage electrode 72, an
interconnection layers 74, 76 are formed. Thus, a DRAM comprising
memory cells including one transistor and one capacitor is
fabricated.
[0160] As described above, according to the present embodiment, a
width of the contact part of the storage electrode 72 along
extension of the bit line 44 can be decreased, whereby a parasitic
capacitance between the bit line 44 and the storage electrode 72
can be much small.
[0161] [A Fourth Embodiment]
[0162] The semiconductor device and the method for fabricating the
same according to a fourth embodiment of the present invention will
be explained with reference to FIGS. 19, 20A-20B, and 21A-21B. The
same members of the present embodiment as those of the
semiconductor device and the method for fabricating the same
according to the first to the third embodiments are represented by
the same reference numbers not to repeat or to simplify their
explanation.
[0163] FIG. 19 is a diagrammatic sectional view of the
semiconductor device according to the present embodiment. FIGS.
20A-20B and 21A-21B are sectional views of the semiconductor device
according to the present embodiment in the steps of the method for
fabricating the semiconductor device, which show the method.
[0164] As shown in FIG. 19, the semiconductor device according to
the present embodiment is basically the same as the semiconductor
device according to the first embodiment shown in FIG. 3. The
semiconductor device according to the present embodiment is
characterized in that a plate electrode 62 is not buried between
storage electrodes 72, but a thin plate electrode 62 is formed
along the storage electrodes and the etching stopper film 54.
[0165] Next, the method for fabricating the semiconductor device
according to the present embodiment will be explained with
reference to FIGS. 20A-20B and 21A-21B.
[0166] First, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment, a memory cell transistor, a peripheral circuit
transistor, a bit line 44, an interconnection layer 46, an etching
stopper film 54, an inter-layer insulation film 56, a mask film 58,
an opening 60 are formed (FIG. 20A).
[0167] Next, a photoresist film (not shown) used in forming the
opening 60 is removed by, e.g., plasma ashing, and the mask film 58
of amorphous silicon film is removed by, e.g., dry etching.
[0168] Then, a 10-50 nm-thick conducting film and a 100-300
nm-thick insulation film are deposited on the entire surface by,
e.g., CVD method, and the conducting film and the insulation film
on the inter-layer insulation film 56 are selectively removed by
CMP method or etching back to form the plate electrode 62 of the
conducting film formed along the inside wall and the bottom of the
opening 60, and an insulation film 78 of the insulation film buried
in the opening 60 with the plate electrode 62 formed in. At this
time, over-etching is performed until the surfaces of the plate
electrode 62 and the insulation film 78 are lower about 100-300 nm
than the surface of the inter-layer insulation film 56 (FIG.
20B).
[0169] Then, a 200-500 nm-thick silicon nitride film is deposited
on the entire surface by, e.g., CVD method, and the silicon nitride
film on the inter-layer insulation film 56 is selectively removed
by CMP or etching-back to be buried in the opening 60 on the plate
electrode 62 and the insulation film 78 (FIG. 21A).
[0170] Next, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment shown in FIGS. 7A to 8B, a capacitor dielectric film 70,
the storage electrode 72, interconnection layers 74, 76, etc. are
formed. As shown in FIG. 21B, the interconnection layer 74 can be
connected to the plate electrode 62 at the bottom of the opening
60.
[0171] Thus, a DRAM comprising memory cell each including one
transistor and one capacitor is fabricated.
[0172] As described above, according to the present embodiment, in
place of burying the plate electrode 62 completely between the
storage electrodes 72, the plate electrode 62 can be formed thin
along the storage electrode 72 and the etching stopper film 54.
[0173] The method for fabricating the semiconductor device
according to the present embodiment has a merit that plasma damage
to the capacitor can be decreased when the process for
simultaneously forming the contact hole for connecting the
interconnection layer 76 of the peripheral circuit to the
interconnection layer 46 and the contact hole for connecting the
interconnection layer 74 to the plate electrode is considered. That
is, the plate electrode 62 and the interconnection layer 74 are
contacted each other near the bottom of the opening 60, whereby a
depth difference between the peripheral circuit contact hole and
the contact hole for connecting the plate electrode 62 can be
small. Accordingly, a period time in which the capacitor is exposed
to plasm damage due to charge-up, etc. until the peripheral circuit
contact hole is opened after the contact hole for connecting the
plate electrode 62 has been completely opened can be shortened.
Thus, the method for fabricating the semiconductor device according
to the present embodiment is very effective from the viewpoint of
ensuring reliability of the capacitor.
[0174] In the present embodiment, the plate electrode 62 is formed
along the inside wall of the opening 60, but the storage electrode
72 may be also formed along the inside wall of the opening 68.
[0175] In the present embodiment, the plate electrode 62 is formed
along the inside wall of the opening 60 of the semiconductor device
according to the first embodiment. This may be also applicable to
the semiconductor device according to the second and the third
embodiments.
[0176] [A Fifth Embodiment]
[0177] The semiconductor device and the method for fabricating the
same according to a fifth embodiment of the present invention will
be explained with reference to FIGS. 22, 23A-23B, 24A-24B, and
25A-25B. The same members of the present embodiment as those of the
semiconductor device and the method for fabricating the same
according to the first to the fourth embodiments are represented by
the same reference numbers not to repeat or to simplify their
explanation.
[0178] FIG. 22 is a diagrammatic sectional view of the
semiconductor device according to the present embodiment. FIGS.
23A-23B, 24A-24B, and 25A-25B are sectional views of the
semiconductor device according to the present embodiment in the
steps of the method for fabricating the same, which show the
method.
[0179] As shown in FIG. 22, the semiconductor device according to
the present embodiment is characterized in that an interconnection
layer 76 of a peripheral circuit region is connected to an
interconnection layer 46 through a plug 84 of the same conducting
layer as a storage electrode 72. This structure of the
semiconductor device makes it unnecessary to form a contact hole
deep for connecting the peripheral circuit interconnection layer 76
to the interconnection layer 46, without adding to a fabrication
step number. When the semiconductor device according to the first
embodiment uses the structure of burying the plug in the contact
hole, the method for fabricating the semiconductor device
additionally requires the step of burying a conducting film to be
the plug. However, the present embodiment can delete this step.
[0180] Next, the method for fabricating the semiconductor device
according to the present embodiment will be explained with
reference to FIGS. 23A-23B, 24A-24B, and 25A-25B.
[0181] In the same way as, e.g., in the method for fabricating the
semiconductor device according to the first embodiment, a memory
cell transistor, a peripheral circuit transistor, a bit line 44, an
interconnection layer 46, a plate electrode 62, etc. are formed. At
this time, in the steps of FIGS. 5A and 5B, a plug 52 connected to
a plug 40, and a plug 80 connected to the interconnection layer 46
are simultaneously formed (FIG. 23A).
[0182] Next, a photoresist film 66 having an opening as exemplified
in FIG. 9 formed in the memory cell region and an opening formed in
a region where the contact hole of the peripheral circuit region is
to be formed is formed by the lithography.
[0183] Then, with the photoresist film 66 and the silicon nitride
film 64 as a mask and with the etching stopper film 54 as a
stopper, the inter-layer insulation film 56 is anisotropically
etched to form the opening 68 in the memory cell region and the
contact hole 82 in the peripheral circuit region (FIG. 23B).
[0184] In the present embodiment, in which the opening 68 and the
contact hole 82 are simultaneously formed, it is difficult to use
the isotropically wet etching for etching the inter-layer
insulation film 56 as used in the method for fabricating the
semiconductor device according to the first embodiment. On the
other hand, when the inter-layer insulation film 56 is
anisotropically etched, there is a risk that unnecessary insulation
film may remain on the side wall of the plate electrode 62 because
the side wall of the opening 68 contours an inversely tapered shape
of the plate electrode 62, and, in this case, the anisotropically
etching is followed by a little isotropically etching to thereby
remove the unnecessary insulation film.
[0185] Then, after the photoresist film 66 is removed, a 10-30
nm-thick Ta.sub.2O.sub.5 film or BST is deposited on the entire
surface by, e.g., CVD method to form the capacitor dielectric film
70 of Ta.sub.2O.sub.5 or BST.
[0186] Then, the capacitor dielectric film 70 is anisotropically
etched to be left selectively on the side walls of the opening 68
and the contact hole 82 (FIG. 24A).
[0187] Next, thermal treatment is performed by sufficiently
crystallizing the capacitor dielectric film 70 and supplementing
oxygen defects of the capacitor dielectric film 70. At this time,
the plug 52 is covered by the etching stopper film 54 of silicon
nitride film, which is known as an oxidation mask, and the surface
is not oxidized. The storage electrode 72 has not been formed yet,
and electric characteristics between the plug 52 and the storage
electrode 72 are not deteriorated.
[0188] Then, the etching stopper film 54 exposed in the opening 68
is selectively removed by anisotropically etching, such as RIE or
others to expose the plug 52 in the opening 68 and the plug 80 in
the contact hole 82 (FIG. 24B).
[0189] Next, a 50-300 nm-thick Ru film is deposited on the entire
surface by, e.g., CVD method, and the Ru film on the inter-layer
insulation film 56 is selectively removed by CMP method or etching
back to form the storage electrode 72 of the Ru film in the opening
68, electrically connected to the source/drain diffused layer 28
through the plug 52, and the plug 84 formed in the contact hole 82
of the Ru film, connected to the interconnection layer 46 through
the plug 80 (FIG. 25A).
[0190] Then, as required, the interconnection layer 74 connected to
the plate electrode 62, the interconnection layer 76 connected to
the interconnection layer 46 through the plug 84, etc. are formed
(FIG. 25B).
[0191] Thus, a DRAM comprising memory cell each including one
transistor and one capacitor is fabricated.
[0192] As described above, according to the present invention, the
plug 84 for leading out the interconnection layer 46 of the
peripheral circuit is formed of the conducting layer as the storage
electrode, whereby it is not necessary to add the step for forming
a deep contact hole for connecting the interconnection layer 76 of
the peripheral circuit to the interconnection layer 46. When the
structure in which the plug is buried in the contact hole is used
in the method for fabricating the semiconductor device according to
the first embodiment, the step of burying the conducting film to be
the pug must be added. However, the present embodiment can omit
this step.
[0193] In the present embodiment, the plug 84 and the storage
electrode 72 are formed of the same conducting layer in the
semiconductor device according to the first embodiment, but this is
also applicable to the semiconductor device according to the second
to the fourth embodiments.
[0194] [A Sixth Embodiment]
[0195] The semiconductor device and the method for fabricating the
same according to a sixth embodiment of the present invention will
be explained with reference to FIGS. 26, 27A-27B, 28A-28B, and
29A-29B. The same members of the present embodiment as those of the
semiconductor device and the method for fabricating the same
according to the first to the fifth embodiments are represented by
the same reference numbers to repeat or to simplify their
explanation.
[0196] FIG. 26 is a diagrammatic sectional view of the
semiconductor device according to the present embodiment, which
show a structure thereof. FIGS. 27A-27B, 28A-28B, and 29A-29B are
sectional views of the semiconductor device according to the
present embodiment in the steps of the method for fabricating the
same, which show the method.
[0197] The semiconductor device according to the present embodiment
is characterized in that, as shown in FIG. 26, an interconnection
layer 76 of a peripheral circuit region is connected to an
interconnection layer 46 through a plug 88 of the conducting layer
forming a plate electrode 62. The structure of the semiconductor
device makes it unnecessary to form a deep contact hole for
connecting the interconnection layer 76 of the peripheral circuit
to the interconnection layer 46. This adds no fabrication step. The
use of this structure of burying the plug in the contact hole in
the method for fabricating the semiconductor device according to
the first embodiment requires an additional step of burying a
conducting film to be the plug. The present embodiment can omit
this step.
[0198] Next, the method for fabricating the semiconductor device
according to the present embodiment will be explained with
reference to FIGS. 27A-27B, 28A-28B, and 29A-29B.
[0199] First, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment shown in FIG. 4A to FIG. 5B, a memory cell transistor, a
peripheral circuit transistor, a bit line 44, an interconnection
layer 46, a plug 52, etc. are formed. At this time, in the steps
shown in FIGS. 5A and 5B, the plug 52 and a plug 80 are
simultaneously formed, connected respectively to the plug 40 and
the interconnection layer 46 (FIG. 27A).
[0200] Next, an etching stopper film 54 of a silicon nitride film,
an inter-layer insulation film 56 of a silicon oxide film and a
mask film 58 of an amorphous silicon film are formed on the
inter-layer insulation film 48 by, e.g., CVD method.
[0201] Then, the mask film 58, the inter-layer insulation film 56
and the etching stopper film 54 are patterned by the lithography
and etching to form an openings 60, 86 down to the inter-layer
insulation film 48 and the plug 80 (FIG. 27B). A region for the
opening 60 formed in corresponds to a region for a plate electrode
62 formed in, and a region for the opening 86 formed in corresponds
to a region for a contact hole for the peripheral circuit to be
formed in.
[0202] Next, the photoresist film (not shown) which has been used
in forming the opening 60 is removed by, e.g., plasma ashing, and
the mask film 58 of amorphous silicon film is removed by, e.g., dry
etching.
[0203] Next, in the same way as, e.g., in the method for
fabricating the semiconductor device shown in FIGS. 6A and 6B, the
plate electrode 62 is formed, buried in the opening 60 and having
he upper surface covered by the silicon nitride film 64. At this
time, the conducting film which is the same conducting film as the
plate electrode 62 and the silicon nitride film are also buried in
the opening 86. A plug 88 and the silicon nitride film covering the
upper surface of the plug 88 are formed in the opening 86 (FIG.
28A).
[0204] Then, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment shown in FIG. 7A, the inter-layer insulation 56 in the
memory region is removed to form the opening 68, and the capacitor
dielectric film 70 is formed selectively on the inside wall of the
opening 86 (FIG. 28B).
[0205] Next, thermal treatment is performed for sufficiently
crystallizing the capacitor dielectric film 70 and supplementing
oxygen defects of the capacitor dielectric film. At this time, the
plug 52 covered by the silicon nitride film, which is known as an
oxidation mask, is not oxidized. The storage electrode 72 has not
been formed yet, and electric characteristics between the plug 52
and the storage electrode 72 are not deteriorated.
[0206] Then, the etching stopper film 54 exposed in the opening 68
is removed by anisotropic etching, such as RIE or others. To expose
the plug 52 in the opening 68 (FIG. 29A).
[0207] Next, in the same way as, e.g., in the method for
fabricating the semiconductor device according to the first
embodiment shown in FIGS. 8A and 8B, the storage electrode 72
buried in the opening 68, the interconnection layer 74 connected to
the plate electrode 62, the interconnection layer 76 connected to
the interconnection layer 46 through the plugs 88, 80, etc. are
formed (FIG. 29B).
[0208] Thus, a DRAM comprising memory cell each including one
transistor and one capacitor is fabricated.
[0209] As described above, according to the present embodiment, the
plug 88 for leading out the interconnection layer 46 of the
peripheral circuit is formed of the conductor layer forming the
plate electrode 62, whereby the additional step of forming a deep
contact hole for connecting the interconnection layer 76 to the
interconnection layer 46 of the peripheral circuit is not
necessary. When the structure of burying the plug in the contact
hole is applied to the method for fabricating the semiconductor
device according to the first embodiment, the step of burying the
conducting film to be the plug must be added, but the present
embodiment can omit this step.
[0210] In the present embodiment, the semiconductor device
according to the first embodiment has the plug 88 formed of the
conducting layer forming the plate electrode 62, and this may be
also applied to the semiconductor device according to the second to
the fourth embodiments.
[0211] [Modifications]
[0212] The present invention is not limited to the above-described
embodiments and cover other various modifications.
[0213] For example, in the first embodiment, after the capacitor
dielectric film 70 is selectively left on the side wall of the
opening 68 by anisotropic etching, the thermal treatment for
sufficiently crystallizing the capacitor dielectric film 70 and
supplementing oxygen defects of the capacitor dielectric film is
performed. However, the thermal oxidation does not essentially
follow the anisotropic etching of the capacitor dielectric film 70.
The thermal treatment for sufficiently crystallizing the capacitor
dielectric film 70 and supplementing oxygen defects of the
capacitor dielectric film may be performed at least after the
capacitor dielectric film 70 is deposited and before the storage
electrode 72 is formed. The timing can be suitable selected
corresponding to materials forming the capacitor.
[0214] For example, in the method for fabricating the semiconductor
device according to the first to the sixth embodiments, the thermal
oxidation may be performed immediately after the capacitor
dielectric film is deposited, formed on the entire surface. In this
case, because the dielectric film 70 is left over a large area,
orientations of crystals of the capacitor dielectric film 70 can be
made uniform. This is a merit.
[0215] In the method for fabricating the semiconductor device
according to the first, and the fourth to the sixth embodiments,
when the thermal processing in an oxidizing atmosphere is
unnecessary, the capacitor dielectric film 70 is not formed in a
step corresponding to the step of FIG. 7A but, in a step
corresponding to the step of FIG. 7B, is deposited after the
etching stopper film 54 is removed. Then, thermal treatment may be
performed with the capacitor dielectric film 70 formed on the
entire surface or after anisotropic etching is performed.
[0216] Similarly, in the method for fabricating the semiconductor
device according to the second or the third embodiment, when the
thermal treatment in an oxidizing atmosphere is unnecessary, the
capacitor dielectric film 70 is not formed in the step of FIG. 11B
or FIG. 16B, but, in the step of FIG. 12A or FIG. 17B, is deposited
after the etching stopper film 54 or the inter-layer insulation
films 48, 42 are removed. Then, thermal treatment may be performed
with the capacitor dielectric film 70 formed on the entire surface
or after anisotropic etching is performed.
[0217] In the method for fabricating the semiconductor device
according to the first embodiment, the photoresist film 66 for
removing the inter-layer insulation film 56 to form the opening 68
for the storage electrode to be buried in has the pattern shown in
FIG. 9. However, the pattern of the photoresist film 66 is not
limited to the pattern of FIG. 9.
[0218] The photoresist film 66 may have any pattern as long as the
photoresist film 66 can expose a part of each of pillar-shaped
inter-layer insulation film 56 left in the memory cell regions. For
example, the photoresist film 66 may have a pattern of stripes as
shown in FIGS. 18 and 31A which are parallelly extended in the
direction of extension of the word lines (gate electrodes 20). The
photoresist film 66 may have a pattern of stripes as shown in FIG.
31B which are parallelly extended in the direction of extension of
the bit lines. As shown in FIG. 32A, the photoresist film 66 may
have a pattern having discrete openings for respective
pillar-shaped inter-layer insulation film 56. As shown in FIG. 32B,
the photoresist film 66 may have a pattern of stripes which are
extended slant to the word liens and the bit lines.
[0219] In the first to the sixth embodiments, the side wall of the
opening 60 for the plate electrode 62 to be buried in is inversely
tapered but may not be essentially inversely tapered. The side wall
of the opening 60 may be substantially vertical or forward
tapered.
* * * * *