U.S. patent application number 09/060242 was filed with the patent office on 2001-12-06 for address generator of dynamic memory testing circuit and address generating method thereof.
Invention is credited to KIM, HEON-CHEOL.
Application Number | 20010049807 09/060242 |
Document ID | / |
Family ID | 19513198 |
Filed Date | 2001-12-06 |
United States Patent
Application |
20010049807 |
Kind Code |
A1 |
KIM, HEON-CHEOL |
December 6, 2001 |
ADDRESS GENERATOR OF DYNAMIC MEMORY TESTING CIRCUIT AND ADDRESS
GENERATING METHOD THEREOF
Abstract
A memory address generating apparatus and method of a dynamic
memory testing circuit for generating addresses for testing a
dynamic memory which uses all the available addresses of the
dynamic memory, which does not use the most significant addresses,
and which does not use middle addresses among all the available
addresses are provided. The address generator can obtain an
up-counted address by up counting the addresses used by the dynamic
memory. It can obtain a down-counted address by inverting the N-bit
up-counted value, or by subtracting the N-bit up-counted value from
the maximum address, or by combining the inverted MSB portion of
the N-bit up-counted value with the LSB portion of the N-bit
up-counted value subtracted from the LSB portion of the maximum
address used in the dynamic memory. The down and up counted
addresses are used as addresses for selectively testing the dynamic
memory according to a selected testing method.
Inventors: |
KIM, HEON-CHEOL;
(YONGIN-CITY, KR) |
Correspondence
Address: |
STEVEN M MILLS, ESQ.
SAMUELS GAUTHIER & STEVENS, LLP
225 FRANKLIN STREET
SUITE 3300
BOSTON
MA
02110
|
Family ID: |
19513198 |
Appl. No.: |
09/060242 |
Filed: |
April 14, 1998 |
Current U.S.
Class: |
714/743 |
Current CPC
Class: |
G11C 29/20 20130101 |
Class at
Publication: |
714/743 |
International
Class: |
G11C 029/00; G06F
011/00; G01R 031/28 |
Claims
What is claimed is:
1. An apparatus for generating memory addresses in a dynamic memory
testing circuit for testing the dynamic memory using all available
addresses of the dynamic memory, comprising: an N-bit binary
counter for performing counting operation and for generating an
N-bit counted value word as an address used by the dynamic memory,
wherein N is the number obtained by adding the number of bits of
the row address of the dynamic memory to the number of bits of the
column address of the dynamic memory; inverting means for inverting
the counted value word to generate an N-bit inverted value word;
and first selecting means for selectively forwarding to the dynamic
memory one of the inverted value word and the counted value word in
response to a first select signal used to control the first
selecting means.
2. The apparatus of claim 1 wherein the N-bit binary counter is an
up counter.
3. The apparatus of claim 2, further comprising second selecting
means for selectively outputting to the dynamic memory one of the
row and column addresses generated from the first selecting means,
in response to a second select signal.
4. The apparatus of claim 2, wherein, when the column address of
the dynamic memory is to be generated, the N-bit binary up counter
outputs the most significant bit (MSB) portion of the N-bit counted
value word as the row address and the least significant bit (LSB)
portion of the N-bit counted value word as the column address.
5. The apparatus of claim 2, wherein, when the row address of the
dynamic memory is to be generated, the N-bit binary up counter
outputs the LSB portion of the N-bit counted value word as the row
address and the MSB portion of the N-bit counted value word as the
column address.
6. The apparatus of claim 1 wherein the N-bit binary counter is a
down counter.
7. The apparatus of claim 6, further comprising second selecting
means for selectively outputting to the dynamic memory one of the
row and column addresses generated from the first selecting means,
in response to a second select signal.
8. The apparatus of claim 6, wherein, when the column address of
the dynamic memory is to be generated, the N-bit binary down
counter outputs the MSB portion of the N-bit counted value word as
the row address and the LSB portion of the N-bit counted value word
as the column address.
9. The apparatus of claim 6, wherein, when the row address of the
dynamic memory is to generated, the N-bit binary down counter
outputs the LSB portion of the N-bit counted value word as the row
address and the MSB portion of the N-bit counted value word as the
column address.
10. An apparatus for generating memory addresses in a dynamic
memory testing circuit for testing a dynamic memory which does not
use some of its most significant addresses comprising: an N-bit
binary up counter for performing an up counting operation and for
generating an N-bit counted value word as an address used by the
dynamic memory, wherein N is the number of bits obtained by adding
the number of bits of the row addresses of the dynamic memory to
the number of bits of the column addresses of the dynamic memory;
subtracting means for subtracting the counted value word from a
maximum address of the dynamic memory to generate a subtracted
value word of N bits; and first selecting means for selectively
outputting to the dynamic memory one of the subtracted value word
and the counted value word in response to a first select signal
used to control the first selecting means.
11. The apparatus of claim 10, further comprising second selecting
means for selectively outputting to the dynamic memory one of the
row and column addresses generated from the first selecting means,
in response to a second select signal.
12. The apparatus of claim 10, wherein, when the column address of
the dynamic memory is to be generated, the N-bit binary up counter
outputs the MSB portion of the counted value word as the row
address and the LSB portion of the counted value word as the column
address.
13. The apparatus of claim 10, wherein, when the row address of the
dynamic memory is to be generated, the N-bit binary up counter
outputs the LSB portion of the N-bit counted value word as the row
address and the MSB portion of the N-bit counted value word as the
column address.
14. An apparatus for generating addresses in a dynamic memory
testing circuit for testing a dynamic memory which does not use
some of its most significant addresses, comprising: an N-bit binary
down counter for performing a down counting operation and for
generating an N-bit counted value word as an address used by the
dynamic memory, wherein N is the number of bits obtained by adding
the number of bits of the row addresses of the dynamic memory to
the number of bits of the column addresses of the dynamic memory;
subtracting means for subtracting the counted value word from a
minimum address of the dynamic memory to generate a subtracted
value word of N bits; and first selecting means for selectively
outputting to the dynamic memory one of the subtracted value word
and the counted value word in response to a first select signal
used to control the first selecting means.
15. The apparatus of claim 14, further comprising second selecting
means for selectively outputting to the dynamic memory one of the
row and column addresses generated from the first selecting means,
in response to a second select signal.
16. The apparatus of claim 14, wherein, when the column address of
the dynamic memory is to be generated, the N-bit binary down
counter outputs the MSB portion of the N-bit counted value word as
the row address and the LSB portion of the N-bit counted value word
as the column address.
17. The apparatus of claim 14, wherein, when the row address of the
dynamic memory is to be generated, the N-bit binary down counter
outputs the LSB portion of the N-bit counted value word as the row
address and the MSB portion of the N-bit counted value word as the
column address.
18. An apparatus for generating memory addresses in a dynamic
memory testing circuit for testing a dynamic memory which does not
use some of its middle addresses among all of its available
addresses, said middle addresses being between a minimum address
and a maximum address used by said dynamic memory, said apparatus
comprising: an N-bit binary up counter for performing an up
counting operation and for generating an N-bit counted value word
as an address used by the dynamic memory, wherein N is the number
of bits obtained by adding the number of bits of the row addresses
of the dynamic memory to the number of bits of the column addresses
of the dynamic memory; inverting means for inverting the MSB
portion of the counted value word to generate a MSB inverted value
word; subtracting means for subtracting the LSB portion of the
counted value word from the LSB portion of the maximum address used
in the dynamic memory to generate a LSB subtracted value word; bit
combining means for combining the MSB inverted value word with the
LSB subtracted value word to generate a combined word; and first
selecting means for selectively outputting to the dynamic memory
one of the combined word and the N-bit counted value word in
response to a first select signal used to control the first
selecting means.
19. The apparatus of claim 18, further comprising second selecting
means for selectively outputting to the dynamic memory one of the
row and column addresses generated from the first selecting means,
in response to a second select signal.
20. The apparatus of claim 18, wherein, when the column address of
the dynamic memory is to be generated, the N-bit binary up counter
outputs the MSB portion of the N-bit counted value word as the row
address and the LSB portion of the N-bit counted value word as the
column address.
21. The apparatus of claim 18, wherein, when the row address of the
dynamic memory is to be generated, the N-bit binary up counter
outputs the LSB portion of the N-bit counted value word as the row
address and the MSB portion of the N-bit counted value word as the
column address.
22. An apparatus for generating memory addresses in a dynamic
memory testing circuit for testing a dynamic memory which does not
use some of its middle addresses among all of its available
addresses, said middle addresses being between a minimum address
and a maximum address used by said dynamic memory, said apparatus
comprising: an N-bit binary down counter for performing a down
counting operation and for generating an N-bit counted value word
as an address used by the dynamic memory, wherein N is the number
of bits obtained by adding the number of bits of the row addresses
of the dynamic memory to the number of bits of the column addresses
of the dynamic memory; inverting means for inverting the MSB
portion of the counted value word to generate a MSB inverted value
word; subtracting means for subtracting the LSB portion of the
counted value word from the LSB portion of the minimum address used
in the dynamic memory to generate a LSB subtracted value word; bit
combining means for combining the MSB inverted value word with the
LSB subtracted value word to generate a combined word; and first
selecting means for selectively outputting to the dynamic memory
one of the combined word and the N-bit counted value word in
response to a first select signal used to control the first
selecting means.
23. The apparatus of claim 22, further comprising second selecting
means for selectively outputting to the dynamic memory one of the
row and column addresses generated from the first selecting means,
in response to a second select signal.
24. The apparatus of claim 22, wherein, when the column address of
the dynamic memory is to be generated, the N-bit binary down
counter outputs the MSB portion of the N-bit counted value word as
the row address and the LSB portion of the N-bit counted value word
as the column address.
25. The apparatus of claim 22, wherein, when the row address of the
dynamic memory is to be generated, the N-bit binary down counter
outputs the LSB portion of the N-bit counted value word as the row
address and the MSB portion of the N-bit counted value word as the
column address.
26. A method for generating addresses in a dynamic memory testing
circuit for testing a dynamic memory which uses all available
addresses of the dynamic memory, comprising: (a) obtaining N-bit
addresses used by the dynamic memory by performing an up counting
operation, wherein N is the number of bits obtained by adding the
number of bits of the row addresses of the dynamic memory to the
number of bits of the column addresses of the dynamic memory; (b)
inverting the counted N-bit addresses to form inverted addresses;
(c) determining whether the dynamic memory is to be tested by
increasing or decreasing addresses; (d) providing the N-bit
addresses as addresses for testing the dynamic memory where the
dynamic memory is tested by increasing the addresses; and (e)
providing the inverted N-bit addresses as addresses for testing the
dynamic where the dynamic memory is to be tested by decreasing the
addresses.
27. The method of claim 26, further comprising: following step (e),
determining whether a row address or a column address is to be
generated; selecting the row address from the addresses for testing
the dynamic memory when the row address is to be generated; and
selecting the column address from the addresses for testing the
dynamic memory when the column address is to be generated.
28. A method for generating addresses in a dynamic memory testing
circuit for testing a dynamic memory which uses all available
addresses of the dynamic memory, comprising: (a) performing a down
counting operation to generate N-bit counted addresses used by the
dynamic memory, wherein N is the number of bits obtained by adding
the number of bits of the row addresses of the dynamic memory to
the number of the column addresses of the dynamic memory; (b)
inverting the counted N-bit addresses to generate inverted N-bit
addresses; (c) determining whether the dynamic memory is to be
tested by increasing or decreasing addresses; (d) providing the
inverted N-bit addresses as addresses for testing the dynamic
memory in the case of testing the dynamic memory by increasing the
addresses; and (e) providing the N-bit counted addresses as
addresses for testing the dynamic memory in the case of testing the
dynamic memory by decreasing the addresses.
29. The method of claim 28, wherein the method for generating
addresses further comprises: following step (e), determining
whether a row address or a column address is to be generated;
selecting the row address from addresses for testing the dynamic
memory when the row address is to be generated; and selecting the
column address from addresses for testing the dynamic memory when
the column address is to be generated.
30. A method for generating memory addresses in a dynamic memory
testing circuit for testing the dynamic memory which does not use
some of its most significant addresses, comprising: (a) obtaining
an N-bit address used by the dynamic memory by performing an up
counting operation, wherein N is the number of bits obtained by
adding the number of bits of the row addresses of the dynamic
memory to the number of bits of the column addresses of the dynamic
memory; (b) subtracting the N-bit address from a maximum address of
the dynamic memory to generate a subtracted value word of N-bits;
(c) determining whether the dynamic memory is to be tested by
increasing or decreasing the addresses; (d) providing the N-bit
address as an address for testing the dynamic memory when the
dynamic memory is to be tested by increasing the addresses; and (e)
providing the subtracted value word as an address for testing the
dynamic memory when the dynamic memory is to be tested by
decreasing the addresses.
31. The method of claim 30, further comprising: following step (e),
determining whether the row address or the column address is to be
generated; selecting the row address from the addresses for testing
the dynamic memory when the column address is to be generated; and
selecting the column address from the addresses for testing the
dynamic memory when the column address is to be generated.
32. A method for generating memory addresses in a dynamic memory
testing circuit for testing the dynamic memory which does not use
some of its most significant addresses, comprising: (a) obtaining
an N-bit address used by the dynamic memory by performing a down
counting operation, wherein N is the number of bits obtained by
adding the number of bits of the row addresses of the dynamic
memory to the number of bits of the column addresses of the dynamic
memory; (b) subtracting the N-bit address from a minimum address of
the dynamic memory to generate a subtracted value word of N-bits;
(c) determining whether the dynamic memory is to be tested by
increasing or decreasing the addresses; (d) providing the
subtracted value word as an address for testing the dynamic memory
when the dynamic memory is tested by increasing the addresses; and
(e) providing the N-bit address as an address for testing the
dynamic memory when the dynamic memory is tested by decreasing the
addresses.
33. The method of claim 32, further comprising: following step (e),
determining whether the row address or the column address is to be
generated; selecting the row address from the addresses for testing
the dynamic memory when the row address is to be generated; and
selecting the column address from the addresses for testing the
dynamic memory when the column address is to be generated.
34. A method for generating memory addresses in a dynamic memory
testing circuit for testing a dynamic memory which does not use
some of its middle addresses among all of its available addresses,
said middle addresses being between a minimum address and a maximum
address of said dynamic memory, said method comprising: (a)
obtaining an N-bit address used by the dynamic memory by performing
an up counting operation, wherein N is the number of bits obtained
by adding the number of bits of the row addresses of the dynamic
memory to the number of bits of the column addresses of the dynamic
memory; (b) inverting the MSB portion of the N-bit address to
generate a MSB inverted word; (c) subtracting the LSB portion of
the N-bit address from the LSB portion of the maximum address used
by the dynamic memory to generate a LSB subtracted value word; (d)
combining the MSB inverted word with the LSB subtracted word to
generate a combined word; (e) determining whether the dynamic
memory is to be tested by increasing or decreasing addresses; (f)
providing the N-bit address as an address for testing the dynamic
memory when the dynamic memory is tested by increasing the
addresses; and (g) providing the combined word as an address for
testing the dynamic memory when the dynamic memory is tested by
decreasing the address.
35. The method of claim 34, further comprising: following step (g),
determining whether the row address or the column address is to be
generated; selecting the row address from addresses for testing the
dynamic memory when the row address is to be generated; and
selecting the column address from addresses for testing the dynamic
memory when the column address is to be generated.
36. A method for generating memory addresses in a dynamic memory
testing circuit for testing a dynamic memory which does not use
some of its middle addresses among all its available addresses,
said middle addresses being between a minimum address and a maximum
address of said dynamic memory, said method comprising: (a)
obtaining an N-bit address used by the dynamic memory by performing
a down counting operation, wherein N is the number of bits obtained
by adding the number of bits of the row addresses of the dynamic
memory to the number of bits of the column addresses of the dynamic
memory; (b) inverting the MSB portion of the N-bit address to
generate a MSB inverted word; (c) subtracting the LSB portion of
the N-bit address from the LSB portion of the minimum address used
in the dynamic memory to generate a LSB subtracted value word; (d)
combining the MSB inverted word with the LSB subtracted word to
generate a combined word; (e) determining whether the dynamic
memory is to be tested by increasing or decreasing addresses; (f)
providing the combined word as an address for testing the dynamic
memory, when the dynamic memory is tested by increasing the
addresses; and (g) providing the N-bit address as an address for
testing the dynamic memory when the dynamic memory is tested by
decreasing the addresses.
37. The method of claim 36, further comprising: following step (g),
determining whether the row address or the column address is to be
generated; selecting the row address from addresses for testing the
dynamic memory when the row address is to be generated; and
selecting the column address from addresses for testing the dynamic
memory when the column address is to be generated.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to testing a memory and more
particularly to an address generator of a built-in self test
circuit for testing a memory such as a dynamic random access memory
(DRAM) and an address generating method thereof.
[0003] 2. Description of the Related Art
[0004] A built-in self test (BIST) circuit can typically be used as
part of a memory testing circuit to test a memory. In a DRAM BIST,
the memory to be tested is a DRAM. An address generator in such a
BIST circuit is used to generate addresses of the memory to access
memory locations to be tested and therefore typically performs many
up and down counting operations according to the method being used
to test the memory. In the case of an address generator which uses
an up/down counter, the size of the circuitry becomes an important
consideration since such counters can be very large. Accordingly,
it is hard to optimize the area of such devices.
[0005] In the case of testing a DRAM which does not use all its
available addresses, if the addresses are generated using an
up/down counter, various additional circuits are necessary to
accomodate the skipping of addresses. This additional circuitry
adds to the difficulty in optimizing the area of the BIST circuit
including the address generator. Also, in the case that the DRAM
does not use all the available addresses, if the address generator
is designed using the up/down counter or separate up and down
counters, respective counters for counting the column address and
the row address of the DRAM are produced. This also greatly
increases circuit size and complexity. Also, the hardware of the
BIST controlling portion for controlling the up/down counter or the
up and down counters can be very large and complex.
SUMMARY OF THE INVENTION
[0006] It is a first object of the present invention to provide an
address generator of a dynamic memory testing circuit, for
generating addresses for testing a dynamic memory which uses all
the available addresses.
[0007] It is a second object of the present invention to provide an
address generator of a dynamic memory testing circuit, for
generating addresses for testing a dynamic memory which does not
use some of the addresses of the memory, and more particularly, a
dynamic memory which does not use its most significant addresses
among all the available addresses.
[0008] It is a third object of the present invention to provide an
address generator of a dynamic memory testing circuit, for
generating addresses for testing a dynamic memory which does not
use some of the middle addresses among all the available
addresses.
[0009] It is a fourth object of the present invention to provide an
address generating method of a dynamic memory testing circuit, for
generating addresses for testing a dynamic memory which uses all
its available addresses.
[0010] It is a fifth object of the present invention to provide an
address generating method of a dynamic memory testing circuit, for
generating addresses for testing a dynamic memory which does not
use some of the addresses of the memory, and more particularly, a
dynamic memory which does not use its most significant addresses
among all the available addresses.
[0011] It is a sixth object of the present invention to provide an
address generating method of a dynamic memory testing circuit,
simply generating addresses for testing a dynamic memory which does
not use some of the middle addresses among all the available
addresses.
[0012] To achieve these and other objects, there is provided an
address generator of a dynamic memory testing circuit for testing
the dynamic memory which uses all the available addresses,
comprising an N-bit binary up counter where N is the total of the
number of memory row address bits and the number of column address
bits, an inverting means, and a first selecting means. The N-bit
binary up counter performs an up counting operation and outputs the
counted value of N bits as an address used by the dynamic memory.
The inverting means inverts the counted value of N bits and outputs
the inverted value. The first selecting means selectively outputs
either the output of the inverting means or the counted values of N
bits to the dynamic memory, depending on the state of a select
signal generated corresponding to a step of the process of testing
the dynamic memory.
[0013] In accordance with another aspect of the invention, there is
provided an address generator of a dynamic memory testing circuit
for testing a dynamic memory which does not use some of the most
significant addresses among all the available addresses, comprising
an N-bit binary up counter where N is the total of the number of
memory row address bits and the number of column address bits, a
subtracting means, and a first selecting means. The N-bit binary up
counter performs an up counting and outputs the counted value of N
bits as an address used by the dynamic memory. The subtracting
means subtracts the counted value of N bits from the maximum
address and outputs the subtracted value of N bits. The first
selecting means selectively outputs either the subtracted value of
N bits or the counted values of N bits to the dynamic memory
depending on the state of a select signal generated corresponding
to a step of the process of testing the dynamic memory.
[0014] In accordance with another aspect of the invention, there is
provided an address generator of a dynamic memory testing circuit
for testing the dynamic memory which does not use some of the
middle addresses among all the available addresses, comprising an
N-bit binary up counter where N is the total of the number of
memory row address bits and the number of column address bits, an
inverting means, a subtracting means, a bit combining means, and a
first selecting means. The N-bit binary up counter performs an up
counting operation and outputs the counted value of N bits as an
address used by the dynamic memory. The inverting means inverts the
most significant bit (MSB) portion of the counted value of N bits
and outputs the inverted value. The subtracting means subtracts the
least significant bit (LSB) portion among the counted values of N
bits from the LSB portion of the maximum address used in the
dynamic memory and outputs the result. The bit combining means
combines the output of the inverting means with the output of the
subtracting means. The first selecting means selectively outputs to
the dynamic memory either the output of the bit combining means or
the counted values of N bits, depending on the state of a first
select signal generated corresponding to a step of the process of
testing the dynamic memory.
[0015] In accordance with another aspect of the invention, there is
provided a method for generating addresses of a dynamic memory
testing circuit for testing a dynamic memory which uses all the
available addresses, comprising the steps of (a) obtaining
addresses of N bits used by the dynamic memory by performing an up
counting operation, the number N being the total of the number of
memory row address bits and the number of column address bits, (b)
inverting the counted N-bit address, (c) determining whether the
dynamic memory is to be tested by increasing or decreasing
addresses, (d) generating the N-bit address as addresses for
testing the dynamic memory in the case of testing the dynamic
memory by increasing the addresses, and (e) generating inverted
N-bit addresses as addresses for testing the dynamic memory in the
case of testing the dynamic memory by decreasing the addresses.
[0016] In accordance with another aspect of the invention, there is
provided a method for generating addresses of a dynamic memory
testing circuit for testing the dynamic memory which does not use
some of most significant addresses among all the available
addresses, comprising the steps of (a) obtaining N-bit addresses
used by the dynamic memory by performing an up counting operation,
the number N being the total of the number of memory row address
bits and the number of column address bits, (b) subtracting the
N-bit address from the maximum address, and (c) determining whether
the dynamic memory is to be tested by increasing or decreasing the
addresses, (d) generating the N-bit addresses for testing the
dynamic memory when the dynamic memory is to be tested by
increasing the addresses, and (e) generating the subtracted result
as an address for testing the dynamic memory when the dynamic
memory is to be tested by decreasing the addresses.
[0017] In accordance with another aspect of the invention, there is
provided a method for generating addresses of a dynamic memory
testing circuit for testing the dynamic memory which does not use
some of the middle addresses among all the available addresses,
comprising the steps of (a) obtaining the N-bit addresses used by
the dynamic memory by performing an up counting operation, the
number N being the total of the number of memory row address bits
and the number of column address bits, (b) inverting the MSB
portion in the N-bit address, (c) subtracting the LSB portion of
the N-bit address from the LSB portion of the maximum address used
by the dynamic memory, (d) combining the inverted result with the
subtracted result, (e) determining whether the dynamic memory is to
be tested by increasing or decreasing the addresses, (f) generating
the N-bit address as an address for testing the dynamic memory in
the case of testing the dynamic memory by increasing the addresses,
and (g) generating the combined result as an address for testing
the dynamic memory in the case of testing the dynamic memory by
decreasing the addresses.
[0018] In each of these aspects of the invention, a down counter
can be used instead of an up counter. In either case, the address
generating apparatus and method of the invention provide memory
testing addresses in either an ascending or descending order,
depending on the status of control signals used to set the mode of
operation as desired.
[0019] The invention can operate to generate testing addresses in
the desired order and using only the selected portions of addresses
using only a single counter, either an up counter or a down
counter. Because only a single counter is used, significant savings
in counter circuit size and complexity can be realized. In
addition, because only a single counter can be used, the associated
controlling circuitry is also smaller and less complex and,
therefore, less costly to develop and manufacture.
BRIEF DESCRIPTION OF THE DRAWING(S)
[0020] The above objects and advantages of the present invention
will become more apparent from the following detailed description
of preferred embodiments thereof with reference to the attached
drawings in which:
[0021] FIG. 1 is a schematic block diagram of a DRAM BIST circuit
in accordance with the invention;
[0022] FIG. 2 is a schematic circuit diagram of one embodiment of
an address generator according to the present invention;
[0023] FIG. 3 is a flowchart describing a method for generating
addresses according to the present invention which can be performed
in the address generator shown in FIG. 2;
[0024] FIG. 4 is a schematic circuit diagram of an alternative
embodiment of an address generator according to the present
invention;
[0025] FIG. 5 is a flowchart describing a method for generating
addresses according to the present invention which can be performed
in the address generator shown in FIG. 4.
[0026] FIG. 6 is a circuit diagram of another alternative
embodiment of an address generator according to the present
invention; and
[0027] FIG. 7 is a flowchart describing a method for generating
addresses according to the present invention which can be performed
in the address generator shown in FIG. 6.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0028] Hereinafter, the configuration and operation of a DRAM BIST
circuit which uses an address generator according to the present
invention and an address generating method thereof will be
described with reference to the attached drawing s.
[0029] Referring to FIG. 1, a general DRAM BIST circuit includes a
refresh counter 10, a stage counter 12, a data generating portion
14, an address generating portion 16, a comparing portion 18, and a
BIST controlling portion 22. The refresh counter 10 determines a
refresh timing of a DRAM 20. The stage counter 12 counts the
respective steps of a memory testing method which proceeds by
increasing or decreasing the memory addresses. The counter 12
outputs the counted result to the address generating portion 16
through the BIST controlling portion 22.
[0030] The data generating portion 14 generates data to be written
in the DRAM 20 and outputs reference data to the comparing portion
18 through the BIST controlling portion 22. The BIST controlling
portion 22 controls the refresh counter 10, the stage counter 12,
the data generating portion 14, and the comparing portion 18 in
order to test the DRAM 20. The reference data is used for
discriminating whether the data read from the DRAM 20 is correct.
The comparing portion 18 compares data read from the DRAM 20 with
the reference data output from the BIST controlling portion 22 and
outputs the compared result to the BIST controlling portion 22. The
BIST controlling portion 22 determines from the compared result
whether errors exist in data stored in the DRAM 20. The address
generating portion 16 performs an up/down counting operation in
response to a control signal output from the BIST controlling
portion 22 and outputs the generated addresses to the DRAM 20 and
the BIST controlling portion 22. Using the address generated by the
address generating portion 16, the contents of the addressed DRAM
location are read for comparison with the associated reference
data.
[0031] Hereinafter, the configuration and operation of the address
generator according to the present invention corresponding to the
address generating portion 16 shown in FIG. 1 and an address
generating method performed in the address generator will be
described with reference to the attached drawings.
[0032] An address generator 16A for generating addresses for
testing a dynamic memory which uses all the available addresses and
an address generating method thereof will now be described. FIG. 2
is a schematic circuit diagram of one embodiment of an address
generator 16A according to the present invention, which includes an
up (or down) counter 40, an inverter 42, a first multiplexer 44
corresponding to a first selecting portion, and a second
multiplexer 46 corresponding to a second selecting portion.
[0033] FIG. 3 is a flowchart for describing one embodiment of an
address generating method according to the present invention, which
can be performed in the address generator 16A shown in FIG. 2. In
the embodiment of FIG. 3, the method includes the steps of
obtaining and inverting N-bit addresses by performing up and down
counting operations (steps 60 and 62) and generating tested
addresses corresponding to the memory testing method (steps 64
through 68).
[0034] Referring to FIGS. 2 and 3, the up (or down) counter 40,
which is an N-bit binary counter, performs the up (or down)
counting and outputs the counted value as an N-bit address for
testing a dynamic memory (not shown) (step 60). N is the number of
bits obtained by adding the number of bits of the column and row
addresses of the dynamic memory.
[0035] In one embodiment, the LSB portion of the counter word is
used to address the memory columns and the MSB portion is used to
address the rows. In this embodiment, in the case in which the
dynamic memory is tested by first running or counting through
column addresses and then running through the row addresses, the up
(or down) counter 40 up (or down) counts the addresses constructed
by the least significant bit (LSB) portion set as the column
addresses and the most significant bit (MSB) portion set as the row
addresses. However, in the case of testing the dynamic memory by
first increasing the row addresses and next increasing the column
addresses, the up (or down) counter 40 counts the addresses
constructed by the MSB portion set as the column addresses and the
LSB portion set as the row addresses.
[0036] After the step 60, the inverter 42 receives and inverts the
output of the up (or down) counter 40 for the down (or up) counting
of the addresses. The inverter 42 transfers the inverted N-bit
address to the first multiplexer (MUX) 44 (step 62). Accordingly,
addresses generated in an inverse order to the order produced by
the up (or down) counter 40 can be obtained. After step 62, the
BIST controlling portion 22 shown in FIG. 1 determines whether the
dynamic memory is to be tested by decreasing the addresses or
increasing the addresses, which is determined by the current stage
value input from the stage counter 12 in order to select the
address to be input to the dynamic memory (not shown) (step
64).
[0037] When the up (or down) counter 40 is an up counter and the
dynamic memory is to be tested decreasing the addresses, the BIST
controlling portion 22 sets the {overscore (UP)}/DOWN signal to a
logic high or "1" value. The first MUX 44 outputs, in response to
the high {overscore (UP)}/DOWN signal, the N-bit address inverted
in the inverter 42 as a testing address for testing the dynamic
memory (step 66). However, in the case of testing the dynamic
memory increasing the addresses, the BIST controlling portion 22
sets the {overscore (UP)}/DOWN signal to a logic low or "0" value.
The first MUX 44 outputs, in response to the logic low {overscore
(UP)}/DOWN value, the N-bit address output from the counter 40 as
the testing address (step 68).
[0038] Alternatively, in the case that the up (or down) counter 40
is a down counter and the dynamic memory is to be tested decreasing
the addresses, the BIST controlling portion 22 sets the
UP/{overscore (DOWN)} signal to a logic 0. The first MUX 44
outputs, in response to the UP/{overscore (DOWN)} signal at a 0
value, the N-bit address output from counter 40 as the testing
address (step 68). However, in the case of testing the dynamic
memory by increasing the addresses, the BIST controlling portion 22
generates the UP/{overscore (DOWN)} signal at a 1 value. The first
MUX 44 outputs the inverted N-bit address as the testing address in
response to the logic high UP/{overscore (DOWN)} signal (step
66).
[0039] A second MUX 46 receives the testing address selected in the
first MUX 44 and selectively outputs a column address of m bits and
a row address of n bits to the dynamic memory through an output
terminal OUT in response to a {overscore (ROW)}/COLUMN logic signal
which is provided as an output from the BIST controlling portion
22.
[0040] In accordance with another aspect of the invention, an
address generator for testing the dynamic memory which does not use
some of the most significant addresses among all the available
addresses and an address generating method thereof will now be
described in detail. FIG. 4 is a schematic circuit diagram of
another embodiment of an address generator 16B according to the
present invention, which includes an up (or down) counter 80, a
subtracting circuit 82, a first multiplexer 84 corresponding to a
first selecting portion, and a second multiplexer 86 corresponding
to a second selecting portion.
[0041] FIG. 5 is a flowchart for describing one embodiment of an
address generating method according to the present invention, which
can be performed in the address generator 16B shown in FIG. 4. In
the embodiment of FIG. 5, the method includes the steps of
obtaining N-bit addresses by performing the up and down counting
operations (steps 100 and 102) and generating the counted addresses
in accordance with the memory testing method (steps 104 through
108).
[0042] Referring to FIGS. 4 and 5, the up (or down) counter 80,
which is an N-bit binary counter, performs the up (or down)
counting and outputs the counted value as an N-bit address which
can be used in the dynamic memory (not shown) (step 100). In the
case of testing the dynamic memory by first increasing the row
addresses without using some of the column addresses which are
available to the dynamic memory, the up (or down) counter 80 up (or
down) counts the N-bit addresses including the LSB portion of the
addresses set as the row address and the MSB portion set as the
column address to the maximum (or minimum) address. However, in the
case of testing the dynamic memory by first increasing the column
addresses without using some of the row addresses which are
available to the dynamic memory, the up (or down) counter 80 counts
the N-bit address including the MSB portion set as the row address
and the LSB portion set as the column address to the maximum (or
minimum) address.
[0043] After step 100, for down-counting (or up-counting) of
addresses, the subtracting circuit 82 subtracts the N-bit address
counted in the up (or down) counter 80 from the maximum (or
minimum) address input through an input terminal IN and outputs the
subtracted N-bit address to the first multiplexer (MUX) 84 (step
102). Therefore, the addresses generated in an inverse order from
the order of the up (or down) counter 80 is available. After step
102, in order to select an address to be input to the dynamic
memory (not shown), the BIST controlling portion 22 shown in FIG. 1
determines, on the basis of the current stage value input from the
stage counter 12, whether the dynamic memory should be tested by
decreasing or increasing the addresses (step 104).
[0044] When the up (or down) counter 80 is an up counter and the
dynamic memory is to be tested by decreasing the addresses, the
BIST controlling portion 22 generates an {overscore (UP)}/DOWN
signal at a logic high or I value. The first MUX 84 outputs, in
response to the high UP/DOWN signal, the N-bit address subtracted
in the subtracting circuit 82 as the testing address for testing
the dynamic memory (step 108). However, in the case of testing the
dynamic memory by increasing the addresses, the BIST controlling
portion 22 sets {overscore (UP)}/DOWN signal to a logic low or 0
value. The first MUX 84 outputs, in response to the low {overscore
(UP)}/DOWN signal, the N-bit address output from the up (or down)
counter 80 as the testing address (step 106).
[0045] Also, when the up (or down) counter 80 is a down counter and
the dynamic memory is to be tested by decreasing the addresses, the
BIST controlling portion 22 generates an UP/{overscore (DOWN)}
signal at a logic low or 0 level. The first MUX 84 outputs, in
response to the low {overscore (UP)}/DOWN signal, the N-bit address
output from the up (or down) counter 80 as the testing address
(step 106). However, when the dynamic memory is to be tested by
increasing the addresses, the BIST controlling portion 22 sets
UP/{overscore (DOWN)} signal to a logic high or 1 value. The first
MUX 84 outputs, in response to the high {overscore (UP)}/DOWN
signal, the N-bit address subtracted in the subtracting circuit 82
as the testing address (step 108).
[0046] The second MUX 86 receives the testing address selected in
the first MUX 84 and selectively outputs the row address of m bits
and the column address of n bits to the dynamic memory through the
output terminal OUT in response to a {overscore (ROW)}/COLUMN
signal output from the BIST controlling portion 22.
[0047] Hence, in this embodiment of the invention, since some of
the most significant addresses among all the available addresses
are not used in the memory testing, the address generating
circuitry 16B generates addresses referenced to the maximum
available memory address. Therefore, the up (or down) counter 80 of
the address generating circuitry 16B counts to (or from) the
maximum available address.
[0048] In accordance with another aspect of the invention, an
address generator for testing the dynamic memory which does not use
some of the middle addresses among all the available addresses and
an address generating method thereof will now be described. In this
embodiment, some portion of the addresses between the most
significant address and the least significant address, referred to
herein as "middle" addresses, are the only address of the dynamic
memory that are tested in accordance with the invention.
[0049] FIG. 6 is a schematic circuit diagram of another embodiment
of the address generator 16C according to the present invention.
The address generator 16C includes an up (or down) counter 120, an
inverter 122, a subtracting circuit 124, a first multiplexer 126
corresponding to a first selecting portion, and a second
multiplexer 128 corresponding to a second selecting portion.
[0050] FIG. 7 is a flowchart for describing one embodiment of an
address generating method according to the present invention, which
can be performed in the address generator 16C shown in FIG. 6. In
the embodiment of FIG. 7, the method includes the steps of
obtaining N-bit addresses by performing an up (or down) counting
operation (step 140), performing a down (or up) counting operation
(steps 142 through 146), and generating the counted addresses in
accordance with the memory testing method (steps 148 through
152).
[0051] Referring to FIGS. 6 and 7, the up (or down) counter 120,
which is an N-bit binary counter, performs the up (or down)
counting and outputs the counted value as the N-bit address which
can be used in the dynamic memory (not shown) (step 140). In step
140, when the dynamic memory is to be tested by first increasing
the column address without using some of the column addresses which
are available to the dynamic memory, the up (or down) counter 120
counts the N-bit address constructed by the LSB portion set as the
column address and the MSB portion set as the row address. However,
in the case of testing the dynamic memory by first increasing the
row addresses without using some of the row addresses, the up (or
down) counter 120 counts the N-bit addresses constructed by the MSB
side set as the column addresses and the LSB side set as the row
addresses.
[0052] After step 140, the inverter 122 and the subtracter 124
generate addresses in the inverse order (steps 142 through 146).
Namely, the inverter 122 inverts m bits of the MSB side among the
N-bit addresses counted in the counter 120 (step 142). After the
step of 142, the subtracter 124 subtracts n bits of the LSB side of
the N-bit addresses counted in the up (or down) counter 120 from n
bits of the LSB side of the maximum (or minimum) address input
through the input terminal IN (step 144). After the step 144, the
subtracted n bits and the inverted m bits are combined in a node
125. The obtained result is output to the first multiplexer (MUX)
126 as the N-bit addresses (step 146). After the step 146, in order
to select the addresses to be input to the dynamic memory (not
shown), the BIST controlling portion 22 shown in FIG. 1 determines
whether the dynamic memory is to be tested by decreasing or
increasing the addresses, which is determined by the current stage
value input from the stage counter 12 (step 48).
[0053] When the up (or down) counter 120 is an up counter and the
dynamic memory is to be tested by decreasing the addresses, the
BIST controlling portion 22 sets an {overscore (UP)}/DOWN signal at
a logic high or 1 value. The first MUX 126 outputs the combined
N-bit addresses as the testing address for testing the dynamic
memory, in response to the high {overscore (UP)}/DOWN signal (step
152). However, in the case of testing the dynamic memory by
increasing the addresses, the BIST controlling portion 22 sets the
{overscore (UP)}/DOWN signal to a logic low or 0 value. The first
MUX 126 outputs the N-bit addresses output from the up (or down)
counter 120 as the testing address in response to the low
{overscore (UP)}/DOWN signal (step 150).
[0054] Also, when the up (or down) counter 120 is a down counter
and the dynamic memory is to be tested by increasing the addresses,
the BIST controlling portion 22 sets an UP/{overscore (DOWN)}
signal to a logic low or 0 value. The first MUX 126 outputs the
N-bit addresses output from the up(or down) counter 120 as the
testing address, in response to the low UP/{overscore (DOWN)}
signal. However, when the dynamic memory is to be tested by
increasing the addresses, the BIST controlling portion 22 sets the
UP/{overscore (DOWN)} signal to a logic high or 1 value. The first
MUX 126 outputs the inverted N-bit addresses as the testing
address, in response to the high UP/{overscore (DOWN)} signal (step
152).
[0055] The second MUX 128 receives the testing address output from
the first MUX 126 and selectively outputs the row addresses of m
bits and the column addresses of n bits to the dynamic memory
through the output terminal OUT, in response to the {overscore
(ROW)}/COLUMN signal output from the BIST controlling portion
22.
[0056] While this invention has been particularly shown and
described with references to preferred embodiments thereof, it will
be understood by those skilled in the art that various changes in
form and details may be made therein without departing from the
spirit and scope of the invention as defined in the following
claims.
* * * * *