U.S. patent application number 09/797952 was filed with the patent office on 2001-12-06 for semiconductor device and method for producing it.
Invention is credited to Fukunaga, Takeshi, Koyama, Jun, Yamazaki, Shunpei.
Application Number | 20010049163 09/797952 |
Document ID | / |
Family ID | 26552733 |
Filed Date | 2001-12-06 |
United States Patent
Application |
20010049163 |
Kind Code |
A1 |
Yamazaki, Shunpei ; et
al. |
December 6, 2001 |
Semiconductor device and method for producing it
Abstract
Disclosed is a bottom-gate-type semiconductor device comprising
crystalline semiconductor layers, in which the source/drain regions
each have a laminate structure comprising a first conductive layer
(n+ layer), a second conductive layer (n.sup.- layer) of which the
resistance is higher than that of the first conductive layer, and
an intrinsic or substantially intrinsic semiconductor layer
(i-layer). In this, the n.sup.-layer functions as an LDD region,
and the i-layer functions as an in-plane offset region. The
semiconductor device has high reliability and high reproducibility,
and is produced in a simple process favorable to
mass-production.
Inventors: |
Yamazaki, Shunpei; (Tokyo,
JP) ; Koyama, Jun; (Kanagawa, JP) ; Fukunaga,
Takeshi; (Kanagawa, JP) |
Correspondence
Address: |
NIXON PEABODY, LLP
8180 GREENSBORO DRIVE
SUITE 800
MCLEAN
VA
22102
US
|
Family ID: |
26552733 |
Appl. No.: |
09/797952 |
Filed: |
March 5, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09797952 |
Mar 5, 2001 |
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09476378 |
Jan 3, 2000 |
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6204535 |
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09476378 |
Jan 3, 2000 |
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09157938 |
Sep 22, 1998 |
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6013930 |
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Current U.S.
Class: |
438/158 ;
257/E21.414; 257/E29.278; 257/E29.279; 438/151; 438/166 |
Current CPC
Class: |
H01L 29/78621 20130101;
G02F 1/13454 20130101; H01L 27/1274 20130101; H01L 29/66765
20130101; Y10S 438/907 20130101; H01L 27/1214 20130101; H01L
29/78624 20130101; H01L 27/1222 20130101 |
Class at
Publication: |
438/158 ;
438/166; 438/151 |
International
Class: |
H01L 021/00; H01L
021/84 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 24, 1997 |
JP |
9-278124 |
Sep 30, 1997 |
JP |
9-282565 |
Claims
In the claims:
1. A method for producing a semiconductor device, comprising the
steps:
2. forming a gate electrode, a gate-insulating layer, and an
amorphous semiconductor film on an insulating surface;
3. exposing the amorphous semiconductor film to laser beams or to
intense light equivalent to laser beams to thereby convert it into
a semiconductor film having a crystalline structure;
4. adding an impurity selected from Group 15 only or from Group 13
and Group 15 to the semiconductor film having a crystalline
structure to form conductive layers;
5. forming a source electrode and a drain electrode on the
conductive layers, and
6. etching the semiconductor film having a crystalline structure
via the source electrode and the drain electrode both acting as
masks for the film to thereby form a channel-forming region.
7. A method according to claim 1, further comprising at least once
a laser annealing step of processing the semiconductor film having
a crystalline structure .
8. A method according to claim 1, wherein the impurity selected
from Group 15 is phosphorus, and that from Group 13 and Group 15 is
boron and phosphorus.
9. A method according to claim 1, wherein the impurity addition is
performed through ion implantation or ion doping.
10. A method according to claim 1, further comprising a step of
performing heat treatment through lamp annealing.
11. A method according to claim 1, wherein at least said gate
insulating film and said amorphous semiconductor film are formed
continuously.
12. A method according to claim 6, wherein the continuous forming
steps are performed in a multi-chamber.
13. A method according to claim 6, wherein the continuous forming
steps are performed in a single chamber.
14. A method according to claim 1, wherein the semiconductor device
is a display device.
15. A method according to claim 1, wherein the semiconductor device
is an electronic instrument selected from the group consisting of a
video camera, a still camera, a projector, a projection TV, a
head-mount display, a car navigation, a personal computer, a mobile
computer, and a portable telephone.
16. A method for producing a semiconductor device, comprising the
steps of:
17. forming a gate electrode, a gate-insulating layer, and an
amorphous semiconductor film on an insulating surface;
18. exposing the amorphous semiconductor film to laser beams or to
intense light equivalent to laser beams to thereby convert it into
a semiconductor film having a crystalline structure;
19. adding an impurity selected from Group 15 only or from Group 13
and Group 15 to the semiconductor film having a crystalline
structure to form conductive layers;
20. forming a source electrode and a drain electrode on the
conductive layers;
21. etching the semiconductor film having a crystalline structure
via the source electrode and the drain electrode both acting as
masks for the film to thereby form a channel-forming region;
and
22. adding an impurity for threshold voltage control to the
semiconductor film via the source electrode and the drain electrode
both acting as masks for the film.
23. A method according to claim 11, further comprising at least
once a laser annealing step of processing the semiconductor film
having a crystalline structure.
24. A method according to claim 11, wherein the impurity selected
from Group 15 is phosphorus, and that from Group 13 and Group 15 is
boron and phosphorus.
25. A method according to claim 11, wherein the impurity addition
is performed through ion implantation or ion doping.
26. A method according to claim 11, further comprising a step of
performing heat treatment through lamp annealing.
27. A method according to claim 11, wherein at least said gate
insulating film and said amorphous semiconductor film are formed
continuously.
28. A method according to claim 16, wherein the continuous forming
steps are performed in a multi-chamber.
29. A method according to claim 16, wherein the continuous forming
steps are performed in a single chamber.
30. A method according to claim 11, wherein the semiconductor
device is a display device.
31. A method according to claim 11, wherein the semiconductor
device is an electronic instrument selected from the group
consisting of a video camera, a still camera, a projector, a
projection TV, a head-mount display, a car navigation, a personal
computer, a mobile computer, and a portable telephone.
32. A method for producing a semiconductor device, comprising the
steps of:
33. forming a gate electrode, a gate-insulating layer, and an
amorphous semiconductor film on an insulating surface,
34. exposing the amorphous semiconductor film to laser beams or to
intense light of which the intensity is equivalent to that of laser
beams, to thereby crystallize the film into a semiconductor film
having a crystalline structure,
35. adding an impurity selected from Group 13 and/or Group 15 to
the semiconductor film having a crystalline structure through ion
implantation or ion doping, to thereby form first and second
conductive layers containing the impurity,
36. exposing the conductive layers to laser beams or to intense
light of which the intensity is equivalent to that of laser beams,
to thereby activate the impurity,
37. forming a source electrode and a drain electrode on the
conductive layers, and
38. etching the semiconductor film having a crystalline structure
via the source electrode and the drain electrode both acting as
masks for the film to thereby form a channel-forming region,
39. wherein thicknesses of the first and second conductive layers
are controlled by the concentration profile of the impurity.
40. A method according to claim 21, wherein the impurity selected
from Group 13 is boron, indium or gallium, and that from Group 15
is phosphorus, arsenic or antimony.
41. A method according to claim 21, wherein at least said gate
insulating film and said amorphous semiconductor film are formed
continuously.
42. A method according to claim 23, wherein the continuous forming
steps are performed in a multi-chamber.
43. A method according to claim 23, wherein the continuous forming
steps are performed in a single chamber.
44. A method according to claim 21, wherein the semiconductor
device is a display device.
45. A method according to claim 21, wherein the semiconductor
device is a n electronic instrument selected from the group
consisting of a video camera, a still camera, a projector, a
projection TV, a head-mount display, a car navigation, a personal
computer, a mobile computer, and a portable telephone.
46. A method for producing a semiconductor device, comprising the
steps of:
47. forming a gate electrode, a gate-insulating layer, and an
amorphous semiconductor film on a substrate having an insulating
surface,
48. exposing the amorphous semiconductor film to laser beams or to
intense light of which the intensity is equivalent to that of laser
beams, to thereby crystallize the film into a semiconductor film
having a crystalline structure,
49. adding an impurity selected from Group 13 and/or Group 15 to
the semiconductor film having a crystalline structure through ion
implantation or ion doping, to thereby form first and second
conductive layers containing the impurity,
50. exposing the conductive layers to laser beams or to intense
light of which the intensity is equivalent to that of laser beams,
to thereby activate the impurity,
51. forming a source electrode and a drain electrode on the
conductive layers,
52. etching the semiconductor film having a crystalline structure
via the source electrode and the drain electrode both acting as
masks for the film to thereby form a channel-forming region,
and
53. adding to the film an impurity for threshold voltage control,
via the source electrode and the drain electrode both acting as
masks for the film,
54. wherein thicknesses of the first and second conductive layers
are controlled by the concentration profile of the impurity.
55. A method according to claim 28, wherein the impurity selected
from Group 13 is boron, indium or gallium, and that from Group 15
is phosphorus, arsenic or antimony.
56. A method according to claim 28, wherein at least said gate
insulating film and said amorphous semiconductor film are formed
continuously.
57. A method according to claim 30, wherein the continuous forming
steps are performed in a multi-chamber.
58. A method according to claim 30, wherein the continuous forming
steps are performed in a single chamber.
59. A method according to claim 28, wherein the semiconductor
device is a display device.
60. A method according to claim 28, wherein the semiconductor
device is an electronic instrument selected from the group
consisting of a video camera, a still camera, a projector, a
projection TV, a head-mount display, a car navigation, personal
computer, a mobile computer, and a portable telephone.
Description
[0001] The present invention relates to a semiconductor device that
comprises thin semiconductor films having a crystalline structure,
and to a method for producing it. In particular, it relates to the
constitution of thin film transistors (hereinafter referred to as
TFT) having an inverse stagger structure. It also relates to the
constitution of semiconductor circuits, electro-optical devices and
electronic instruments having those TFT.
[0002] The terminology "semiconductor device" referred to herein is
directed to any and every device that functions on the basis of
semiconductor characteristics; and TFT, semiconductor circuits,
electro-optical devices and electronic instruments referred to
herein is all within the category of that terminology,
semiconductor device.
BACKGROUND OF THE INVENTION
[0003] TFT have heretofore been being used as switching elements in
active matrix-type liquid crystal devices (hereinafter referred to
as AMLCD). At present, devices with TFT circuits that comprise
active layers of amorphous silicon films have a high market share.
In particular, inverse stagger structures capable of being produced
in simple processes are much employed for constructing TFT.
[0004] With recent developments in high-quality AMLCD, however, TFT
are being required to have much better operating characteristics
(especially for high operating speed). In such situations,
amorphous silicon TFT are often unsatisfactory as their operating
speed is not high, and high-quality devices comprising amorphous
silicon films are difficult to produce.
[0005] Accordingly, polysilicon TFT have become much highlighted in
place of amorphous silicon TFT, and TFT comprising polysilicon
films as the active layers are being actively studied and developed
in the art. At present, some polysilicon TFT devices are on the
market.
[0006] Many reports have already been disclosed, relating to
inverse stagger-type TFT structures comprising active layers of
polysilicon films. For example, referred to is a report of
"Fabrication of Low-Temperature Bottom-Gate Poly-Si TFTs on
Large-Area Substrate by Linear-Beam Excimer Laser Crystallization
and Ion Doping Method: H. Hayashi, et al., IEDM 95, pp. 829-832,
1995".
[0007] In that report, they illustrated one typical example (FIG.
4) of inverse stagger structures comprising polysilicon films.
However, inverse stagger structures of that type (that is,
so-called channel-stop-type ones) have various problems.
[0008] First, in those structures, the active layers having an
overall thickness of 50 nm or so are extremely thin. Therefore, in
those, impact ionization at the junction of the channel-forming
region and the drain region is occurred, whereby the structures are
significantly deteriorated due to hot carrier implantation. For
these reasons, a large LDD region (light doped drain region) must
be formed in those structures.
[0009] In this connection, the most critical problem is how to
control the LDD region. The LDD region requires extremely delicate
control of the impurity concentration therein and the length of
itself. In particular, the length control of the region is
problematic. At present, the length of the LDD region is defined by
mask patterning. In fine TFT, however, any minor patterning error
in masking the LDD region will produce significant differences in
TFT characteristics.
[0010] Another serious problem is that the sheet resistivity in the
LDD region significantly varies depending on the variation in the
thickness of the active layers. Moreover, the variation in the
taper angle of the gate electrodes often causes the variation in
the function of the LDD region.
[0011] In addition, the LDD region requires patterning, which
directly complicates the production process while lowering the
throughput. It is presumed that the production of the inverse
stagger structure described in the report noted above requires at
least 6 masks (up to the step of forming the source/drain
electrodes).
[0012] As mentioned above, the channel-stop-type inverse stagger
structure indispensably requires the transverse in-plane LDD region
to be formed at the both sides of the channel-forming region, in
which, however, a reproducible LDD region is extremely difficult to
form.
SUMMARY OF THE INVENTION
[0013] The subject matter of the present invention is to provide a
technique for producing highly-reliable and highly-reproducible
semiconductor devices in an extremely simple process applicable to
mass-production.
[0014] One aspect of the invention is a semiconductor device having
a semiconductor film comprising a source region, a drain region and
a channel-forming region, the semiconductor films having a
crystalline structure,
[0015] wherein the source region and the drain region each have a
laminate structure comprising at least a first conductive layer, a
second conductive layer of which the resistance is higher than that
of the first conductive layer, and a third semiconductor layer of
which the conductivity type is the same as that of the
channel-forming region, the layers being laminated in that order
toward the gate-insulating film.
[0016] In one embodiment of the constitution of this aspect, the
semiconductor film having a crystalline structure have a grain
boundary distribution peculiar to fusion-crystallized films.
[0017] In another embodiment, the concentration profile of the
impurity constituting the first and second conductive layers varies
continuously from the first conductive layer to the second
conductive layer.
[0018] In still another embodiment, the second conductive layer
contains an impurity that varies continuously within the range of
from 5.times.1017 to 1.times.1019 atoms/cm3.
[0019] In still another embodiment, two offset regions each having
a different thickness exist between the channel-forming region and
the second conductive layer.
[0020] In still another embodiment, an offset region of which the
thickness is larger than that of the channel-forming region exists
between the channel-forming region and the second conductive
layer.
[0021] Another aspect of the invention is a semiconductor device
having a gate electrode formed on a substrate having an insulating
surface; a semiconductor film comprising a source region, a drain
region and a channel-forming region, the semiconductor having a
crystalline structure; and a source electrode and a drain electrode
as formed on the source region and the drain region,
respectively,
[0022] wherein the source region and the drain region each have a
laminate structure comprising at least a first conductive layer, a
second conductive layer of which the resistance is higher than that
of the first conductive layer, and a third semiconductor layer of
which the conductivity type is the same as that of the
channel-forming region, the layers being laminated in that order
toward the gate-insulating film, and
[0023] the source electrode and/or the drain electrode overlap(s)
with the gate electrode on the channel-forming region.
[0024] Still another aspect of the invention is a semiconductor
device having a semiconductor film comprising a source region, a
drain region and a channel-forming region, the semiconductor film
having a crystalline structure,
[0025] wherein the source region and the drain region each have a
laminate structure comprising at least a first conductive layer, a
second conductive layer of which the resistance is higher than that
of the first conductive layer, and a third semiconductor layer of
which the conductivity type is the same as that of the
channel-forming region, the layers being laminated in that order
toward the gate-insulating film, and
[0026] wherein an HRD structure comprising two offset regions each
having a different thickness and the second conductive layer is
formed between the channel-forming region and the first conductive
layer.
[0027] In one embodiment of the constitution of this aspect, one of
the two offset regions each having a different thickness is for
offset in the in-plane direction and is formed of a semiconductor
layer of which both the conductivity type and the thickness are the
same as those of the channel-forming region, while the other is for
offset in the thickness direction and is formed of a semiconductor
layer of which the conductivity type is the same as that of the
channel-forming region but of which the thickness is larger than
that of the channel-forming region.
[0028] Still another aspect of the invention is a method for
producing a semiconductor device, which comprises the steps of;
[0029] forming a gate electrode, a gate-insulating layer, and an
amorphous semiconductor film on a substrate having an insulating
surface,
[0030] exposing the amorphous semiconductor film to laser beams or
to intense light equivalent to laser beams to thereby convert it
into a semiconductor film having a crystalline structure,
[0031] adding an impurity selected from Group 15 only or from Group
13 and Group 15 to the semiconductor film having a crystalline
structure to form conductive layers,
[0032] forming a source electrode and a drain electrode on the
conductive layers, and
[0033] etching the semiconductor film having a crystalline
structure via the source electrode and the drain electrode both
acting as masks for the film to thereby form a channel-forming
region.
[0034] Still another aspect of the invention is a method for
producing a semiconductor device, which comprises the steps of:
[0035] forming a gate electrode, a gate-insulating layer, and an
amorphous semiconductor film on a substrate having an insulating
surface;
[0036] irradiating the amorphous semiconductor film with laser
beams or to intense light equivalent to laser beams to thereby
convert it into a semiconductor film having a crystalline
structure,
[0037] adding an impurity selected from Group 15 only or from Group
13 and Group 15 to the semiconductor film having a crystalline
structure to form conductive layers,
[0038] forming a source electrode and a drain electrode on the
conductive layers,
[0039] etching the semiconductor film having a crystalline
structure via the source electrode and the drain electrode both
acting as masks for the film to thereby form a channel-forming
region, and
[0040] adding to only the channel-forming region an impurity for
threshold voltage control, via the source electrode and the drain
electrode both acting as masks for the region.
[0041] Still another aspect of the invention is a bottom-gate-type
semiconductor device having a semiconductor film comprising a
source region, a drain region and a channel-forming region, the
semiconductor film having a crystalline structure,
[0042] wherein the semiconductor film has a grain boundary
distribution peculiar to fusion-crystallized films, and
[0043] wherein the source region and the drain region each have a
laminate structure comprising at least a first conductive layer, a
second conductive layer of which the resistance is higher than that
of the first conductive layer, and a third semiconductor layer of
which the conductivity type is the same as that of the
channel-forming region, the layers being laminated in that order
toward the gate-insulating film.
[0044] Still another aspect of the invention is a bottom-gate-type
semiconductor device having a semiconductor film comprising a
source region, a drain region and a channel-forming region, all of
semiconductor layers having a crystalline structure, wherein;
[0045] the semiconductor layers have a grain boundary distribution
peculiar to fusion-crystallized films,
[0046] the source region and the drain region each have a laminate
structure comprising at least a first conductive layer, a second
conductive layer of which the resistance is higher than that of the
first conductive layer, and a semiconductor layer of which the
conductivity type is the same as that of the channel-forming
region, the layers being laminated in that order toward the
gate-insulating film, and
[0047] the concentration profile of the impurity constituting the
first and second conductive layers varies continuously from the
first conductive layer to the second conductive layer.
[0048] Still another aspect of the invention is a bottom-gate-type
semiconductor device comprising a source region, a drain region and
a channel-forming region, all of semiconductor layers having a
crystalline structure, wherein;
[0049] the semiconductor layers have a grain boundary distribution
peculiar to fusion-crystallized films,
[0050] the source region and the drain region each have a laminate
structure comprising at least a first conductive layer, a second
conductive layer of which the resistance is higher than that of the
first conductive layer, and a semiconductor layer of which the
conductivity type is the same as that of the channel-forming
region, the layers being laminated in that order toward the
gate-insulating film, and
[0051] the second conductive layer contains an impurity that varies
continuously within the range of from 5.times.1017 to 1.times.1019
atoms/cm3.
[0052] Still another aspect of the invention is a bottom-gate-type
semiconductor device comprising a source region, a drain region and
a channel-forming region, all of semiconductor layers having a
crystalline structure, wherein;
[0053] the semiconductor layers have a grain boundary distribution
peculiar to fusion-crystallized films,
[0054] the source region and the drain region each have a laminate
structure comprising at least a first conductive layer, a second
conductive layer of which the resistance is higher than that of the
first conductive layer, and a semiconductor layer of which the
conductivity type is the same as that of the channel-forming
region, the layers being laminated in that order toward the
gate-insulating film, and
[0055] two offset regions each having a different thickness exist
between the channel-forming region and the second conductive
layer.
[0056] Still another aspect of the invention is a bottom-gate-type
semiconductor device comprising a source region, a drain region and
a channel-forming region, all of semiconductor layers having a
crystalline structure, wherein;
[0057] the semiconductor layers have a grain boundary distribution
peculiar to fusion-crystallized films,
[0058] the source region and the drain region each have a laminate
structure comprising at least a first conductive layer, a second
conductive layer of which the resistance is higher than that of the
first conductive layer, and a semiconductor layer of which the
conductivity type is the same as that of the channel-forming
region, the layers being laminated in that order toward the
gate-insulating film, and
[0059] an offset region of which the thickness is larger than that
of the channel-forming region exists between the channel-forming
region and the second conductive layer.
[0060] Still another aspect of the invention is a bottom-gate-type
semiconductor device comprising;
[0061] a gate electrode formed on a substrate having an insulating
surface,
[0062] a source region, a drain region and a channel-forming
region, all of semiconductor layers having a crystalline
structure,
[0063] and a source electrode and a drain electrode as formed on
the source region and the drain region, respectively, wherein;
[0064] the semiconductor layers have a grain boundary distribution
peculiar to fusion-crystallized films,
[0065] the source region and the drain region each have a laminate
structure comprising at least a first conductive layer, a second
conductive layer of which the resistance is higher than that of the
first conductive layer, and a semiconductor layer of which the
conductivity type is the same as that of the channel-forming
region, the layers being laminated in that order toward the
gate-insulating film, and
[0066] the source electrode and/or the drain electrode overlap(s)
with the gate electrode on the charnel-forming region.
[0067] Still another aspect of the invention is a bottom-gate-type
semiconductor device comprising a source region, a drain region and
a channel-forming region, all of semiconductor layers having a
crystalline structure, wherein;
[0068] the semiconductor layers have a grain boundary distribution
peculiar to fusion-crystallized films,
[0069] the source region and the drain region each have a laminate
structure comprising at least a first conductive layer, a second
conductive layer of which the resistance is higher than that of the
first conductive layer, and a semiconductor layer of which the
conductivity type is the same as that of the channel-forming
region, the layers being laminated in that order toward the
gate-insulating film, and
[0070] an HRD structure comprising two offset regions each having a
different thickness and the second conductive layer exists between
the channel-forming region and the first conductive layer.
[0071] In one embodiment of the constitutions noted above, one of
the two offset regions each having a different thickness is for
offset in the in-plane direction and is formed of a semiconductor
layer of which both the conductivity type and the thickness are the
same as those of the channel-forming region, while the other is for
offset in the thickness direction and is formed of a semiconductor
layer of which the conductivity type is the same as that of the
channel--forming region but of which the thickness is larger than
that of the channel-forming region.
[0072] Still another aspect of the invention is a method for
producing a semiconductor device, which comprises;
[0073] a step of forming a gate electrode, a gate-insulating layer,
and an amorphous semiconductor film on a substrate having an
insulating surface,
[0074] a step of exposing the amorphous semiconductor film to laser
beams or to intense light of which the intensity is equivalent to
that of laser beams, to thereby crystallize the film into a
semiconductor film having a crystalline structure,
[0075] a step of adding an impurity selected from Group 13 and/or
Group 15 to the semiconductor film having a crystalline structure
through ion implantation or ion doping, to thereby form first and
second conductive layers containing the impurity,
[0076] a step of exposing the conductive layers to laser beams or
to intense light of which the intensity is equivalent to that of
laser beams, to thereby activate the impurity,
[0077] a step of forming a source electrode and a drain electrode
on the conductive layers, and
[0078] a step of etching the semiconductor film having a
crystalline structure via the source electrode and the drain
electrode both acting as masks for the film to thereby form a
channel-forming region, and wherein;
[0079] the thicknesses of the first and second conductive layers
are controlled by the concentration profile of the impurity.
[0080] Still another aspect of the invention is a method for
producing a semiconductor device, which comprises;
[0081] a step of forming a gate electrode, a gate-insulating layer,
and an amorphous semiconductor film on a substrate having an
insulating surface,
[0082] a step of exposing the amorphous semiconductor film to laser
beams or to intense light of which the intensity is equivalent to
that of laser beams, to thereby crystallize the film into a
semiconductor film having a crystalline structure,
[0083] a step of adding an impurity selected from Group 13 and/or
Group 15 to the semiconductor film having a crystalline structure
through ion implantation or ion doping, to thereby form first and
second conductive layers containing the impurity,
[0084] a step of exposing the conductive layers to laser beams or
to intense light of which the intensity is equivalent to that of
laser beams, to thereby activate the impurity,
[0085] a step of forming a source electrode and a drain electrode
on the conductive layers,
[0086] a step of etching the semiconductor film having a
crystalline structure via the source electrode and the drain
electrode both acting as masks for the film to thereby form a
channel-forming region, and
[0087] a step of adding to the channel-forming region an impurity
for threshold voltage control, via the source electrode and the
drain electrode both acting as masks for the region, and
wherein;
[0088] the thicknesses of the first and second conductive layers
are controlled by the concentration profile of the impurity.
BRIEF DESCRIPTION OF THE DRAWINGS
[0089] FIG. 1A to FIG. 1D, and FIG. 2A to FIG. 2C show a process
for producing a thin film transistor in Embodiment 1.
[0090] FIG. 3 is an enlarged view showing the constitution of the
thin film transistor in Embodiment 1.
[0091] FIG. 4 is a graph showing an impurity concentration profile
in a semiconductor film in Embodiment 1.
[0092] FIG. 5A to FIG. 5C show the constitution of a thin film
transistor in Embodiment 2.
[0093] FIG. 6A to FIG. 6C show the constitution of a thin film
transistor in Embodiment 3.
[0094] FIG. 7A and FIG. 7B show the constitution of a thin film
transistor in Embodiment 4.
[0095] FIG. 8 shows the constitution of a CMOS circuit in
Embodiment 5.
[0096] FIG. 9 is a graph showing impurity concentration profiles in
a semiconductor film in Embodiment 5.
[0097] FIG. 10A and FIG. 10B shows the constitution of a thin film
transistor in Embodiment 7.
[0098] FIG. 11A to FIG. 11C show the constitution of a CMOS circuit
in Embodiment 8.
[0099] FIG. 12A to FIG. 12D, and FIG. 13A to FIG. 13C show a
process for producing a semiconductor circuit in Embodiment 10.
[0100] FIG. 14A and FIG. 14B show the constitution of a pixel
matrix circuit in Embodiment 10.
[0101] FIG. 15A to FIG. 15D show a process for producing a
semiconductor circuit in Embodiment 11.
[0102] FIG. 16 show sa process for producing a semiconductor
circuit in Embodiment 12.
[0103] FIG. 17A and FIG. 17B show a process for producing a
semiconductor circuit in Embodiment 13.
[0104] FIG. 18A and FIG. 18B show the constitution of a pixel
matrix circuit in Embodiment 14.
[0105] FIG. 19A and FIG. 19B show the constitution of a pixel TFT
in Embodiment 15.
[0106] FIG. 20 shows the constitution of a pixel TFT in Embodiment
16.
[0107] FIG. 21 shows the constitution of a pixel matrix circuit in
Embodiment 16.
[0108] FIG. 22 shows the constitution of a pixel TFT in Embodiment
17.
[0109] FIG. 23 shows the constitution of an external terminal
connecting site in Embodiment 18.
[0110] FIG. 24 shows a means of exposing a semiconductor circuit in
Embodiment 19.
[0111] FIG. 25A and FIG. 25B each show the constitution of an
electro-optical device in Embodiment 20.
[0112] FIG. 26A to FIG. 26F show outlines of various electronic
instruments in Embodiment 21.
[0113] FIG. 27A and FIG. 27B show the pattern constitution of a
semiconductor circuit in Embodiment 22.
[0114] FIG. 28A and FIG. 28B show the pattern constitution of a
semiconductor circuit in Embodiment 23.
[0115] FIG. 29 shows the constitution of a multi chamber in
Embodiment 24.
DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
[0116] The following Embodiments are to demonstrate preferred
embodiments of the invention having the constitution noted above,
which, however, are not intended to restrict the scope of the
invention. In those, referred to are FIG. 1 to FIG. 29.
[0117] [Embodiment 1]
[0118] This is to demonstrate one typical embodiment of the
invention with reference to FIGS. 1A to 3. First referred to are
FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2C which illustrate a method
for producing the semiconductor device of the invention. As
illustrated, a undercoating film 102 of an insulating film
comprising mainly silicon is formed on a glass substrate 101 to
prepare a substrate having an insulating surface. A gate electrode
(first wiring) 103 of a conductive film is formed on the film
102.
[0119] The line width of the gate electrode 103 is from 1 to 10 m
(typically from 3 to 5 m ). The thickness thereof is from 200 to
500 nm (typically from 250 to 300 nm). In this Embodiment, used is
an aluminum film (containing 2 wt. % scandium) having a thickness
of 250 nm to form the gate electrode having a line width of 3
m.
[0120] As the gate electrode 103, also usable is any of tantalum,
tungsten, titanium, chromium, molybdenum, conductive silicon, metal
silicide or their laminates, in place of aluminum. The aluminum
film is patterned (first patterning to form the gate
electrode).
[0121] Next, the gate electrode 103 is subjected to anodic
oxidation to form an oxide film 104 having a thickness of from 50
to 200 nm (typically from 100 to 150 nm). The oxide film 104 is to
protect the gate electrode. In this Embodiment, the anodic
oxidation is performed in an ethylene glycol solution containing 3%
tartaric acid (this is neutralized with ammonia) at a voltage of 80
V and a formation current of from 5 to 6 mA. The oxide film thus
formed may have a thickness of about 100 nm or so.
[0122] Next formed is a gate-insulating layer comprising a silicon
nitride film 105 (having a thickness of from 0 to 200 nm, typically
from 25 to 100 nm, but preferably 50 nm) and a silicon oxynitride
or silicon oxide film 106 of SiOxNy (having a thickness of from 150
to 300 nm, typically 200 .mu.m). In this Embodiment, the
gate-insulating layer includes the oxide film 104.
[0123] After the gate-insulating film has been formed, an amorphous
semiconductor film 107 comprising mainly silicon is formed over
this. In this Embodiment, formed is an amorphous silicon film,
which, however, is not limitative. In place of the amorphous
silicon film, also usable is any other compound semiconductor film
(e.g., germanium-containing amorphous silicon film, etc.).
[0124] In this Embodiment, since a channel-etched bottom-gate-type
structure is formed, the amorphous silicon film 107 should be
thick. Its thickness may fall between 100 and 600 nm (typically
between 200 and 300 .mu.m, but preferably 250 nm). In this
Embodiment, the thickness of the film 107 is 200 nm. As will be
mentioned hereinafter, the optimum thickness of the amorphous
silicon film to be formed in this step will be determined depending
on the offset region and the LDD region to be formed in TFT of the
invention.
[0125] In this Embodiment, the amorphous silicon film 107 is formed
through low pressure thermal CVD. For this, it is desirable that
the concentration of impurities of carbon, oxygen and nitrogen is
drastically and severely controlled during the film forming step.
If those impurities exist and remain too much in the film formed in
this step, they may have some negative influences on the uniformity
of the crystallinity of the crystalline semiconductor film to be
formed from the film.
[0126] In this Embodiment, the impurity concentration is so
controlled that carbon and nitrogen are less than 5.times.1018
atoms/cm3 (typically not more than 5.times.1017 atoms/cm3), and
oxygen is less than 1.5.times.1019 atoms/cm3 (typically not more
than 1.times.1018 atoms/cm3). Under this control, the impurity
concentration to be finally in the channel-forming region of TFT
could be within the defined range.
[0127] As a result of these steps, obtained is the structure of
FIG. 1A, which is then exposed to laser beams to thereby
crystallize the amorphous silicon film 107. (FIG. 1B)
[0128] As the laser beams, a pulse-oscillation excimer laser may be
employed, for which is used KrF (248 nm), XeCl (308 nm), ArF (193
nm) or the like as the excitation gas. In place of this, available
are any other various laser beams including Nd:YAG laser harmonics,
etc.
[0129] For thick amorphous semiconductor films, as in this
Embodiment, preferred are laser beams having a long wavelength as
facilitating uniform and entire crystallization of the films. Also
preferred is additionally heating the substrate at a temperature
falling within the range between 50 and 500_C or so, during
exposure to laser beams. In consideration of wavelength cycle of
the laser beams to be used into consideration, still preferred is
so controlling the thickness of the amorphous semiconductor film to
be crystallized that the light absorbing efficiency of the film is
increased.
[0130] In this Embodiment, pulse-oscillation XeCl excimer laser
beams are transformed into linear beams in an optical system, and
scanned over the amorphous silicon film 107 from one end of the
substrate to the other end thereof, whereby the entire surface of
the film 107 is annealed with the laser beams.
[0131] In this step, the oscillation frequency is 30 MHz, the
scanning speed is 2.4 mm/sec, the laser energy is from 300 to 400
mJ/cm2, and the substrate is heated at 400_C from its back surface.
As a result of this step, formed is a crystalline semiconductor
film (in this Embodiment, crystalline silicon film) 108.
[0132] Since the heat absorption differs between the amorphous
silicon film and the glass substrate, the amorphous silicon film
could be intensively heated if the upper surface of the film is
exposed to laser beams. In that manner, therefore, the amorphous
silicon film could be heated at a temperature higher than the
temperature that the glass substrate could bear (650_C or so).
[0133] Semiconductor films crystallized through exposure to laser
beams such as that formed in this Embodiment (the semiconductor
films of that type are herein referred to as fusion-crystallized
films) have a grain boundary distribution (existence distribution
of grain boundaries) peculiar to laser crystallization. Observing
the grain boundaries in the film through a known technique of
secondary etching could definitely clarify the crystal grains and
the grain boundaries existing in the film, from which it is known
that the film is an aggregate of crystal grains having a grain size
of from tens to hundreds nm.
[0134] On the other hand, semiconductor films crystallized by any
other crystallization means obviously differ from the
fusion-crystallized films in the mode of grain boundary
distribution. This is because, in the crystallization with laser
beams (or with intense light of which the intensity is equivalent
to that of laser beams), the semiconductor layers being
crystallized are once fused; whilst in the semiconductor layers
being crystallized by any other means, the grains grows in a mode
of solid-phase growth. Thus, the crystallization mechanism of this
invention differs from those of the any other methods.
[0135] Next, an element selected from Group 15 (typically
phosphorus, arsenic or antimony) is added to the crystalline
semiconductor film through ion implantation (with mass separation)
or ion doping (without mass separation). In this Embodiment,
phosphorus is added to the crystalline silicon film 108 while being
so controlled that the phosphorus concentration in the depth that
ranges between 30 and 100 nm (typically between 30 and 50 nm) from
the surface of the film 108 may fall between 1.times.1019 and
3.times.1021 atoms/cm3, but typically between 1.times.1020 and
1.times.1021 atoms/cm3.
[0136] In this Embodiment, the region 109 thus formed in that
manner noted above to have such a high phosphorus concentration is
referred to as an n+ layer (or a first conductive layer). The
thickness of this layer is defined to fall between 30 and 100 nm
(typically between 30 and 50 nm). In the present case, the n+ layer
109 will function later as a part of source/drain electrodes. In
this Embodiment, the n+ layer is formed to have a thickness of 30
nm.
[0137] The region 110 to be formed below the n+ layer 109 has a low
phosphorus concentration, and this is referred to as an n- layer
(or a second conductive layer). In the present case, the resistance
of the n- layer 110 is higher than that of the n+ layer 109, and
the n- layer 110 function later as an LDD region for field
relaxation. In this Embodiment, the n- layer 110 has a thickness of
30 nm. The intrinsic or substantially intrinsic region 120 to be
formed below the n- layer 110 is referred to as an i-layer. In the
i-layer 120, formed is a channel-forming region. (FIG. 1C)
[0138] In this step of phosphorus addition, the phosphorus
concentration profile in the direction of the depth of the film 108
is of critical importance. This will be described with reference to
FIG. 4. The concentration profile illustrated in FIG. 4 is for an
example of phosphine (PH3) addition as performed through ion-doping
at an accelerated voltage of 80 keV and an RF power of 20 W.
[0139] In FIG. 4, 401 indicates a crystalline silicon film, and 402
indicates the concentration profile of phosphorus added to the
film. The concentration profile is determined, depending on the
defined conditions of the RF power, the species of the ion added,
the accelerated voltage, etc.
[0140] In the illustrated case, the peak of the concentration
profile 402 is inside the n+ layer 403 or around the interface of
the n+ layer 403, and the phosphorus concentration decreases more
in the deeper site of the crystalline silicon film 401 (that is, in
the site nearer to the gate-insulating film). In this, the
phosphorus concentration varies continuously throughout the inside
of the film, and therefore, the n- layer 404 is always formed below
the n+layer 403.
[0141] Also inside the n.sup.- layer 404, the phosphorus
concentration continuously decreases. In this Embodiment, the
region in which the phosphorus concentration is over
1.times.10.sup.19 atoms/cm.sup.3 is considered as the n.sup.+ layer
403, while that in which the phosphorus concentration falls within
the range between 5.times.10.sup.17 and 1.times.10.sup.19
atoms/cm.sup.3 is as the n.sup.- layer 404. However, since no
definite boundary exists between the layers 403 and 404, the
phosphorus concentration range noted above may be a rough criterion
for those layers.
[0142] The region having a greatly lowered phosphorus concentration
and the layer below the region constitute an intrinsic or
substantially intrinsic region (i-layer) 405. The intrinsic region
is a region to which no impurity is intentionally added. The
substantially intrinsic region indicates a region in which the
impurity concentration (the phosphorus concentration in this
Embodiment) is not higher than the spin density of the silicon
film, or a region having an impurity concentration of from
1.times.10.sup.14 to 1.times.10.sup.17 atoms/cm.sup.3 and
exhibiting one conductivity.
[0143] The intrinsic or substantially intrinsic region of that type
is formed below the n.sup.- layer 404. However, the i-layer 405 is
basically formed of a semiconductor layer of which the conductivity
is the same as that of the channel-forming region. In other words,
where the channel-forming region is of a weakly n-type or p-type,
the i-layer has the same type of conductivity as that of the
channel-forming region.
[0144] As in the above, the ion implantation or ion doping to form
the n.sup.+ layer produces the n layer below the n.sup.+ layer.
However, if the n.sup.+ layer is formed according to a conventional
film forming method, the constitution of that type could not be
realized. Where the conditions for ion addition are suitably
defined, the thicknesses of the n.sup.+ layer and the n.sup.- layer
to be formed are easy to control.
[0145] In particular, the thickness of the n.sup.- layer requires
highly accurate control, as it is to be the thickness of the LDD
region to be formed later. In ion doping or the like where the
conditions for ion addition are suitably defined, the ion
concentration profile in the depthwise direction of the film can be
controlled accurately, and the thickness of the LDD region to be
formed later is easy to control. In the present invention, the
thickness of the n.sup.- layer 110 is controlled to fall between 30
and 200 nm (typically between 50 and 150 nm).
[0146] The concentration profile illustrated in FIG. 4 is one
attained in one doping step. Apart from this, the doping step may
be repeated plural times to control the thicknesses of the n.sup.+
layer 403 and the n.sup.- layer 404. For example, doping at a high
dose to produce the peak of the concentration profile in a
relatively shallow site where the n+layer 403 is to be formed may
be combined with doping at a low dose to produce the peak of the
concentration profile in a relatively deep site where the n.sup.-
layer 404 is to be formed.
[0147] After the n.sup.+ layer 109 and the n.sup.- layer 110 have
been formed in that manner noted above, they are again exposed to
laser beams whereby the impurity (phosphorus) added thereto is
activated. (FIG. 1D)
[0148] Apart from laser annealing, also available for this is lamp
annealing (exposure to intense light) or furnace annealing (heating
in an electric furnace). In the furnace annealing, however, the
heat resistance of the glass substrate is taken into
consideration.
[0149] In this Embodiment, the layers are subjected to laser
annealing with XeCl excimer laser beams. For this, the processing
conditions may be basically the same as those for the
crystallization step noted above. In this, however, the laser
energy may be from 200 to 350 mJ/cm.sup.2 (typically from 250 to
300 mJ/cm.sup.2). During the laser annealing, the substrate is
heated at 300_C from its back surface, whereby the phosphorus
activation is promoted.
[0150] In the laser activation step, the crystalline silicon film
108 damaged in the phosphorus addition step may be restored. In
this step, the region of the film 108 made to be amorphous due to
the ion collision in the ion addition step may be
recrystallized.
[0151] After the phosphorus activation step, the crystalline
silicon film is patterned to form an island semiconductor layer
111. In this step, the length of the layer 111 in the direction
vertical to the carrier-moving direction in the final TFT to be
produced herein (this length corresponds to the channel width, W)
is so controlled that it falls between 1 and 30 _m (typically
between 10 and 20 _m). The second patterning step is thus performed
herein. (FIG. 2A)
[0152] Though not shown in the drawings, a part of the exposed
gate-insulating layer is etched to form a contact hole (in the
region 118 in FIG. 2C), through which the gate electrode (first
wiring) and the electrodes to be formed in the next step (second
wiring) are electrically connected with each other. The third
patterning step is thus performed herein.
[0153] Next, a conductive metal film (not shown) is formed, which
is then patterned to give the source electrode 112 and the drain
electrode 113. In this Embodiment, a three-layered laminate film of
Ti (50 nm)/Al (200 to 300 nm)/Ti (50 nm) is formed. In this step,
formed is the wiring for electrically connecting the electrodes 112
and 113 with the gate electrode. The fourth patterning step is thus
performed herein. (FIG. 2B)
[0154] As will be again mentioned hereinafter, the length of the
region 114 just above the gate electrode 103, or that as sandwiched
between the source electrode 112 and the drain electrode 113 (this
region 114 is referred to as a channel-etching region, and its
length is indicated by C.sup.1) will determine the length of the
channel-forming region and that of the offset region to be formed
later. The length C.sup.1 may fall between 2 and 20 m (typically
between 5 and 10 _m). In this Embodiment, C.sup.1=4 _m.
[0155] Next, the island semiconductor layer 111 is self-alignedly
dry-etched via the source electrode 112 and the drain electrode 113
both acting as masks. In this step, therefore, only the
channel-etching region 114 is etched. (FIG. 2C)
[0156] In this etching step, the n.sup.+ layer 109 and the n layer
110 are completely removed, but the intrinsic or substantially
intrinsic region (i-layer) only is not removed and remains as it is
without being etched. In the present invention, only the
semiconductor layer of being from 10 to 100 run (typically from 10
to 75 nm, but preferably from 15 to 45 nm) in thickness remains as
it is without being etched in this etching step. In this
Embodiment, the semiconductor layer having a thickness of 30 nm
remains as it is in this step.
[0157] After the island semiconductor layer 111 has been thus
etched (in the channel-etching step), a protective film 115 of a
silicon oxide film or a silicon nitride film is formed over this to
obtain an inverse stagger-type TFT having the structure shown in
FIG. 2C.
[0158] In that condition, the region of the channel-etched, island
semiconductor layer 111 that is positioned just above the gate
electrode 112 is a channel-forming region 116. In the constitution
in this Embodiment, the width of the gate electrode corresponds to
the length of the channel-forming region, and the length
represented by Ll is referred to as a channel length. The regions
117 positioned outside the edges of the gate electrode 103 are
outside the electric field of the gate electrode 103, and are
offset regions. The length of the regions 117 is represented by
X.sup.1.
[0159] In this Embodiment, the line width of the gate electrode 103
(this corresponds to L.sup.1) is about 2.8 _m in consideration of
the anodic oxidation loss that gave the oxide film of 100 nm thick,
and the length (C.sup.1) of the channel-etching region 114 is 4 _m.
In this, therefore, the length (X.sup.1) of each offset region is
about 0.6 _m.
[0160] An enlarged view of the drain region (the semiconductor
layer contacted with the drain electrode 113) is shown in FIG. 3.
In FIG. 3, 103 is the gate electrode, 301 is the channel-forming
region, 302 is the n.sup.+ layer (source or drain electrode), 303
and 304 are the offset regions each having a different thickness,
and 305 is the n.sup.- layer (LDD region).
[0161] Though not shown herein, the source region (the
semiconductor layer contacted with the source electrode 112) has
the same structure as above.
[0162] The TFT structure is graphically drawn in FIG. 3, in which
special attention should be paid to the relationship between the
thicknesses of the regions constituting the structure. In the most
preferred constitution of the present invention, the constituent
regions satisfy the condition that the thickness of the n.sup.+
layer 302<that of the n.sup.- layer 305<that of the offset
region (i-layer) 304.
[0163] This is because the n.sup.+ layer 302 functions only as an
electrode and may be thin. On the other hand, the n.sup.- layer 305
and the offset region 304 should be satisfactorily thick for
effective field relaxation.
[0164] In the constitution of this Embodiment, the two offset
regions 303 and 304 each having a different thickness, and the LDD
region 305 exist between the channel-forming region 301 and the
n.sup.+ region 302. In this, the region 303 is an offset region in
the in-plane direction, which is formed by mask alignment, and this
is referred to as a mask offset region.
[0165] The region 304 is an offset region in the direction of the
thickness of the film, and its thickness corresponds to the
thickness of the i-layer. This is referred to as a thickness offset
region. The thickness of the thickness offset region 304 may fall
between 100 and 300 nm (typically between 150 and 200 nm). However,
this must be larger than the thickness of the channel-forming
region. If its thickness is smaller than the thickness of the
channel-forming region, the thickness offset region 304 could not
exhibit good offsetting ability.
[0166] We, the present inventors refer to the structure of that
type comprising offset+LDD, as an HRD (high resistance drain)
structure, and differentiate it from ordinary LDD structures. In
this Embodiment, the HRD structure is a three-stage structure
comprising mask offset+thickness offset+LDD.
[0167] In this case, the LDD region 305 is controlled by its
thickness and the impurity concentration therein, and therefore has
the advantage of high reproducibility and uniform characteristics.
Contrary to this, the LDD region as formed by conventional
patterning has the problem of non-uniform characteristics to be
caused by the patterning error, as so mentioned hereinabove with
reference to the prior art.
[0168] As being controlled by the patterning, the length (X.sup.1)
of the mask offset region 303 is influenced by the patterning error
and even by the glass shrinkage error. However, since the region
303 is followed by the thickness offset region 304 and the LDD
region 305, the influence of the error on the length of the region
303 is thereby reduced and the fluctuation in the characteristics
of the region 303 may be reduced.
[0169] The length (X.sup.1) of the mask offset region 303 may be
represented by (C.sup.1-L.sup.1)/2 where L.sup.1 indicates the
channel length and C.sup.1 indicates the length of the
channel-etching region. Accordingly, the intended offset length
(X.sup.1) can be defined in the patterning step of forming
source/drain electrodes. In the constitution of this Embodiment,
the offset length (X.sup.1) may be from 0.3 to 3 _m (typically from
1 to 2 _m).
[0170] The inverse stagger-type TFT having the structure shown in
FIG. 2C could not be realized in any prior art of TFT having
conventional amorphous silicon films as the active layers (island
semiconductor layers). This is because, in the case of TFT
comprising such an amorphous silicon film, if the source/drain
electrodes are not so constructed as to overlap with the gate
electrode, the carrier (electron or hole) mobility is extremely
low.
[0171] Even if the source/drain electrodes are so constructed as to
overlap with the gate electrode in TFT comprising an amorphous
silicon film, the mobility (field effect mobility) of those TFT
will be at most from 1 to 10 cm.sup.2 Vs or so. Contrary to this,
if TFT comprising an amorphous silicon film are constructed like in
the present Embodiment, their mobility is too low to function as
switching devices.
[0172] As opposed to those conventional TFT, the TFT of the present
invention comprises crystalline silicon films as the active layers,
and the carrier mobility therein is fully high. Therefore, the
structure of this Embodiment ensures a satisfactorily high carrier
mobility. In other words, using the semiconductor films having a
crystalline structure as the active layers realizes the TFT
structure of this Embodiment.
[0173] Since the inverse stagger-type TFT of this Embodiment has
the HRD structure, it is highly resistant to hot carrier
implantation to be caused by impact ionization, and therefore has
high reliability. In addition, in the TFT of this Embodiment, the
LDD region is formed in a well controlled manner and governs the
other regions. Therefore, the characteristics of the TFT vary
little.
[0174] Accordingly, the structure of this Embodiment is favorable
to TFT circuits that are required to have high voltage resistance
but not so quick operating mobility.
[0175] As is known from the process of this Embodiment, only 4
masks are used to produce the inverse stagger-type TFT having the
structure of FIG. 2C. Considering the fact that conventional
channel-stop-type TFT require 6 masks, the structure of this
Embodiment means significant improvements in the throughput and the
yield of inverse stagger-type TFT.
[0176] As in the above, using the structure of this Embodiment
makes it possible to produce bottom-gate-type TFT of high
reliability and high producibility on a mass-production scale.
[0177] The bottom-gate-type TFT (N-channel-type TFT) as produced
according to the process of this Embodiment realize a mobility of
from 10 to 150 m.sup.2 Vs (typically from 60 to 120 cm.sup.2/Vs)
and a threshold voltage of from 1 to 4 V.
[0178] [Embodiment 2]
[0179] This is to demonstrate another embodiment of the invention,
which is different from Embodiment 1. The basic process of
producing TFT in this Embodiment 2 is the same as that in
Embodiment 1. The differences of Embodiment 2 from Embodiment 1 are
described herein.
[0180] First prepared is the structure of FIG. 5A according to the
process of Embodiment 1. The difference between the structure
herein and that in Embodiment 1 is that the length of the
channel-etching region 500 to be between the source electrode 501
and the drain electrode 502 is C.sup.2 herein. In this, C.sup.2 is
narrower than the width of the gate electrode, and may fall between
2 and 9 _m (typically between 2 and 4 _m). Specifically, this
Embodiment is characterized in that the gate electrode overlaps
with the source/drain electrodes.
[0181] This structure of FIG. 5A is subjected to the
channel-etching step as in Embodiment 1, and then coated with
protective films. Thus is formed the structure of FIG. SB. In this,
the region indicated by 503 is a channel-forming region, and the
channel length is indicated by L.sup.2 (=C.sup.2). By suitably
designing the masks, the length (Y.sup.2) of the overlapping
regions (hereinafter referred to as mask-overlapping regions) is
controlled to be (E-L.sup.2)/2 where E is the width of the gate
electrode.
[0182] FIG. 5C is an enlarged view of the drain region, in which
the carriers pass through the channel-forming region 503
(thickness: 50 nm), the mask-overlapping region 504 (thickness: 160
nm) and the LDD region 505 (thickness: 50 nm) and reach the n.sup.+
layer 506 (thickness: 40 nm) and the drain electrode 502, while the
TFT is driven.
[0183] In this structure, the electric field from the gate
electrode covers the mask-overlapping region 504, but is attenuated
toward the LDD region 505. In this, therefore, the region 504 has
substantially the same function as that of the LDD region.
Needless-to-say, the region 504 nearest to the LDD region 505 is
entirely free from the influence of the electric field, and this
functions also as an offset (thickness offset) region.
[0184] In this Embodiment, the HRD structure having the
mask-overlapping region is comprising overlapping substantial
LDD+thickness offset+impurity-poor LDD. In the HRD structure in
which the mask-overlapping region 504 is thin, the LDD region may
be comprising overlapping substantial LDD+impurity-poor LDD.
[0185] In the structure of this Embodiment, the overlapping region
504 and the LDD region 505 each are well controlled to have a
controlled thickness. Therefore, the characteristics of TFT having
this structure vary little. The length (Y.sup.2) of each
overlapping region may contain a patterning error. However, since
the overlapping LDD, the thickness offset and the impurity-poor LDD
are not influenced by the patterning error, the length error of
Y.sup.2 has few negative influences on the characteristics of
TFT.
[0186] The structure of this Embodiment has a reduced offset
component and is favorable to TFT circuits that are required to
have quick operating mobility.
[0187] Another advantage of the structure of this Embodiment is
that minor carriers having accumulated in the channel-forming
region due to impact ionization can rapidly move to the source
electrode without causing substrate floatation. Therefore, using
the structure of this Embodiment realizes TFT that ensure quick
operating motion and have high voltage resistance.
[0188] [Embodiment 3]
[0189] This is to demonstrate still another embodiment of the
invention, which is different from Embodiments 1 and 2. The basic
process of producing TFT in this Embodiment 3 is the same as that
in Embodiment 1. The differences of Embodiment 3 from Embodiment 1
are described herein.
[0190] First prepared is the structure of FIG. 6A according to the
process of Embodiment 1. The difference between the structure
herein and that in Embodiment 1 is that the length of the
channel-etching region 600 to be between the source electrode 601
and the drain electrode 603 is C.sup.3 herein. In this, C.sup.3 is
the same as the width of the gate electrode, and may fall between 1
and 10 _m (typically between 3 and 5 _m).
[0191] This structure of FIG. 6A is subjected to the
channel-etching step as in Embodiment 1, and then coated with
protective films. Thus is formed the structure of FIG. 6B. In this,
the region indicated by 603 is a channel-forming region, and the
channel length is indicated by L.sup.3 (=C.sup.3).
[0192] FIG. 6C is an enlarged view of the drain region, in which
the carriers pass through the channel-forming region 603
(thickness: 100 nm), the thickness offset region 604 (thickness:
150 nm) and the LDD region 605 (thickness: 100 nm) and reach the
n.sup.+ layer 606 (thickness: 50 nm) and the drain electrode 602,
while the TFT is driven. In this Embodiment, the HRD structure has
a two-stage structure of offset+LDD.
[0193] In the structure of this Embodiment, the thickness offset
region 604 and the LDD region 605 each are well controlled to have
a controlled thickness. Therefore, the characteristics of TFT
having this structure vary little. In addition, the voltage
resistance of TFT having this structure is high.
[0194] [Embodiment 4]
[0195] This is to demonstrate still another embodiment of the
invention, which is different from Embodiments 1 to 3. The basic
process of producing TFT in this Embodiment 4 is the same as that
in Embodiment 1. The differences of Embodiment 4 from Embodiment 1
are described herein.
[0196] First prepared is the structure of FIG. 7A according to the
process of Embodiment 1. The difference between the structure
herein and that in Embodiment 1 is that any one of the source
electrode 701 or the drain electrode 702 overlaps with the gate
electrode while the other does not.
[0197] In this Embodiment, the length of the channel-etching region
700 is C.sup.4, which may fall between 1 and 10 _m (typically
between 3 and 6 _m).
[0198] This structure of FIG. 7A is subjected to the
channel-etching step as in Embodiment 1, and then coated with
protective films. Thus is formed the structure of FIG. 7B. In this,
the region indicated by 703 is a channel-forming region, and the
channel length is indicated by L.sup.4 (=C.sup.4 X.sup.4).
[0199] In this, X.sup.4 indicates the length of the mask offset
region 704. For the numerical limitation of X.sup.4, referred to is
Embodiment 1. For the numerical limitation of the length of the
mask-overlapping region 705, referred to is Embodiment 2.
[0200] The structure of this Embodiment comprises a combination of
the HRD structure of Embodiment 1 and the HRD structure (or LDD
structure) of Embodiment 2. For the details of the constituent
structures herein, referred to are those in Embodiments 1 and
2.
[0201] In this Embodiment, it is desirable that the source region
has the HRD structure (or LDD structure) of Embodiment 2 while the
drain region has the HRD structure of Embodiment 1.
[0202] The electric field concentration is great in the channel
edge (junction) adjacent to the drain region. Therefore, for
example, it is desirable that the drain region in this Embodiment
has the resistance component-rich HRD structure as in Embodiment 1.
On the contrary, the source region in this Embodiment is not
required to have such high voltage resistance. To the source region
herein, therefore, the resistance component-poor HRD (or LDD)
structure as in Embodiment 2 is favorable.
[0203] In this Embodiment, any one of the source/drain regions may
be combined with the structure of Embodiment 2. In any manner,
producers may suitably select any of HRD and LDD structures such as
those illustrated in Embodiments 1 to 3 to construct various types
of source/drain regions and to design and produce optimum
structures of TFT circuits comprising the thus-constructed
source/drain regions. In that case, various patterning of 3.sup.2=9
combinations is available.
[0204] [Embodiment 5]
[0205] This is to demonstrate the construction of a CMOS circuit
(inverter circuit) comprising the bottom-gate-type TFT having the
constitution of any of Embodiments 1 to 4, with reference to FIG.
8. The CMOS circuit is comprising N-channel-type TFT and
P-channel-type TFT as complementarily formed and combined on one
substrate.
[0206] The CMOS circuit illustrated in FIG. 8 comprises the
structure of Embodiment 4, in which 801 is a source electrode for a
P-channel-type TFT, 802 is a source electrode for an N-channel-type
TFT, and 803 is a drain electrode for both the N/P TFT.
[0207] The N-channel-type TFT comprises n+layers 804 and 805 and
n.sup.- layers 806 and 807 all formed according to the process of
Embodiment 1. On the other hand, the P-channel-type TFT comprises
p.sup.++ layers 808 and 809 and p.sup.- layers 810 and 811.
[0208] It is extremely easy to form the CMOS circuit on one
substrate. In the case of the present invention, the structure of
FIG. 2A is first prepared according to the process of Embodiment
1.
[0209] Irrespective of N/P types, an element selected from Group 15
is added to the entire surface of this structure. To produce the
P-channel-type TFT in this structure, the region to be the
N-channel-type TFT is masked with a resist mask or the like, and an
element selected from Group 13 (typically boron, indium or gallium)
is added to this.
[0210] In this Embodiment, boron is added to produce the
P-channel-type TFT. In this case, the dose of boron must be higher
than the phosphorus concentration by which the type of the
conductivity of the intended region is inverted. In order to
completely convert all the n.sup.+ layer and the n.sup.- layer to
the p.sup.++ layer and the p.sup.- layer, the concentration profile
in boron addition must be so controlled that the boron depth is
larger than the phosphorus depth.
[0211] Accordingly, the boron concentration profile in the film is
as in FIG. 9. In FIG. 9, 900 is a semiconductor film, 901 is a
phosphorus concentration profile prior to boron addition, 902 is a
boron concentration profile after boron addition, 903 is a p.sup.++
layer, 904 is a p.sup.- layer, and 905 is an i-layer.
[0212] In this case, the p.sup.++ layer has a thickness of from 10
to 150 nm (typically from 50 to 100 nm), and the boron
concentration in the p.sup.++ layer is so controlled that it falls
between 3.times.10.sup.19 and 1.times.10.sup.22 atoms/cm.sup.3, but
typically between 3.times.10.sup.19 and 3.times.20.sup.21
atoms/cm.sup.3.
[0213] On the other hand, the p.sup.- layer has a thickness of from
30 to 300 nm (typically from 100 to 200 nm), and the boron
concentration in the p.sup.- layer is so controlled that it falls
between 5.times.10.sup.17 and 3.times.10.sup.19 atoms/cm.sup.3.
However, since the P-channel-type TFT naturally has high
durability, the formation of the p.sup.- layer for the LDD region
is not always necessary. The reason why the thickness of the
p.sup.- layer 904 is specifically referred to herein is because the
p.sup.- layer is all the time formed in the ion implantation for
boron addition that brings about the continuously varying boron
concentration profile.
[0214] In this Embodiment, both the N-channel-type TFT and the
P-channel-type TFT have the HRD structure (comprising overlapping
regions) of Embodiment 2 in their source regions, while having the
HRD structure (comprising mask offset regions) of Embodiment 1 in
their drain regions.
[0215] Accordingly, as will be obvious from the top view of FIG. 8,
the source region in the P-channel-type TFT has an overlapping
region having a length of Yi, while the drain region therein has a
mask offset region having a length of Xi. On the other hand, the
source region in the N-channel-type TFT has an overlapping region
having a length of Yj, while the drain region therein has a mask
offset region having a length of Xj.
[0216] In this case, the lengths of Xi, Xj, Yi and Yj can freely be
varied depending on mask designing. Accordingly, each length of
those may be suitably determined in accordance with the necessity
for the circuit constitution, and it is not always necessary to
unify the lengths in the N-channel-type and P-channel-type TFT.
[0217] In the CMOS circuit having the structure illustrated herein,
the voltage resistance of the region to be the common drain is
high. Therefore, the structure of the illustrated type is extremely
useful in constructing circuits for high operating voltage.
[0218] FIG. 8 shows the constitution of the CMOS circuit comprising
TFT of Embodiments 1 to 4. Needless-to-say, however, any other
combinations except the illustrated constitution are acceptable.
Nine combinations are available for one TFT. Therefore, 9.sup.2=81
modifications or variations are acceptable for patterning
constitution of one CMOS circuit. From those plural combinations.
the optimum ones may be selected and employed in accordance with
the necessary properties of the circuits to be produced.
[0219] As has been illustrated in this Embodiment, the present
invention is easily applicable to P-channel-type TFT. In that case,
the bottom-gate-type TFT (P-channel-type TFT) of the invention
realize a mobility of from 10 to 100 cm.sup.2/Vs (typically from 50
to 100 cm.sup.2/Vs) and a threshold voltage of from -1.5 to -5
V.
[0220] [Embodiment 6]
[0221] This is to demonstrate one embodiment of the means of
controlling the threshold voltage of TFT of the invention.
[0222] For threshold voltage control, an element selected from
Group 13 (typically boron, indium, gallium) or Group 15 (typically
phosphorus, arsenic, antimony) may be added to a channel-forming
region. This technique is referred to as channel doping.
[0223] The technique of channel doping is effective in the present
invention, for which any of the following two methods is preferred
as being simple.
[0224] The first method comprises adding a gas that contains an
impurity for threshold voltage control (e.g., diborane, phosphine,
etc.) to the film forming gas for the amorphous silicon film. In
this method, the formed film contains a predetermined amount of the
impurity. This method does not require any additional step for
impurity addition. However, in this method, both the N-type and
P-type TFT have the same impurity concentration. Therefore, this
method is not available for the case where the N-type and P-type
TFT have a different impurity concentration.
[0225] The second method comprises adding an impurity selectively
to the channel-forming region (or to the channel-forming region and
the mask offset region) via the source/drain electrodes acting as
masks, after the channel-etching step (for forming the
channel-forming region) as in FIG. 2C.
[0226] For this, available is any of ion implantation, ion doping,
plasma processing, gaseous phase addition (for impurity diffusion
from gaseous atmosphere), solid phase addition (for impurity
diffusion from solid film) and the like. Since the channel-forming
region is thin, gaseous phase addition, solid phase addition and
the like that cause no damage to the region are preferred.
[0227] In ion implantation, it is desirable to cover the entire
surface of TFT with a protective film, by which the channel-forming
region is protected from being damaged.
[0228] After the impurity has been added to the film, it is
activated through laser annealing, lamp annealing, furnace
annealing or their combination. In this step, the damage of the
channel-forming region is almost completely recovered.
[0229] In this Embodiment, the concentration of the impurity for
threshold voltage control, which is added to the channel-forming
region, may fall between 1.times.10.sup.15 and 5.times.10.sup.18
atoms/cm.sup.3 (typically between 1.times.10.sup.15 and
5.times.10.sup.17 atoms/cm.sup.3).
[0230] The threshold voltage of the N-channel-type TFT of the
invention, to which the embodiment of this Embodiment has been
applied, may fall between 1.5 and 3.5 V. The threshold voltage of
the P-channel-type TFT of the invention, to which the same has been
applied, may fall between -1.5 and -3.5 V.
[0231] The constitution of this Embodiment may be combined with any
constitution of Embodiments 1 to 5. Where it is combined with the
CMOS circuit of Embodiment 5, the type of the impurity and even the
concentration thereof may be changed in the N-type TFT and the
P-type TFT.
[0232] [Embodiment 7]
[0233] The structure of FIG. 2C has the source electrode 112 and
the drain electrode 113 that entirely surround the island
semiconductor layer. This Embodiment is to demonstrate a structure
partly different from the structure of FIG. 2C.
[0234] Referred to is the structure of FIG. 10A, which is basically
the same as the structure of FIG. 2C but is partly different from
it. The structure of FIG. 10A is characterized in that the shape of
the source electrode 11 and that of the drain electrode 12 differ
from those in FIG. 2C. Specifically, in the structure of FIG. 10A,
the source electrode 11 and the drain electrode 12 are formed
partly inside the island semiconductor layer (strictly, inside the
source/drain regions) by the distance of "a".
[0235] The region indicated by 13 has a thickness that is the same
as the thickness of the channel-forming region 14, and has a width
that is the same as the distance of "a". Though graphically shown
in the drawing, the distance "a" is from 1 to 300 _m (typically
from 10 to 200 _m).
[0236] The characteristics of this Embodiment will be mentioned
below, with reference to the process of producing the structure of
this Embodiment. As in FIG. 10B, the source electrode 11 and the
drain electrode 12 are formed herein. In this, the edges 16 of an
island semiconductor layer 15 are exposed outside.
[0237] The structure of FIG. 10B is subjected to a channel-etching
step, where the island semiconductor layer 15 is self-alignedly
etched via the source electrode 11 and the drain electrode 12 both
acting as masks. In this, the edges 16 are also etched.
[0238] As a result of the etching, obtained is the structure of
FIG. 10A. In the thus-obtained structure, it is obvious that the
thickness of the edges 16 is the same as that of the
channel-forming region 14.
[0239] In this Embodiment, the protrusions 13 of the island
semiconductor layer are formed for the following two reasons.
[0240] These are used for etching monitoring in the channel-etching
step.
[0241] In the subsequent steps of forming a protective film and an
interlayer insulating film, these protrusions are effective for
reducing the coverage failure to be caused by the height of the
island semiconductor layer.
[0242] For the etching monitoring, the products being produced are
sampled and the samplings are inspected at their protrusions to
check the etching degree at the channel-forming region.
[0243] The structure of this Embodiment may be combined with any
structure of Embodiments 1 to 6.
[0244] [Embodiment 8]
[0245] This is to demonstrate one embodiment of the circuit
constitution of the CMOS circuit (inverter circuit) of Embodiment
5, with reference to FIG. 11A to FIG. 11C.
[0246] FIG. 11A shows a CMOS circuit of which the structure is the
same as that in FIG. 8. The CMOS circuit illustrated comprises a
gate electrode 20, an N-type TFT semiconductor layer 21, a P-type
TFT semiconductor layer 22, an N-type TFT source electrode 23, a
P-type TFT source electrode 24 and a common drain electrode 25.
[0247] The terminals, a, b, c and d correspond to those of a, b, c
and d, respectively, of the inverter circuit shown in FIG. 11
C.
[0248] FIG. 11B shows a modification of the CMOS circuit, in one
and the same semiconductor layer of the drain region is formed for
both the N-type TFT and the P-type TFT. The numeral and code
references in FIG. 11B correspond to those in FIG. 11A.
[0249] In the structure of FIG. 11B, all TFT can be formed at an
extremely high density. Therefore, this structure is extremely
effective in producing large-scale integration circuits. In this,
the common semiconductor layer will form PN junctions, which,
however, produce no problem.
[0250] [Embodiment 9]
[0251] In Embodiment 1, the amorphous semiconductor film is
crystallized with laser beams, especially with pulse-oscillation
excimer laser beams for fusion crystallization. In this, laser
beams or intense light of which the intensity is equivalent to
laser beams can be used for crystallizing the amorphous
semiconductor film through solid phase crystal growth, without
distorting the glass substrate.
[0252] As the light source for generating such intense light or
laser beams, usable is any of IR lamps such as halogen lamps, or
continuous oscillation lasers such as Ar lasers. RTA (rapid thermal
annealing) for which are used IR lamps or continuous oscillation
lasers ensures crystallization of amorphous semiconductor films
under heat for a few seconds to tens seconds, and therefore
realizes great improvements in throughput.
[0253] Where amorphous semiconductor (e.g., silicon) films are
exposed to light from IR lamps or to continuous oscillation laser
beams, the light absorbed by the films is converted into heat, and
the thus-generated heat acts on the films to form crystal nuclei
therein. In those films, the nuclei grow in the solid phase,
resulting in that the films are converted into crystalline
semiconductor films.
[0254] Where a halogen lamp (peak wavelength: 1.15 _m, wavelength
range: 0.4 to 4 _m) is used, the heating time may fall between 10
and 60 seconds, but typically between 15 and 30 seconds. With this,
amorphous semiconductor films are heated at 700 to 1000_C. In this
case, even through the films are heated at 700 to 1000_C, the
underlying glass substrate is not heated over its distortion point
(650 to 700_C or so), since the glass substrate hardly absorbs IR
rays and since the exposure time is short.
[0255] After amorphous semiconductor films have been crystallized
with IR lamps or continuous oscillation laser beams, it is
desirable that the resulting crystalline semiconductor films are
further exposed to laser beams for annealing to thereby increase
the degree of crystallinity of the films. In this case, the
annealing with laser beams may be performed for activating the
impurity added to the films.
[0256] The RTA technique of this Embodiment for crystallizing
semiconductor films may be combined with all other Embodiments
illustrated herein.
[0257] [Embodiment 10]
[0258] This is to demonstrate the production of an
active-matrix-type display device that comprises a driver circuit
(peripheries-driving circuit) and a pixel matrix circuit as
integrated on one substrate, with reference to the basic process of
Embodiment 1.
[0259] In this Embodiment, the basic constitution of the driver
circuit comprises a CMOS circuit (of the type illustrated in FIG.
11B). Apart from the driver circuit, the other information
processing circuits of D/A converter circuit, memory circuit,-co
rrection circuit and others (these are differentiated from the
driver circuit and will be referred to as logic circuits) may also
comprise TFT of the invention. For those logic circuits, a CMOS
circuit is the base circuit.
[0260] A multi-gate TFT is usable as the pixel matrix circuit. In
this Embodiment, used is a double-gate structure for the pixel
matrix circuit, which, however, is not limitative. Apart from this,
any of a single-gate structure or a triple-gate structure is
available.
[0261] According to the process of Embodiment 1, an amorphous
silicon film was crystallized through laser irradiation to form the
structure of FIG. 1B. This is in FIG. 12A.
[0262] In FIG. 12A, 30 is a glass substrate, 31 is a undercoating
film, 32 is a PTFT gate electrode to be a CMOS circuit, and 33 is
an NTFT gate electrode. In this, 34 and 35 are pixel TFT gate
electrodes, and these are connected with each other in the site not
shown in the drawing. As the material for the gate electrodes 32 to
35, used is an aluminum film (containing 2 wt. % Sc). To protect
the gate electrodes from being thermally and physically damaged,
aluminum oxide films 3000 and 3001 are formed through anodic
oxidation around the gate electrodes 32 and 33 of the CMOS circuit,
and the pixel TFT gate electrodes 34 and 35 are also coated with an
aluminum oxide film 3002 as formed through anodic oxidation. The
oxide films 3001 to 3002 are formed in the same manner as in
Embodiment 1.
[0263] As the material for the gate electrodes, also available is
any of metallic suicides and other metals of titanium, chromium or
the like, in place of aluminum. For example, as a conductive film
capable of being subjected to anodic oxidation, available is any of
a laminate film comprising tantalum (Ta) and tantalum nitride
(TaN), or a simple substance film of tantalum. On the surface of
the electrodes of that type, an oxide film of Ta.sup.2O.sup.5 may
be formed through anodic oxidation. As having higher heat
resistance than an aluminum film, the laminate film of tantalum
(Ta) and tantalum nitride (TaN) may be directly processed according
to the process of the invention without forming an oxide film
thereover through anodic oxidation.
[0264] Over the oxide films 3000 to 3002, formed are a silicon
nitride film 36 and a silicon oxynitride film 37. In place of the
silicon oxynitride film 37, a silicon oxide film may be formed. In
the pixel TFT and the CMOS circuit, the laminate of the silicon
nitride film 36 and the silicon oxynitride film 37 as formed over
the oxide films 3000 to 3002 functions as a gate-insulating
layer.
[0265] Over the silicon oxynitride film 37, formed is a crystalline
silicon film 3003 through laser crystallization as in Embodiment
1.
[0266] Next, phosphorus is added to the structure of FIG. 12A, in
which are formed an n.sup.+ layer 38, an n.sup.- layer 39 and an
i-layer 40 in the crystalline silicon film 3003, as in FIG. 12B.
For the details of these layers, referred to is the description of
Embodiment 1.
[0267] Next, boron, which is an element selected from Group 13, is
added to the region to be the PTFT of the CMOS circuit through ion
implantation or ion doping, while the area except this region is
masked with a resist mask (not shown). In this Embodiment, the
boron dose is three times the phosphorus dose in the previous step,
by which are formed a p.sup.++ layer 41 and a p.sup.- layer 42. In
this step, the type of the ion to be doped and the accelerated
voltage for the ion doping must be so controlled that an intrinsic
or substantially intrinsic i-layer 40 may remain below the p.sup.-
layer 42. For the details of the p.sup.++ layer 41 and the p.sup.-
layer 42, referred to is the description of Embodiment 5. (FIG.
12C)
[0268] Next, this is annealed with laser beams, by which the
crystallinity of the crystalline silicon film 3003 having become
partly amorphous due to the addition of phosphorus and boron
thereto is improved. The laser annealing activates the impurities
(phosphorus and boron) in the film 3003. Prior to this laser
annealing, the film 3003 may be dehydrogenated through RTA to
thereby prevent hydrogen bumping in the laser annealing step. (FIG.
12D)
[0269] Next, the crystalline silicon film 3003 is etched to form
island semiconductor layers 43 and 44. In this step, contact holes
are formed through the film 3003, through which a part of the gate
wiring is connected with the electrodes to be formed in the next
step (second wiring).
[0270] The laser annealing may be performed after the formation of
the island semiconductor layers 43 and 44 of the crystalline
silicon film.
[0271] Next, a thin conductive film is formed over the layers 43
and 44, and patterned to form source electrodes 45 (NTFT) and 46
(PTFT) and a common drain electrode 47 for the CMOS circuit. In the
same manner, a source electrode 48 and a drain electrode 49 for the
pixel TFT are informed. The electrode indicated by 50 functions
only as a mask, and this is referred to as a mask electrode herein.
(FIG. 13A)
[0272] The structure of FIG. 13A thus constructed is etched to form
channel-forming regions 51 to 54. In this case, the driver circuit
is so constructed that mask offset regions are formed adjacent to
the drain regions only of the both TFT, while overlapping regions
are formed adjacent to the both source regions.
[0273] In this, the pixel TFT is so constructed that mask offset
regions are formed adjacent to the source electrode 48 and to the
drain electrode 49, while an overlapping region is formed below the
mask electrode 50.
[0274] In the pixel TFT, the source/drain regions are switched
during charging and discharging for image information inputting.
Therefore, the both edges of the TFT must have high voltage
resistance. In this structure, if the concentration of the
resistance components is too high in the area below the mask
electrode 50, the switching motion of the device will be retarded.
In order to evade this problem, it is desirable that an overlapping
region is provided in this area to thereby facilitate the carrier
movement therethrough.
[0275] This Embodiment is to demonstrate one embodiment which is
considered to be the most preferred one, and is not limited to only
the structure illustrated herein. Producers may select the optimum
structure in combination with any of the structures of Embodiments
1 to 4, while taking the advantages of the structures of
Embodiments 1 to 4 into consideration.
[0276] Next, a protective film 55 of a silicon oxynitride film
having a thickness of 200 nm is formed over the structure of FIG.
13B, and this is further coated with an interlayer insulating film
of an organic resin film. To form the organic resin film 56,
available is any of polyimide, polyamide, polyimidamide or acrylic
resin.
[0277] Next, a contact hole is formed through the interlayer
insulating film 56, into which is formed a pixel electrode 57 of a
transparent conductive film (typically ITO). Finally, this is
hydrogenated to complete an active matrix substrate, as in FIG.
13C.
[0278] Next, a liquid crystal layer is put between the active
matrix substrate produced herein and a counter substrate, according
to a known cell-constructing method, to produce an
active-matrix-type liquid crystal display device.
[0279] To produce the active matrix substrate of this Embodiment,
seven patterning steps are necessary, which are as follows:
[0280] Gate electrode patterning.
[0281] boron-doped region patterning.
[0282] island semiconductor layer patterning.
[0283] Gate contact patterning.
[0284] Source/drain electrodes patterning.
[0285] ITO contact patterning.
[0286] ITO patterning.
[0287] As above, producing the active matrix substrate requires
only a small number of masks. Therefore, the throughput of the
display device comprising the substrate is greatly increased. In
addition, any desired circuits can be freely designed and formed on
the substrate while using the TFT of Embodiments 1 to 5. Therefore,
according to the technique of this Embodiment, display devices of
high reliability and high reproducibility are easy to realize.
[0288] FIG. 14A shows a top view of a part of the pixel matrix
circuit of this Embodiment, in which the reference numerals have
the same meanings as above. The part of this drawing not referred
to hereinabove is described below.
[0289] A cross-sectional view of FIG. 14A as cut along the line
A-A' is shown in FIG. 14B. Though not shown in FIG. 13C, a capacity
wiring 58 of an aluminum film, which is the same as that for the
gate wiring, is formed in parallel to the gate wiring, as in FIG.
14B. The surface of the capacity wiring 58 is subjected to anodic
oxidation to have an oxide film 3005 thereon.
[0290] The capacity wiring 58 provides a subsidiary capacitance
(Cs) in the region 1401 that overlaps with the drain electrode 50
(the region 1401 is surrounded by the dotted line in the drawing).
In this case, the gate-insulating layers 3005, 36 and 37 are the
dielectrics for the subsidiary capacitance. The constitution of the
subsidiary capacitance is not limited to only the embodiment
illustrated in this Embodiment.
[0291] [Embodiment 11]
[0292] Embodiment 10 is to demonstrate an embodiment of using a
semiconductor film as crystallized through laser irradiation to
form a driver circuit (peripheries-driving circuit) and a pixel
matrix circuit as integrated on one substrate. Being different from
that, this Embodiment is to demonstrate an embodiment of
crystallizing a semiconductor film through RTA.
[0293] FIG. 15A to FIG. 15D show a process of the embodiment of
this Embodiment. In those drawings, the numeral references have the
same meanings as those in FIG. 12A to FIG. 12D. An amorphous
silicon film having a thickness of from 100 to 600 nm is formed on
a silicon oxynitricle film 37. In this Embodiment, the thickness of
the amorphous silicon film is 200 nm. Next, the amorphous silicon
film is crystallized through RTA for solid phase crystal growth, as
in Embodiment 9, to convert it into a crystalline silicon film
3004.
[0294] In the crystallization step of this Embodiment, used is a
halogen lamp (peak wavelength: 1.15 _m, wavelength range: 0.4 to 4
_m). The light from the lamp is linearly focused to give a linear
beam having a width of 10 mm, and scanned over the substrate.
Depending on the scanning rate, the exposure time was controlled to
fall between 10 and 60 seconds but typically between 15 and 30
seconds. By controlling the output of the halogen lamp, the
amorphous silicon film is heated at 700 to 1000_C. In this
Embodiment, the scanning rate is 0.5 mm/sec (this corresponds to an
exposure time of 20 seconds), the output of the halogen lamp is 7.7
W, and the amorphous silicon film is thus heated at about 920_C to
be crystallized into the crystalline silicon film 3004.
[0295] After the crystallization through RTA, the crystalline
silicon film 3004 is annealed by exposing it to laser beams of
excimer laser, YAG laser or the like or to intense light equivalent
to such laser beams. The annealing is to additionally crystallize
the amorphous component still remaining in the crystalline silicon
film 3004 to thereby enhance the crystallinity of the film
3004.
[0296] Solid phase crystallization in an electric furnace takes
tens hours, but RTA crystallization takes only tens seconds.
Therefore, the latter is advantageous in that the throughput of the
devices produced is high and that the thermal damage to glass
substrates is small.
[0297] After the RTA crystallization, the crystalline silicon film
3004 is processed in the same manner as in Embodiment 10. Briefly,
as in FIG. 15B, phosphorus is added to the film 3004 to form an
n.sup.+ layer 38, an n.sup.- layer 39, and an i-layer 40. Next,
boron is added thereto to form a p.sup.++ layer 41 and a p.sup.-
layer 42, as in FIG. 15C.
[0298] Next, this is annealed with laser beams, as in FIG. 15D, by
which the crystallinity of the crystalline silicon film 3004 having
become partly amorphous due to the addition of phosphorus and boron
thereto is improved. The laser annealing activates the impurities
(phosphorus and boron) in the film 3004. Prior to this laser
annealing, the film 3004 may be dehydrogenated through RTA to
thereby prevent hydrogen bumping in the laser annealing step.
[0299] Next, the structure of FIG. 15D is processed according to
the process of Embodiment 10 illustrated in FIG. 13A to FIG. 13C
and FIG. 14A and FIG. 14B, whereby is formed an active-matrix-type
display device having a driver circuit and a pixel matrix circuit
as integrated on the substrate.
[0300] [Embodiment 12]
[0301] This Embodiment is to demonstrate still another embodiment
of producing an active-matrix-type display device, which is
different from the embodiments of Embodiments 10 and 11.
[0302] The process of this Embodiment is characterized in that the
fusion crystallization with laser beams or the solid phase
crystallization through RTA is not followed by laser annealing for
improving the crystallinity of the crystalline film formed. In
other words, in this Embodiment, the crystalline film formed is
directly subjected to the next step of adding phosphorus to the
film. In this, the phosphorus addition may be performed in the same
manner as in Embodiment 10.
[0303] Specifically, the process of this Embodiment is
characterized in that the crystallinity of the channel-forming
region is improved (in this step, the impurities added are
activated, and the film is recrystallized) after a protective film
55 is formed as in FIG. 16. In this process, the channel-forming
regions 51 to 54 are self-alignedly exposed to laser beams via the
protective film 55 of a silicon oxynitride film.
[0304] The laser annealing of the structure of FIG. 16 is
advantageous in that it prevents out-diffusion of impurities of
phosphorus and boron from the source/drain regions and that the
power of the laser beams (laser energy) necessary for it may be
reduced to a half or so.
[0305] This Embodiment is not limited to only the structure
illustrated in the drawings. Producers may select the optimum
structure in combination with any of the TFT structures of
Embodiments 1 to 4, while taking the advantages of those structures
of Embodiments 1 to 4 into consideration, for designing the
intended circuits. This Embodiment may be combined with any
structures of all other Embodiments.
[0306] [Embodiment 13]
[0307] This Embodiment is to demonstrate still another embodiment
of producing an active-matrix-type display device, in which the
laser annealing step just after the crystallization step in the
processes of Embodiments 10 and 11 is omitted, like in Embodiment
12. In this Embodiment, the crystallization step is followed by ion
doping for adding phosphorus to the crystalline silicon film to
form the n.sup.+ layer 38 and the n.sup.- layer 39 (see FIG. 12B,
FIG. 15B). Next, boron is added thereto also through ion doping to
form the p.sup.++ layer 41 and the p.sup.- layer 42 for PTFT in the
semiconductor layer (see FIG. 12C, FIG. 15C).
[0308] The structure thus produced is subjected to RTA. In this
Embodiment, this RTA treatment is to active the impurities added
(phosphorus and boron) and to dehydrogenate the semiconductor layer
(since hydrogen ions are implanted into the layer along with
phosphorus and boron ions in the ion doping not followed by mass
separation). (FIG. 17A)
[0309] Next, this is annealed with laser beams. In this step, the
semiconductor layer having become amorphous in the previous steps
of adding the impurities is recrystallized to improve the
crystallinity of the layer. If desired, this laser annealing step
may be performed after the semiconductor layer is etched to give an
island semiconductor layer.
[0310] After this, the structure is processed in the same manner as
in Embodiment 10. This Embodiment is not limited to only the
structure illustrated in the drawings. Producers may select the
optimum structure in combination with any of the TFT structures of
Embodiments 1 to 4, while talking the advantages of those
structures of Embodiments 1 to 4 into consideration, for designing
the intended circuits. This Embodiment may be combined with any
structures of all other Embodiments.
[0311] [Embodiment 14]
[0312] This Embodiment is to demonstrate the production of a
reflection-type liquid crystal display device, based on the process
of Embodiment 10. FIG. 18A shows a top view of one pixel of a pixel
matrix circuit of a reflection-type liquid crystal display
device.
[0313] In FIG. 18A, the parts corresponds to those in Embodiment 10
are designated by the same numerals as in Embodiment 10, and the
detailed description of the parts is omitted herein. FIG. 18B is a
cross-sectional view of FIG. 18A as cut along the line B-B'.
[0314] The difference between Embodiment 14 and Embodiment 10 is
that the capacity wiring 59 covers the entire area of the pixel in
the former. Being different from the transmittance-type device of
Embodiment 10, the reflection-type device of this Embodiment 14 is
not required to have a large aperture. Therefore, in this, the back
surface of the pixel electrode 61 could be everywhere in
service.
[0315] In this Embodiment, the drain electrode 60 is so positioned
that it covers the entire area of the pixel and overlaps with the
capacity wiring 59 in a largest possible range. In that manner,
almost all area of the pixel can be utilized as the subsidiary
capacitance, whereby the device may have a large capacity. The
dielectrics for the subsidiary capacitance are the oxide film 3005
formed through anodic oxidation, the silicon nitride film 36 and
the silicon oxynitride film 37.
[0316] The pixel electrode 61 is a reflective electrode, and it is
desirable that the electrode is made from aluminum having high
reflectivity or from a material comprising mainly aluminum. Where
the liquid crystal display device of this Embodiment is used in
projection-type displays, it is desirable that the pixel electrode
has a flat and smooth surface. On the other hand, where it is used
in direct viewing displays, the surface of the pixel electrode must
be roughened to make it have an increased irregular reflectivity
and have a broadened angle of visibility.
[0317] This Embodiment is not limited to only the structure
illustrated in the drawings. Producers may select the optimum
structure in combination with any of the TFT structures of
Embodiments 1 to 4, while taking the advantages of those structures
of Embodiments 1 to 4 into consideration, for designing the
intended circuits. This Embodiment may be combined with any
structures of all other Embodiments.
[0318] [Embodiment 15]
[0319] This Embodiment is to demonstrate a modification of the
liquid crystal display device of Embodiment 10. Herein formed are
BM (black matrices) in the device.
[0320] According to the process of Embodiment 10, a layered
structure having an interlayer insulating film 56 is formed. In
this Embodiment, the interlayer insulating film 56 is made of a
photosensitive acrylic resin. The interlayer insulating film 56 is
patterned, and half-etched to form depressions 65 and 66. (FIG.
19A)
[0321] The entire surface of the structure of FIG. 19A is coated
with a black resin film (not shown). The black resin film is an
organic resin film containing graphite, carbon, dye or the like.
The organic resin film may be a film of polyimide, acrylic resin or
the like. In this Embodiment, used is a photosensitive acrylic
resin containing graphite as dispersed therein.
[0322] After thus coated with the black resin film, the region of
the depressions 65 and 66 only is selectively exposed, whereby the
black resin film remains only in that region. Next, this may be
ashed in an oxygen plasma atmosphere to thereby increase the
surface smoothness of the black resin films remained.
[0323] In that manner, formed are black matrices 67 and 68 of the
black resin. Next is formed a pixel electrode 69 of an ITO film. In
this Embodiment, the pixel electrode 69 is so patterned that the
edge of the pixel electrode 69 overlaps with the edge of the black
matrix 68 (that is, the edge of the pixel electrode 69 is inside
the BM, black matrix 68, as so indicated by 70).
[0324] As in the above, completed is an active matrix substrate
having the structure of FIG. 19B. This is used in ordinary cell
construction to produce liquid crystal display devices. The black
matrices produced in this Embodiment have the advantage of not
producing parasitic capacitance with other wiring parts.
[0325] This Embodiment is not limited to only the structure
illustrated in the drawings. Producers may select the optimum
structure in combination with any of the TFT structures of
Embodiments 1 to 4, while taking the advantages of those structures
of Embodiments 1 to 4 into consideration, for designing the
intended circuits. This Embodiment may be combined with any
structures of all other Embodiments.
[0326] [Embodiment 16]
[0327] This is to demonstrate a modification of Embodiment 15, with
reference to FIG. 20 and FIG. 21. The black matrices formed herein
are different from those in Embodiment 15. Concretely, a conductive
film is used to form the black matrices herein.
[0328] In FIG. 20, 56 is an interlayer insulating film of an
organic resin film, and 71 to 74 are black matrices or wiring
patterns acting also as black matrices, which are made of a
conductive film. The conductive film may be any of titanium film,
chromium film, titanium/aluminum laminate film or the like.
[0329] As being conductive, the black matrices in this Embodiment
have various additional functions. The pattern 71 is a black matrix
as fixed to the common voltage (earth voltage). The pattern 72 is
connected with the drain electrode of a CMOS circuit, and is used
as a lead wire. In that manner, this Embodiment easily realizes a
multi-layered wiring structure.
[0330] The pattern 73 is connected with the source electrode of the
CMOS circuit, and functions as a connection wire and also as a
black matrix. The pattern 74 is a black matrix as positioned in the
pixel matrix circuit, and this is basically provided over the other
wiring patterns and TFT.
[0331] Over the black matrices (or wiring patterns also acting as
black matrices) 71 to 74, further provided is an interlayer
insulating film 75. The interlayer insulating film 75 may be made
of a silicon oxide film, a silicon nitride film, a silicon
oxynitride film, an organic resin film or a laminate of those
films. The interlayer insulating film 75 functions later as the
dielectric for subsidiary capacitance.
[0332] Through the interlayer insulating film 75, formed is a
contact hole, in which is formed a pixel electrode 76 of ITO. In
the pixel matrix circuit, the black matrix 74 and the pixel
electrode 76 produce subsidiary capacitance 77.
[0333] FIG. 21 shows one embodiment of the positioning of black
matrices in the pixel matrix circuit. In the embodiment of FIG. 21,
a black matrix 78 is positioned to overlap with the structure of
FIG. 14A. In FIG. 21, the thick line 79 is a pixel electrode, and
80 is a contact part at which the pixel electrode 79 is contacted
with the underlying drain electrode.
[0334] The black matrix 78 basically covers the other wiring
patterns and TFT, while having opening windows only in the
image-displaying region 81 and the contact part 80. For
transmission-type liquid crystal display devices such as that
illustrated in this Embodiment, the most important matter is to
reduce the area that is occupied by the black matrices to thereby
broaden the area of the image-displaying region 81 (that is, to
increase the aperture of the device).
[0335] This Embodiment is not limited to only the structure
illustrated in the drawings. Producers may select the optimum
structure in combination with any of the TFT structures of
Embodiments 1 to 4, while taking the advantages of those structures
of Embodiments 1 to 4 into consideration, for designing the
intended circuits. This Embodiment may be combined with any
structures of all other Embodiments.
[0336] [Embodiment 17]
[0337] This is to demonstrate still another embodiment of producing
an active matrix substrate, in which the TFT structure differs from
that illustrated in Embodiment 10. Herein referred to is FIG.
22.
[0338] The most important point in the structure of FIG. 22 is that
the uppermost part of each semiconductor layer (in source/drain
regions) is a first conductive layer (n.sup.+ region or p.sup.++
region), and that each conductive layer is covered with a
protective film 55 and an interlayer insulating film 56, and is
electrically connected with lead electrodes 81 to 85.
[0339] To produce the illustrated structure, channel etching to
give the channel-forming regions is performed via resist masks.
After the channel etching in that manner, the protective film 55
and the interlayer insulating film 56 are formed over the
conductive layers, and thereafter the lead electrodes 81 to 85 are
formed.
[0340] In the structure of this Embodiment, the lead electrodes
(these function as source/drain electrodes or as rounding wires) 81
to 85 are spaced from the gate electrode by the interlayer
insulating film 56. Accordingly, in this structure, the parasitic
capacitance between the source/drain electrodes and the gate
electrode can be much more reduced. More effectively, the
interlayer insulating film 56 is made from an organic resin
material having a small dielectric constant.
[0341] The structure of this Embodiment is applicable to TFT of
Embodiments 1 to 4. Needless-to-say, it can be combined with any
structures of all other Embodiments. This Embodiment is not limited
to only the structure illustrated in the drawings. Producers may
select the optimum structure in combination with any of the TFT
structures of Embodiments 1 to 4, while taking the advantages of
those structures of Embodiments 1 to 4 into consideration, for
designing the intended circuits.
[0342] [Embodiment 18]
[0343] This is to demonstrate one embodiment of connecting the
active matrix substrate of any of Embodiments 10 to 18 with
external terminals, with reference to FIG. 23. FIG. 23 is an
enlarged view of a connecting site at which the active matrix
substrate is connected with an external terminal (typically,
flexible print circuit, FPC). The connecting site is referred to as
an FPC connecting site, and this is positioned at the edge of the
active matrix substrate.
[0344] In FIG. 23, 101 is a glass substrate, and 86 is an
insulating layer. The insulating layer 86 has a laminate structure
comprising the undercoating film 102, the silicon nitride film 104
and the silicon oxynitride film 105 all shown in FIG. 1(A). A
second wiring layer 87 is formed over the substrate 101 and the
layer 86. The second wiring layer 87 is a connecting wire layer via
which the information from the external terminal is transmitted to
the source/drain electrodes, the gate electrode, etc.
[0345] This Embodiment is characterized in that the second wiring
layer 87 is in direct contact with the glass substrate 101. To
realize this structure, the insulating layer 86 below the FPC
connecting site must be completely removed in the third patterning
step in the process of Embodiment 1. In this structure, the second
wiring layer 87 is directly formed on the hard glass substrate.
Therefore, in this, FPC is firmly fixed to the second wiring layer
87 in the FPC connecting site.
[0346] In the FPC connecting site, the interlayer insulating film
56 is partially removed in the subsequent step, whereby the
overlying ITO film 57 is directly contacted with the second wiring
layer 87. In this structure, the ITO film 57 is so laminated over
the second wiring layer 87 that it is directly contacted with at
least the second wiring layer 87 in the FPO connecting site. As the
case may be, an independent pattern of an electrode pad of the ITO
film 57 may be formed only in the FPC connecting site.
[0347] The ITO film 57 functions as a buffer layer for anisotropic
conductive films 88 to be formed in the subsequent step. The
anisotropic conductive films 88 contain conductive particles (of
gold-coated silica glass or the like), and the conductive particles
are pushed into the ITO film to improve the ohmic contact between
the FPC terminal 89 and the ITO film 57.
[0348] At the FPC connecting site having the constitution shown in
FIG. 23, the FPC terminal 89 is pressed against the active matrix
substrate via the anisotropic conductive films 88 formed
therebetween. In that manner, the external terminal, FPC is
connected with the active matrix substrate, as in FIG. 23. The
connecting mode illustrated herein may be applied to the active
matrix substrate of any of Embodiments 10 to 20 to attain good
electrical connection of the substrate to external terminals.
[0349] [Embodiment 19]
[0350] This is to demonstrate one embodiment for improving the
patterning efficiency in forming TFT of the invention on large-area
glass substrates.
[0351] Where fine semiconductor circuits are formed on large-area
glass substrates, there occurs a problem of patterning error doe to
warping or shrinkage of glass substrates. To solve this problem,
specifically noted is an exposing method where is used an exposing
device of a so-called stepper. In stepper exposure, only a part of
one reticule 90 can be selectively exposed.
[0352] In this Embodiment, the necessary circuit patterns for the
driver circuit and the pixel matrix circuit are formed in different
portions of one reticule. In this case, the region for the
repetition of one and the same structure is formed through
repetitive exposure for one and the same circuit pattern.
[0353] FIG. 24 is referred to, in which patterns A, C, G and I are
circuit patterns for forming the edges of the driver circuit;
patterns B and H are repetitive circuit patterns for the driver
circuit to be scanned horizontally; patterns D and F are repetitive
circuit patterns for the driver circuit to be scanned vertically;
and a pattern E is a repetitive circuit pattern for the pixel
matrix circuit.
[0354] In that manner, for the driver circuit and the pixel matrix
circuit that are comprising repetitive circuits having the same
structure unit, only their edges are formed of their own
independent circuit patterns while their inside areas are formed of
one and the same circuit pattern unit to be repeated, and these are
combined to give the complete patterns.
[0355] In this system, the same circuit pattern units may be used
in forming the complete patterns. Therefore, in this, the number of
the circuit pattern units to be written in one reticule may be
reduced, and the size of the reticule to be used may be reduced. In
addition, in this, since one reticule can be repeatedly used many
times for large-area substrates, the time for mask changing is
reduced and the throughput of the device formed is increased.
[0356] For example, for a pixel matrix circuit of SXGA, 1280 pixels
are aligned in rows and 1024 pixels in columns. For this, the
pattern circuits corresponding to 256 pixels may be written in rows
for the pattern E, and five repetitive exposures may be done for
those rows; while the pattern circuits corresponding to 256 pixels
may be written in columns, and four repetitive exposures may be
done for those columns.
[0357] In this system where the number of repetitive exposures in
rows and in columns are represented by n and m, respectively, while
the number of pixels in rows and in columns are by X and Y,
respectively, X/n pixel patterns in rows and Y/m patterns in
columns must be written for the circuit patterns to form the pixel
matrix circuit. According to this regularity, high-precision
displays with 1920.times.1080 pixels, such as ATV (advanced TV),
can be easily realized.
[0358] [Embodiment 20]
[0359] This is to demonstrate one embodiment of AMLCD
(active-matrix-type liquid crystal display) comprising the active
matrix substrate of any of Embodiments 10 to 17. The AMLCD of this
Embodiment comprises inverse stagger-type TFT for the driving
circuit and the pixel matrix circuit as formed on one and the same
substrate. In this, the basic structure of the driving circuits is
designed on the basis of a CMOS circuit. Therefore, the power for
the AMLCD of this Embodiment is low.
[0360] FIG. 25A and FIG. 25B show the outward appearance of the
AMLCD of this Embodiment. In FIG. 25A, 1101 is an active matrix
substrate, on which is mounted a TFT of the invention that
comprises a pixel matrix circuit 1102, a source driving circuit
1103 and a gate driving circuit 1104. In this, 1105 is a counter
substrate.
[0361] The active matrix substrate 1101 and the counter substrate
1105 are stuck together with their one end being aligned. At the
other end, the counter substrate 1105 is partly cut, and FPC
(flexible print circuit) 1106 is connected with the exposed area of
the active matrix substrate. Via the FPC 1106, external information
is transmitted into the inside of the circuit.
[0362] On the exposed area of the active matrix substrate connected
with the FPC 1106, mounted are IC chips 1107 and 1108. These IC
chips comprise various circuits, such as video
information-processing circuit, timing pulse-generating circuit,
-co rrecting circuit, memory circuit, arithmetic circuit, etc., as
formed on silicon substrates. In FIG. 25C, two IC chips are mounted
on the active matrix substrate. However, one IC chips or three or
more IC chips may be mounted thereon.
[0363] FIG. 25B is another modification of AMLCD of this
Embodiment. In FIG. 25A and FIG. 25B., the same parts are
represented by the same numeral references. The embodiment of FIG.
25A differs from that of FIG. 25A in that the signal information as
processed by the IC chips in FIG. 25A is processed by the logic
circuit 1109 of TFT formed on the substrate in the embodiment of
FIG. 25B.
[0364] In the embodiment of FIG. 25B, the basic structure of the
logic circuit 1109 may be designed on the basis of a CMOS circuit,
like that in the driving circuits 1103 and 1104, for which is used
the inverse stagger-type TFT of the invention.
[0365] TFT of the invention are usable not only as switching
elements for AMLCD but also as those for EL (electroluminescent)
display devices. In addition, bottom-gate-type TFT of the invention
are usable in circuits for image sensors, etc.
[0366] As in the above, TFT of the invention are applicable to
various electro-optical devices. The terminology "electro-optical
device" as referred to herein includes any and every device for
converting electric information into optical information and vice
verse.
[0367] In the AMLCD of this Embodiment, the black matrices may be
formed on the counter substrate, or on the active matrix substrate
(BM on TFT).
[0368] Color filters may be used for color imaging through the
device of this Embodiment. Without using color filters, the liquid
crystal molecules in the device of this Embodiment may be driven in
ECB (electric field control birefringence) mode, GH (guest-host)
mode or the like.
[0369] Like the technique disclosed in Japanese Patent Application
Laid-Open (JP-A) Hei-815686, the device of this Embodiment may be
combined with a micro-lens array.
[0370] [Embodiment 21]
[0371] AMLCD of Embodiment 20 is usable as the display in various
electronic instruments. Electronic instruments as referred to
herein are directed to those comprising electro-optical devices
such as typically AMLCD.
[0372] The electronic instruments include video cameras, still
cameras, projectors, projection TV, head-mount displays, car
navigations, personal computers (including notebook-type ones),
portable information terminals (mobile computers, portable
telephones, etc.), etc. Some examples of those electronic
instruments are shown in FIG. 26A to FIG. 26F.
[0373] FIG. 26A is a portable telephone. Its body 2001 is provided
with a voice-outputting member 2002, a voice-inputting member 2003,
a display device 2004, a control switch 2005, and an antenna 2006.
In this, the invention is applicable to the display device 2004,
etc.
[0374] FIG. 26B is a video camera. Its body 2101 is provided with a
display device 2102, a voice-inputting member 2103, a control
switch 2104, a battery 2105, and an image-receiving member 2106. In
this, the invention is applicable to the display device 2102.
[0375] FIG. 26C is a mobile computer. Its body 2201 is provided
with a camera member 2202, an image-receiving member 2203, a
control switch 2204, and a display device 2205. In this, the
invention is applicable to the display device 2205, etc.
[0376] FIG. 26D is a head-mount display. Its body 2301 is provided
with a display device 2302, and a band member 2303. In this, the
invention is applicable to the display device 2302.
[0377] FIG. 26E is a rear projector. Its body 2401 is provided with
a light source 2402, a display device 2403, a polarized beam
splitter 2404, reflectors 2405 and 2406, and a screen 2407. In
this, the invention is applicable to the display device 2403.
[0378] FIG. F is a front projector. Its body 2501 is provided with
a light source 2502, a display device 2503, an optical system 2504,
and a screen 2505. In this, the invention is applicable to the
display device 2503.
[0379] As in the above, the present invention has extremely broad
application ranges, and is applicable to various electronic
instruments in various fields. Apart from the examples noted above,
the invention is applicable to light bulletin boards, advertising
propaganda displays, etc.
[0380] [Embodiment 22]
[0381] This is to demonstrate one embodiment of the constitution of
a circuit comprising the inverse stagger-type TFT of the invention.
Herein referred to are FIG. 27A and FIG. 27B that illustrate the
constitution of a shift register circuit. In this Embodiment,
employed is the layer structure of Embodiment 10.
[0382] FIG. 27A shows a circuit pattern of one stage of a shift
register circuit, and FIG. 27B shows the equivalent circuit pattern
of the shift register circuit. In this Embodiment, the positional
relationship between FIG. 27A and FIG. 27B nearly corresponds to
each other. Therefore,, the reference codes in FIG. 27B are
referred to in FIG. 27A.
[0383] In FIG. 27A, the circuit comprising TFT (a) to TFT (d) and
TFT (g) to TFT (j) is a clocked inverter circuit; and the circuit
comprising TFT (e) and TFT (f) is an inverter circuit. TFT (e) has
a double-gate structure.
[0384] In this, 1201 is a CLK line (clock signal line), 1202 is an
inverse CLK line (inverse clock signal line), 1203 is a GND wiring
line (ground line), and 1204 is a Vdd line (power source line).
Those wiring patterns as shadowed with lines rising to the left are
all second wiring layers (indicated by 45 to 49 in FIG. 13A).
[0385] The wiring 1205 functions as the gate electrode of TFT (a).
The wiring patterns as shadowed with lines rising to the right are
all first wiring layers (indicated by 32 to 35 in FIG. 12A). The
area in which the first wiring layer overlaps with the
semiconductor layer is referred to as the gate electrode.
[0386] In the constitution of this Embodiment, overlapping regions
(ov in FIG. 27B) are provided in the source side of TFT, while mask
offset regions (of in FIG. 27B) are in the drain side thereof.
Accordingly, in FIG. 27B, the clocked inverter circuit comprising
TFT (a) to TFT (d) has a constitution of ov/of/ov/of/of/ov/of/ov in
that order from the top.
[0387] Specifically, the structure of the part of TFT (a) and TFT
(b) is nearly the same as the double-gate structure of the pixel
TFT in Embodiment 10, and therefore this part has a repetition of
ov/of/ov/of. On the other hand, the part of TFT (b) and TFT (c) has
a CMOS structure in which the drain electrode is common to NTFT and
PTFT. Therefore, as in Embodiment 5, this part has a repetition of
ov/of/of/ov.
[0388] The other circuits are basically the same as above. TFT (e)
has a double-gate structure, and therefore has a repeated TFT
structure of ov/of/ov/of in that order from its side to which it is
connected with the GND line 1203.
[0389] As having the constitution noted above, the semiconductor
circuit of this Embodiment has high voltage resistance and high
reliability without sacrificing its operating motion speed. Using
the semiconductor circuit of the type of this Embodiment in
electro-optical devices improves the reliability of the
devices.
[0390] [Embodiment 23]
[0391] This is to demonstrate another embodiment of the
constitution of a circuit comprising the inverse stagger-type TFT
of the invention. Herein referred to are FIG. 28A and FIG. 28B that
illustrate the constitution of a buffer circuit (the left side of
the drawings) and an analog switch circuit (the right side of the
drawings). In this Embodiment, employed is the layer structure of
Embodiment 20. FIG. 28A shows a circuit pattern, and FIG. 28B shows
the equivalent circuit pattern of FIG. 28A.
[0392] In FIG. 28(A), TFT (a') to TFT (h') are TFT of the
invention. In this, TFT (a') and TFT (c'), and TFT (b') and TFT
(d') form one buffer circuit each. Like the pixel matrix circuit,
the buffer circuit is driven at a highest operating voltage in
liquid crystal display devices, and is therefore required to have
high voltage resistance.
[0393] TFT (e') and TFT (f'), and TFT (g') and TFT (h') (pairs for
PTFT) form one analog switch circuit each. Also like the pixel
matrix circuit, the analog switch circuit is driven at a highest
operating voltage in liquid crystal display devices, and is
therefore required to have high voltage resistance.
[0394] First referred to herein is the buffer circuit comprising
TFT (a') and TFT (c'). 1201 is a source electrode (Vdd line) for
TFT (a'); 1202 is a source electrode (GND line) for TFT (c'); 1203
is a common drain electrode (output signal line) for TFT (a') and
TFT (c'); and 1204 is a common gate electrode (input signal line)
for the two TFT.
[0395] 1205 is a first conductive layer (n.sup.+ layer) in the side
of the drain region; 1206 is a first conductive layer (n.sup.+
layer) in the side of the source region; and 1307 is a thin
i-layer. TFT (c') has the same structure as above, except that a
p.sup.++ layer is substituted for the n.sup.+ layer.
[0396] The buffer circuit has the structure of Embodiment 5 in
order to have high voltage resistance. Specifically, in this
circuit, an overlapping region (ov) is formed in the source side
and a mask offset region (of) is in the drain side. In that
condition, only the drain region is made to have high voltage
resistance, while the resistance component in the source region is
reduced.
[0397] The same structure can apply to the buffer circuit
comprising TFT (b') and TFT (d').
[0398] Next referred to is the analog switch circuit comprising TFT
(e') and TFT (f'). The gate electrode 1204 in the buffer circuit
noted above is connected with the gate electrode for TFT (e'),
while the common drain electrode for TFT (a') and TFT (c') is with
the gate electrode for TFT (f').
[0399] 1208 and 1210 are common source electrodes (input data
signal lines) in the analog switch circuit; and 1209 is a common
drain electrode (output data signal line). The electrode 1208 is
for TFT (e') and TFT (f'); while the electrode 1210 is for TFT (g')
and TFT (h'). These electrodes 1208 and 1210 transmit different
image signals.
[0400] In this structure, when any one of TFT (e') or TFT (f) is
"ON", the data signal (image signal) transferred from the input
data signal line 1208 is transmitted to the pixel matrix circuit
via the output data signal line 1209. Therefore, also in TFT (e')
and TFT (f') constituting the analog switch circuit, a mask offset
region is provided in the drain side and an overlapping region is
in the source side.
[0401] The same structure can apply to the buffer circuit
comprising TFT (g') and TFT (h').
[0402] [Embodiment 24]
[0403] This embodiment shows an example in which at the formation
steps of the gate insulating film and the semiconductor film
(amorphous silicon film) in the manufacturing steps of each
Embodiment 1 to Embodiment 26, the respective films are
continuously formed without being exposed to the atmosphere.
[0404] As a method of forming the gate insulating film and the
semiconductor film, any method such as plasma CVD method and
sputtering method can be employed. However, it is important to
prevent contamination materials of the atmosphere (oxygen, boron,
metal elements or the like) from attaching to the interface between
the gate insulating film and the semiconductor film by avoiding
exposure of the films to the atmosphere. In this embodiment, a
multi-chamber (for instance, a device shown in FIG. 29) that is
provided with an exclusive chamber for forming the gate insulating
film and an exclusive chamber for forming starting semiconductor
film, is used, and by moving each chamber, the gate insulating film
and the semiconductor film are continuously formed so as to form a
lamination without being exposed to the atmosphere. Incidentally,
it is preferable to reduce the contamination material on the
surface, where the semiconductor film is to be formed, by means of
active hydrogen or hydrogen compounds before forming the
semiconductor film.
[0405] FIG. 29 schematically shows a device (a continuous film
formation system) viewed from the top thereof, which will be
described in this embodiment. In FIG. 29, reference numerals
2912-2916 denote chambers having air-tight property. A vacuum
discharge pump and an inert gas introducing system are arranged in
each chamber.
[0406] The present embodiment is applied to the cases in which the
gate insulating film and the semiconductor film of Embodiment 1 are
formed.
[0407] Chambers denoted by 2912 and 2913 serve as load-lock
chambers for carrying a sample (substrate to be processed) 2910
into the system. Reference numeral 2914 denotes a first chamber for
forming the gate insulating film (a first layer). Numeral 2915
denotes a second chamber for forming the gate insulating film (a
second layer). Numeral 2916 denotes a third chamber for forming the
semiconductor film (amorphous silicon film). Also, numeral 2911
denotes a common chamber of the sample, which is disposed commonly
to each chamber. Reference numerals 2923-2927 denote gate valves of
each chamber; 2931, a robot arm; 2933 and 2934, cassettes. In this
embodiment, the case in which the gate insulating film has a
double-layer structure is shown. It is needless to say, however,
that the present embodiment is also applicable to a case in which
the gate insulating film has a single-layer structure, and for
example, to the case in which the gate insulating film is consisted
from silicon oxide only.
[0408] In this embodiment, in order to prevent the contamination,
the gate insulating film and the semiconductor film are formed so
as to form a lamination by different chambers from each other
utilizing the device shown in FIG. 29. It is a matter of course
that the device shown in FIG. 29 is just an example.
[0409] Also, an arrangement is applicable in which a lamination is
carried out by changing reaction gases within a single chamber.
When serial film formation is conducted within the single chamber,
it is preferable to reduce the contamination material, in
particular, oxygen (because oxygen inhibits the crystallization) on
the surface, where the semiconductor film is to be formed, by means
of the active hydrogen or hydrogen compounds before forming the
semiconductor film. In this case, degassing is carried out by
changing oxygen attached to an inner wall of the chamber and
electrodes into OH group by utilizing active hydrogen or hydrogen
compounds which are generated from plasma process that uses a
reaction gas such as hydrogen/NH.sub.3, H.sub.2, Ar and He.
Accordingly, oxygen is prevented from mixing in upon the formation
of the semiconductor film at the initial stage. Further, at the
formation of each film, the same temperature(50_C) and the same
pressure (20%) are preferably used.
[0410] With the above arrangement, contamination of the gate
insulating film and the semiconductor film is prevented to thereby
realize stable and good electrical characteristics.
[0411] As in the above, using the semiconductor device structure of
the present invention in semiconductor circuits that are required
to have high voltage resistance realizes the increase in the
reliability of the semiconductor circuits. This is important for
producing electro-optical devices of high reliability.
[0412] As has been described in detail hereinabove with reference
to its embodiments, the present invention provides a technique of
producing TFT on a mass-production scale in which is used an
extremely small number of masks (typically, 4 masks).
[0413] According to the present invention, it is possible to form
electric field buffer layers (LDD region, mask offset region,
thickness offset region, etc.) for absorbing data fluctuations,
between the channel-forming region and the source/drain electrodes
in semiconductor devices. Providing the semiconductor devices of
that type, therefore, the present invention realizes TFT of high
reliability and high reproducibility.
[0414] In addition, the present invention is applicable to
semiconductor devices of any and every type, including
semiconductor circuits comprising TFT noted above, electro-optical
devices comprising a combination of such semiconductor circuits and
liquid crystal layers, etc., and even electronic instruments
comprising displays of such electro-optical devices.
[0415] While the invention has been described in detail and with
reference to specific embodiments thereof, it will be apparent to
one skilled in the art that various changes and modifications can
be made therein without departing from the spirit and scope
thereof.
* * * * *