U.S. patent application number 09/922103 was filed with the patent office on 2001-12-06 for stackable ball grid array semiconductor package and fabrication method thereof.
This patent application is currently assigned to Hyundai Electronics Industries Co., Inc.. Invention is credited to Chun, Dong Seok.
Application Number | 20010048151 09/922103 |
Document ID | / |
Family ID | 19537977 |
Filed Date | 2001-12-06 |
United States Patent
Application |
20010048151 |
Kind Code |
A1 |
Chun, Dong Seok |
December 6, 2001 |
Stackable ball grid array semiconductor package and fabrication
method thereof
Abstract
A stackable Ball Grid Array (BGA) semiconductor chip package and
a fabrication method thereof increases reliability and mount
density of a semiconductor package. The stackable BGA semiconductor
chip package includes a supporting member that includes a
supporting plate and a supporting frame formed on edges of the
supporting plate. Conductive patterns are formed in and extend
through the supporting member. First metal traces are formed on a
bottom of the supporting plate and the first metal traces are
connected to first ends of the conductive patterns in the
supporting member. Second metal traces are attached to an upper
surface of a semiconductor chip, and the semiconductor chip is
attached to the supporting member. The second metal traces are
connected to bond pads of the chip, and to upper ends of the
conductive patterns in the supporting member. A plurality of
conductive balls are then attached to exposed portions of the first
and/or the second metal traces.
Inventors: |
Chun, Dong Seok;
(Choongcheongbuk-Do, KR) |
Correspondence
Address: |
FLESHNER & KIM, LLP
P.O. Box 221200
Chantilly
VA
20153-1200
US
|
Assignee: |
Hyundai Electronics Industries Co.,
Inc.
|
Family ID: |
19537977 |
Appl. No.: |
09/922103 |
Filed: |
August 6, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09922103 |
Aug 6, 2001 |
|
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09239152 |
Jan 28, 1999 |
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6291259 |
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Current U.S.
Class: |
257/686 ;
257/738; 257/777; 257/778; 257/E23.124; 257/E23.19;
257/E25.023 |
Current CPC
Class: |
H01L 2225/1058 20130101;
H01L 2224/73219 20130101; H01L 23/3107 20130101; H01L 24/50
20130101; H01L 23/055 20130101; H01L 2924/181 20130101; H01L 24/86
20130101; H01L 25/105 20130101; H01L 2924/181 20130101; H01L
2924/00 20130101 |
Class at
Publication: |
257/686 ;
257/738; 257/777; 257/778 |
International
Class: |
H01L 023/02; H01L
023/48; H01L 023/52; H01L 029/40 |
Foreign Application Data
Date |
Code |
Application Number |
May 30, 1998 |
KR |
20098/1998 |
Claims
What is claimed is:
1. A stackable chip package, comprising: a supporting member having
a plurality of conductive patterns formed therein; a plurality of
first conductive traces formed on a first surface of the supporting
member, wherein respective ones first conductive traces are
electrically coupled to corresponding ones of the conductive
patterns; a chip having chip pads, wherein the chip is attached to
a second surface of the supporting member; and a plurality of
second conductive traces, wherein portions of the second conductive
traces are arranged over the chip, and wherein respective ones of
the second conductive traces are electrically coupled to
corresponding ones of the chip pads and corresponding ones of the
conductive patterns.
2. The stackable chip package of claim 1, wherein first ends of the
second conductive traces are arranged over the chip, wherein middle
portions of respective ones of the second conductive traces are
electrically coupled to corresponding chip pads, and wherein second
ends of respective ones of the second conductive traces are
electrically coupled to corresponding ones of the conductive
patterns.
3. The stackable chip package of claim 1, further comprising a
solder resist covering portions of the plurality of first
conductive traces, wherein the solder resist leaves connecting
portions of the first conductive traces exposed.
4. The stackable chip package of claim 3, further comprising a
plurality of conductive members, wherein respective ones of the
conductive members are electrically coupled to corresponding ones
of the connecting portions of the first conductive traces, and
wherein the plurality of conductive members act as leads of the
chip package.
5. The stackable chip package of claim 1, further comprising a
solder resist covering portions of the plurality of second
conductive traces, wherein the solder resist leaves connecting
portions of the second conductive traces exposed.
6. The stackable chip package of claim 5, further comprising a
plurality of conductive members, wherein respective ones of the
conductive members are electrically coupled to corresponding ones
of the connecting portions of the second conductive traces, and
wherein the plurality of conductive members act as leads of the
chip package.
7. The stackable chip package of claim 6, wherein the plurality of
conductive members are arranged in an array over the chip.
8. The stackable chip package of claim 1, further comprising a
molding resin that covers portions of the second conductive traces,
and portions of the chip.
9. The stackable chip package of claim 1, wherein the supporting
member comprises a supporting plate and a supporting frame formed
at peripheral portions of the supporting plate.
10. The stackable chip package of claim 9, wherein the plurality of
conductive patterns are formed in the supporting frame.
11. The stackable chip package of claim 1, further comprising an
elastomer that attaches the plurality of second conductive traces
to the chip.
12. The stackable chip package of claim 11, wherein an adhesive is
interposed between the second conductive traces and the
elastomer.
13. The stackable chip package of claim 1, wherein the plurality of
first conductive traces are arranged on the first surface of the
supporting member in substantially the same pattern as the
plurality of second conductive traces are arranged over the
chip.
14. A stackable chip package, comprising: a supporting member
having a plurality of conductive patterns formed therein; a chip
having chip pads, wherein the chip is attached to a upper surface
of the supporting member; a plurality of first conductive traces,
wherein a first end of each first conductive trace is electrically
coupled to a corresponding conductive pattern and a second end of
each first conductive trace terminates below said chip; a plurality
of second conductive traces, wherein a first end of each second
conductive trace terminates above said chip, a middle portion of
each second conductive trace is electrically coupled to a
corresponding chip pad, and a second end of each second conductive
trace is electrically coupled to a corresponding conductive
pattern.
15. The stackable chip package of claim 14, wherein said plurality
of first conductive traces is formed on a lower surface of said
supporting member.
16. The stackable chip package of claim 14, further comprising a
solder resist covering portions of the plurality of first
conductive traces, wherein the solder resist leaves connecting
portions of the first conductive traces exposed.
17. The stackable chip package of claim 16, further comprising a
plurality of conductive members, wherein respective ones of the
conductive members are electrically coupled to corresponding ones
of the connecting portions of the first conductive traces, and
wherein the plurality of conductive members act as leads of the
chip package.
18. The stackable chip package of claim 14, further comprising a
solder resist covering portions of the plurality of second
conductive traces, wherein the solder resist leaves connecting
portions of the second conductive traces exposed.
19. The stackable chip package of claim 18, further comprising a
plurality of conductive members, wherein respective ones of the
conductive members are electrically coupled to corresponding ones
of the connecting portions of the second conductive traces, and
wherein the plurality of conductive members act as leads of the
chip package.
20. The stackable chip package of claim 19, wherein the plurality
of conductive members are arranged in an array over the chip.
21. The stackable chip package of claim 14, further comprising a
molding resin that covers portions of the second conductive traces,
and portions of the chip.
22. The stackable chip package of claim 14, wherein the supporting
member comprises a supporting plate and supporting frame formed at
peripheral portions of the supporting plate.
23. The stackable chip package of claim 22, wherein the plurality
of conductive patterns are formed in the supporting frame.
24. The stackable chip package of claim 14, further comprising an
elastomer that attaches the plurality of second conductive traces
to the chip.
25. The stackable chip package of claim 24, wherein an adhesive is
interposed between the second conductive traces and the
elastomer.
26. The stackable chip package of claim 14, wherein the plurality
of first conductive traces are arranged on the lower surface of the
supporting member in substantially the same pattern as the
plurality of second conductive traces are arranged over the chip.
Description
[0001] This application is a divisional of application Ser. No.
09/239,152, filed Jan. 28, 1999.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a stackable ball grid array
(BGA) semiconductor package and a fabrication method thereof.
[0004] 2. Background of the Related Art
[0005] Currently, there is an effort to produce a highly integrated
semiconductor package having a large number of exterior
connections. One example is a BGA semiconductor package in which a
plurality of solder balls which are attached to a substrate are
used as external terminals. In these BGA packages, a plurality of
solder balls are attached to an upper or a lower surface of a
substrate by the application of heat. The solder balls, which act
as external terminals, are not easily bent or deformed by inpacts
with solid objects.
[0006] FIG. 1 shows a structure of a background art BGA
semiconductor package. As seen in FIG. 1, an elastomer 2 is
attached to a center portion of an upper surface of a semiconductor
chip 1, and a high strength adhesive resin 3 is formed on the
elastomer 2. A plurality of metal traces, which transmit electric
signals, are formed on the adhesive resin 3. First ends 4a of the
metal traces extend across a top surface of the adhesive resin 3,
and second ends 4b of each of the metal 5 traces are connected to
chip pads 6 formed on a marginal portion of the upper surface of
the semiconductor chip 1. A solder resist 5 covers the metal traces
4a and the adhesive resin 3, except for exposed portions of the
first ends 4a of the metal traces, onto which solder balls will be
attached. An encapsulant 7, such as a molding resin, covers the
upper surface of the semiconductor chip 1, and the portions of the
metal 10 traces that are not covered with the solder resist 5.
Conductive balls 8 are then attached to the exposed portions of the
metal traces to serve as output terminals.
[0007] Since the conductive balls are exposed on only one side of
the package (in FIG. 1, the conductive balls are exposed at the
upper surface thereof), it is impossible to fabricate a stackable
package of high mount density.
SUMMARY OF THE INVENTION
[0008] It is an object of the present invention to provide a
stackable BGA semiconductor package, and a fabrication method
thereof, that maintain advantages of the conventional BGA
package.
[0009] A stackable chip package embodying the invention includes a
supporting member having a plurality of conductive patterns formed
therein. A plurality of first conductive traces are formed on a
surface of the supporting member, and respective ones of the first
conductive traces are coupled to corresponding ones of the
conductive patterns. A chip having chip pads is attached to a
second surface of the supporting member, and a plurality of second
conductive traces are arranged over the chip. Respective ones of
the second conductive traces are electrically coupled to
corresponding chip pads on the chip, and corresponding ones of the
conductive patterns in the supporting member. An embodiment of the
invention could also include a solder resist that covers selected
portions of the first and second conductive traces. The solder
resist would leave connecting portions of the first and second
conductive traces exposed. Exterior leads, in the form of
conductive balls, could then be connected to the connecting
portions of the first and second conductive traces. A device
embodying the invention could also include a molding resin that
encapsulates portions of the conductive traces and the chip. The
supporting member could include a supporting plate and a supporting
frame that surrounds the supporting plate.
[0010] In a method embodying the invention, a supporting member
having a plurality of conductive patterns is first formed. A
plurality of first conductive traces are then formed on a first
surface of the supporting member such that the conductive traces
are electrically coupled to corresponding ones of the conductive
patterns in the supporting member. A plurality of second traces are
then attached to a surface of a chip, and the chip is attached to a
second surface of the supporting member. Respective ones of the
second conductive traces are attached to corresponding chip pads on
the chip, and to corresponding ones of the conductive patterns in
the supporting member. A method embodying the invention could also
include the step of forming layers of solder resist over the first
and second conductive traces, and removing portions of the solder
resist to expose connecting portions of the first and second
conductive traces. A method embodying the invention could also
include attaching leads, in the form of conductive balls, to
respective ones of the exposed connecting portions of the first and
second conductive traces.
[0011] Additional advantages, objects, and features of the
invention will be set forth in part in the description which
follows and in part will become apparent to those having ordinary
skill in the art upon examination of the following or may be
learned from practice of the invention. The objects and advantages
of the invention may be realized and attained as particularly
pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The accompanying drawings illustrate embodiments of the
invention and together with the description serve to explain the
principles of the invention. In the drawing figures, like elements
are identified with like reference numerals, and:
[0013] FIG. 1 is a vertical cross-sectional diagram of a background
art BGA semiconductor package;
[0014] FIG. 2 is a vertical cross-sectional diagram of a stackable
BGA semiconductor package according to a first embodiment of the
present invention;
[0015] FIG. 3 is a vertical cross-sectional diagram of a stackable
BGA semiconductor package according to a second embodiment of the
present invention;
[0016] FIG. 4 is a vertical cross-sectional diagram of stacked BGA
semiconductor packages according to the present invention; and
[0017] FIGS. 5A through 5H illustrate steps of a method of
manufacturing a stackable BGA semiconductor package according to
the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0018] FIG. 2 illustrates a stackable BGA semiconductor package
according to a first embodiment of the present invention. As shown
in FIG. 2, a supporting member 21 includes a supporting plate 23
surrounded by a supporting frame 25 having a predetermined height.
Metal traces 24a are attached to a lower surface of the supporting
plate 23. In addition, a solder resist 27 covers portions of the
metal traces 24a and the supporting plate 23 to prevent short
circuiting between solder balls and the metal traces, and to
protect the metal traces 24a from outside impacts. The solder
resist 27 is partially removed to expose portions of the metal
traces 24a. The exposed portions of the metal traces 24a act as
connecting portions 24b. The connecting portions 24b are used to
electrically connect the metal traces 24a to conductive balls that
act as external terminals.
[0019] Metal patterns 26 are formed between upper and lower
surfaces of the supporting frame 25. One end of each of the metal
patterns 26 is connected with an end of each of the metal traces
24a. The other end of each of the metal patterns 26 is exposed at
the upper surface of the supporting frame 25.
[0020] A semiconductor chip 1 is attached by an adhesive onto the
supporting plate 23 of the supporting member 21. An elastomer 2 is
attached to a center portion of the upper surface of the
semiconductor chip 1, and a high strength adhesive resin 3 is
formed on the elastomer 2. Metal traces which transmit electric
signals are attached onto the adhesive resin 3. First ends 4a of
the metal traces extend over the top surface of the adhesive resin.
Middle portions 4b of the metal traces are connected with chip pads
6 formed on a marginal portion of the upper surface of the
semiconductor chip 1. Second ends 4c of the metal traces are
connected with upper surfaces of the metal patterns 26 formed in
the supporting frame 25.
[0021] A solder resist 5 covers the upper surface of the adhesive
resin 3 and portions of the first ends 4a of the metal traces.
Conductive balls 8a are attached to the exposed portions of the
first ends 4a of the metal traces. An encapsulant 28, such as a
molding resin, covers exposed portions of the upper surface of the
semiconductor chip 1, the metal traces, and the upper portion of
the supporting frame 25.
[0022] Electrical signals which are output by the semiconductor
chip 1 through the chip pads 6 can be externally transmitted over
the conductive balls 8a connected with the first ends 4a of the
metal traces. The electrical signals can also be externally
transmitted through the connecting portions 24b on the lower part
of the supporting member 21, which are connected to the second ends
4c of the metal traces through the metal patterns 26.
[0023] FIG. 3 is a vertical cross-sectional diagram of a stackable
BGA semiconductor package according to a second embodiment of the
present invention. The second embodiment is the same as the
embodiment shown in FIG. 2, except that conductive balls 8b are
also attached to the exposed portions 24b, of the metal traces 24a
formed on the lower part of the supporting member 21.
[0024] With each of the embodiments shown in FIGS. 2 and 3, it
becomes possible to stack a plurality of BGA semiconductor packages
over a single mounting position on a printed circuit board. Thus,
the density of the semiconductor devices on a circuit board can be
increased by using BGA packages embodying the invention.
[0025] FIG. 4 illustrates stacked BGA semiconductor packages using
the stackable BGA semiconductor package according to the first
embodiment of the present invention shown in FIG. 2. As shown
therein, a plurality of stackable BGA semiconductor packages 100,
110, 120, 130 are stacked. Conductive balls 108a, which are formed
on an upper surface of the first package 100, connect the first
ends 4a of the metal traces on the first package 100 to the
connecting portions 24b formed on a lower surface of the second BGA
semiconductor package 110. Conductive balls 118a formed on an upper
surface of the second package 110 connect the first ends 4a of the
metal traces on the second package 110 to the connecting portions
24b on a lower surface of the third BGA semiconductor package 120.
Conductive balls 128a formed on an upper surface of the third
package 120 connect the first ends 4a of the metal traces on the
third package 120 to the connecting portions 24b on a lower surface
of the fourth package 130.
[0026] FIG. 4 illustrates four stacked BGA packages, but the actual
number of stacked BGA packages may be variously adjusted by a user
according to his requirements. Conductive balls 138a formed on the
fourth package 130 can serve as external terminals which transmit
signals from all the BGA packages to external circuits. For
instance, the conductive balls 138a could be connected to pads of a
printed circuit board.
[0027] A method of fabricating a stackable BGA semiconductor chip
package according to the present invention will now be described
with reference to FIGS. 5A-5H.
[0028] In FIG. 5A, first the supporting member 21 is provided. The
supporting member 21, includes the supporting plate 23 and the
supporting frame 25. Metal traces 24a are formed on a lower surface
of the supporting plate 23. The solder resist 27 covers portions of
the metal traces 24a, but leaves the connecting portions 24b
exposed. The metal patterns 26 formed in the supporting frame 25,
are exposed at the upper surface of the supporting frame 25, and
are connected with the metal traces 24a on the bottom of the
supporting plate 23.
[0029] As shown in FIG. 5B, the semiconductor chip 1, which has
chip pads 6 on a marginal portion of an upper surface thereof, is
connected to a lower surface of an elastomer 2. A high strength
adhesive 3 is attached to an upper surface of the elastomer 2. The
metal traces are then attached to the upper surface of the adhesive
3. First end portions of each of the metal traces are attached to
the adhesive 3, and the other end portions thereof extend from
outer sides of the adhesive 3. Next, a layer of the solder resist 5
is formed on the metal traces and on the adhesive resin 3.
[0030] Next, as shown in FIG. 5C, the semiconductor chip assembly
shown in FIG. 5B is attached to the supporting member 21 shown in
FIG. 5A.
[0031] In FIG. 5D, using a bond tool 30, the chip pads 6 formed on
the semiconductor chip 1 are connected to the middle portions 4b of
the metal traces by pressing down the middle portions 4b.
[0032] As shown in FIG. 5E, second ends 4c of the metal traces are
cut off by the bond tool 30, and the second ends 4c are connected
with upper surfaces of the metal patterns 26 in the supporting
frame 25.
[0033] As shown in FIG. 5F and 5G, a molding resin 28 is molded
over the package so that it covers the exposed portions of the
metal traces and the exposed portions of the chip 1 and chip pads
6. Next, portions of the solder resist 5 formed on the metal traces
is removed to expose portions of the first ends 4a of the metal
traces that will be connected to conductive balls.
[0034] As shown in FIG. 5G, the conductive balls 8a are then placed
on the exposed portions of the first ends 4a of the metal traces,
and a reflow process is performed to attach the conductive balls 8a
to the metal traces.
[0035] One BGA package embodying the invention can be attached to a
second BGA package embodying the invention by stacking the second
package on the first package so that conductive balls on the first
package align with corresponding connecting portions on a bottom
surface of the second package, and then performing a reflow process
to connect the two packages.
[0036] The foregoing embodiments are merely exemplary and are not
to be construed as limiting the present invention. The present
teaching can be readily applied to other types of apparatuses. The
description of the present invention is intended to be
illustrative, and not to limit the scope of the claims. Many
alternatives, modifications, and variations will be apparent to
those skilled in the art. In the claims, means-plus-function
clauses are intended to cover the structures described herein as
performing the recited function and not only structural equivalents
but also equivalent structures. For example, although metal traces
and a conductive region in a semiconductor may not be structural
equivalents in that metal traces use metal as an electrical
conductor, whereas the conductive region in a semiconductor relies
on charge carriers in the material to provide electrical
conductivity, in the environment of conducting electricity, metal
traces and a conductive region of a semiconductor may be equivalent
structures.
* * * * *