U.S. patent application number 09/532731 was filed with the patent office on 2001-11-29 for dual damascene process using sacrificial spin-on materials.
Invention is credited to Kai, James K., Singh, Bhanwar, Wang, Fei.
Application Number | 20010046778 09/532731 |
Document ID | / |
Family ID | 25538437 |
Filed Date | 2001-11-29 |
United States Patent
Application |
20010046778 |
Kind Code |
A1 |
Wang, Fei ; et al. |
November 29, 2001 |
Dual damascene process using sacrificial spin-on materials
Abstract
A dual damascene process includes the steps of forming a contact
hole in an oxide layer disposed above a semiconductor substrate,
disposing a layer of anti-reflective coating material on top of the
oxide layer and in the contact hole, and partially etching the
layer of anti-reflective coating material and the oxide layer to
form the wiring trough. The partial etching step includes the steps
of spin coating photoresist on top of the anti-reflective coating
material, exposing the photoresist through a mask containing a
pattern of the wiring trough, developing the photoresist to expose
portions of the anti-reflective coating material, dry etching the
exposed portions of the anti-reflective coating material to expose
portions of the oxide layer, and wet etching the exposed portions
of the oxide layer to form the wiring trough.
Inventors: |
Wang, Fei; (San Jose,
CA) ; Singh, Bhanwar; (Morgan Hill, CA) ; Kai,
James K.; (San Francisco, CA) |
Correspondence
Address: |
Foley & Lardner
Washington Harbour
3000 K Street N W Suite 500
Washington
DC
20007-5109
US
|
Family ID: |
25538437 |
Appl. No.: |
09/532731 |
Filed: |
March 22, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09532731 |
Mar 22, 2000 |
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08992537 |
Dec 17, 1997 |
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6057239 |
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Current U.S.
Class: |
438/706 ;
257/E21.579; 438/710; 438/712 |
Current CPC
Class: |
H01L 21/76808
20130101 |
Class at
Publication: |
438/706 ;
438/710; 438/712 |
International
Class: |
H01L 021/302 |
Claims
We claim:
1. A dual damascene process comprising the steps of: forming a
contact hole in an oxide layer; disposing a layer of
anti-reflective coating material on top of the oxide layer and
filling the contact hole with the anti-reflective coating material;
etching the anti-reflective coating material to expose portions of
the oxide layer; etching the exposed portions of the oxide layer to
form a wiring trough; removing the anti-reflective coating
material; and filling the contact hole and the wiring trough with a
metal.
2. The process as recited in claim 1, wherein the step of etching
the anti-reflective coating material includes the steps of:
depositing photoresist on top of the anti-reflective coating
material; exposing the photoresist through a mask containing a
pattern of the wiring trough; developing the photoresist to expose
portions of the anti-reflective coating material; and etching the
exposed portions of the anti-reflective coating material.
3. The process as recited in claim 1, wherein the step of disposing
the layer of anti-reflective coating material includes the step of
spin coating the layer of anti-reflective coating material.
4. The process as recited in claim 3, wherein the step of spin
coating the layer of anti-reflective coating material includes the
step of selecting an anti-reflective coating material that is
non-photosensitive.
5. A dual damascene process for forming a semiconductor structure
having a wiring trough and a contact hole defined contiguously
therein, said process comprising the steps of: forming the contact
hole in an oxide layer; disposing a layer of anti-reflective
coating material on top of the oxide layer and in the contact hole;
and etching the layer of anti-reflective coating material and the
oxide layer to form the wiring trough.
6. The process as recited in claim 5, wherein the step of etching
to form the wiring trough includes the steps of: depositing
photoresist on top of the anti-reflective coating material;
exposing the photoresist through a mask containing a pattern of the
wiring trough; developing the photoresist to expose portions of the
anti-reflective coating material; etching the exposed portions of
the anti-reflective coating material to expose portions of the
oxide layer; and etching the exposed portions of the oxide layer to
form the wiring trough.
7. The process as recited in claim 6, wherein the step of etching
the exposed portions of the anti-reflective coating material
includes the step of anisotropic etching.
8. The process as recited in claim 6, wherein the step of etching
the exposed portions of the oxide layer includes the step of
buffered-oxide etching.
9. The process as recited in claim 5, wherein the step of disposing
the layer of anti-reflective coating material includes the step of
spin coating the layer of anti-reflective coating material.
10. The process as recited in claim 9, wherein the step of spin
coating the layer of anti-reflective coating material includes the
step of selecting an anti-reflective coating material that is
non-photosensitive.
11. A semiconductor structure comprising: a substrate; an oxide
layer disposed above the substrate, the oxide layer having a
contact hole formed therein; and a layer of anti-reflective coating
material disposed on top of the oxide layer, the anti-reflective
coating material filling the contact hole.
12. The semiconductor structure as recited in claim 11, further
comprising a photoresist disposed on top of the layer of
anti-reflective coating material, the photoresist having a wiring
trough pattern.
13. The semiconductor structure as recited in claim 12, wherein the
wiring trough pattern defines an opening aligned with the contact
hole.
14. The semiconductor structure as recited in claim 13, wherein the
width of the opening is larger than the width of the contact
hole.
15. The semiconductor structure as recited in claim 11, wherein the
anti-reflective coating material includes a non-photosensitive
material.
16. The semiconductor structure as recited in claim 11, further
comprising: a first nitride layer disposed on top of the substrate;
a second oxide layer disposed on top of the first nitride layer;
and a second nitride layer disposed on top of the second oxide
layer, wherein the first oxide layer is disposed on top of the
second nitride layer.
17. The semiconductor structure as recited in claim 16, wherein the
contact hole extends through the first oxide layer, the second
nitride layer, and the second nitride layer.
18. The semiconductor structure as recited in claim 17, wherein the
anti-reflective coating material disposed on top of the oxide layer
defines an opening aligned with the contact hole.
19. The semiconductor structure as recited in claim 18, wherein the
oxide layer further defines a wiring trough aligned with the
contact hole.
20. The semiconductor structure as recited in claim 19, wherein the
widths of the opening and the wiring trough are substantially equal
to each other and larger than the width of the contact hole.
21. A semiconductor structure made using the process of claim
1.
22. A semiconductor structure made using the process of claim 5.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates generally to a dual damascene process
for forming a contact hole for an integrated circuit (IC) and more
particularly to a dual damascene process that uses a sacrificial
layer of spin-on material for protecting the contact hole profile
during the damascene etch process.
[0003] 2. Description of the Related Art
[0004] A conventional dual damascene process is described in Licata
et al., "Dual Damascene Al Wiring for 256M DRAM," Proceedings of
the 12th International VLSI Multilevel Interconection Conference,
edited by T. E. Wade (VMIC, Tampa), pp. 596-602 (1995). FIGS. 1A-1F
illustrate the steps of the conventional dual damascene
process.
[0005] FIG. 1A illustrates an oxide layer 20 disposed on top of a
semiconductor substrate 10. A layer of photoresist 30 is spin
coated on top of the oxide layer 20, exposed through a mask (not
shown) containing a contact hole pattern, and developed. An etch
opening 31 is thus formed. Using the remaining photoresist as an
etch mask, the oxide layer 20 is then etched to form a contact hole
32 and the remaining photoresist is then removed producing the
structure shown in FIG. 1B.
[0006] Next, a layer of photoresist 33 is applied a second time
(FIG. 1C). The photoresist 33 is then exposed through a mask (not
shown) and developed to form an etch opening 34 (FIG. 1D). Using
the remaining photoresist as an etch mask, the oxide layer 20 is
etched to form a wiring trough 35 as shown in FIG. 1E. This etch
step is known as a damascene etch step. The remaining photoresist
is removed and the contact hole 32 and the wiring trough 35 are
filled with metal 36.
[0007] The above-described process is difficult to control for
three reasons.
[0008] First, the reflectivity from the topography substrate makes
the width of the etch opening 34 in the photoresist 33 difficult to
control.
[0009] Second, as feature sizes have become smaller, the aspect
ratio (height/width) of the contact hole 32 has increased. At high
aspect ratios, it is difficult for the photoresist 33 to completely
flow into and fill the contact hole 32. If the contact hole is not
completely filled, there is a possibility that the photoresist 33
disposed within the contact hole 32 may partially or even
completely develop away and provide little or no protection for the
contact hole profile during the subsequent damascene etch step.
[0010] Third, the thickness of the photoresist 33 over the
topography substrate varies signficantly, and so the exposure depth
of the photoresist 33 is difficult to control. This is likely to
cause an over-development of the photoresist 33 disposed within the
contact hole 32 and possibly erode the contact hole profile during
the subsequent damascene etch step.
SUMMARY OF THE INVENTION
[0011] An object of this invention is to provide a dual damascene
process that produces more consistent results by employing an
improved process control.
[0012] Another object of this invention is to provide a dual
damascene process for forming a semiconductor structure with
improved damascene etch profiles.
[0013] Still another object of this invention is to provide for use
in a dual damascene process a semiconductor structure having a
sacrificial layer of anti-reflective coating material.
[0014] The above and other objects of the invention are
accomplished by a dual damascene process including the steps of
forming a contact hole in an oxide layer disposed above a
semiconductor substrate, disposing a layer of anti-reflective
coating material on top of the oxide layer and in the contact hole,
and partially etching the layer of anti-reflective coating material
and the oxide layer to form the wiring trough.
[0015] The partial etching step includes the steps of spin coating
photoresist on top of the anti-reflective coating material,
exposing the photoresist through a mask containing a pattern of the
wiring trough, developing the photoresist to expose portions of the
anti-reflective coating material, dry etching the exposed portions
of the anti-reflective coating material to expose portions of the
oxide layer, and wet etching the exposed portions of the oxide
layer to form the wiring trough. The anti-reflective coating
material can be non-photosensitive, and is termed a "sacrificial
layer" because it is added and then "sacrificed" (i.e., removed)
for the purpose of performing an interim function in the dual
damascene process.
[0016] The dual damascene process according to the invention
employs a semiconductor structure including a substrate, an oxide
layer disposed above the substrate, and a layer of anti-reflective
coating material disposed on top of the oxide layer. The oxide
layer has a contact hole which is filled by the anti-reflective
coating material when the anti-reflective coating material is
disposed on top of the oxide layer. A photoresist formed to have a
wiring trough pattern is disposed on top of the layer of the
anti-reflective coating material. The wiring trough pattern defines
an opening which is aligned with the contact hole and which has a
width larger than that of the contact hole. The photoresist is used
as a mask during the damascene etching step that forms the wiring
trough in the oxide layer in alignment with the contact hole.
[0017] Additional objects, features and advantages of the invention
will be set forth in the description of preferred embodiments which
follows.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The invention is described in detail herein with reference
to the drawings in which:
[0019] FIG. 1A-1F illustrate a conventional dual damascene process;
and
[0020] FIG. 2A-2H illustrate a dual damascene process according to
a first embodiment of the invention.
[0021] FIG. 3A-3H illustrate a dual damascene process according to
a second embodiment of the invention.
[0022] The accompanying drawings, which are incorporated in and
constitute a part of the specification, illustrate presently
preferred exemplary embodiments of the invention, and, together
with the general description given above and the detailed
description of the preferred embodiments given below, serve to
explain the principles of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0023] FIG. 2A-2H illustrate a dual damascene process according to
a first embodiment of the invention. FIG. 2A illustrates an oxide
layer 20 disposed on top of a semiconductor substrate 10. A layer
of photoresist 30 is spin coated on top of the oxide layer 20,
exposed through a mask (not shown) containing a contact hole
pattern, and developed in a weak alkaline medium to remove the
exposed photoresist. An etch opening 31 is thus formed. Using the
remaining photoresist as an etch mask, the oxide layer 20 is then
wet etched to form a contact hole 32 and the remaining photoresist
is removed (FIG. 2B). The wet etch may be either a buffered-oxide
etch (BOE) dip or a hydrofluoric (HF) dip.
[0024] Next, a sacrificial layer 40 of spin-on material is applied
on top of the oxide layer 20 (FIG. 2C). The spin-on material is an
anti-reflective coating material and can be any of the following:
CD11, BARLi, or low dielectric constant materials such as BCB, HSQ,
SOG, and Flare. CD11 is preferred when employing deep ultraviolet
wavelength photolithography and BARLi is preferred when employing
i-line wavelength photolithography. A layer of photoresist 50 is
then spin coated on top of the sacrificial layer 40, exposed
through a mask (not shown) containing a wiring trough pattern, and
developed in a weak alkaline medium to remove the exposed
photoresist. An etch opening 51 is thus formed.
[0025] Afterwards, using the remaining photoresist as an etch mask,
the sacrificial layer 40 is anisotropically etched to form an
opening 52 (FIG. 2E). The anisotropic etch process may be carried
out as a dry etch, preferably a plasma etch. Then, using the
remaining photoresist and the remaining sacrificial layer as an
etch mask, the oxide layer 20 is etched in BOE or HF solution to
form a wiring trough 53 as shown in FIG. 2F. When HSQ or SOG is
used as the sacrificial layer 40, the sacrificial layer etch step
and the oxide etch step can be carried out at the same time using a
dry etch, preferably a plasma etch.
[0026] The remaining photoresist and the remaining sacrificial
layer are then removed (FIG. 2G). When HSQ (or SOG) is used as the
sacrificial layer 40, BOE or HF solution can be used to remove the
HSQ (or SOG) layer after the photoresist 50 is stripped because the
HSQ (or SOG) etch rate in BOE or HF solution is much faster than
that of oxide. Metal 36 is deposited on top of the oxide layer 20
to fill the contact hole 32 and the wiring trough 53, and polished
to obtain the structure shown in FIG. 2H. The metal 36 may be
tungsten, copper, aluminum, or any alloy thereof.
[0027] FIG. 3A-3H illustrate a dual damascene process according to
a second embodiment of the invention. FIG. 3A illustrates a first
oxide layer 20 disposed on top of a first nitride layer 13, a
second oxide layer 12, a second nitride layer 11, and a
semiconductor substrate 10. A layer of photoresist 30 is spin
coated on top of the oxide layer 20, exposed through a mask (not
shown) containing a contact hole pattern, and developed in a weak
alkaline medium to remove the exposed photoresist. An etch opening
31 is thus formed. Using the remaining photoresist as an etch mask,
the oxide layer 20, the first nitride layer 13, and the second
oxide layer 12 are then plasma etched to form a contact hole 32.
The remaining photoresist is then removed (FIG. 3B).
[0028] Next, a sacrificial layer 40 of spin-on material is applied
on top of the oxide layer 20 (FIG. 3C). The spin-on material is an
anti-reflective coating material and can be any of the following:
CD11, BARLi, or low dielectric constant materials such as BCB, HSQ,
SOG, and Flare. CD11 is preferred when employing deep ultraviolet
wavelength photolithography and BARLi is preferred when employing
i-line wavelength photolithography. A layer of photoresist 50 is
then spin coated on top of the sacrificial layer 40, exposed
through a mask (not shown) containing a wiring trough pattern, and
developed in a weak alkaline medium to remove the exposed
photoresist. An etch opening 51 is thus formed.
[0029] Afterwards, using the remaining photoresist as an etch mask,
the sacrificial layer 40 is anisotropically etched to form an
opening 52 (FIG. 3E). The anisotropic etch process may be carried
out as a dry etch, preferably plasma etch. Then, using the
remaining photoresist and the remaining sacrificial layer- as an
etch mask, the oxide layer 20 is plasma etched to form a wiring
trough 53 as shown in FIG. 3F. The nitride layer 13 functions well
as an etch stop for this etching step. When HSQ (or SOG) is used as
the sacrificial layer 40, the sacrificial layer etch step and the
oxide etch step can be carried out at the same time using a dry
etch, preferably a plasma etch.
[0030] The remaining photoresist and the remaining sacrificial
layer are then removed in oxygen plasma (FIG. 3G). When HSQ (or
SOG) is used as the sacrificial layer 40, BOE or HF solution can be
used to remove the HSQ (or SOG) layer after the photoresist 50 is
stripped because the HSQ (or SOG) etch rate in BOE or HF solution
is much faster than that of either nitride or oxide. Metal 36 is
deposited on top of the oxide layer 20 to fill the contact hole 32
and the wiring trough 35, and polished to obtain the structure
shown in FIG. 3H. The metal 36 may be tungsten, copper, aluminum,
or any alloy thereof.
[0031] While particular embodiments according to the invention have
been illustrated and described above, it will be clear that the
invention can take a variety of forms and embodiments within the
scope of the appended claims.
* * * * *