U.S. patent application number 09/916759 was filed with the patent office on 2001-11-29 for circuits and methods for a memory cell wirh a trench plate trench capacitor and a vertical bipolar read device.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Forbes, Leonard.
Application Number | 20010046154 09/916759 |
Document ID | / |
Family ID | 22026999 |
Filed Date | 2001-11-29 |
United States Patent
Application |
20010046154 |
Kind Code |
A1 |
Forbes, Leonard |
November 29, 2001 |
Circuits and methods for a memory cell wirh a trench plate trench
capacitor and a vertical bipolar read device
Abstract
A memory device is described which has an n-channel field effect
transistor coupled between a memory cell and a data communication
line. An NPN bipolar junction transistor is also coupled between
the memory cell and the data communication line in parallel to the
n-channel access transistor. A base connection of the NPN bipolar
junction transistor is described as coupled to a body of the
n-channel access transistor. During operation the n-channel field
effect transistor is used for writing data to a memory cell, while
the NPN bipolar junction transistor is used for read operations in
conjunction with a current sense amplifier circuit. The access
transistors are described as fabricated as a single vertical
pillar.
Inventors: |
Forbes, Leonard; (Corvallis,
OR) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
22026999 |
Appl. No.: |
09/916759 |
Filed: |
July 27, 2001 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
09916759 |
Jul 27, 2001 |
|
|
|
09498433 |
Feb 4, 2000 |
|
|
|
Current U.S.
Class: |
365/149 ;
257/E27.017; 257/E27.084; 257/E27.096 |
Current CPC
Class: |
G11C 11/405 20130101;
H01L 27/10841 20130101; H01L 27/0635 20130101; H01L 27/108
20130101; G11C 8/16 20130101; G11C 11/404 20130101 |
Class at
Publication: |
365/149 |
International
Class: |
G11C 011/24 |
Claims
What is claimed is:
1. A memory cell access device comprising: an n-channel field
effect transistor coupled between a trench plate trench capacitor
and a data communication line; and an NPN bipolar junction
transistor coupled between the trench plate trench capacitor and
the data communication line, such that the n-channel transistor and
the NPN bipolar junction transistor are connected in parallel, a
base connection of the NPN bipolar junction transistor is coupled
to a body of the n-channel field effect transistor.
2. The memory cell access device of claim 1, wherein the n-channel
field effect transistor and the NPN bipolar junction transistor are
fabricated as a single unit.
3. The memory cell access device of claim 2, wherein the single
unit comprises: a first layer of n-type semiconductor material; a
p-type semiconductor material fabricated outwardly from the first
layer of n-type semiconductor material; a gate fabricated adjacent
to the p-type semiconductor material and electrically separated by
a layer of gate insulation; and a second layer of n-type
semiconductor material fabricated on top of the p-type
semiconductor material, such that the p-type semiconductor material
functions as both a body of the n-channel field effect transistor
and a base of the NPN bipolar junction transistor.
4. The memory cell access device of claim 3, wherein the p-type
semiconductor material has a doping profile such that a top portion
of the p-type semiconductor material is more heavily doped than a
bottom portion of the p-type semiconductor material.
5. The memory cell access device of claim 3, wherein a portion of
the first layer of n-type material functions as one plate of the
trench plate trench capacitor.
6. The memory cell access device of claim 5, wherein the portion of
the first layer of n-type material that functions as one plate of
the trench capacitor is surrounded by a polysilicon mesh that
functions as the second plate of the trench plate trench
capacitor.
7. The memory cell access device of claim 1, wherein the n-channel
field effect transistor is used to write date to the memory cell,
and the NPN bipolar junction transistor is used to read data from
the memory cell.
8. A low voltage memory cell access device fabricated as a vertical
pillar structure, the memory cell access device comprising: a field
effect transistor coupled between a trench plate trench capacitor
and a data communication line; and a bipolar junction transistor
coupled between the trench plate trench capacitor and the data
communication line, such that the field effect transistor and the
bipolar junction transistor are connected in parallel, a base
connection of the bipolar junction transistor is coupled to a body
of the field effect transistor.
9. The low voltage memory cell access device of claim 8 wherein the
field effect transistor is an n-channel transistor and the bipolar
junction transistor is an NPN transistor.
10. The low voltage memory cell access device of claim 9 wherein
the field effect transistor and the bipolar junction transistor are
fabricated as a common structure comprising: a first layer of
n-type semiconductor material; a p-type semiconductor material
fabricated on top of the first layer of n-type semiconductor
material; a gate fabricated adjacent to the p-type semiconductor
material and electrically separated by a layer of gate insulation;
a second layer of n-type semiconductor material
fabricated-outwardly from the p-type semiconductor material, such
that the p-type semiconductor material functions as both a body of
the n-channel field effect transistor and a base of the NPN bipolar
junction transistor; and a base contact formed adjacent to the
p-type semiconductor material on a side opposite the gate.
11. The low voltage memory cell access device of claim 10, wherein
the first layer of n-type semiconductor material includes a portion
that functions as a first plate of the trench plate trench
capacitor.
12. The low voltage memory cell access device of claim 10, and
further comprising a first word line coupled to the gate for
activating the n-channel transistor, and a second word line coupled
to the base contact for activating the NPN bipolar junction
transistor.
13. The low voltage memory cell access device of claim 8, wherein
the p-type semiconductor material has a doping profile such that a
top portion of the p-type semiconductor material is more heavily
doped than a bottom portion of the p-type semiconductor
material.
14. The low voltage memory cell access device of claim 8, wherein
the low voltage memory cell access device is fabricated using a
silicon-on-insulator (SOI) construction.
15. The low voltage memory cell access device of claim 8, wherein
the low voltage memory cell access device is fabricated in bulk
silicon.
16. A memory device having a low voltage supply, the memory device
comprising: a plurality of memory cells; a plurality of data
communication bit lines; and a plurality of memory cell access
devices coupled between the plurality of memory cells and the
plurality of data communication bit lines, each of the plurality of
memory cell access devices comprising: a field effect transistor,
and a bipolar junction transistor, such that the field effect
transistor and the bipolar junction access transistor are connected
in parallel between a trench plate trench capacitor and a data
communication bit line.
17. The memory device of claim 16, wherein each memory cell access
device includes a field effect transistor and a bipolar junction
transistor that share a common pillar of semiconductor
material.
18. The memory device of claim 16 wherein the memory device is a
dynamic random access memory (DRAM).
19. The memory device of claim 16 wherein the field effect
transistor is an n-channel transistor and the bipolar junction
transistor is an NPN transistor.
20. The memory device of claim 16 further comprising a plurality of
current sense amplifiers coupled to the plurality of data
communication bit lines for sensing data stored on the plurality of
memory cells.
21. A method of accessing a memory cell, the method comprising the
steps of: activating a field effect transistor coupled between a
trench plate trench capacitor of the memory cell and a data
communication line for writing data to the memory cell; and
activating a bipolar junction transistor coupled between the trench
plate trench capacitor of the memory cell and a data communication
line for reading a charge stored on the memory cell.
22. The method of claim 21 wherein the field effect transistor is
an n-channel transistor and the bipolar junction transistor is an
NPN transistor.
23. The method of claim 22 wherein a body of the n-channel
transistor is coupled to a base of the NPN transistor.
24. The method of claim 23 wherein a gate voltage of the field
effect transistor varies between zero and three volts.
25. The method of claim 23 wherein a base voltage of the NPN access
transistor varies between 0.7 and approximately 1.4 volts.
26. The method of claim 23 wherein the field effect transistor and
the bipolar junction access transistor are fabricated in a common
vertical pillar structure.
27. The method of claim 26 wherein the common vertical pillar
structure comprises: a first layer of n-type semiconductor
material; a p-type semiconductor material fabricated on top of the
first layer of n-type semiconductor material; a gate fabricated
adjacent to the p-type semiconductor material and electrically
separated by a layer of gate insulation; and a second layer of
n-type semiconductor material fabricated outwardly from the p-type
semiconductor material.
Description
RELATED APPLICATIONS
[0001] This application is related to the following co-pending,
commonly assigned applications which are incorporated by
reference:
[0002] U.S. application Ser. No. 09/028,249 entitled "VERTICAL
BIPOLAR READ ACCESS FOR LOW VOLTAGE MEMORY CELL,"
[0003] U.S. application Ser. No. 08/944,312 entitled "CIRCUIT AND
METHOD FOR A FOLDED BIT LINE MEMORY USING TRENCH PLATE CAPACITOR
CELLS WITH BODY BIAS CONTACTS,"
[0004] U.S. application Ser. No. 08/939,732, entitled "CIRCUIT AND
METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR
AND TRENCH PLATE TRENCH CAPACITOR"
[0005] U.S. application Ser. No. 08/939,742, entitled "CIRCUIT AND
METHOD FOR A FOLDED BIT LINE MEMORY CELL WITH VERTICAL TRANSISTOR
AND TRENCH CAPACITOR," and
[0006] U.S. application Ser. No. 08/944,890, entitled "CIRCUIT AND
METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR
AND TRENCH PLATE TRENCH CAPACITOR."
TECHNICAL FIELD OF THE INVENTION
[0007] The present invention relates generally to integrated
circuits and in particular the present invention relates to
integrated circuit memory devices.
BACKGROUND OF THE INVENTION
[0008] Complimentary metal oxide semiconductor field effect
transistors (CMOS FETs) are prevalent in integrated circuit
technology because they generally demand less power than bipolar
transistors. Threshold voltage variations of CMOS transistors,
however, are beginning to pose impractical limitations on CMOS
devices as power supply voltages are reduced. In a 0.2 micron CMOS
technology a 0.4 V distribution in threshold voltages might be
anticipated. With a one volt power supply, this distribution can
cause large variations in the speed of a logic circuit, such as
those used in integrated memory circuits. For example, a threshold
voltage of 0.6 V is required in a DRAM memory cell access
transistor to insure low sub-threshold voltage leakage currents. If
a threshold voltage distribution of 0.4 volts is experienced, there
will be instances where little or no excess voltage above threshold
voltage is available. As such, data transfer from a memory cell via
such a transistor will be very slow.
[0009] A basic problem with CMOS access transistors results from
the fact that CMOS devices do not function well at low voltages and
require the use of higher than desirable power supply voltages,
currently around two volts in 0.2 micron CMOS technology. Various
techniques have been proposed to compensate for this in CMOS
technology. For example, some form of transistor forward body bias,
or specialized circuits to compensate for threshold voltage
variations can be used.
[0010] Various types of lateral MOS transistors have been described
and utilized in CMOS technology. Lateral bipolar transistors have
received renewed interest with the advent of bipolar complementary
metal oxide semiconductor (BiCMOS) technologies.
[0011] For the reasons stated above, and for other reasons stated
below which will become apparent to those skilled in the art upon
reading and understanding the present specification, there is a
need in the art for an access device for use in a low voltage
memory device which performs fast read access of memory data.
SUMMARY OF THE INVENTION
[0012] The above mentioned problems with integrated circuit memory
devices and other problems are addressed by the present invention
and which will be understood by reading and studying the following
specification. A memory cell access device is described which uses
a combination of bipolar junction and CMOS transistors as access
devices to store and read data on a trench plate trench
capacitor.
[0013] In particular, one embodiment of the present invention
provides a memory cell access device that has two access
transistors. The first access transistor is an n-channel field
effect transistor (FET) that is coupled between a trench plate
trench capacitor and a data communication line. The second access
transistor is an NPN bipolar junction transistor that is coupled
between the trench plate trench capacitor and the data
communication line. The n-channel access transistor and the NPN
bipolar junction transistor are connected in parallel, and a base
connection of the NPN bipolar junction transistor is coupled to a
body of the n-channel field effect transistor.
[0014] In another embodiment, a low voltage memory cell access
device fabricated as a vertical pillar structure is provided. The
memory cell access device includes a field effect transistor that
is coupled between a trench plate trench capacitor and a data
communication line. The memory cell access device also includes a
bipolar junction transistor that is coupled between the memory cell
and the data communication line. The field effect transistor and
the bipolar junction transistor are connected in parallel, with a
base connection of the bipolar junction transistor that is coupled
to a body of the field effect transistor.
[0015] In another embodiment, a memory device having a low voltage
supply is provided. The memory device comprises a plurality of
memory cells, a plurality of data communication bit lines, and a
plurality of memory cell access devices coupled between the
plurality of memory cells and the plurality of data communication
bit lines. Each of the plurality of memory cell access devices
comprises a field effect transistor and a bipolar junction
transistor. The field effect transistor and the bipolar junction
transistor are connected in parallel between a trench plate trench
capacitor and a data communication bit line.
[0016] In another embodiment, a method of accessing a memory cell
is provided. The method includes activating a field effect
transistor coupled between a trench plate trench capacitor and a
data communication line for writing data to the memory cell, and
activating a bipolar junction transistor coupled between the trench
plate trench capacitor and a data communication line for reading a
charge stored on the memory cell.
BRIEF DESCRIPTION OF THE INVENTION
[0017] FIG. 1 is a block diagram of an embodiment of a memory
device according to the teachings of the present invention.
[0018] FIG. 2 is an embodiment of a portion of an array of memory
cells according to the teachings of the present invention.
[0019] FIG. 3A is a schematic diagram that illustrates an
embodiment of a memory cell with a vertical access device according
to the teachings of the present invention.
[0020] FIG. 3B is a cross sectional view that illustrates an
integrated circuit embodiment of the vertical access device of FIG.
3A.
[0021] FIG. 3C is a cross sectional view that illustrates another
integrated circuit embodiment of the vertical access device of FIG.
3A.
DETAILED DESCRIPTION
[0022] In the following detailed description of the invention,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown, by way of illustration, specific
embodiments in which the invention may be practiced. In the
drawings, like numerals describe substantially similar components
throughout the several views. These embodiments are described in
sufficient detail to enable those skilled in the art to practice
the invention. Other embodiments may be utilized and structural,
logical, and electrical changes may be made without departing from
the scope of the present invention. The terms wafer and substrate
used in the following description include any structure having an
exposed surface with which to form the integrated circuit (IC)
structure of the invention. The term substrate is understood to
include semiconductor wafers. The term substrate is also used to
refer to semiconductor structures during processing, and may
include other layers that have been fabricated thereupon. Both
wafer and substrate include doped and undoped semiconductors,
epitaxial semiconductor layers supported by a base semiconductor or
insulator, as well as other semiconductor structures well known to
one skilled in the art. The term conductor is understood to include
semiconductors, and the term insulator is defined to include any
material that is less electrically conductive than the materials
referred to as conductors. The following detailed description is,
therefore, not to be taken in a limiting sense.
[0023] The term "horizontal" as used in this application is defined
as a plane parallel to the conventional plane or surface of a wafer
or substrate, regardless of the orientation of the wafer or
substrate. The term "vertical" refers to a direction perpendicular
to the horizontal as defined above. Prepositions, such as "on",
"side" (as in "sidewall"), "higher", "lower", "over" and "under"
are defined with respect to the conventional plane or surface being
on the top surface of the wafer or substrate, regardless of the
orientation of the wafer or substrate.
[0024] Smaller integrated circuit devices combined with the
development of vertical integrated circuit structures, make it
possible to use bipolar junction transistor action rather than just
field effect transistor operation. In fact, a bipolar junction
transistor structure can be used as a data read access device and a
field effect transistor used as a data write access device, as
described herein. Below, an embodiment of the present invention is
described in terms of a dynamic random access memory (DRAM) device.
Embodiments of an access device constructed according to the
teachings of the present invention are also shown and described. It
is understood, however, that these embodiments are provided by way
of example and not by way of limitation.
DRAM DEVICE
[0025] FIG. 1 is a simplified block diagram of an embodiment of a
memory device incorporating access devices constructed according to
the teachings of the present invention. Memory device 100 includes
an array of memory cells 102, address decoder 104, row access
circuitry 106, column access circuitry 108, control circuitry 110,
and Input/Output circuit (I/O) 112.
[0026] In one embodiment, each cell in array 102 includes an access
device with a bipolar junction transistor coupled in parallel with
a field effect transistor between a data communication or digit
line and a trench plate trench capacitor. The access device is used
to charge and discharge the trench plate trench capacitor to store
and read data from the memory cell. The field effect transistor
charges the capacitor. The bipolar junction transistor reads the
charge stored on the capacitor by discharging the capacitor and
providing the current to a current sense amplifier. The bipolar
junction transistor typically conducts a higher current compared to
its counterpart field effect transistor. Thus, the access device
provides the advantage of increased speed in reading the data
stored in the memory cell by allowing the capacitor to be
discharged more quickly.
[0027] Memory device 100 can be coupled to an external
microprocessor 114, or memory controller for memory accessing.
Memory device 100 receives control signals from the microprocessor
114, such as WE*, RAS* and CAS* signals. Memory device 100 is used
to store data which is accessed via I/O lines. It will be
appreciated by those skilled in the art that additional circuitry
and control signals can be provided, and that the memory device of
FIG. 1 has been simplified to help focus on embodiments of the
present invention.
[0028] It will be understood that the above description of a DRAM
is intended to provide a general understanding of the memory and is
not a complete description of all the elements and features of a
DRAM. Further, the embodiments of the present invention are equally
applicable to any size and type of memory circuit and are not
intended to be limited to the DRAM described above. Other
alternative types of devices include SRAM or Flash memories.
Additionally, the DRAM could be a synchronous DRAM commonly
referred to as SGRAM, SDRAM, SDRAM II, and DDR SDRAM, as well as
Synchlink or Rambus DRAMs.
[0029] Referring to FIG. 2, an embodiment of a portion of array 102
is provided. The simplified schematic diagram illustrates a portion
of a column of the array 102. The column is generally defined by a
pair of data communication or digit lines 120 and 122. Access
devices 124 are located along the digit lines for coupling trench
plate trench capacitors 126 to a digit line. Access devices 124
include field effect transistor 123 in parallel with bipolar
junction transistor 125. The field effect transistors 123 are
activated by a word line (W-WL) to write data to a trench plate
trench capacitor, which defines a row of the memory array. The
bipolar junction transistors 125 are activated by a word line
(R-WL) to read data from a trench plate trench capacitor.
[0030] Current sense amplifier 128 is provided to detect current
signals provided to the digit lines by a bipolar junction
transistor during a read operation. In one embodiment, a clamped
bit line sense amplifier, as shown, can be used. The current from
the digit lines are injected to the cross coupled pair of inverters
(M1/M3 and M2/M4). Transistors M5 and M6 serve to clamp the digit
lines at a fixed voltage, e.g., 0.7 volts. The impedance looking
into the source of transistors M1 and M2 is very low but the
current injected here from the data lines serves to upset the cross
coupled inverters which provides a high speed large signal output.
Alternatively, other sense amplifiers can be used that allow a
current from a trench plate trench capacitor to be sensed.
[0031] As described above, a large variation in a threshold voltage
of the field effect access transistors can result in slow data
access. This slow access is most troubling in data read operations.
Embodiments of the present invention avoid this access speed
problem while maintaining a higher threshold voltage. That is, for
access devices 124 in a DRAM circuit a larger threshold voltage
value is desired to reduce memory cell leakage and increase
retention time in the memory cells. By using the bipolar junction
transistor in parallel with the field effect transistor, a larger
threshold voltage can be maintained without increasing cell leakage
and reducing retention time.
Memory Cell Access Device
[0032] FIG. 3A illustrates a schematic diagram of a vertical access
device 200 having both a bipolar junction transistor 202 and a
metal-oxide semiconductor field effect transistor (MOSFET) 204
which can be formed in either bulk or SOI technology. Bipolar
junction transistor 202 is an NPN transistor having emitter 206,
collector 208 and base 210. Transistor 204 is an n-channel MOSFET
having first source/drain region 212, second source/drain region
214 and gate 216. The access device can be fabricated as a single
unit, or as separate transistors.
[0033] FIG. 3B and 3C provide alternative fabricated integrated
circuit embodiments of an access device 300 constructed according
to the teachings of the present invention. FIG. 3B is a bulk
silicon embodiment of an access device formed in a single pillar of
monocrystalline semiconductor material. Access device 300 includes
a parallel combination of a bipolar junction transistor and a field
effect transistor. Access device 300 is coupled to trench plate
trench capacitor 301. Access device 300 includes n+ semiconductor
layer 304. Layer 304 serves as an emitter for the bipolar junction
transistor, a source/drain region for the field effect transistor
and a plate of the trench plate trench capacitor. P-doped
semiconductor layer 306 is fabricated on layer 304. The vertical
doping profile of region 306 is varied, as explained below, to
optimize bipolar transistor action. An n+ semiconductor layer 312
is provided on top of layer 306. Polysilicon region 316 is
fabricated to operate as a gate isolated from layer 306 by gate
oxide layer 314. A polysilicon base contact 320 is provided
opposite gate 316 on oxide layer 319 and in contact with region
306. Further, trench plate trench capacitor 301 includes a
polysilicon mesh (POLY) that surrounds a portion of layer 304. The
polysilicon mesh forms a second plate of capacitor 301.
[0034] FIG. 3C is an SOI embodiment of an access device 300
constructed according to the teachings of the present invention. In
this embodiment, access device-300 includes n+ semiconductor layer
304 that extends down through a polysilicon mesh (POLY). The
polysilicon mesh and layer 304 are formed on insulator layer 303,
e.g., an oxide, or insulating base layer. The remaining components
of the access device are substantially the same as the access
device of FIG. 3B, although fabrication techniques may differ.
[0035] A vertical doping profile of region 306 of the access device
is optimized for both bipolar transistor action and biasing the
body of the field effect transistor to a value around 0.9 V to
forward bias the base emitter junction. The doping profile is
controlled so that the top portion 310 of layer 306 is more heavily
doped p-type than a bottom region 308. This difference in doping is
represented by the designations P and P-. The actual doping levels
with respect to other structures or base layers can be varied, and
relative doping levels between the top and bottom regions of layer
306 is only represented herein.
[0036] One way to create the difference in the doping profile is to
use the effects of the fabrication of emitter 312. When the
emitter, or top n-type layer 312, is fabricated a relatively higher
base doping level near emitter 312 can be created. This doping
profile is required in a vertical NPN transistor to give
field-aided diffusion in the base and a high current gain, .beta..
If the base doping is around 10.sup.18/cm.sup.3, as is common in
NPN transistors, then region 310 also serves to make the n-channel
vertical MOSFET enhancement mode, which is difficult to achieve by
other techniques since implantations for threshold voltage
adjustment cannot be conveniently done.
[0037] The following comparison further illustrates the advantage
of using a bipolar junction transistor for data read operations in
a low voltage memory. If n-channel field effect transistor 204 of
FIG. 3A is used to discharge the capacitor, it is customary to
precharge a data communication "bit" line to 1/2V.sub.DD, or in
this illustration 1.5 volts. The peak transfer current I.sub.D is
estimated to be around 40 .mu.A assuming a Vt of 0.5 volts. That
is, the drain current is calculated by: 1 I D = Co ( W L ) ( ( Vgs
- Vt ) 2 2 where W = L I D = 80 A V 2 * 1 * ( 1 2 V ) 2 = 40 A
[0038] If the memory cell is assumed to store 50 fC, the charge
from the memory cell requires 1.2 nano-seconds to transfer to the
bit line through transistor 204.
[0039] A faster data transfer is possible if bipolar access
transistor 202 is used with a clamped bit line where the bit line
is precharged to a lower voltage, such as 0.7 V. The peak bipolar
current is determined mostly by the base current I.sub.B and the
variation of current gain, .beta., with peak current. Assuming a
base current of 4.0 .mu.A, a peak collector value of 400 .mu.A is
estimated by:
I.sub.C=.beta.I.sub.B where .beta.=100
[0040] If the memory cell is assumed to store the 70 fC, the charge
from the memory cell requires only 0.18 nano-seconds to transfer to
the bit line. A substantial decrease in transfer time, therefore,
is experienced by using a bipolar access transistor during read
operations in the low voltage memory.
Access Operations in a DRAM Embodiment
[0041] During a write operation the base of BJT transistor 202 is
coupled to a low voltage, such as 0.7 volts. The body potential in
layer 306, therefore, is held at the low level resulting in a
MOSFET body bias which increases as the memory is charged due to an
elevated bit line potential. As a result, the threshold voltage of
transistor 204 rises to around one volt. A bootstrapped voltage as
known to those skilled in the art can be used to drive the gate
voltage above three volts, such as four volts. This booted voltage
is necessary because the supply voltage is limited to three volts,
and a second supply is typically not provided. The time required
for the write operation is not critical and can be much longer than
the read response. Thus, the reduced power requirements of the
MOSFET are desirable.
[0042] During a read operation the bit lines are clamped to a low
voltage (near the base low voltage), in this example 0.7 V. The
voltage of the bit lines does not change significantly during a
read operation, unlike in a memory using a conventional voltage
sense amplifier, since here current not voltage is being sensed.
During a read operation, the read word line goes to a higher
voltage, such as 1.4 V, to forward bias the base-emitter junction
and turn on the bipolar transistor 202. The bipolar transistor will
be strongly forward biased and quickly discharge the charge stored
on the memory storage capacitor onto the bit line where it can be
sensed as a current. The memory cell discharges to about 0.7 V at
which point the bipolar transistor saturates and stops functioning.
The memory cell data state voltage levels are therefore
approximately two volts when charged, and 0.7 V when
discharged.
[0043] It is estimated that a bit line current sense amplifier is
about eight times faster than the a bit line differential voltage
sense amplifier commonly used in DRAMs. Further, as detailed above,
current transfer from a memory cell to a bit line using the bipolar
transfer device is about eight times faster than an n-channel
MOSFET transfer device. The net result is that the present
invention, when used in a low voltage memory device for data read
operations, is about eight times faster than commonly used CMOS
DRAMs. Further, a vertical access transistor device with a trench
plate trench capacitor is only 4F.sup.2 in area. A DRAM according
to the present invention, therefore, is about one-half the area of
conventional DRAM's and about eight times faster.
[0044] In operation, the bipolar device would be used for reads and
the MOSFET device on the other side of the device pillar can most
conveniently be used for write operations to store information on
the memory capacitor in a conventional manner. The present
invention can be scaled to lower power supply voltages and smaller
dimensions, in which case the use of the bipolar access device
becomes yet more advantageous. For one volt power supply voltages,
the threshold voltage variations of MOSFETs will become a large
fraction of the total voltage available.
Conclusion
[0045] Embodiments of an access device for a memory device have
been described which use an n-channel field effect transistor and a
bipolar junction transistor coupled in parallel between a trench
plate trench capacitor and a data communication line. A base
connection of the NPN bipolar junction transistor has been
described as coupled to a body of the n-channel access transistor
to control threshold voltage variations of the n-channel field
effect transistor. During operation the n-channel field effect
transistor is used for writing data to a trench plate trench
capacitor, while the NPN bipolar junction transistor is used for
read operations in conjunction with a current sense amplifier
circuit. The access transistors are described as fabricated as a
single vertical pillar.
[0046] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention.
* * * * *