U.S. patent application number 09/821964 was filed with the patent office on 2001-11-22 for magnetoresistive memory having elevated interference immunity.
Invention is credited to Plasa, Gunther, Thewes, Roland, Weber, Werner.
Application Number | 20010043488 09/821964 |
Document ID | / |
Family ID | 7882947 |
Filed Date | 2001-11-22 |
United States Patent
Application |
20010043488 |
Kind Code |
A1 |
Weber, Werner ; et
al. |
November 22, 2001 |
Magnetoresistive memory having elevated interference immunity
Abstract
The magnetoresistive memory provides for an improvement in
interference immunity even though only a small chip area is used.
Word lines are situated vertically between two complementary bit
lines, a magnetoresistive memory system of a regular location is
situated between a bit line and a word line, and an appertaining
magnetoresistive layer system of a complementary memory location is
situated between the complementary bit line and the word line in
the vertical direction.
Inventors: |
Weber, Werner; (Munchen,
DE) ; Thewes, Roland; (Grobenzell, DE) ;
Plasa, Gunther; (Villach, AT) |
Correspondence
Address: |
LERNER AND GREENBERG, P.A.
Post Office Box 2480
Hollywood
FL
33022-2480
US
|
Family ID: |
7882947 |
Appl. No.: |
09/821964 |
Filed: |
March 30, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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09821964 |
Mar 30, 2001 |
|
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PCT/DE99/03135 |
Sep 29, 1999 |
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Current U.S.
Class: |
365/158 ;
257/E27.005 |
Current CPC
Class: |
G11C 11/1659 20130101;
G11C 11/161 20130101; H01L 27/222 20130101; G11C 11/16 20130101;
G11C 11/1675 20130101; G11C 11/1653 20130101 |
Class at
Publication: |
365/158 |
International
Class: |
G11C 011/00 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 30, 1998 |
DE |
198 45 069.9 |
Claims
We claim:
1. A magnetoresistive memory, comprising a vertically stacked
assembly of a layer for a first bit line, a magnetoresistive layer
system of a first memory location, a layer for word lines, a
magnetoresistive layer system of a second memory location, and a
layer for an second bit line vertically stacked on top of one
another, wherein logic states to be stored in said first memory
location and said second memory location are inverses of one
another.
2. The magnetoresistive memory according to claim 1, wherein said
second memory location in a described state always comprises an
inverse state of a state of said first location therebeneath, and
wherein a current in said bit line flows in a direction opposite to
a direction of a current in said second bit line situated
thereabove.
3. The magnetoresistive memory according to claim 1, wherein each
said magnetoresistive layer system comprises a magnetically soft
layer, a magnetically hard layer, and a thin tunnel oxide
separating said magnetically soft layer from said magnetically hard
layer.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This is a continuation of copending International
Application PCT/DE99/03135, filed Sep. 29, 1999, which designated
the United States.
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
[0002] The present invention relates to a magnetoresistive
write-read memory (MRAM) whose storage effect consists in the
magnetically controlled electrical resistance of the memory
locations.
[0003] International PCT publication WO 95/10112 and U.S. Pat. No.
5,699,293 teach a non-volatile write/read memory in which a
non-magnetic non-conductive layer is present between two
ferromagnetic layers, with one layer having a fixed orientation and
the other layer having a magnetic orientation that is defined by
the operation. The resistance across the two ferromagnetic layers
varies with the orientation of the respective magnetic moments.
SUMMARY OF THE INVENTION
[0004] It is accordingly an object of the invention to provide a
magnetoresistive read/write memory, which overcomes the
above-mentioned disadvantages of the heretofore-known devices and
methods of this general type and which makes it possible to
increase the interference immunity given an optimally small chip
surface area.
[0005] With the foregoing and other objects in view there is
provided, in accordance with the invention, a magnetoresistive
memory, comprising a vertically stacked assembly of a layer for a
first bit line, a magnetoresistive layer system of a first memory
location, a layer for word lines, a magnetoresistive layer system
of a second memory location, and a layer for an second bit line
vertically stacked on top of one another, wherein logic states to
be stored in the first memory location and the second memory
location are inverses of one another.
[0006] In accordance with an added feature of the invention, the
second memory location in a described state always comprises an
inverse state of a state of the first location beneath it, and
wherein a current in the bit line flows in a direction opposite to
a direction of a current in the second bit line situated above
it.
[0007] In accordance with a concomitant feature of the invention,
each magnetoresistive layer system comprises a magnetically soft
layer, a magnetically hard layer, and a thin tunnel oxide
separating the two magnetic layers from one another.
[0008] Other features which are considered as characteristic for
the invention are set forth in the appended claims.
[0009] Although the invention is illustrated and described herein
as embodied in a magnetoresistive memory having elevated
interference immunity, it is nevertheless not intended to be
limited to the details shown, since various modifications and
structural changes may be made therein without departing from the
spirit of the invention and within the scope and range of
equivalents of the claims.
[0010] The construction and method of operation of the invention,
however, together with additional objects and advantages thereof
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] FIG. 1 is a sectional view of an MRAM according to the
invention; and
[0012] FIG. 2 is a sectional view of a magnetoresistive layer
system that is present in FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0013] The invention may be summarized in that a local reference
memory location for each individual memory location is provided and
a common word line is disposed between these two memory locations
vertically. This makes possible a very compact and effective
interference compensation.
[0014] Referring now to the figures of the drawing in detail and
first, particularly, to FIG. 1 thereof, there is shown a part of a
magnetoresistive memory having two word lines WL and two bit lines
BL, {overscore (BL)}. Between the bit line BL and the word lines
WL, magnetoresistive layer systems MRS are respectively situated.
In the same way, such magnetoresistive layer systems are also
situated between the word lines WL and the additional bit line
{overscore (BL)}. Consequently, it is possible to achieve a total
memory location area of only 4F.sup.2, with F being the smallest
resolvable structural width. The layer systems between the bit line
BL and the word line WL form regular memory locations Z, and the
layer systems between the word lines WL and the additional bit line
{overscore (BL)} form complementary memory locations {overscore
(Z)}. The states stored in the complementary memory locations
{overscore (Z)} are the inverse of those stored in the respective
underlying memory locations Z; i.e., inverse states are written in
by way of the bit lines BL and {overscore (BL)}, respectively. The
bit line {overscore (BL)} carries the inverse signal of the signal
on the bit line BL, whereby a current {overscore (I)} flowing in
the bit line {overscore (BL)} flows in the opposite direction to
the direction of a current in the bit line BL. Since the
resistances of the magnetoresistive layer systems differ only on
the order of approx. 10% in dependence upon their stored status,
the influence of interference must be accounted for. Since the
signals on the bit lines BL and {overscore (BL)} are the inverse of
one another, it is possible to achieve an amplification of the
payload signal and an attenuation of the noise quantities that act
equally on the two complementary locations, and thus to increase
the interference immunity, by difference formation.
[0015] FIG. 2 shows the magnetoresistive layer system MRS of the
locations Z and {overscore (Z)} of FIG. 1. The layer system MRS
essentially consists of a magnetically soft layer WM and a
magnetically hard layer HM, which are separated by a tunnel oxide
TOX. The ferromagnetic layers typically consist of a material
containing at least one substance from a list that includes iron,
nickel, and cobalt, with the material of the layer HM having a
higher coercive field strength than the material of the layer WM.
The tunnel oxide TOX consists of alumina Al.sub.2O.sub.3, for
example. Instead of the tunnel oxide TOX, other thin insulator
layers such as silicon nitride or the like can also be used.
[0016] The magnetoresistive layer system can vary the magnetization
direction of the magnetically soft layer WM of a location Z for a
long period of time, and can thereby store logical states of zero
or one, with sufficient currents in a selected bit line BL and a
selected word line WL. The reading of the location Z is then
accomplished in that a current flows from the appertaining word
line to the appertaining bit line through the location, the
intensity of which depends on the magnetization direction of the
magnetically soft layer WM. The current intensity differs when the
magnetization directions in the layers WM and HM are parallel from
when they are antiparallel, because the tunneling probability is
different in each case.
* * * * *