U.S. patent application number 09/852735 was filed with the patent office on 2001-11-22 for esd protection apparatus and method for fabricating the same.
This patent application is currently assigned to NEC CORPORATION. Invention is credited to Okushima, Mototsugu.
Application Number | 20010043449 09/852735 |
Document ID | / |
Family ID | 18648438 |
Filed Date | 2001-11-22 |
United States Patent
Application |
20010043449 |
Kind Code |
A1 |
Okushima, Mototsugu |
November 22, 2001 |
ESD protection apparatus and method for fabricating the same
Abstract
To make electric current concentration and electric field
concentration hardly take place in junction parts even in case of
performing miniaturization and to achieve triggering at low
voltage. An ESD protection apparatus is installed between an input
terminal 6 of a semiconductor integrated circuit chip and a CMOS
transistor 100 and includes a trigger element 310 comprising diodes
311, 312 which are broken down by overvoltage applied to the input
terminal 6 and an ESD protection element 210 including longitudinal
bipolar transistors 211, 212 for discharging the accumulated
electric charge of the input terminal 6 by being electrically
communicated owing to the breakdown of the diodes 311, 312.
Inventors: |
Okushima, Mototsugu; (Tokyo,
JP) |
Correspondence
Address: |
YOUNG & THOMPSON
745 SOUTH 23RD STREET 2ND FLOOR
ARLINGTON
VA
22202
|
Assignee: |
NEC CORPORATION
|
Family ID: |
18648438 |
Appl. No.: |
09/852735 |
Filed: |
May 11, 2001 |
Current U.S.
Class: |
361/56 |
Current CPC
Class: |
H01L 27/0255 20130101;
H01L 27/0259 20130101; H01L 2924/0002 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
361/56 |
International
Class: |
H02H 009/00 |
Foreign Application Data
Date |
Code |
Application Number |
May 15, 2000 |
JP |
2000-141304 |
Claims
What is claimed is:
1. An ESD protection apparatus installed between a pad of a
semiconductor integrated circuit chip and an inner circuit of said
semiconductor integrated circuit chip, comprising: a trigger
element having a diode to be broken down by overvoltage applied to
said pad; and an ESD protection element having a longitudinal
bipolar transistor for discharging the accumulated electric charge
of said pad by being electrically communicated attributed to the
breakdown of said diode.
2. The ESD protection apparatus according to claim 1, wherein said
diode comprises a single diode or plural diodes connected in
series; said overvoltage is a forward voltage for the diode; and
said breakdown is a substantial breakdown owing to conduction.
3. The ESD protection apparatus according to claim 1, wherein said
pad is an input terminal or an output terminal; said trigger
element comprises a first and a second diodes and a first and a
second resistors; said ESD protection element comprises NPN type
first and second longitudinal bipolar transistors; a cathode of
said first diode is connected with said pad and an anode of said
first diode is connected with a base of said first longitudinal
bipolar transistor; a cathode of said second diode is connected
with an electric power source terminal and an anode of said second
diode is connected with a base of said second longitudinal bipolar
transistor; said first resistor is connected between the anode of
said first diode and a ground terminal; said second resistor is
connected between the anode of said second diode and said pad; a
collector of said first longitudinal bipolar transistor is
connected with said pad and an emitter of said first longitudinal
bipolar transistor is connected with said ground terminal; and a
collector of said second longitudinal bipolar transistor is
connected with said electric power source terminal and an emitter
of said second longitudinal bipolar transistor is connected with
said pad; and at least either of said first diode, said first
resistor and said first longitudinal bipolar transistor or said
second diode, said second resistor and said second longitudinal
bipolar transistor are provided.
4. The ESD protection apparatus according to claim 1, wherein said
pad is an input terminal or an output terminal; said trigger
element comprises first and second diodes and first and second
resistors; said ESD protection element comprises PNP type first and
second longitudinal bipolar transistors; a cathode of said first
diode is connected with a base of said first longitudinal bipolar
transistor and an anode of said first diode is connected with a
ground terminal; a cathode of said second diode is connected with a
base of said second longitudinal bipolar transistor and an anode of
said second diode is connected with said pad; said first resistor
is connected between the cathode of said first diode and said pad;
said second resistor is connected between the cathode of said
second diode and said electric power source terminal; a collector
of said first longitudinal bipolar transistor is connected with
said ground terminal and an emitter of said first longitudinal
bipolar transistor is connected with said pad; and a collector of
said second longitudinal bipolar transistor is connected with said
pad and an emitter of said second longitudinal bipolar transistor
is connected with said electric power source terminal; and at least
either of said first diode, said first resistor and said first
longitudinal bipolar transistor or said second diode, said second
resistor and said second longitudinal bipolar transistor are
provided.
5. The ESD protection apparatus according to claim 1, wherein said
pad is an electric power source terminal; said longitudinal bipolar
transistor is NPN type; the cathode of said diode is connected with
said pad and the anode of said diode is connected with the base of
said longitudinal bipolar transistor; a resistor is connected
between the anode of said diode and a ground terminal; and the
collector of said longitudinal bipolar transistor is connected with
said pad and the emitter of said longitudinal bipolar transistor is
connected with said ground terminal.
6. The ESD protection apparatus according to claim 1, wherein said
pad is an electric power terminal; said longitudinal bipolar
transistor is of PNP type; a cathode of said diode is connected
with a base of said longitudinal bipolar transistor and an anode of
said diode is connected with a ground terminal; a resistor is
connected between the cathode of said diode and said electric power
terminal; and a collector of said longitudinal bipolar transistor
is connected with said ground terminal and an emitter of said
longitudinal bipolar transistor is connected with said pad.
7. The ESD protection apparatus according to claim 2, wherein said
pad is an input terminal or an output terminal; said trigger
element comprises first and second diodes and first and second
resistors; said ESD protection element comprises NPN type first and
second longitudinal bipolar transistors; an anode of said first
diode is connected with said pad and a cathode of said first diode
is connected with a base of said first longitudinal bipolar
transistor; an anode of said second diode is connected with an
electric power source terminal and a cathode of said second diode
is connected with a base of said second longitudinal bipolar
transistor; said first resistor is connected between the cathode of
said first diode and the ground terminal; said second resistor is
connected between the cathode of said second diode and said pad; a
collector of said first longitudinal bipolar transistor is
connected with said pad and an emitter of said first longitudinal
bipolar transistor is connected with said ground terminal; and a
collector of said second longitudinal bipolar transistor is
connected with said electric power source terminal and an emitter
of said second longitudinal bipolar transistor is connected with
said pad; and at least either of said first diode, said first
resistor and said first longitudinal bipolar transistor or said
second diode, said second resistor and said second longitudinal
bipolar transistor are provided.
8. The ESD protection apparatus according to claim 2, wherein said
pad is an input terminal or an output terminal; said trigger
element comprises first and second diodes and first and second
resistors; said ESD protection element comprises PNP type first and
second longitudinal bipolar transistors; an anode of said first
diode is connected with a base of said first longitudinal bipolar
transistor and a cathode of said first diode is connected with a
ground terminal; an anode of said second diode is connected with a
base of said second longitudinal bipolar transistor and a cathode
of said second diode is connected with said pad; said first
resistor is connected between the anode of said first diode and
said pad; said second resistor is connected between the anode of
said second diode and said electric power source terminal; the
collector of said first longitudinal bipolar transistor is
connected with said ground terminal and the emitter of said first
longitudinal bipolar transistor is connected with said pad; the
collector of said second longitudinal bipolar transistor is
connected with said pad and the emitter of said second longitudinal
bipolar transistor is connected with said electric power source
terminal; and at least either of said first diode, said first
resistor and said first longitudinal bipolar transistor or said
second diode, said second resistor and said second longitudinal
bipolar transistor are provided.
9. The ESD protection apparatus according to claim 2, wherein said
pad is an electric power source terminal; said longitudinal bipolar
transistor is of NPN type; an anode of said diode is connected with
said pad and a cathode of said diode is connected with a base of
said longitudinal bipolar transistor; a resistor is connected
between the cathode of said diode and a ground terminal; a
collector of said longitudinal bipolar transistor is connected with
said pad and an emitter of said longitudinal bipolar transistor is
connected with said ground terminal; and at least either of said
first diode, said first resistor and said first longitudinal
bipolar transistor or said second diode, said second resistor and
said second longitudinal bipolar transistor are provided.
10. The ESD protection apparatus according to claim 2, wherein said
pad is an electric power source terminal; said longitudinal bipolar
transistor is of PNP type; an anode of said diode is connected with
a base of said longitudinal bipolar transistor and a cathode of
said diode is connected with a ground terminal; a resistor is
connected between the anode of said diode and said electric power
source terminal; a collector of said longitudinal bipolar
transistor is connected with said ground terminal and an emitter of
said longitudinal bipolar transistor is connected with said pad;
and at least either of said first diode, said first resistor and
said first longitudinal bipolar transistor or said second diode,
said second resistor and said second longitudinal bipolar
transistor are provided.
11. An ESD protection apparatus installed between a pad of a
semiconductor integrated circuit chip and an inner circuit of said
semiconductor integrated circuit chip, comprising: a trigger
element having a first longitudinal bipolar transistor whose
collector and base act as a diode to be broken down by overvoltage
applied to said pad and which discharges the accumulated electric
charge of said pad by being electrically communicated due to the
breakdown of the diode; and an ESD protection element having a
second longitudinal bipolar transistor for discharging the
accumulated electric charge of said pad by being electrically
communicated attributed to the breakdown of the diode.
12. The ESD protection device according to claim 11, wherein said
pad is an input terminal or an output terminal; said trigger
element comprises an NPN type longitudinal bipolar transistor A and
an NPN type longitudinal bipolar transistor B acting as said first
longitudinal bipolar transistor, and a first and a second
resistors; said ESD protection element comprises an NPN type
longitudinal bipolar transistor C and an NPN type longitudinal
bipolar transistor D acting as said second longitudinal bipolar
transistor; collectors of said longitudinal bipolar transistors A,
C are connected with said pad, bases thereof are connected with
each other and emitters thereof are connected with a ground
terminal; said first resistor is connected between the bases of
said longitudinal bipolar transistors A, C and said ground
terminal; collectors of said longitudinal bipolar transistors B, D
are connected with an electric power source terminal, bases thereof
are connected with each other and emitters thereof are connected
with said pads; said second resistor is connected between the bases
of said longitudinal bipolar transistors B, D and said pads; and at
least either of said first resistor and said first longitudinal
bipolar transistor or said second resistor and said second
longitudinal bipolar transistor are provided.
13. The ESD protection apparatus according to claim 11, wherein
said pad is an electric power source terminal; said first and
second longitudinal bipolar transistors are NPN type and their
collectors are connected with said pad and their bases are
connected with each other and their emitters are connected with a
ground terminal; and a resistor is connected between the bases of
said first and second longitudinal bipolar transistors and the
ground terminal.
14. The ESD protection apparatus according to claim 11, wherein
said pad is an input terminal or an output terminal; said trigger
element comprises a PNP type longitudinal bipolar transistor A and
a PNP type longitudinal bipolar transistor, B acting as said first
longitudinal bipolar transistor, and a first and a second
resistors; said ESD protection element comprises a PNP type
longitudinal bipolar transistor C and a PNP type longitudinal
bipolar transistor D acting as said second longitudinal bipolar
transistor; emitters of said bipolar transistors A, C are connected
with said pads, bases thereof are connected with each other and
collectors thereof are connected with a ground terminal; said first
resistor is connected between the bases of said longitudinal
bipolar transistors A, C and said pads; emitters of said
longitudinal bipolar transistors B, D are connected with an
electric power source terminal, bases thereof are connected with
each other and collectors thereof are connected with said pads;
said second resistor is connected between the bases of said
longitudinal bipolar transistors B, D and said electric power
source terminal; and at least either of said first resistor and
said first longitudinal bipolar transistor or said second resistor
and said second longitudinal bipolar transistor are provided.
15. The ESD protection apparatus according to claim 11, wherein
said pad is an electric power source terminal; said first and
second longitudinal bipolar transistors are PNP type, and
collectors thereof are connected with a ground terminal, bases
thereof are connected with each other and emitters thereof are
connected with said pads; and resistors are connected between the
bases of said first and second longitudinal bipolar transistors and
said pads.
16. The ESD protection apparatus according to claim 11, wherein
collector layers of said first longitudinal bipolar transistor and
an emitter layers of said second longitudinal bipolar transistor
are simultaneously formed.
17. The ESD protection apparatus according to claim 11, wherein a
collector layer of said first longitudinal bipolar transistor and
an emitter layer of said second longitudinal bipolar transistor are
a common layer.
18. The ESD protection apparatus according to claim 1, wherein said
longitudinal bipolar transistor or said diode comprises all or some
of: a first N.sup.- type well formed on a P type silicon substrate
surface; a second N.sup.- type well adjacent to the first N.sup.-
type well and formed on said P type silicon substrate surface; a
second N.sup.+ layer formed on the second N.sup.- type well
surface; a P.sup.- type well formed on said first N.sup.- type well
surface; a P.sup.+ layer and a first N.sup.+ layer formed on the
P.sup.- type well surface apart from each other; and an insulation
material installed between the P.sup.+ layer and the first N.sup.+
layer for preventing an electric connection with said P+.sup.+
layer and the first N.sup.+ layer, and said second N.sup.- type
well and said P.sup.- type well are insulated by the insulation
material for isolation, and said P type silicon substrate and said
P.sup.- type well are insulated by the insulation material for
isolation.
19. The ESD protection apparatus according to claim 1, wherein said
longitudinal bipolar transistor or said diode comprises all or some
of: a first P.sup.- type well formed on a N type silicon substrate
surface; a second P.sup.- type well adjacent to the first P.sup.-
type well and formed on said N type silicon substrate surface; a
second P.sup.+ layer formed on this second P.sup.- type well
surface; a N.sup.- type well formed on said first P.sup.- type well
surface; a N.sup.+ layer and a first P.sup.+ layer formed on the
N.sup.- type well surface apart from each other; and an insulation
material installed between the N.sup.+ layer and the first P.sup.+
layer for preventing the electric connection with said P.sup.+
layer and first N.sup.+ layer, and said second P.sup.- type well
and said N.sup.- type well are insulated by the insulation material
for isolation, and said N type silicon substrate and said N.sup.-
type well are insulated by the insulation material for
isolation.
20. The ESD protection apparatus according to claim 18, wherein
said P.sup.+ layer and said first and second N.sup.+ layers are
formed simultaneously with the P.sup.+ layer and the N.sup.+ layers
of a CMOS transistor constituting said inner circuit.
21. The ESD protection apparatus according to claim 19, wherein
said N.sup.+ layer and said first and second P.sup.+ layers are
formed simultaneously with the N.sup.+ layers and the P.sup.+ layer
of the CMOS constituting said inner circuit.
22. The ESD protection apparatus according to the claim 18, wherein
said second N.sup.- type well is formed simultaneously with the
N.sup.- type well of the CMOS transistor constituting said inner
circuit.
23. The ESD protection apparatus according to the claim 19, wherein
said second P.sup.- type well is formed simultaneously with the
P.sup.- type well of the CMOS transistor constituting said inner
circuit.
24. The ESD protection apparatus according to claim 18, wherein
said insulation material is a dummy gate electrode or a simple
insulation film formed simultaneously with a gate electrode and a
gate insulation film of the CMOS transistor constituting said inner
circuit.
25. The ESD protection apparatus according to claim 24, wherein
said dummy gate electrode or said insulation film is formed in a
ring shape on said silicon substrate surface.
26. The ESD protection apparatus according to claim 1, wherein said
diode comprises: an N.sup.- type well formed on a P type silicon
substrate surface; a P.sup.+ layer and an N.sup.+ layer formed on
the N.sup.- type well surface apart from each other; and an
insulation material formed inside from said P type silicon
substrate surface between the P.sup.+ layer and N.sup.+ layer.
27. The ESD protection apparatus according to claim 1, wherein said
diode comprises: a P.sup.- type well formed on an N type silicon
substrate surface; a P.sup.+ layer and an N.sup.+ layer formed on
the P.sup.- type well surface apart from each other; and an
insulation material formed inside from said P type silicon
substrate surface between the P.sup.+ layer and N.sup.+ layer.
28. The ESD protection apparatus according to claim 1, wherein said
diode comprises: an N.sup.- type well formed on a P type silicon
substrate surface; a P.sup.- type well formed on the N.sup.- type
well surface; a P.sup.+ layer and N.sup.+ layer formed on the
P.sup.- type well surface apart from each other; and an insulation
material installed on said P type silicon substrate surface between
the P.sup.+ layer and N.sup.+ layer for preventing electric
connection between said P.sup.+ layer and N.sup.+ layer, and said P
type silicon substrate and said P.sup.- type well are insulated by
the insulation material for isolation.
29. The ESD protection apparatus according to claim 1, wherein said
diode comprises: a P.sup.- type well formed on an N type silicon
substrate surface; an N.sup.- type well formed on the P.sup.- type
well surface; a P.sup.+ layer and N.sup.+ layer formed on the
N.sup.- type well surface apart from each other; and an insulation
material installed on said N type silicon substrate surface between
the P.sup.- layer and N.sup.+ layer for preventing electric
connection between said P.sup.+ layer and N.sup.+ layer, and said N
type silicon substrate and said N.sup.+ type well are insulated by
the insulation material for isolation.
30. The ESD protection apparatus according to claim 1, wherein said
diode comprises: a P.sup.- type well formed on a silicon substrate
surface; N.sup.+ layer and the P.sup.+ layer formed on the P.sup.+
type well surface apart from each other; and a dummy gate electrode
installed on said P.sup.- type well between the N.sup.+ layer and
P.sup.+ layer through an insulation film and connected with a
ground terminal.
31. The ESD protection apparatus according to claim 1, wherein said
diode comprises: a N.sup.- type well formed on a silicon substrate
surface; N.sup.+ layer and the P.sup.+ layer formed on the N.sup.-
type well surface apart from each other; and a dummy gate electrode
installed on said N.sup.- type well between the N.sup.+ layer and
P.sup.+ layer through an insulation film and connected with a
ground terminal.
32. A method for fabricating an ESD protection apparatus according
to claim 1, comprising: a first step of simultaneously forming an
N.sup.- type well of a CMOS transistor composing said inner circuit
and an N.sup.- type well for collector connection to be connected
with the collector of said longitudinal bipolar transistor on a P
type silicon substrate; a second step of simultaneously forming a
collector N.sup.- type well to be a collector of said longitudinal
bipolar transistor and an N.sup.- type well of said diode on said P
type silicon substrate; a third step of simultaneously forming a
P.sup.- type layer to be a base in the collector N.sup.- type well
of said longitudinal bipolar transistor and a P.sup.- type layer to
be an anode in the N.sup.- type well of said diode; a fourth step
of simultaneously forming an N.sup.+ type layer in the P.sup.- type
well of said CMOS transistor, an N.sup.+ type layer in the N.sup.-
type well for collector connection of said longitudinal bipolar
transistor, an N.sup.+ type layer to be an emitter in the P.sup.-
type layer of said longitudinal bipolar transistor, and an N.sup.+
type layer to be a cathode in the P.sup.- type layer of said diode;
and a fifth step of simultaneously forming a P.sup.+ type layer on
the N.sup.- type well of said CMOS transistor, a P.sup.+ type layer
on the P.sup.- type layer of said longitudinal bipolar transistor,
and a P.sup.+ type layer on the P.sup.- type layer of said
diode.
33. A method for fabricating the ESD protection apparatus according
to claim 2, comprising: a first step of simultaneously forming an
N.sup.- type well of a CMOS transistor constituting said inner
circuit and the N.sup.- type well for collector connection to be
connected with said longitudinal bipolar transistor on a P type
silicon substrate; a second step of simultaneously forming a
collector N.sup.- type well to be a collector of said longitudinal
bipolar transistor and the N.sup.- type well of said diode on said
P type silicon substrate; a third step of simultaneously forming a
P.sup.- type layer to be a base in the collector N.sup.- type well
of said longitudinal bipolar transistor and the P.sup.- type layer
to be a cathode in the N.sup.- type well of said diode; a fourth
step of simultaneously forming an N.sup.+ layer in the P.sup.- type
well of said CMOS transistor, the N.sup.+ layer in the N.sup.- type
well for collector connection of said longitudinal bipolar
transistor, the N.sup.+ layer to be an emitter in the P.sup.- type
layer of said longitudinal bipolar transistor, and the N.sup.+
layer to be an anode in the P.sup.- type layer of said diode; and a
fifth step of simultaneously forming the P.sup.+ layer in the
N.sup.- type well of said CMOS transistor, the P.sup.+ layer in the
P.sup.+ type layer of said longitudinal bipolar transistor and the
P.sup.- layer in the P.sup.- type layer of said diode.
34. The method for fabricating an ESD protection apparatus
according to claim 32, further comprising a step of forming a dummy
gate electrode simultaneously with a gate electrode of said CMOS
transistor in the region where the collector N.sup.- type well of
said longitudinal bipolar transistor and N.sup.- type well of said
diode are formed in said second step, wherein said dummy gate
electrode is to prevent connection in the subsequent steps between
the N.sup.+ type layers of said longitudinal bipolar transistor and
said diode formed in said fourth step and the P.sup.+ type layers
of said longitudinal bipolar transistor and said diode formed in
the fifth step.
35. The method for fabricating an ESD protection apparatus
according to claim 32, further comprising a step of forming an
insulation layer which prevents connection in the subsequent steps
between the N.sup.+ type layers of said longitudinal bipolar
transistor and said diode formed in said fourth step and the
P.sup.+ type layers of said longitudinal bipolar transistor and
said diode formed in the fifth step.
36. The method for fabricating an ESD protection apparatus
according to claim 32, wherein an N replaces said conductive type P
and a P replaces said conductive type N.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an ESD protection apparatus
to be installed in a semiconductor integrated circuit chip in order
to protect a semiconductor integrated circuit from electrostatic
discharge (ESD) and to a method for fabricating the protection
apparatus.
[0003] 2. Description of the Prior Art
[0004] A conventional ESD protection apparatus in the CMOS process
generally protects a semiconductor integrated circuit using a
MOSFET transverse parasitic bipolar transistor by releasing the
electric current in the transverse direction in a silicon
substrate. On the other hand, the ESD protection apparatus has been
required to be further miniaturized since the number of pins to be
mounted on one chip has been increased sharply following the recent
acute requirement of development of semiconductor integrated
circuits made finer.
BRIEF SUMMARY OF THE INVENTION
[0005] Object of the Invention
[0006] However, as the miniaturization has been proceeding further,
the electric current concentration and electric field concentration
upon the junction parts has been increased more, so that the ESD
protection apparatus has sometimes been broken owing to the heat
generation. Therefore, there has been a limit to further improve
the capability of the ESD protection apparatus. Further, the gate
insulation film of a CMOS transistor has recently been made
thinner, so that the gate insulation film sometimes has been broken
before the ESD protection apparatus starts operating (reference to
FIG. 33). Consequently, it has highly been expected to develop the
ESD protection apparatus capable of triggering at a lower
voltage.
[0007] Hence, the present invention aims to provide an ESD
protection apparatus in which electric current concentration and
electric field concentration upon the junction parts hardly take
place even if miniaturization is advanced and which is capable of
triggering at a lower voltage and to provide a method for
fabricating such an ESD protection apparatus.
SUMMARY OF THE INVENTION
[0008] The ESD protection apparatus of the present invention is to
be installed between a pad of a semiconductor integrated circuit
chip and an inner circuit of the semiconductor integrated circuit
chip. The ESD protection apparatus is provided with a trigger
element comprising a diode to be broken down by overvoltage applied
to the pad and an ESD protection element comprising a longitudinal
bipolar transistor for discharging the accumulated electric charge
of the pad by being electrically communicated attributed to the
breakdown of the diode (claim 1).
[0009] As compared with a transverse bipolar transistor, a
longitudinal bipolar transistor has a wide junction surface area
for the same occupancy surface area, so that even if
miniaturization is promoted, the electric current concentration and
the electric field concentration hardly take place. On the other
hand, a diode is easy to set a desired breakdown voltage by
changing the impurity concentration. Consequently, an ESD
protection apparatus in which electric current concentration and
electric field concentration upon the junction parts hardly take
place even if miniaturization is advanced and which is capable of
triggering at a lower voltage can be obtained by utilizing the
breakdown voltage of a diode for the trigger of a longitudinal
bipolar transistor.
[0010] A first practical example of an ESD protection apparatus of
the present invention is as follows (claim 3). The pad is an input
terminal or an output terminal. The trigger element comprises a
first and a second diodes and a first and a second resistors. The
ESD protection element comprises NPN type first and second
longitudinal bipolar transistors. Regarding the first diode, the
cathode is connected with the pad and the anode is connected with
the base of the first longitudinal bipolar transistor. Regarding
the second diode, the cathode is connected with an electric power
source terminal and the anode is connected with the base of the
second longitudinal bipolar transistor. The first resistor is
connected between the anode of the first diode and the ground
terminal. The second resistor is connected between the anode of the
second diode and the pad. Regarding the first longitudinal bipolar
transistor, the collector is connected with the pad and the emitter
is connected with the ground terminal. Regarding the second
longitudinal bipolar transistor, the collector is connected with
the electric power source terminal and the emitter is connected
with the pad. Incidentally, at least either of a first diode, a
first resistor and a first longitudinal bipolar transistor or a
second diode, a second resistor and a second longitudinal bipolar
transistor may be provided (the same is applied also for other
claims).
[0011] A second practical example of an ESD protection apparatus of
the present invention is as follows (claim 5). The pad is an
electric power source terminal. The longitudinal bipolar transistor
is NPN type. Regarding the diode, the cathode is connected with the
pad and the anode is connected with the base of the longitudinal
bipolar transistor. A resistor is connected between the anode of
the diode and a ground terminal. Regarding the longitudinal bipolar
transistor, the collector is connected with the pad and the emitter
is connected with the ground terminal.
[0012] An ESD protection apparatus of the present invention may has
the following constitution (claim 11). The trigger element
comprises, as a diode to be broken down by overvoltage applied to
the pad, a first longitudinal bipolar transistor whose collector
and base work and which discharges the accumulated electric charge
of the pad by being electrically communicated attributed to the
breakdown of the diode. The ESD protection element comprises a
second longitudinal bipolar transistor for discharging the
accumulated electric charge of the pad by being electrically
communicated attributed to the breakdown of the diode.
[0013] Practical examples of this case are as follows (claims 12,
13). The pad is an input terminal or an output terminal. The
trigger element comprises an NPN type longitudinal bipolar
transistor A and an NPN longitudinal bipolar transistor B working
as the first longitudinal bipolar transistor and a first and a
second resistors. The ESD protection element comprises an NPN type
longitudinal bipolar transistor C and an NPN type longitudinal
bipolar transistor D working as the second longitudinal bipolar
transistor. Regarding the longitudinal bipolar transistors A, C,
the collectors are connected with the pad and the bases are
connected with each other and the emitters are connected with a
ground terminal. The first resistor is connected between the bases
of the longitudinal bipolar transistors A, C and the ground
terminal. Regarding the longitudinal bipolar transistors B, D, the
collectors are connected with an electric power source terminal and
the bases are connected with each other and the emitters are
connected with the pad. The second resistor is connected between
the bases of the longitudinal bipolar transistors B, D and the pad
(claim 12).
[0014] The pad is an electric power source terminal. The first and
second longitudinal bipolar transistors are NPN type and their
collectors are connected with the pad and their bases are connected
with each other and their emitters are connected with a ground
terminal. A resistor is connected between the bases of the first
and second longitudinal bipolar transistors and the ground terminal
(claim 13).
[0015] The conductive types P and N maybe taken as reverse
conductive types N and P, respectively (claims 4, 6, 14 and 15).
Even if the P and the N are reversed, the kind of a carrier alone
is changed and naturally the same function can be realized.
Incidentally, when the longitudinal bipolar transistor is taken as
PNP type, the positions of the diode and the resistor are replaced
with each other.
[0016] The diode may comprise a single diode or plural diodes
connected in series, the overvoltage may be an forward voltage for
the diode and the breakdown may be a substantial breakdown by being
electrically communicated (claims 2 and 7 to 10). The diode forward
descending voltage is, compared with the breakdown voltage, hard to
depend on high impurity concentration and a low voltage.
Consequently, by selecting the number of diodes to be connected in
series, a desired substantial breakdown voltage can be accurately
set.
[0017] In the ESD protection apparatus according to claims 11, 12,
13 and 14 or 15, the collector layers of the above described first
longitudinal bipolar transistor and the above described second
longitudinal bipolar transistor may be as simultaneously formed
(claim 16).
[0018] In the ESD protection apparatus according to claims 11, 12,
13 and 14 or 15, the above described first longitudinal bipolar
transistor and the above described second longitudinal bipolar
transistor may have a common collector layer (claim 17).
[0019] In the ESD protection apparatus according to claims 1, 2, 3,
5, 7, 9, 11 and 12 or 13, the longitudinal bipolar transistor or
the diode comprises all or some of: a first N.sup.- type well
formed on the P type silicon substrate surface; a second N.sup.-
type well adjacent to this first N.sup.- type well and formed on
the P type silicon substrate surface; a second N.sup.+ layer formed
on this second N.sup.- type well surface; the P.sup.- type well
formed on the first N.sup.- type well surface; the P.sup.+ layer
and a first N.sup.+ layer formed on this P.sup.- type well surface
apart from each other; the insulation material installed between
these P.sup.+ layer and the first N.sup.+ layer for preventing the
electric connection with the P.sup.+ layer and the first N.sup.+
layer, wherein the second N.sup.- type well and the P.sup.- type
well may be insulated by the insulation material for isolation and
the P type silicon substrate and the P.sup.- type well may be
insulated by the insulation material for isolation (claim 18). In
this case, the conductive type P and N may be taken as the reverse
conductive N and P, respectively (claim 19).
[0020] In the ESD protection apparatus according to claim 18, the
P.sup.+ layer and the first and second N.sup.+ layers may be formed
simultaneously with the P.sup.+ layer and the N.sup.+ layer of the
CMOS transistor constituting the inner circuit (claim 20). The same
is also applied for the ESD protection apparatus according to claim
19 (claim 21).
[0021] In the ESD protection device according to claim 18, a second
N.sup.- type well may be formed simultaneously with the N.sup.-
type well of the CMOS transistor constituting the inner circuit
(claim 22). The same is also applied for the ESD protection
apparatus according to claim 19 (claim 23).
[0022] In the ESD protection device according to claim 18 or claim
19, the insulation material maybe a dummy gate or a mere insulation
material formed simultaneously formed with the gate electrode and
the gate insulation film of the CMOS transistor constituting the
inner circuit (claim 24). This dummy electrode or the insulation
film may be formed in a ring shape on the silicon substrate surface
(claim 25).
[0023] In the ESD protection apparatus according to claims 1, 2, 3,
5 and 7 or 9, the diode may comprises: the N.sup.- type well formed
on the P type silicon substrate surface; the P.sup.+ layer and the
N.sup.+ layer formed on the N.sup.- type well surface apart from
each other; and the insulation material formed in the inside from
the above described P type silicon substrate surface between these
P.sup.+ layer and N.sup.+ layer (Claim 26) . In this case, in the
ESD protection apparatus according to claims 1, 2, 4, 6 and 8 or
10, the conductive type P and N may be the reverse conductive type
N and P, respectively (claim 27).
[0024] In the ESD protection apparatus according to claims 1, 2, 3,
5 and 7 or 9, the diode comprises: the N.sup.- type well formed on
the P type silicon substrate surface; the P.sup.- type well formed
on this N.sup.- type well surface; the P.sup.+ layer and the N
.sup.+ layer formed on this P.sup.- type well surface apart from
each other; and the insulation material installed on the P type
silicon substrate surface between these P.sup.+ layer and N.sup.+
layer, wherein the P type silicon substrate and the P.sup.- type
well may be insulated by the insulation material for isolation
(claim 28). In this case, in the ESD protection apparatus according
to claims 1, 2, 4, 6 and 8 or 10, the conductive type P and N may
be taken as the reverse conductive type N and P, respectively
(claim 29).
[0025] An ESD protection apparatus of the present invention may
further have the following constitution (claim 30). The diode
comprises a P.sup.- type well formed on the surface of a silicon
substrate, an N.sup.+ type layer and a P.sup.+ type layer formed on
the P.sup.- type well surface at an interval from each other, and a
dummy gate electrode formed on the P.sup.- type well via an
insulation film and between the N.sup.+ type layer and the P.sup.+
type layer and connected with a ground terminal. In this case, the
electric field between the N.sup.+ layer and the dummy gate
electrode is intensified, the ESD trigger at a lower voltage.
Incidentally, the conductive type P and N may be the reverse
conductive type N and P, respectively (claim 31).
[0026] A method for fabricating an ESD protection apparatus
relevant to the present invention is a method for fabricating an
ESD protection apparatus according to claim 1 and comprises the
following steps (claim 32). (1) A first step of simultaneously
forming an N.sup.- type well of a CMOS transistor composing the
inner circuit and an N.sup.- type well for connector connection to
be connected with the collector of the longitudinal bipolar
transistor on a P type silicon substrate. (2) A second step of
simultaneously forming a collector N.sup.- type well to be a
collector of the longitudinal bipolar transistor and an N.sup.-
type well of the diode on the P type silicon substrate. (3) A third
step of simultaneously forming a P.sup.- type layer to be a base in
the collector N.sup.- type well of the longitudinal bipolar
transistor and a P.sup.- type layer to be an anode in the N.sup.-
type well of the diode. (4) A fourth step of simultaneously forming
an N.sup.+ type layer in the P.sup.- type well of the CMOS
transistor, an N.sup.+ type layer in the N.sup.- type well for
collector connection of the longitudinal bipolar transistor, an
N.sup.+ type layer to be an emitter in the P.sup.- type layer of
the longitudinal bipolar transistor, and an N.sup.+ type layer to
be a cathode in the P.sup.- type layer of the diode. (5) A fifth
step of simultaneously forming a P.sup.+ type layer on the N.sup.-
type well of the CMOS transistor, a P.sup.+ type layer on the
P.sup.- type layer of the longitudinal bipolar transistor, and a
P.sup.+ type layer on the P.sup.- type layer of the diode. In this
case, the method for fabricating the ESD protection apparatus
according to claim 2 allows the anode and the cathode to be
reversed (claim 33).
[0027] An ESD protection apparatus relevant to the present
invention can be fabricated simultaneously in the fabrication
process of a CMOS transistor except the steps (2) and (3). Since
the steps (2) and (3) comprise ion implantation in the same parts,
required is only one sheet of mask to be added in the conventional
CMOS transistor fabrication process.
[0028] Further, the ESD protection apparatus fabrication method may
further comprise a step of forming a dummy gate electrode
simultaneously with a gate electrode of the CMOS transistor in the
region where the collector N.sup.- type well of the longitudinal
bipolar transistor and N.sup.- type well of the diode are formed in
the second step (2). Incidentally, the dummy gate electrode is to
prevent connection between the N.sup.+ type layers of the
longitudinal bipolar transistor and the diode formed in the step
(4) and the P.sup.+ type layers of the longitudinal bipolar
transistor and the diode formed in the step (5) in the subsequent
steps (claim 34). Alternatively, the ESD protection apparatus
fabrication method may further comprise a step of forming an
insulation layer which prevents connection between the N.sup.+ type
layers of the longitudinal bipolar transistor and the diode formed
in the step (4) and the P.sup.+ type layers of the longitudinal
bipolar transistor and the diode formed in the step (5) in the
subsequent steps (claim 35). In the method for fabricating the ESD
protection apparatus relevant to the present invention also, the
conductive type P and N may be the reverse type N and P,
respectively (claim 36).
[0029] In other words, as a method for protecting a semiconductor
device from electrostatic discharge (ESD) , the present invention
provides a structure of an ESD protection apparatus in which a
trigger element working at a low voltage and a longitudinal bipolar
transistor are formed employing a fabrication method mutually
compatible with a conventional CMOSFET fabrication process and
which prevents electric current concentration and provides high ESD
withstand level by enabling the trigger element to work at a lower
voltage at which the gate insulation film of a MOS transistor in
the inside is not broken at the time when the electrostatic pulses
are applied to the input/output pad or an electric power source pad
and making the longitudinal bipolar transistor work by the
triggered electric current, and releasing the large quantity of
electric charge in the longitudinal direction of the silicon
substrate and the present invention provides a method for
fabricating an ESD protection apparatus with such a structure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0030] FIG. 1 is a circuit diagram illustrating a first embodiment
of an ESD protection apparatus of the present invention;
[0031] FIG. 2 is a plan view of the ESD protection apparatus of
FIG. 1;
[0032] FIG. 3 is a longitudinal cross-section figure cut along the
III-III line in FIG. 2;
[0033] FIG. 4 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 2 and FIG. 3;
[0034] FIG. 5 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 2 and FIG. 3;
[0035] FIG. 6 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 2 and FIG. 3;
[0036] FIG. 7 is a graph showing the voltage-ampere characteristic
in case of applying electrostatic pulses of ESD to the pad in the
ESD protection apparatus of FIG. 1;
[0037] FIG. 8 is a graph showing the breakdown current values per
unit length in case of using the ESD protection apparatus of FIG. 1
and in case of using a transverse parasitic bipolar transistor, a
conventional MOS transistor;
[0038] FIG. 9 is a circuit diagram illustrating a second embodiment
of an ESD protection apparatus of the present invention;
[0039] FIG. 10 is a plan view illustrating a third embodiment of an
ESD protection apparatus of the present invention;
[0040] FIG. 11 is a longitudinal cross-section figure cut along the
XI-XI line in FIG. 10;
[0041] FIG. 12 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 10 and FIG.
11;
[0042] FIG. 13 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 10 and FIG.
11;
[0043] FIG. 14 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 10 and FIG.
11;
[0044] FIG. 15 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 10 and FIG.
11;
[0045] FIG. 16 is a circuit diagram illustrating a fourth
embodiment of an ESD protection apparatus of the present
invention;
[0046] FIG. 17 is a plane view of the ESD protection apparatus in
FIG. 16;
[0047] FIG. 18 is a longitudinal cross-section figure cut along the
XVIII-XVIII line in FIG. 17;
[0048] FIG. 19 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 16;
[0049] FIG. 20 is a cross-section figure showing the method for
fabricating the ESD protection apparatus of FIG. 16;
[0050] FIG. 21 is a plan view illustrating a fifth embodiment of an
ESD protection apparatus of the present invention;
[0051] FIG. 22 is a longitudinal cross-section figure cut along the
XXII-XXII line in FIG. 21;
[0052] FIG. 23 is a plan view illustrating a sixth embodiment of an
ESD protection apparatus of the present invention;
[0053] FIG. 24 is a longitudinal cross-section figure cut along the
XXIV-XXIV line in FIG. 23;
[0054] FIG. 25 is a cross-section figure illustrating a seventh
embodiment of an ESD protection apparatus of the present
invention;
[0055] FIG. 26 is a circuit diagram showing a eighth embodiment of
the ESD protection apparatus relevant to the present invention;
[0056] FIG. 27 is a longitudinal cross-sectional view of the ESD
protection apparatus of FIG. 26;
[0057] FIG. 28 is a graph showing a comparison result of
characteristics of a trigger element using the breakdown of an
inverse diode and the trigger element multistage-connecting the
forward diodes in series;
[0058] FIG. 29 is a graph showing an electric current voltage
characteristic at the time when electrostatic pulses of the ESD are
applied to the pad in the ESD protection apparatus of FIG. 26;
[0059] FIG. 30 is a circuit diagram showing a ninth embodiment of
the ESD protection apparatus relevant to the present invention;
[0060] FIG. 31 is a cross-sectional view of a tenth embodiment of
the ESD protection apparatus relevant to the present invention;
[0061] FIG. 32A is a cross-sectional view showing a diode
comprising a P.sup.+ layer/an N well formed in the existing CMOS
process in the eighth embodiment;
[0062] FIG. 32B is a cross-sectional view showing one portion of
the longitudinal bipolar transistor in the tenth embodiment;
and
[0063] FIG. 33 is a graph showing the voltage-ampere characteristic
in case of applying electrostatic pulses of ESD of a pad in a
conventional technique.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0064] FIG. 1 to FIG. 3 illustrates a first embodiment of an ESD
protection apparatus relevant to the present invention and FIG. 1
is a circuit diagram, FIG. 2 is a plan view, and FIG. 3 is a
longitudinal cross-section figure along the III-III line in FIG. 2.
Hereinafter, description will be given with reference to these
figures. The ESD protection apparatus of this embodiment works as
an input buffer protection circuit.
[0065] The ESD protection apparatus of this embodiment is installed
between an input terminal (an input pad) 6 of a semiconductor
integrated circuit chip and a CMOS transistor 100 and comprises a
trigger element 310 comprising diodes 311, 312 which are broken
down by overvoltage applied to the input terminal 6 and an ESD
protection element 210 comprising longitudinal bipolar transistors
211, 212 for discharging the accumulated electric charge of the
input terminal 6 by being electrically communicated owing to the
breakdown of the diodes 311, 312. Incidentally, FIG. 2 and FIG. 3
show only the longitudinal bipolar transistor 211 as some of ESD
protection element 210 and only the diode 311 as some of the
trigger element 310.
[0066] The CMOS transistor 100 is a CMOS inverter comprising an
NMOS transistor 101 and a PMOS transistor 102. Regarding the diode
311, the cathode is connected with the input terminal 6 and the
anode is connected with the base of the longitudinal bipolar
transistor 211. Regarding the diode 312, the cathode is connected
with an electric power terminal 7 and the anode is connected with
the base of the longitudinal bipolar transistor 212. A resistor 313
is connected with the anode of the diode 311 and a ground terminal
8. A resistor 314 is connected between the anode of the diode 312
and the input terminal 6. The longitudinal bipolar transistors 211,
212 are both NPN type. Regarding the longitudinal bipolar
transistor 211, the collector is connected with the input terminal
6 and the emitter is connected with the ground terminal 8.
Regarding the longitudinal bipolar transistor 212, the collector is
connected with electric power terminal 7 and the emitter is
connected with the input terminal 6. The resistors 313, 314 are
made of a singly crystal silicon, a polysilicon, a metal or the
like formed in the same semiconductor integrated circuit chip.
[0067] Since today it has swiftly been promote to make the gate
insulation film of a CMOS transistor thinner, it is required for
the ESD protection apparatus 210 works at a lower voltage at which
the gate insulation film of the CMOS transistor 100 is broken. In
this embodiment, the base potential of the longitudinal bipolar
transistors 211, 212 is increased by voltage decreased at the time
when the trigger current, which is the breakdown current of the
diodes 311, 312, flows in the resistors 313, 314 to turn on
longitudinal bipolar transistors 211, 212. Consequently, the large
quantity of the electric charge attributed to the static
electricity accumulated in the input terminal 6 is released in the
longitudinal direction of the silicon substrate. As a result,
electric current concentration can be prevented and a high ESD
withstand level can be obtained.
[0068] To form the trigger element 310 comprising the ESD
protection element 210 comprising longitudinal bipolar transistors
211, 212 and the diodes 311, 312 can be carried out by adding only
one ion implantation mask in the common fabrication process of a
CMOSFET. Hereinafter, the fabrication method will be described with
the reference to FIG. 2 and FIG. 3.
[0069] At first, the ESD protection element 210 will be described.
Simultaneously with the N.sup.+ type diffusion layer 1 of the CMOS
transistor 100, the collector lead parts 10 and the emitters 11 are
formed and simultaneously with the P.sup.+ type diffusion layer 2
of the CMOS transistor 100, the base lead parts 12 are formed. The
dummy gate electrodes 13 formed simultaneously with the gate
electrodes 3 of the CMOS transistor 100 are employed in order to
separate the silicide of the emitters 11 and the base lead parts
12. The dummy gate electrodes 13 are not for applying potential but
separate the silicide. Opening parts 50 are formed in a resist
using an additional mask for ion implantation and ion implantation
is carried out to simultaneously form the P.sup.- region bases 16
and the collector N wells 17. The collector N wells 17 formed at
that time and the collector lead parts 10 formed separately are
connected with each other by the N wells 14 for connection
simultaneously formed with the N well 5 of the CMOS transistor 100.
Consequently, longitudinal bipolar transistors can be fabricated
utilizing the CMOS process. Incidentally, the ion implantation may
be carried out either before or after of the formation of the gate
electrodes 3.
[0070] The trigger element 310 will be described next. The N.sup.30
P.sup.- type diode has the same structure as the emitters 11 and
bases 16 of the ESD protection element 210 and simultaneously with
the N.sup.+ type diffusion layer 1 of the CMOS transistor 100, the
N.sup.+ part 21 is formed and simultaneously with the P.sup.- type
diffusion layer 2 of the CMOS transistor 100, the lead parts 22 of
the P.sup.- parts 26 are formed. Consequently, it is enabled to set
a desired trigger voltage and the leakage level in the opposed
direction.
[0071] FIG. 4 to FIG .6 are cross-section illustrations
illustrating the method for fabricating the ESD protection
apparatus of this embodiment. Hereinafter, the method for
fabricating the ESD protection apparatus of the present invention
will be described in details.
[0072] At first, as illustrated in FIG. 4, simultaneously with
formation of N well 5 of CMOS transistor 100, collector lead parts
10 and N wells 14 for connection of the ESD protection element 210
are formed. The doping concentration of these regions is about
10.sup.17/cm.sup.-3 to 10.sup.18/cm.sup.31 3. Also, simultaneously
with formation of the gate electrodes 3 of the CMOS transistor 100,
the dummy gate electrodes 13 of the ESD protection element 210 and
a dummy gate electrode 23 of the trigger element 310 are formed.
That is for preventing the emitters 11 and the base lead parts 12
of the ESD protection element 210 from being connected with the
silicide formed later on the diffusion layer. In the same manner,
that is for preventing the N.sup.+ part 21 and the lead parts 22 of
trigger element 310 from being connected with the silicide
later.
[0073] Successively, using opening parts 50 of a resist with a
prescribed shape as a mask as illustrated in FIG. 5, ion
implantation in about 10.sup.18/cm.sup.-3 dose is carried out to
form the bases 16 of the ESD protection element 210 and
continuously ion implantation in about 10.sup.18/cm.sup.-3 dose is
carried out to form the collector N wells 17. At that time, the
P.sup.- part 26 and the N well 27 of the trigger element 310 are
simultaneously formed.
[0074] Successively, as illustrated in FIG. 6, simultaneously with
formation of the N.sup.+ type diffusion layer 1 of the CMOS
transistors 100, the collector lead parts 10, emitters 11, N.sup.+
parts 21, and the like are formed.
[0075] Successively, as illustrated in FIG. 3, simultaneously with
the P.sup.- type diffusion layer 2 of the CMOS transistors 100, the
base lead parts 12 and lead parts 22 are formed. Finally, wirings
are formed on these upper layers to form a circuit as illustrated
in FIG. 1.
[0076] Next, the operation of the ESD protection apparatus of this
embodiment will be described with the reference to FIG. 1 and FIG.
3.
[0077] The following description is of the operation at the time
when the electrostatic pulses are applied to the input terminal 6.
At first , when pulses of positive ESD relative to the ground
terminal 8 are applied to the input terminal 6, high voltage is
applied to the ESD protection element 210, trigger element 310, and
the gate insulation film of the CMOS transistors 100. Therefore, it
is required to release the electric charge by ESD by operation of
the ESD protection element 210 before the gate insulation film of
the CMOS transistors 100 is broken down.
[0078] If the gate insulation film of the CMOS transistors 100 is 4
nm, the gate insulation film is broken by stress of constant
voltage of about 8V. That is, it is required for the ESD protection
element 210 to operate at a voltage lower than that. However, in
the case where the ESD protection element 210, which comprises
longitudinal bipolar transistors, is formed, since the withstand
voltage between the collector N wells 17 and the P.sup.- region
bases 16 are about as high as 10V, it is insufficient to protect
the CMOS transistors 100 whose gate insulation film is thin and
fine only by the ESD protection element 210.
[0079] Hence, it is required to form the trigger element 310 which
operates at a voltage as low as possible and not lower than the
electric power source voltage. Since the P.sup.- part 26 of the
trigger element 310 is formed by ion implantation, a desired
trigger voltage or leakage level in the opposed direction can be
set by controlling the dose quantity and it is easy to obtain
trigger voltage of about 4 V.
[0080] FIG. 7 shows the voltage-ampere characteristic in case of
electrostatic pulses application to the pad. At first, when the
trigger element 310 works at about 4V, the resultant trigger
current and the resistor 313 increase the base potential of the ESD
protection element 210 to start the ESD protection element 210.
When the ESD protection element 210 starts working, the electric
charge applied to the input terminal 6 by the ESD can be released
to the ground terminal 8 through the longitudinal bipolar
transistor 211. Consequently, if the withstand voltage of the gate
insulation film of the inner circuits of the CMOS transistors 100
is 8 V, the electric charge can be released at a lower voltage than
that, so that the breakdown of the gate insulation film can be
prevented.
[0081] Further, when pulses of negative ESD are applied to the
input terminal 6 in relation to the ground terminal 8, since the
collector N wells 17 and the P substrate 51 of the ESD protection
element 210 shown in FIG. 3 are in N.sup.+/P.sup.- normal
direction, electric charge can smoothly be released.
[0082] FIG. 8 shows the breakdown electric current values per unit
length in case of using the ESD protection apparatus of the present
invention and in case of using a transverse parasitic bipolar
transistor, which is a conventional MOS transistor. The breakdown
electric current of the ESD protection element of this embodiment
comprising longitudinal bipolar transistors is higher than that of
an ESD protection element comprising transverse bipolar
transistors. Also, if the inner gate insulation film is as thin as
about 2 nm, the breakdown electric current is sharply lowered in
case of the transverse bipolar transistors, the decrease is slight
in case of the longitudinal bipolar transistors.
[0083] FIG. 9 is a circuit diagram showing a second embodiment of
an ESD protection apparatus relevant to the present invention.
Hereinafter, description will be given with reference to the
figure. The ESD protection apparatus of this embodiment works as an
electric power source protection circuit.
[0084] The ESD protection apparatus of this embodiment is installed
between an electric power terminal (an electric power pad) 7 of a
semiconductor integrated circuit chip and an inner circuit 103 and
comprises a trigger element 315 comprising a diode 316 to be broken
down by overvoltage applied to the electric power terminal 7 and an
ESD protection element 213 comprising a longitudinal bipolar
transistor 214 for discharging the accumulated electric charge of
the electric power terminal 7 by being electrically communicated
owing to the breakdown of the diode 316.
[0085] Regarding the diode 316, the cathode is connected with the
electric power terminal 7 and the anode is connected with the base
of the longitudinal bipolar transistor 214. A resistor 317 is
connected between the anode of the diode 316 and a ground terminal
8. Regarding the longitudinal bipolar transistor 214, it is NPN
type, and the collector is connected with the electric power
terminal 7 and the emitter is connected with the ground terminal
8.
[0086] The plan view and the cross-section figure are same as FIG.
2 and FIG. 3 except the reference numerals. Consequently, the ESD
protection apparatus of this embodiment also performs the same
functions and effects.
[0087] FIG. 10 to FIG. 15 illustrate a third embodiment of an ESD
protection apparatus relevant to the present invention. FIG. 10
shows a plan view, FIG. 11 shows the longitudinal cross-section
figure cut along the XI-XI line in FIG. 10, and FIG. 12 to FIG. 15
show the cross-section figures illustrating the fabrication method.
Hereinafter, description will be given with reference to these
figures. Incidentally, the same reference numerals are assigned to
these same as the parts in FIG. 2 and FIG. 6 and their description
is omitted.
[0088] The ESD protection apparatus of this embodiment is an
example in which insulation films 18, 28 (SiO.sub.2 or SiN)
covering the diffusion layer as to prevent silicide formation are
used for resistor element formation in place of the dummy gate
electrodes 13, 23 for silicide separation (in FIG. 2 and FIG.
3).
[0089] At first, as illustrated in FIG. 12, simultaneously with
formation of the N well 5 of the CMOS transistors 100, the N well
14 for connection with the collector lead parts 10 of the ESD
protection element 200 is formed.
[0090] Successively, as illustrated in FIG. 13, using opening parts
50 of a resist with a prescribed shape as a mask, ion implantation
is carried out to form the bases 16 of the ESD protection element
200 and continuously ion implantation is carried out to form the
collector N wells 17. At that time, the P.sup.- part 26 and the N
well 27 of the trigger element 300 are simultaneously formed.
[0091] Successively, as illustrated in FIG. 14, simultaneously with
formation of the N.sup.+ type diffusion layer 1 of the CMOS
transistors 100, the collector lead parts 10, emitters 11, N.sup.+
parts 21, and the like are formed.
[0092] Successively, as illustrated in FIG. 15, simultaneously with
the P.sup.+ type diffusion layer 2 of the CMOS transistors 100, the
base lead parts 12, lead parts 22, and the like are formed.
[0093] Successively, as illustrated in FIG. 11, the insulation film
18 in ESD protection element 200 and the insulation film 28 in the
trigger element 310 are formed. That is for preventing the
connection of the emitters 11 and the base lead parts 12 of ESD
protection element 200 with each other by the silicide formed in
the diffusion layer thereafter. Simultaneously, that is also for
preventing the connection of the N.sup.+ part 21 and the lead parts
22 of trigger element 300 with each other by the silicide.
[0094] Finally, wirings are formed on these upper layers to form a
circuit as illustrated in FIG. 1.
[0095] FIG. 16 to FIG. 18 illustrate a fourth embodiment of an ESD
protection apparatus relevant to the present invention. FIG. 16
shows a circuit diagram, FIG. 17 shows a plan view, and FIG. 18
shows the longitudinal cross-section figure cut along the
XVIII-XVIII line in FIG. 17. Hereinafter, description will be given
with reference to these figures. In the ESD protection apparatus of
this embodiment, the trigger element is also used as a longitudinal
bipolar transistor of the ESD protection element.
[0096] The ESD protection apparatus of this embodiment is installed
between an electric power terminal (an electric power pad) 7 of a
semiconductor integrated circuit chip and an inner circuit 103 and
comprises a trigger element 400 comprising a diode 402 to be broken
down by overvoltage applied to the electric power terminal 7 and an
ESD protection element 200 comprising a longitudinal bipolar
transistor 201 for discharging the accumulated electric charge of
the electric power terminal 7 by being electrically communicated
owing to the breakdown of the diode 402.
[0097] The diode 402 is between the collector and the base of the
longitudinal bipolar transistor 401. The cathode of the diode 402,
which the collector of the longitudinal bipolar transistor 401, is
connected with the electric power terminal 7 and the anode of the
diode 402, which is the base of the longitudinal bipolar transistor
401, is connected with the base of the longitudinal bipolar
transistor 201. A resistor 403 is connected between the anode of
the diode 402, which is the base of the longitudinal bipolar
transistor 401, and a ground terminal 8. Regarding the longitudinal
bipolar transistors 201, 402, they are NPN type, and the collector
is connected with the electric power terminal 7 and the emitter is
connected with the ground terminal 8.
[0098] In this embodiment, emitter lead parts 40 are formed in the
trigger element 400 and connected as illustrated in FIG. 16 and
FIG. 18. By connecting in such a manner, the longitudinal bipolar
transistor 401 is formed in the trigger element 400 and the trigger
element 400 can work as an ESD protection element. The base
potential of the longitudinal bipolar transistors 201, 401 is
increased by the trigger current of the diode 402 composed of the
N.sup.+ part (the collector) 41 and the P.sup.- part (the base) 46
of the trigger element 400 and the resistor 403 and owing the
cooperation, the electric charge attributed to the static
electricity accumulated in the electric power terminal 7 can be
released by both of them. Incidentally, although the ESD protection
apparatus of this embodiment is employed as the electric power pad,
it may be also employed as an input pad or an output pad by
installing two as same in the first embodiment.
[0099] FIG. 19 and FIG. 20 are cross-section figures illustrating
the method for fabricating the ESD protection apparatus of this
embodiment. Hereinafter, detailed description of the method for
fabricating the ESD protection apparatus of this embodiment will be
given with reference to FIG. 18 to FIG. 20.
[0100] At first, simultaneously with formation of N well 5 of the
CMOS transistors 100, N wells 14 for connection for the collector
lead parts 10 of the ESD protection element 200 and N wells 44 for
emitter connection of the trigger element 400 are formed.
[0101] Successively, as illustrated in FIG. 19, using opening parts
50 of a resist with a prescribed shape as a mask, ion implantation
is carried out to form the bases 16 of the ESD protection element
200 and continuously ion implantation is carried out to form the
collector N wells 17. At that time, the P.sup.- part 46 and the
emitter N well 47 of the trigger element 400 are simultaneously
formed.
[0102] Successively, as illustrated in FIG. 20, simultaneously with
formation of the N.sup.+ type diffusion layer 1 of the CMOS
transistors, the collector lead parts 10 and emitters 11 of the ESD
protection element 200, as well as the emitter lead parts 40 and
collector 41 of the trigger element 400 are formed. Further,
simultaneously with formation of the P.sup.+ type diffusion layer 2
of the CMOS transistors 100, the base lead parts 12 and lead parts
42 of the P.sup.- parts 46 to be base of the trigger element 400
are formed.
[0103] The insulation film 18 of the ESD protection element 200 and
the insulation film 48 of the trigger element 400 are formed. That
is for preventing the emitters 11 and the base lead parts 12 of the
ESD protection element 200 from being connected with the silicide
formed later on the diffusion layer. In the same manner, that is
for preventing the N.sup.+ part 41 and the lead parts 42 of trigger
element 400 from being connected with the silicide later.
[0104] Finally, wirings are formed on these upper layers to form a
circuit as illustrated in FIG. 16.
[0105] FIG. 21 to FIG. 22 illustrate a fifth embodiment of an ESD
protection apparatus relevant to the present invention. FIG. 21
shows a plan view and FIG. 22 shows the longitudinal cross-section
figure cut along the XXII-XXII line in FIG. 21. Hereinafter,
description will be given with reference to these figures. In the
ESD protection apparatus of this embodiment, the collector of the
ESD protection elements is utilized in common in order to
miniaturize the surface area.
[0106] The ESD protection apparatus 230 of this embodiment
comprises one collector N well 17' by making two collector N wells
17 in common in the ESD protection element 200 of the third
embodiment illustrated in FIG. 10 and FIG. 11. The surface area is
miniaturized by using collector lead parts 10 only in both ends of
the collector N well 17'. The method for fabricating the ESD
protection apparatus of this embodiment is same as that of the
third embodiment illustrated in FIG. 12 to FIG. 15.
[0107] FIG. 23 to FIG. 24 illustrate a sixth embodiment of an ESD
protection apparatus relevant to the present invention. FIG. 23
shows a plan view and FIG. 24 shows the longitudinal cross-section
figure cut along the XXIV-XXIV line in FIG. 23. Hereinafter,
description will be given with reference to these figures. In the
ESD protection apparatus of this embodiment, the ESD protection
element and the trigger element are made in common in order to
miniaturize the surface area.
[0108] The ESD protection elements 240 and the trigger element 310
of this embodiment are formed by combining two bases 16 and the
P.sup.- part 26 of the ESD protection element 200 and the trigger
element 300 in the third embodiment illustrated in FIG. 10 and FIG.
11 into one base 16' and at the same time combining two collector N
wells 17 and the N well 27 of the ESD protection element 200 and
the trigger element 300 in the third embodiment into one collector
N well 19. The surface area is miniaturized by using collector lead
parts 10 of the ESD protection elements 240 only in both ends. The
method for fabricating the ESD protection apparatus of this
embodiment is same as that of the third embodiment illustrated in
FIG. 12 to FIG. 15.
[0109] FIG. 25 illustrates the longitudinal cross-section figure of
a seventh embodiment of an ESD protection apparatus relevant to the
present invention. Hereinafter, description will be given with
reference to the figure. In the ESD protection apparatus of this
embodiment, the ESD protection element is made to be a trigger
element capable of triggering at lower voltage.
[0110] The ESD protection apparatus of this embodiment is same as
the first embodiment except that the dummy gate electrode 23 of the
trigger element 310 is fixed in the ground. In case of fixing the
dummy gate electrodes 23 of the trigger element 310 in the ground,
the electric field is intensified between the N.sup.+ part 21 and
the dummy gate electrodes 23, so that triggering is caused at a
lower voltage.
[0111] FIG. 26 and FIG. 27 show a eighth embodiment of the ESD
protection apparatus relevant to the present invention, FIG. 26 is
a circuit diagram and FIG. 27 is a cross-sectional view.
Hereinafter, description will be given with reference to these
drawings. Parts identical with those in FIGS. 1 and 3 are given the
same reference numerals as in FIGS. 1 and 3, and description
thereof will be omitted. The ESD protection apparatus of the
present embodiment acts as an input buffer protection circuit.
[0112] The ESD protection apparatus of the present embodiment is
installed between an input terminal (an input pad) 6 of a
semiconductor integrated circuit chip and a CMOS transistor 100 and
comprises a trigger element 510 comprising diodes 511, 512 which
are broken down by overvoltage applied to the input terminal 6 and
an ESD protection element 210 comprising longitudinal bipolar
transistors 211, 212 for discharging the accumulated electric
charge of the input terminal 6 by being electrically communicated
owing to the breakdown of the diodes 511, 512. The diodes 511, 512
are a plurality of diodes connected in series, and the overvoltage
is a forward voltage for the diodes 511, 512 and the breakdown is a
substantial breakdown by being electrically communicated.
Incidentally, the diodes 511, 512 are illustrated in FIG. 26 as
four diodes connected in series, but in FIG. 27 simplified and
illustrated as two diodes connected in series for convenience's
sake.
[0113] Regarding the diode 511, a cathode is connected with a base
of the longitudinal bipolar transistor 211 and an anode is
connected with the input terminal 6. Regarding the diode 512, the
cathode is connected with the base of the longitudinal bipolar
transistor 212 and the anode is connected with an electric power
source terminal 7. A resistor 313 is connected between the cathode
of the diode 511 and a ground terminal 8. A resistor 314 is
connected between the cathode of the diode 512 and the input
terminal 6.
[0114] The longitudinal bipolar transistor 211, 212 use the same
transistors as those of a first embodiment. The diodes 511, 512 are
formed by an N.sup.+ diffusion layer 1, a P.sup.+ diffusion layer 2
and an N well 5 and the like which are formed at the time of the
usual CMOS process.
[0115] In the first embodiment, for the trigger element, the
breakdown of the inverse diode was utilized. In contrast, in the
present embodiment, the trigger element 510 multistage-connected
for raising a forward diode equal to or more than an electric power
source voltage is employed.
[0116] Especially, a low voltage operation device having equal to
or less than 1.5V has an extremely thin gate insulation film and
therefore is broken down by application of equal to or more than
5V. For realizing low voltage trigger capable of preventing the
breakdown of the gate insulation film in this voltage range, the
present embodiment is effective. In the present embodiment, by
changing serial connection stages of the diode corresponding to the
electric power source voltage, a desired trigger voltage can be
secured.
[0117] FIG. 28 is a graph showing a comparison result of the
characteristics of the trigger element utilizing the breakdown of
the inverse diode and the trigger element multistage-connecting the
forward diodes in series. Hereinafter, description will be given
with reference to this illustration.
[0118] Regarding utilization of the inverse breakdown, when the
triggering at a voltage equal to or less than 5V is to be
performed, by thickening the concentration of coupling, the
lowering of the voltage to a certain degree is possible. However,
before the breakdown, a zener leak is increased, thereby causing a
drawback which is an increase of an off leak at the usual LSI
operation time. For this reason, the lowering of the breakdown
voltage to equal to or more than this is difficult. Hence, by using
the trigger element for multistage-connecting the forward diodes
and supplying the electric current to the base of the longitudinal
bipolar transistor, the ESD protection element triggering at much
lower voltage can be realized.
[0119] FIG. 29 is a graph showing an electric current voltage
characteristic when an ESD electrostatic pulse is applied to a pad
in the ESD protection apparatus of the present embodiment.
Hereinafter, description will be given with reference to this
illustration.
[0120] If a trigger voltage of one stage portion of the diode is
taken as Vf (about 0.6V), the trigger voltage Vf of the diodes of
four stages connected in series is Vf.times.4=about 2.4V. When a
surge of the ESD is applied to the pad and exceeds 2.4V, the
forward series connection diodes are electrically communicated and
inject the electric current into the base of the longitudinal
bipolar transistor. By this trigger electric current, the
longitudinal bipolar transistor which is a protection element of a
high driving force starts operation, thereby discharging a charge
of the ESD.
[0121] In recent years, the CMOS device operating at a low voltage
of about 1.2V uses an extremely thin gate insulation film having a
thickness of about equal to or less than 2.5 nm. The breakdown
withstand pressure of this gate insulation film is about 4V to 5V.
In such a case, by multistage-connecting the forward diodes in
series and setting the triggering voltage in such a manner as to be
larger than the electric power voltage of the CMOS inner circuit,
no malfunction is caused during actual operation of the LSI and the
triggering of the ESD discharge can be performed below the
withstand pressure of the gate insulation film.
[0122] FIG. 30 is a circuit diagram showing a ninth embodiment of
the ESD protection apparatus relevant to the present invention.
Hereinafter, description will be given with reference to this
illustration. The ESD protection apparatus of the present
embodiment acts as an electric power source protection circuit.
[0123] The ESD protection apparatus of the present embodiment
comprises a trigger element 515 comprising a diode 516 which is
provided between the power source terminal 7 and the inner circuit
103 of the semiconductor integrated circuit and is broken down by
overvoltage applied to an electric power source terminal 7, and an
ESD protection element 213 comprising the longitudinal bipolar
transistor 214 for discharging the accumulated electric charge of
the electric power source terminal 7 by being electrically
communicated owing to the breakdown of the diode 516. The diode 516
is a plurality of diodes connected in series, and the overvoltage
is a forward voltage for the diode 516 and the breakdown is a
substantial breakdown by being electrically communicated.
[0124] Regarding the diode 516, a cathode is connected with a base
of the longitudinal bipolar transistor 214 and an anode is
connected with the electric power source terminal 7. A resistor 317
is connected between the cathode of the diode 516 and a ground
terminal 8. A longitudinal bipolar transistor 214 is of NPN type,
and its collector is connected with the electric power source
terminal 7, and its emitter is connected with the ground terminal
8.
[0125] A cross-sectional view thereof corresponds to FIG. 27.
Consequently, the ESD protection apparatus of the present
embodiment also performs the same functions and effects as the
eighth embodiment.
[0126] FIG. 31 is a cross-sectional view showing a tenth embodiment
of the ESD protection apparatus relevant to the present invention.
Hereinafter, description will be given with reference to the
illustration. Incidentally, the circuit diagram of the ESD
protection apparatus of the present embodiment is the same as the
eighth embodiment (FIG. 26).
[0127] In the present embodiment, as a trigger element 510, the
diodes simultaneously formed at the time when the longitudinal
bipolar transistor is formed are used by connecting them in series
in a forward direction. In the eighth embodiment as shown in FIG.
27, a diode comprising P.sup.+ layers 2/an N well 5 is used. In
contrast, in the present embodiment, a diode comprising an N.sup.+
layer 521/a P.sup.- layer 526 formed at the time when the
longitudinal bipolar transistor is formed is used. In a high
electric current area at a time such as the ESD charge discharging
time, a resistance of a well is dominant and this resistance
determines a discharging capacity.
[0128] Regarding the diode comprising P.sup.+ layers 2/an N well 5
as shown in FIG. 27, the electric current flows under a separation
region and therefore a resistance is increased. In contrast to
this, in the present embodiment, a separation between the P.sup.+
layer 522/the N.sup.+ layer 521 is performed by a dummy gate 523 at
a formation time of the longitudinal bipolar transistor, and since
adjustment of the concentration of the P.sup.- layer 526 is
possible by additional injection of the longitudinal bipolar
transistor, the lowering of the resistance at the high electric
current area is possible.
[0129] In the diode comprising the P.sup.+ layers 2/the N well 5 as
shown in FIG. 27, since a parasitic longitudinal bipolar transistor
comprising the P.sup.+ layer/the N well 5/a P substrate 51 is
formed, the electric current flowing into the P substrate 51 is
generated. For this reason, the electric current to be supplied to
the longitudinal bipolar transistor which is a protection element
is reduced. However, in the present embodiment, since an N well 527
formed simultaneously with a collector layer 17 of an ESD
protection element 210 exists, the diode comprising the N.sup.+
layer 521/the P.sup.- layer 526 can prevent the electric current
flowing in a longitudinal direction, and therefore the electric
current can be supplied to the base of the ESD protection element
210 with high efficiency (refer to FIG. 32). Consequently,
according to the present embodiment, since a trigger electric
current can be supplied to a base of the longitudinal bipolar
transistor with high efficiency, the size of the trigger element
can be reduced.
[0130] Incidentally, the present invention is, needless to mention,
not limited to the foregoing first to the tenth embodiments. For
example, the P type may be taken as the N type and the N type may
be taken as the P type. Consequently, the NPN type may be taken as
the PNP type with each N type and P type taken as the inverse
conductive type.
[0131] In an ESD protection apparatus of the present invention,
since the breakdown voltage of a diode is used as a trigger of a
longitudinal bipolar transistor, electric current concentration and
electric field concentration are hardly caused in junction parts
even if miniaturization is promoted and moreover the characteristic
of triggering at a low voltage can be obtained. The method for
fabricating an ESD protection apparatus of the present invention is
make it easy to fabricate an ESD protection apparatus of the
present invention by adding only one mask in a common CMOS
process.
[0132] In other words, the effects of the present invention is as
follows. The first effect is that since electric current is
released in the longitudinal direction by employing a longitudinal
bipolar transistor, electric current concentration is suppressed as
compared with the case of releasing the electric current in the
transverse direction by using a conventional CMOSFET type parasitic
bipolar transistor and consequently the ESD protection element
itself is hardly broken. The second effect is that since the
electric current to be discharged for the same surface area is
high, the surface area required for an ESD protection element can
be miniaturized and consequently decrease of the input capacity
necessary for high speed operation can be performed. The third
effect is that since a longitudinal bipolar transistor and a
trigger element can be formed by adding only one ion implantation
mask for an ESD protection circuit in a common CMOSFET process, the
fabrication method is carried out in a compatible process with the
CMOSFET process. The fourth effect is that owing to the trigger
element capable of working a low voltage, the breakdown of the gate
insulation film in CMOSFET can be prevented. The fifth effect is
that an element capable of triggering at a desired voltage can be
form.
[0133] The invention may be embodied in other specific forms
without departing from the spirit or essential characteristic
thereof. The present embodiments are therefore to be considered in
all respects as illustrative and not restrictive, the scope of the
invention being indicated by the appended claims rather than by the
foregoing description and all changes which come within the meaning
and range of equivalency of the claims as therefore intended to be
embraced therein.
[0134] The entire disclosure of Japanese Patent Application No.
2000-141304 (Filed on May 15 .sup.th, 2000) including
specification, claims, drawings and summary are incorporated herein
by reference in its entirety.
* * * * *