U.S. patent application number 09/842807 was filed with the patent office on 2001-11-22 for frequency multiplier circuit and semiconductor integrated circuit.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to Imayama, Teruo, Masumoto, Hiroshi, Suzuki, Tsuneo.
Application Number | 20010043109 09/842807 |
Document ID | / |
Family ID | 26590931 |
Filed Date | 2001-11-22 |
United States Patent
Application |
20010043109 |
Kind Code |
A1 |
Masumoto, Hiroshi ; et
al. |
November 22, 2001 |
Frequency multiplier circuit and semiconductor integrated
circuit
Abstract
A frequency multiplier circuit comprises: a source oscillator
configured to generate a source oscillator signal using a crystal
oscillator; and n frequency multiplier circuits (n is an integer
which is 2 or more), each of which includes a 90.degree. phase
shifter circuit configured to shift the phase of an input signal by
90.degree., and a mixer configured to generate a doubled signal of
the input signal on the basis of the input signal and an output
signal of the 90.degree. phase shifter circuit, wherein the n
frequency multiplier circuits are cascade-connected, the source
oscillation signal being inputted to a first stage frequency
multiplier circuit of the n frequency multiplier circuits, and a
final stage frequency multiplier circuit of the n frequency
multiplier circuits outputting a signal having a frequency 2.sup.n
times as high as the frequency of the source oscillation
signal.
Inventors: |
Masumoto, Hiroshi;
(Yokohama-Shi, JP) ; Suzuki, Tsuneo;
(Kamakura-Shi, JP) ; Imayama, Teruo;
(Yokohama-Shi, JP) |
Correspondence
Address: |
OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT PC
FOURTH FLOOR
1755 JEFFERSON DAVIS HIGHWAY
ARLINGTON
VA
22202
US
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
72, Horikawa-Cho, Saiwai-ku, Kanagawa-Ken
Kawasaki-Shi
JP
|
Family ID: |
26590931 |
Appl. No.: |
09/842807 |
Filed: |
April 27, 2001 |
Current U.S.
Class: |
327/356 |
Current CPC
Class: |
H03B 19/14 20130101;
H03B 21/04 20130101; H03B 21/01 20130101 |
Class at
Publication: |
327/356 |
International
Class: |
H03B 019/00; G06G
007/16; G06F 007/44 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 27, 2000 |
JP |
2000-127087 |
Nov 30, 2000 |
JP |
2000-364648 |
Claims
What is claimed is:
1. A frequency multiplier circuit comprising: a source oscillator
configured to generate a source oscillator signal using a crystal
oscillator; and n frequency multiplier circuits (n is an integer
which is 2 or more), each of which includes a 90.degree. phase
shifter circuit configured to shift the phase of an input signal by
90.degree., and a mixer configured to generate a doubled signal of
said input signal on the basis of said input signal and an output
signal of said 90.degree. phase shifter circuit, wherein said n
frequency multiplier circuits are cascade-connected, said source
oscillation signal being inputted to a first stage frequency
multiplier circuit of said n frequency multiplier circuits, and a
final stage frequency multiplier circuit of said n frequency
multiplier circuits outputting a signal having a frequency 2.sup.n
times as high as the frequency of said source oscillation
signal.
2. A frequency multiplier circuit as set forth in claim 1, which
further comprises at least one filter circuit, provided between
adjacent two of at least part of stages of said n frequency
multiplier circuits, configured to remove undesired frequency
components.
3. A frequency multiplier circuit as set forth in claim 1, which
further comprises at least one phase shift adjusting circuit
provided so as to correspond to at least part of said n frequency
multiplier circuits, wherein said phase shifter circuit adjusts the
phase shift quantity of a corresponding one of said 90.degree.
phase shifter circuits so that the output dc voltage of a
corresponding one of said mixers 22 is substantially zero.
4. A frequency multiplier circuit as set forth in claim 3, wherein
said 90.degree. phase shifter circuit comprises: a first current
source capable of adjusting a current quantity by the output of
said phase shift adjusting circuit; and a first impedance element
wherein impedance is variably controlled in accordance with a
current quantity flowing through said current source.
5. A frequency multiplier circuit as set forth in claim 3, which
further comprises at least one filter circuit, provided between
adjacent two of at least part of stages of said n frequency
multiplier circuits, configured to remove undesired frequency
components, wherein said phase shift adjusting circuit configured
to adjust a band characteristic of a corresponding one of said
filter circuits so that the output dc voltage of a corresponding
one of said mixers 22 is zero.
6. A frequency multiplier circuit as set forth in claim 5, wherein
said filter circuit comprises: a second current source capable of
adjusting a current quantity by the output of said phase shift
adjusting circuit; and a second impedance element wherein impedance
is variable controlled in accordance with a current quantity
flowing through said current source.
7. A frequency multiplier circuit as set forth in claim 2, wherein
said filter circuit comprises: a first variable impedance element
which is connected between an input terminal and an output terminal
and which is capable of varying impedance by currents; a first
capacitor element connected to said output terminal; a second
variable impedance element configured to control a voltage of said
output terminal in accordance with currents; and a current supply
circuit configured to pass a current, which has the same phase as
that of a current flowing through said second variable impedance
element, through said output terminal.
8. A frequency multiplier circuit as set forth in claim 2, wherein
said filter circuit comprises: a first variable impedance element
which is connected between a first input terminal and a first
output terminal and wherein impedance is variably controlled by a
current flowing through said first input terminal; a second
variable impedance element which is connected between a second
input terminal and a second output terminal and wherein impedance
is variably controlled by a current flowing through said second
input terminal; a first capacitor element connected between said
first and second output terminals; a first transistor configured to
control a voltage of said first output terminal; a second
transistor configured to control a voltage of said second output
terminal; and a second capacitor element connected between the
output terminals of each of said first and second transistors,
wherein said first transistor passes a current, which has the same
phase as that of a current flowing through said second transistor,
through said first output terminal, and said second transistor
passes a current, which has the same phase as that of a current
flowing through said first transistor, through said second output
terminal.
9. A frequency multiplier circuit as set forth in claim 8, wherein
at least one of said first through fourth variable impedance
elements comprises a bipolar transistor configured to variably
control impedance by controlling a current flowing through an
emitter terminal of said bipolar transistor.
10. A frequency multiplier circuit as set forth in claim 9, wherein
at least one of said first through fourth variable impedance
elements comprises a plurality of bipolar transistors which are
Darlington-connected.
11. A frequency multiplier circuit as set forth in claim 7, wherein
said filter circuit further comprises a first limiter amplifier,
connected between said first and second input terminals and said
first and second variable impedance elements, configured to limit a
voltage amplitude of an input signal to a predetermined voltage
range to output the limited signal, and said 90.degree. phase
shifter circuit comprises: first and second phase shifting parts,
cascade-connected to each other, configured to shift the phase of
input signals by substantially 45.degree. to output the
phase-shifted signals; a second limiter amplifier, connected to the
upstream of said first phase shifting part, configured to limit a
voltage amplitude of an input signal to a predetermined voltage to
output the limited signal; and a third limiter amplifier, connected
between said second limiter amplifier and said second phase
shifting part, configured to limit a voltage amplitude of an output
signal of said first phase shifting part to a predetermined voltage
range to output the limited signal.
12. A frequency multiplier circuit as set forth in claim 8, wherein
said filter circuit comprises: a first impedance element connected
between said first variable impedance element and said first output
terminal; a second impedance element connected between said second
variable impedance element and said second output terminal; a third
impedance element connected to said first transistor and said
second capacitor element; and a fourth impedance element connected
between said second transistor and said second capacitor
element.
13. A frequency multiplier circuit as set forth in claim 2, wherein
said filter circuit is provided at least between the first and
second stages of said frequency multiplier circuits.
14. A semiconductor integrated circuit comprising: a local
oscillator circuit configured to generate a local oscillation
signal; an intermediate frequency signal converter configured to
convert a high frequency signal, which is received by an antenna,
into an intermediate frequency signal on the basis of said local
oscillation signal; and a demodulator configured to carry out a
demodulation processing on the basis of said intermediate frequency
signal, wherein said local oscillator circuit comprises: a source
oscillator configured to generate a source oscillation signal using
a crystal oscillator; and n frequency multiplier circuits, each of
which includes a 90.degree. phase shifter circuit configured to
shift the phase of an input signal by 90.degree., and a mixer
configured to output a doubled signal of said input signal on the
basis of said input signal and an output signal of said 90.degree.
phase shifter circuit, said n frequency multiplier circuits being
cascade-connected, and said source oscillation signal being
inputted to a first stage frequency multiplier circuit of said n
frequency multiplier circuits.
15. A frequency multiplier circuit as set forth in claim 1, wherein
a first stage frequency multiplier circuit of said n frequency
multiplier circuits includes: a first waveform shaping circuit
configured to shape the waveform of said source oscillation signal
generated by said source oscillator; and an offset cancel circuit
configured to remove an output dc component of said first waveform
shaping circuit.
16. A frequency multiplier circuit as set forth in claim 1, which
further comprises: at least one second waveform shaping circuit and
at least one phase shift adjusting circuit which are provided so as
to correspond to at least part of frequency multiplier circuits of
said n frequency multiplier circuits, wherein said second waveform
shaping circuit shapes the waveform of an output signal of said
mixer, and said phase shift adjusting circuit adjusts a phase shift
quantity of a corresponding one of said 90.degree. phase shifter
circuit.
17. A frequency multiplier circuit as set forth in claim 1, which
further comprises: third and fourth waveform shaping circuits and a
phase shift adjusting circuit which are provided so as to
correspond to at least part of frequency multiplier circuits of
said n frequency multiplier circuits, wherein said third waveform
shaping circuit shapes the waveform of said input signal, said
fourth waveform shaping circuit phases an output signal of said
90.degree. phase shifter circuit, and said mixer generates a
doubled signal of said input signal on the basis of each of output
signals of said third and fourth waveform shaping circuits.
18. A frequency multiplier circuit as set forth in claim 15,
wherein said first waveform shaping circuit includes a limiter
amplifier and a low-pass filter.
19. A frequency multiplier circuit as set forth in claim 16,
wherein said second waveform shaping circuit includes a limiter
amplifier and a low-pass filter.
20. A frequency multiplier circuit as set forth in claim 17,
wherein at least one of said third and fourth waveform shaping
circuits includes a limiter amplifier and a low-pass filter.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims benefit of priority under 35USC
.sctn.119 to Japanese Patent Application No. 2000-127087 filed on
Apr. 27, 2000 and Japanese Patent Application No. 2000-364648 filed
on Nov. 30, 2000, the entire contents of which are incorporated by
reference herein.
BACKGROUND OF THE INVENTION
[0002] 1. Field of The Invention
[0003] The present invention relates generally to a frequency
multiplier and semiconductor integrated circuit for producing a
local oscillation signal for use in a superheterodyne receiver or
the like.
[0004] 2. Related Background Art
[0005] Recently, there are provided various systems for sending and
receiving weak radio waves to carry out various processes with
non-contact. For example, a keyless entry system is designed to
receive weak radio waves emitted from a transmitting circuit
embedded in a key for a vehicle, by a receiving circuit in the
vehicle to open and close doors and so forth.
[0006] FIG. 19 is a block diagram showing schematic configuration
of a conventional weak radio wave sending/receiving system of this
type. The system of FIG. 19 generally comprises a transmitter 51
and a receiver 52. The transmitter 51 has a transmitting circuit 53
and an antenna 54. The transmitter 51 uses a carrier frequency of
315 MHz to emit AM-modulated (amplitude-modulated) or FM-modulated
(frequency-modulated) signals via the antenna 54.
[0007] The receiver 52 comprises an antenna 11, an SAW filter 12,
an RF amplifier 13, a local oscillator circuit for generating a
local oscillation signal, a mixer 15 for generating an intermediate
frequency signal (IF signal), an IF filter 16, an IF amplifier 17
and a detector circuit 18. The local oscillator circuit 14 has a
source oscillator circuit 21 for generating a reference signal, and
a quintupler circuit 20 for outputting a quintupled signal having a
frequency five times as high as that of the reference signal.
[0008] The source oscillator circuit 21 is designed to generate a
source oscillation signal having a frequency of 65.14 MHz. The
local oscillator circuit 14 is designed to generate a local
oscillator signal f.sub.LO=325.7 MHz which has an increased
frequency five times as high as the frequency of the source
oscillation signal. The mixer 15 is designed to use the local
oscillation signal f.sub.LO to output an intermediate frequency
signal having a frequency of f.sub.LO-f.sub.O=10.7 MHz.
[0009] Thus, a high frequency signal received by the antenna 11 is
converted into an intermediate frequency signal by the mixer 15, so
that the signal processing can be more easily carried out than a
case of performing the signal processing by directly using the high
frequency signal.
[0010] The IF filter 16, which is a band-pass filter, is connected
to the subsequent stage mixer 15. The passing band of the filter 16
is about hundreds kHz centering on an intermediate frequency of
10.7 MHz. After undesired frequency components are removed by the
IF filter 16, the intermediate frequency signals of 10.7 MHz are
amplified by about 70 dB in the IF amplifier 17.
[0011] When the system of FIG. 19 is applied to the above described
keyless entry system, the transmitter 51 is embedded in a key
carried by a human, and the receiver 52 is mounted on a vehicle.
From the transmitter 51, weak radio waves having the frequency of
322 MHz or less are emitted. An allowable field intensity is 500
.mu.V/m or less which is defined by Article 6 of Enforcement
Regulations of Radio Wave Law in Japan. Radio waves having the
frequency of 322MHz or higher can be used. However, the allowable
field intensity from 322 MHz to 10 GHz is 35 .mu.V/m or less which
is very small. In addition, as the frequency increases, the
progressivity of radio waves increases so as not to be put to
practical use, so that the radio waves having a frequency of 322
MHz or higher are hardly used in the country. Therefore, radio
waves having a frequency of about 315 MHz are generally used as
weak radio waves.
[0012] On the other hand, the transmitter 51 preferably has smaller
electric power consumption in order to increase the life of a
battery, so that it is required to simplify the circuit
construction. For example, an SAW vibrator is known as a simple
element capable of oscillating radio waves having a frequency of
about 315 MHz. This element can not only simplify the circuit
construction, but it can also directly oscillate by a frequency of
315 MHz.
[0013] Although there is a crystal oscillator as another oscillator
element, it is technically difficult to directly oscillate the
signal having a frequency of about 315 MHz. After oscillating the
crystal oscillator at a low frequency, it is required to multiply
frequency. Because of this, the SAW vibrator is often used to
constitute the circuit as simple as possible.
[0014] However, there is a problem in that the SAW vibrator has a
large frequency deviation. The frequency deviation of the SAW
vibrator is usually 100 ppm or higher. The frequency deviation of
the transmitter itself grows worse if the SAW vibrator is used as
the transmitter. Because of this, when the performance and yields
of products are intended to be improved, a crystal oscillator is
sometimes used.
[0015] When the SAW vibrator is used as the transmitter, it is
required to improve the frequency precision on the side of the
receiver in order to compensate its disadvantages. In order to
improve the frequency precision, a crystal oscillator having a
small frequency deviation is generally used for the local
oscillator circuit of the receiver. Since the frequency deviation
of the crystal oscillator hardly exceeds 100 ppm at worst, it is
possible to improve the frequency precision of the receiver by
using the crystal oscillator for the local oscillator circuit in
the receiver.
[0016] However, since it is very difficult to directly oscillate a
high frequency of 300 MHz band as described above, a method for
lowering the oscillation frequency of the crystal oscillator itself
to multiply frequency by a frequency multiplier circuit to obtain a
frequency of 300 MHz band is generally used.
[0017] There is proposed a technique using, as a conventional
oscillator circuit, a quintupler circuit 20 for oscillating a
crystal oscillator at 65.14 MHz to generate higher harmonics by
distorting its waveform and extracting fifth-order higher harmonics
by means of a filter or the like to obtain a frequency of 325.7 MHz
when a local oscillation frequency of, e.g., 325.7 MHz (=315+10.7
MHz) is intended to be generated.
[0018] In this quintupler circuit 20, it is required to increase
distortion to generate higher-order higher harmonics in order to
increase the multiple number. Although the level of higher harmonic
components decreases as the order thereof increases, the higher
harmonic components include many undesired components other than
originally required fifth-order higher harmonics.
[0019] Now, assuming that a rectangular wave of an even function is
used as a distorted wave and assuming that it has "1" in an
interval of from (-x) to (+x) and "-1" in other intervals, the
following expression can be expressed:
A(x-.pi./2)+Asin x.multidot.cos .omega.t+A/2 sin 2x.multidot.cos
2.omega.t+A/3.multidot.sin 3x.multidot.cos 3.omega.t+. . .
+A/n.multidot.sin nx.multidot.cos .omega.t (1)
[0020] wherein A is a constant, .omega. is an angular frequency
which is 2.pi.f.sub.LO, t is time, n is a natural number, and the
first term is a dc component.
[0021] In expression (1), for example, assuming that n=5, the
fifth-order higher harmonic components attenuate to 1/5 as large as
a fundamental wave. Assuming that x=.pi./2, the odd orders of
expression (1) remain, and the dc component is zero only in this
case.
[0022] In order to utilize only the fifth-order higher harmonic
components, first through fourth order components and sixth or
higher order components must be removed. Therefore, only the
fifth-order higher harmonic components are extracted by a filter
using the quintupler circuit 20. However, undesired higher harmonic
components remain at a high level. The undesired higher harmonic
components are not only propagated in a space, but the frequencies
are also close to each other, so that it is require to use an SAW
filter or the like.
[0023] If the undesired higher harmonic components come into the
mixer 15 via the space and a transmission line, the higher
harmonics themselves function as jamming waves. In addition, all of
radio waves having a frequency fo' wherein the difference between
the frequency f.sub.LO, and the frequency fo' of undesired radio
waves coming from the outside is equal to an intermediate frequency
of 10.7 MHz function as harmful radio waves.
[0024] If the receiver is influenced by the harmful radio waves,
the keyless entry system may not normally operate, so that it is
required to decrease the influence of undesired higher
harmonics.
[0025] For example, in order to decrease the influence of higher
harmonics in the prior art, it is required to take measures to
provide a shielding for the frequency multiplier circuit or to
spatially increase the distance between the frequency multiplier
circuit and the mixer.
[0026] Since it is required to prevent the multiple number from
increasing in order to reduce the higher harmonics, there is a
limit to the multiple number, so that there is a problem in that
the oscillation frequency can not be so low. If the source
oscillation frequency is high, it is difficult to design the
circuit, and the circuit is complicated. In addition, the cost of
providing the crystal oscillator is also high.
[0027] In order to lower the source oscillation frequency, it is
considered to use a phase locked loop (PLL) circuit. However, if
the PLL circuit is used, it is required to use an oscillator
circuit and a voltage control oscillator (VCO) circuit for
obtaining a phase-comparison frequency. In addition, the circuit
scale increases, and the costs increases by the PLL circuit and the
voltage control oscillator circuit.
[0028] Because of this, it is considered that the PLL circuit and
the voltage control oscillator circuit are included in one chip to
form as an IC and to suppress the increase of the circuit scale and
costs. However, if the voltage control oscillator circuit is
included in the chip, the C/N ratio deteriorates, so that
performance such as sensitivity deteriorates. In order to prevent
this, the voltage control oscillator circuit must be provided
outside, so that it is not possible to reduce the circuit scale
when performance is regarded as important.
[0029] In order to combine the PLL circuit with the voltage control
oscillator circuit, higher harmonics called phase-comparison
spurious occurs, so that it is required to take measures to remove
the higher harmonics.
[0030] Thus, the conventional oscillator circuit is designed to
oscillate at a low frequency using the crystal oscillator in order
to improve the frequency precision of the receiver and to quintuple
the oscillation frequency of the crystal oscillator by the
frequency multiplier circuit, and is provided with a shielding or
the like in order to decrease generated undesired higher harmonic
components. Therefore, there is a limit to the miniaturization of
the circuit, and there is a problem in that it is required to take
measures to remove jamming waves.
SUMMARY OF THE INVENTION
[0031] It is therefore an object of the present invention to
eliminate the aforementioned problems and to provide a frequency
multiplier circuit and semiconductor integrated circuit capable of
surely removing undesired frequency components with a simple
circuit construction.
[0032] In order to accomplish the aforementioned and other objects,
according to one aspect of the present invention, a frequency
multiplier circuit comprises: a source oscillator configured to
generate a source oscillator signal using a crystal oscillator; and
n frequency multiplier circuits (n is an integer which is 2 or
more), each of which includes a 90.degree. phase shifter circuit
configured to shift the phase of an input signal by 90.degree., and
a mixer configured to generate a doubled signal of the input signal
on the basis of the input signal and an output signal of the
90.degree. phase shifter circuit, wherein the n frequency
multiplier circuits are cascade-connected, the source oscillation
signal being inputted to a first stage frequency multiplier circuit
of the n frequency multiplier circuits, and a final stage frequency
multiplier circuit of the n frequency multiplier circuits
outputting a signal having a frequency 2.sup.n times as high as the
frequency of the source oscillation signal.
[0033] According to another aspect of the present invention, a
semiconductor integrated circuit comprises: a local oscillator
circuit configured to generate a local oscillation signal; an
intermediate frequency signal converter configured to convert a
high frequency signal, which is received by an antenna, into an
intermediate frequency signal on the basis of the local oscillation
signal; and a demodulator configured to carry out a demodulation
processing on the basis of the intermediate frequency signal,
wherein the local oscillator circuit comprises: a source oscillator
configured to generate a source oscillation signal using a crystal
oscillator; and n frequency multiplier circuits, each of which
includes a 90.degree. phase shifter circuit configured to shift the
phase of an input signal by 90.degree., and a mixer configured to
output a doubled signal of the input signal on the basis of the
input signal and an output signal of the 90.degree. phase shifter
circuit, the n frequency multiplier circuits being
cascade-connected, and the source oscillation signal being inputted
to a first stage frequency multiplier circuit of the n frequency
multiplier circuits.
[0034] According to the present invention, since the n frequency
multiplier circuits are cascade-connected to supply the source
oscillation signal from the crystal oscillator to the first stage
frequency multiplier circuit, it is possible to output a
sufficiently high frequency signal from the final stage frequency
multiplier circuit even if the source oscillation frequency is low.
Therefore, it is possible to easily design the source oscillator,
and it is possible to stabilize the characteristics of the source
oscillation signal.
[0035] In addition, since the frequency multiplier circuit
comprises the 90.degree. phase shifter circuit and the mixer, it is
possible to realize a frequency multiplier circuit which can
efficiently suppress undesired frequency components and which is
resistant to jamming. It is also possible to obtain a sufficiently
high frequency signal by adjusting the number of stages of
connected frequency multiplier circuits.
[0036] If the frequency multiplier circuit is provided with a
filter circuit, it is possible to surely remove undesired high
frequency components. If a variable impedance element is provided
in the filter circuit, it is possible to control the frequency
characteristics of the filter circuit in accordance with the phase
shift quantity of the phase shifter circuit.
[0037] If both of the filter circuit and the phase shifter circuit
are provided with a limiter amplifier, it is possible to prevent
the frequency characteristics of the filter circuit and the cut-off
frequency of the phase shifter circuit from depending on the input
signal level.
[0038] If an impedance element is connected to the variable
resistor of the filter circuit in series, it is possible to cancel
the fixed phase shift quantity caused by the limiter amplifier of
the phase shifter circuit, and it is possible to control the
frequency characteristics of the filter circuit so as to faithfully
follow the variation in source oscillation frequency.
[0039] If the frequency multiplier circuit according to the present
invention is used for forming a superheterodyne receiver, portions
other than the crystal oscillator and the antenna are provided in
one chip, so that it is possible to miniaturize the receiver and
reduce costs.
BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The present invention will be understood more fully from the
detailed description given herebelow and from the accompanying
drawings of the preferred embodiments of the invention. However,
the drawings are not intended to imply limitation of the invention
to a specific embodiment, but are for explanation and understanding
only.
[0041] In the drawings:
[0042] FIG. 1 is a block diagram of the first preferred embodiment
of a receiver including a frequency multiplier circuit according to
the present invention;
[0043] FIG. 2 is a graph showing a general characteristic of a
bifilter circuit;
[0044] FIG. 3 is a block diagram of the second preferred embodiment
of a receiver including a frequency multiplier circuit according to
the present invention;
[0045] FIG. 4 is a circuit diagram showing an example of a
90.degree. phase shifter circuit using a semiconductor element;
[0046] FIG. 5 is a circuit diagram showing an example of a filter
circuit;
[0047] FIG. 6 is a circuit diagram showing the detailed
construction of the third preferred embodiment of a 90.degree.
phase shifter circuit according to the present invention;
[0048] FIG. 7 is a circuit diagram showing the detailed
construction of a filter circuit;
[0049] FIG. 8 is a small-signal equivalent circuit diagram of the
filter circuit of FIG. 7;
[0050] FIG. 9 is a graph expressed by expression (5);
[0051] FIG. 10 is a circuit diagram of a filter circuit wherein
transistors Q3 and Q4 of FIG. 7 are Darlington-connected;
[0052] FIG. 11 is a circuit diagram of a filter circuit for use in
an actual LSI or the like;
[0053] FIG. 12 is a circuit diagram of a 90.degree. phase shifter
circuit having a limiter amplifier;
[0054] FIG. 13 is a circuit diagram showing an example of a local
oscillator circuit having a filter circuit and no phase shift
adjusting circuit;
[0055] FIG. 14 is a circuit diagram showing an example of a local
oscillator circuit having a phase shift adjusting circuit and no
filter circuit;
[0056] FIG. 15 is a block diagram of the fourth preferred
embodiment of a receiver including a frequency multiplier circuit
according to the present invention;
[0057] FIG. 16 is an enlarged block diagram of an internal
construction of a doubler circuit 2 at the first stage;
[0058] FIG. 17 is a circuit diagram showing the detailed
construction of an offset cancel circuit 82 of FIG. 16:
[0059] FIG. 18 is a circuit diagram showing the detailed
construction of a limiter amplifier of FIG. 16; and
[0060] FIG. 19 is a block diagram showing the schematic
construction of a conventional weak radio wave sending/receiving
system.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0061] Referring now to the accompanying drawings, a frequency
multiplier circuit and semiconductor integrated circuit according
to the present invention will be described below in detail.
First Preferred Embodiment
[0062] FIG. 1 is a block diagram of the first preferred embodiment
of a receiver using a frequency multiplier circuit according to the
present invention. The receiver of FIG. 1 is included in one chip,
except for a source oscillator circuit 1 and an antenna 11. In FIG.
1, the same reference numbers are given to the same elements as
those in FIG. 15, and different points will be mainly described
below.
[0063] The frequency multiplier circuit of FIG. 1 has the same
construction as that in FIG. 15, except that the construction of a
local oscillator circuit 14a for generating local oscillation
signals is different from that in the frequency multiplier circuit
of FIG. 15.
[0064] The local oscillator circuit 14a of FIG. 1 has a source
oscillator circuit 1 for generating source oscillation signals, and
a plurality of cascade-connected frequency multiplier circuits 2.
In fact, each of the frequency multiplier circuit 2 is a doubler
circuit 2 for outputting a signal, the frequency of which is double
the frequency of an input signal. This circuit is provided with a
90.degree. phase shifter circuit 2 and a mixer 22.
[0065] A source oscillation signal generated by the source
oscillator circuit 1 is inputted to the input terminal of the first
stage doubler circuit 2, and a local oscillation signal is
outputted from the output terminal of the final stage doubler
circuit 2. The frequency (local oscillation frequency) f.sub.LO of
the local oscillation signal is, e.g., 325.7 MHz.
[0066] It is considered that an oscillator circuit using, e.g., a
crystal oscillator, is used as the local oscillator circuit 1. By
using the crystal oscillator, the frequency precision of the local
oscillation signal can be improved.
[0067] In this preferred embodiment, the three stages of doubler
circuits 2 are connected, and a source oscillation signal having a
source oscillation frequency of 40.7125 MHz is inputted to the
first stage doubler circuit 2. In domestic weak radio wave
receiving systems, the local oscillation frequency is often set to
be 325.7 MHz with respect to a receiving radio wave having a
frequency of 315 MHz.
[0068] In this case, the source oscillation frequency is 81.425 MHz
when n=2 (quadruple), the source oscillation frequency is 40.7125
MHz when n=3 (octuple), and the source oscillation frequency is
20.35625 MHz when n=4 (16 times).
[0069] The source oscillation frequency based on the crystal
oscillator has stable characteristics when the frequency is low,
and is easily produced. Specifically, the frequency is preferably
about 60 MHz or less.
[0070] Conversely, if the source oscillation frequency is too low,
the source oscillation frequency approaches an intermediate
frequency (IF frequency). Therefore, the source oscillation
frequency is preferably sufficiently lower 10.7 MHz by setting n=7
or more, or the source oscillation frequency is preferably higher
than 10.7 MHz by setting n=less than 4.
[0071] However, if n is increased to decrease the source
oscillation frequency, the doubler circuit 2 generates undesired
frequency components at intervals of the source oscillation
frequency, as will be described later, so that it is difficult to
remove the undesired frequency components by the filter
circuit.
[0072] Even if an SAW filter circuit, which is one of filter
circuits having the highest removing performance, is used as the
filter circuit for removing the undesired frequency components, the
following removing level characteristics are required.
[0073] Since the general characteristics of the SAW filter circuit
are as shown in FIG. 2, required attenuation levels of the
undesired frequency components are as follows when attenuation of
85 dB is intended to be obtained as a whole.
[0074] Filter Circuit Center Frequency .+-.20 MHz . . . 65 dB
[0075] Filter Circuit Center Frequency .+-.25 MHz . . . 40 dB
[0076] Filter Circuit Center Frequency .+-.35 MHz . . . 30 dB
[0077] Filter Circuit Center Frequency .+-.40 MHz or more . . . 20
dB
[0078] Since the undesired frequency components exist at a
frequency of a local oscillation frequency f.sub.LO .+-. (Source
Oscillation Frequency x Integer), it is more difficult to remove
the undesired frequency components as the source oscillation
frequency decreases. Therefore, the source oscillation frequency is
preferably higher in view of the removal of higher harmonics using
the filter circuit.
[0079] Because of this, in domestic weak radio wave receiving
systems using 315 MHz band, it can be seen that an octupler circuit
(n=3) having a source oscillation frequency of 40 MHz is most
preferred. Therefore, in this preferred embodiment, as shown in
FIG. 1, the three stages of doubler circuits 2 are
cascade-connected, and the source oscillation signal having a
frequency of 40.7125 MHz is inputted to the first stage doubler
circuit 2.
[0080] The 90.degree. phase shifter circuit 21 in the doubler
circuit 2 is designed to input a signal, which is caused to be
orthogonal to the sinusoidal waveform of an input signal, i.e., the
phase of which is shifted by 90.degree. from the phase of an input
signal, to the mixer 22.
[0081] Now, considering a rectangular wave, which is in the most
distorted stage, as the input waveform of the mixer, an example of
a waveform can be described so as to have "-1" in an interval in
which the phase is in the range of from -.pi. to 0 and have "+1" in
an interval in which the phase is in the range of from 0 to .pi.. A
state in which this waveform is phase-shifted by X using the phase
shifter circuit can be described so that the interval in which the
phase is in the range of from -.pi.+x to x has "-1" and the
interval in which the phase is in the range of from x to .pi.+x has
"+1".
[0082] However, the signal inputted to the mixer 22 contains higher
harmonic components caused by the non-linearity of the circuit
element, and the signal waveform is generally distorted by the
higher harmonic components.
[0083] Now, considering a rectangular wave as the most distorted
stage, a waveform having "-1" in an interval in which the phase is
in the range of from (-.pi.) to 0 and "+1" in an interval in which
the phase is in the range of from 0 to .pi. is considered as an
example of a waveform.
[0084] If this waveform is phase-shifted by x using the phase
shifter circuit, a waveform is obtained wherein the interval in
which the phase is in the range of from (-.pi.+x) to x has "-1" and
the interval in which the phase is in the range of from x to
(.pi.+x) has "+1" are obtained.
[0085] If the two waveforms are multiplied by the mixer 22, the
multiplied waveform has "-1" in an interval of from (-.pi.) to
(-.pi.+x), "+1" in an interval of from (-.pi.+x) to 0, "-1" in an
interval of from 0 to (+x), and "+1" in an interval of from (+x) to
.pi., so that the period of the waveform is halved.
[0086] If the two waveforms are described by series of an even
function, the following expression (2) is obtained:
B(.pi./2-x)+C.multidot.sin(.pi.-x) cos2.omega.t+C/2.multidot.sin2
(.pi.-x).multidot.cos4.omega.t+C/3.multidot.sin3(.pi.-x)
cos6.omega.t+. . . +C/n.multidot.sin
n(.pi.-x).multidot.cos2n.omega.t (2)
[0087] wherein B and C are constants and n is an integer. According
to this expression, a higher harmonic 2n times as large as a
fundamental wave is obtained. A condition where the quantity of
higher harmonic components is minimum is x=.pi./2. In this case,
expression (2) is expressed by expression (3).
C.multidot.sin(.pi.-x).multidot.cos 2.omega.t+C/3.multidot.sin
3(.pi.-x).multidot.cos6.omega.t+. . . =C.multidot.cos
2.omega.t-C/3.multidot.cos 6.omega.t+C/5.multidot.cos 10.omega.t-.
. .
[0088] As can be seen from expression (3), second, sixth, tenth, .
. . , (4n-2)-th orders remain, and fourth, eighth, twelfth, . . . ,
4n-th orders are removed.
[0089] In expression (3), the level of the secondary higher
harmonic is highest, and the level decreases as the order of the
higher harmonic increases. In addition, a six times high harmonic
is adjacent to a double high harmonic.
[0090] For example, assuming that the source oscillation frequency
is 40.7125 MHz, the frequencies of waves outputted from the first
stage doubler circuit 2 are 81.425 MHz, 244.275 MHz, 407.125 MHz, .
. . . However, an adjacent frequency of 244.275 MHz is sufficiently
spaced from a desired frequency of 81.425 MHz, so that it is
possible to relatively easily remove undesired higher harmonic
components.
[0091] Assuming that n=3, the source oscillation frequency is
40.7125 MHz, and the output frequencies of the respective doubler
circuits 2 are as follows.
[0092] First Stage: 81.425 MHz, 244.275 MHz, 407.12 MHz, . . .
[0093] Second Stage: 162.85 MHz, 488.55 MHz, 814.25 MHz, . . .
(caused by 81.425 MHz)
[0094] 488.55 MHz, 1465.65 MHz, 2442.75 MHz, . . . (caused by
244.275 MHz)
[0095] 814.25 MHz, 2442.75 MHz, 4071.25 MHz, . . . (caused by
407.125 MHz)
[0096] Third Stage: 325.7 MHz, 977.1 MHz, 1628.5 MHz, . . . (caused
by 162.85 MHz)
[0097] 977.1 MHz, 2931.3 MHz, 4885.5 MHz, . . . (caused by 488.55
MHz)
[0098] 1628.5 MHz, 4885.5 MHz, 8142.5 MHz, . . . (caused by 814.25
MHz)
[0099] The frequency of a signal caused by 244.275 MHz which is a
frequency of adjacent undesired higher harmonic components included
in the output of the first stage doubler circuit 2 is 488.55 MHz in
the output of the second stage, and 977.1 MHz in the output of the
third stage. Both are sufficiently spaced from 300 MHz band, so
that there is not a bad influence of the higher harmonic components
such as a noise.
[0100] On the other hand, when the shift of the frequency by the
phase shifter circuit is not 90.degree., the number of undesired
higher harmonics is not only doubled, but the adjacent frequency is
162.85 MHz. This appears to be 325.7 MHz in the output of the
second stage, and 651.4 MHz in the output of the third stage.
Because of this, it is difficult to remove the undesired higher
harmonic components, and the required frequency level is decreased
by the item of sin (.pi.-x) in expression (2), so that the
efficiency of the local oscillator circuit 14a is bad. Therefore,
the phase shift quantity using the phase shifter circuit is most
preferably 90.degree..
[0101] In view of the foregoing, in this preferred embodiment, the
frequency multiplier circuit 2 is formed by the doubler circuit 2
comprising the mixer 22 and the 90.degree. phase shifter circuit 21
to inhibit undesired higher harmonics from being generated, and the
multistage doubler circuits 2 are connected to enhance the multiple
number of the source oscillation frequency. Specifically, when n
stages of doubler circuits 2 are connected, the frequency of the
local oscillation signal outputted from the final stage doubler
circuit 2 is 2.sup.n.times.f wherein f is a source oscillation
frequency.
[0102] In conventional weak radio wave receivers, the multiple
number of the local oscillator circuit 14a is limited to about 5,
whereas in this preferred embodiment, the multiple number is
2.sup.3=8 when n=3 and 2.sup.4 16 when n=4, so that the source
oscillation frequency can be decreased by the increase of the
multiple number.
[0103] For example, the source oscillation frequency is
(315+10.7)/8=40.7125 MHz when n=3, and (315+10.7)/16=20.35625 MHz
when n=4, so that the source oscillation frequency can be more
decreased than the source oscillation frequency of 65.14 MHz which
is conventionally used for quintupling the frequency.
[0104] Thus, since the oscillation frequency of the crystal
oscillator can be decreased, it is possible to easily design the
receiver,so that it is possible to reduce the costs. In addition,
if the doubler circuits 2 are included in an IC, the higher
harmonic component signals generated between the stages of the
doubler circuits 2 do not leak to the outside.
[0105] Thus, in the first preferred embodiment, the three stages of
cascade-connected doubler circuits 2 are provided in the local
oscillator circuit 14a to supply a source oscillation signal of the
crystal oscillator to the first stage doubler circuit 2 to produce
an octupled local oscillator signal, so that it is possible to
generate a local oscillation signal having a sufficiently high
frequency even if the source oscillation frequency is low.
[0106] According to this preferred embodiment, since the
oscillation frequency of the crystal oscillator can be set low, the
receiver can be easily designed, and the whole receiver can be
easily included in a single semiconductor chip except for the
antenna 11, so that undesired higher harmonic components are not
radiated to the outside.
Second Preferred Embodiment
[0107] When the phase shift based on the phase shifter circuit is
not 90.degree. in the first preferred embodiment, the input
waveform of the mixer includes dc components. Considering a
rectangular wave as a distorted wave, and if the rectangular wave
including the dc components are multiplied by the mixer as the
input waveform, the frequency component of the rectangular wave of
the input signal appears in the output of the frequency multiplier
circuit in addition to expression (2). Considering a rectangular
wave of an even function which is "1" in an interval of from -X to
+X and "-1" in other intervals, the rectangular wave can be
described by the following expression: 1 A ( x - / 2 ) + A sin x
cos t + A / 2 sin 2 x cos 2 t + A / 3 sin 3 x cos 3 t + + A / nsin
nx cos n t ( 4 )
[0108] wherein A is a constant, .omega. is an angular frequency of
2.pi.f.sub.LO, t is time, n is a natural number, and the first term
denotes a dc component. For example, assuming that n=2 and the
source oscillation frequency f0, the frequencies outputted from the
respective stages of frequency multiplier circuits are as follows
by expressions (1) and (3).
[0109] First Stage: f0, 2*f0, 3*f0, 4*f0, . . .
[0110] Second Stage: f0, 2*f0, 3*f0, 4*f0, 5*f0, . . . (caused by
f0)
[0111] 2*f0, 2*2*f0, 3*2*f0, 4*2*f0,* . . . (caused by 2*f0)
[0112] 3*f0, 2*3*f0, 3*3*f0, 4*3*f0, . . . (caused by 3*f0)
[0113] 4*f0, 2*4*f0, 3*4*f0, 4*4*f0, . . . (caused by 4*f0)
[0114] Adjacent undesired higher harmonics f0 and 3*f0 from the
output of the first stage become 3*f0 and 5*f0 in the output of the
second stage. The difference from a required frequency 4*f0 is only
to, so that it is difficult to remove this.
[0115] The adjacent undesired frequencies are caused by phase
noises. Assuming that .omega. is an angular velocity and t is time,
the phase .PHI. is expressed as follows.
.PHI.=.omega.*t (5)
[0116] Assuming that the phase noise before passing through the
second stage doubler circuit is d.PHI.1, the phase noise is
expressed as follows by expression (5).
d.PHI.1=.omega.*dt
[0117] Since the time difference dt which is the source of the
phase noise does not vary before and after passing the frequency
multiplier circuit, d.PHI.2=2*.omega.*dt=2*d.PHI.1 is obtained by
expression (5) assuming that the phase noise after passing through
the second stage frequency multiplier circuit is d.PHI.2. By this
expression, the phase noise d.PHI.2 after passing through the
second stage frequency multiplier circuit is twice as large as the
phase noise d.PHI.1 before passing through the second stage
frequency multiplier circuit.
[0118] This means that the signal level of adjacent undesired
frequencies after passing through the second stage frequency
multiplier circuit is twice as high as the signal level before
passing through the second stage frequency multiplier circuit. That
is, assuming that the signal level of a required frequency is 0 dB,
the signal level of adjacent undesired frequencies is increased by
6 dB every time passing through one stage frequency multiplier
circuit.
[0119] Thus, in the first preferred embodiment, the undesired
frequencies are generated in the vicinity of the required
frequency, and the signal level of the adjacent undesired
frequencies is increased by 6 dB every time passing through one
stage doubler circuit. Therefore, the required frequency is easily
interfered by the undesired frequencies, and the receiving
sensitivity may deteriorate, so that communication quality may
deteriorate.
[0120] In the second preferred embodiment, a filter circuit is
provided between stages of doubler circuits 2 to more reduce higher
harmonic noises.
[0121] FIG. 3 is a block diagram of the second preferred embodiment
of a receiver including a frequency multiplier circuit according to
the present invention. The receiver of FIG. 3 can also be included
in a single semiconductor chip except for the antenna 11. In FIG.
3, the same reference numbers are given to the same elements as
those in FIG. 1, and different points will be mainly described
below.
[0122] The receiver of FIG. 3 has the same construction as that in
FIG. 1, except that the construction of a local oscillator circuit
14b is different. The local oscillator circuit 14b of FIG. 3
comprises: n stages of doubler circuits 2 connected to a source
frequency multiplier circuit 1; a filter circuit 31 connected to
the output terminal of the first stage doubler circuit 2; and a
plurality of phase shift adjusting circuits 32 for adjusting the
phase shift quantity of a 90.degree. phase shifter circuit 21 in
each of the doubler circuits 2.
[0123] When a dc error component .DELTA.V exists in an input signal
of a mixer 22, the input signal also leaks to an output signal. For
example, if a signal having an effective value of 100 mV has a dc
error of 1 mV, a leakage of 20 log (1 mV / 100 mV)=-40 dB occurs in
the output.
[0124] The filter circuit 31 is designed to remove the undesired
higher harmonic components included in the output signal of the
first stage doubler circuit 2, and the leakage of the input signal
of the mixer 22. Each of the phase shift adjusting circuits 32 is
designed to adjust the phase shift quantity of the 90.degree. phase
shifter circuit 21 so that the dc component of the output of the
mixer 22 in the corresponding doubler circuits 2 is zero.
[0125] The first stage phase shift adjuster is designed to supply a
signal in proportion to a control signal of the corresponding
90.degree. phase shifter circuit to the filter circuit 31 to
control the frequency characteristics of the filter circuit 31.
[0126] While FIG. 3 has shown an example where the phase shift
adjustment of the 90.degree. phase shifter circuit and the control
of the frequency characteristics of the filter circuit 31 are
carried out on the basis of the output of the mixer 22 in each of
the doubler circuits 2, the phase shift quantity of the phase
shifter circuit and the frequency characteristics of the filter
circuit 31 may be controlled on the basis of a signal other than
the output of the mixer 22.
[0127] While the filter circuit 31 has been connected only to the
output terminal of the first stage doubler circuit 2 in FIG. 3, the
filter circuit 31 may also be connected to the output terminal of
the second and subsequent stages of doubler circuits 2. In this
case, if the filter circuit 31 is connected to the output terminal
of the doubler circuit 2 nearer to the first stage, it is possible
to more efficiently remove undesired higher harmonic
components.
[0128] In the second preferred embodiment, it is premised that the
phase shift quantity of the 90.degree. phase shifter circuit 21 in
the doubler circuit 2 is always 90.degree.. However, in an actual
circuit, the phase shift quantity of the 90.degree. phase shifter
circuit 21 is not always 90.degree. due to the variation in element
and temperature conditions.
[0129] Assuming that the phase shift quantity of the phase shifter
circuit is x, the dc component of the output of the mixer 22 is
B(.pi./2-x) by expression (2).
[0130] Although the dc component of the output of the mixer 22 is
zero when x=-.pi.2, it is not zero when x is not .pi./2, a 4n order
undesired higher harmonic component appears, and the originally
required secondary high harmonic level is lowered by the term
sin(.pi.-x) in expression (2).
[0131] That is, if x=.pi./2, sin(.pi.-x)=1, so that the term
sin(.pi.-x) in expression (2) is maximum, and if x is shifted from
.pi./2, this term is lowered. Therefore, the fact that the dc
component exists in the output of the mixer 22 shows the state that
the originally required secondary higher harmonic level is lowered
and the 4n order undesired higher harmonic component appears.
[0132] Because of this, if the phase shift quantity of the
90.degree. phase shifter circuit 21 is adjusted so that
sin(.pi.-1)=1 in expression (2), the dc component of the output of
the mixer 22 can be zero.
[0133] A CR phase shifter circuit using, e.g., the semiconductor
element shown in FIG. 4, is considered as the 90.degree. phase
shifter circuit 21 capable of adjusting the phase shift quantity.
The CR phase shifter circuit of FIG. 4 comprises: a reference
oscillator 41; a variable resistor R1, the resistance value of
which is variably controlled by the quantity of current flowing
through a current source 42; a variable resistor R2, the resistance
value of which is variably controlled by the quantity of current
flowing through a current source 43; capacitors C1 and C2; and an
amplifier 44. The reference oscillator 41 corresponds to the output
of the previous stage doubler circuit 4.
[0134] The variable resistors R1 and R2 are resistors utilizing the
p-n junction of semiconductors. Assuming that a current flowing
through the p-n junction is I, the value R of resistance of the
variable resistors R1 and R2 is expressed by expression (6).
R=V.sub.T/ I (6)
[0135] In expression (6), R can be varied by varying the current I,
so that the phase shift quantity can be varied.
[0136] In expression (6), V.sub.T is expressed by V.sub.T=kT/q
wherein k is Boltzmann's constant, T is an absolute temperature and
q is the quantity of charges of electrons, and V.sub.T is about 26
mV at ordinary temperatures. The current quantity I can be set by a
current source. If the current quantity I of the current source is
controlled by the dc component of the output of the mixer 22, the
phase shift quantity can be controlled so that the dc component of
the output of the mixer 22 is always zero.
[0137] That is, the CR phase shifter circuit of FIG. 4 can control
the value of resistance of the variable resistors by adjusting the
current quantity I of the current source. By controlling this value
of resistance, the dc component of the output of the mixer 22 can
be changed.
[0138] In order to decrease errors in the phase shift quantity, the
dc gain of the phase shift adjusting circuit 32 is set to be
sufficiently large, and the current quantity I of the current
source is changed in accordance with the change of the dc
component. That is, assuming that a dc error is .DELTA.V and the dc
gain of the control circuit is A, the error decreases as A
increases since .DELTA.V is in proportion to I/A.
[0139] By the above described control, the 90.degree. phase shifter
circuit 21 can be controlled so that the dc component of the output
of the mixer 22 is always 0, and the phase shift quantity of the
90.degree. phase shifter circuit 21 can be always held to be
90.degree.. When the phase shift in the 90.degree. phase shifter
circuit 21 is held to be correctly 90.degree.,the output
frequencies of the respective stages of the doubler circuits 2 are
as follows.
[0140] First Stage:
[0141] 81.425 MHz, 244.275 MHz, 407.125 MHz, . . .
[0142] Second Stage:
[0143] 162.85 MHz, 488.55 MHz, 814.25 MHz, . . . (caused by 81.425
MHz)
[0144] 488.55 MHz, 1465.65 MHz, 2442.75 MHz, . . . (caused by
244.275 MHz)
[0145] 814.25 MHz, 2442.75 MHz, 4071.25 MHz, . . . (caused by
407.125 MHz)
[0146] Third Stage:
[0147] 325.7 MHz, 977.1 MHz, 1628.5 MHz, . . . (caused by 162.85
MHz)
[0148] 977.1 MHz, 2931.3 MHz, 4885.5 MHz, . . . (caused by 488.55
MHz)
[0149] 1628.5 MHz, 4885.5 MHz, 8142.5 MHz, . . . (caused by 814.25
MHz)
[0150] Since the undesired higher harmonic components outputted
from the third stage doubler circuit 2 have frequencies of 977.1
MHz or more which are sufficiently separated, it seems that only a
desired frequency of 325.7 MHz can be easily obtained even if the
filter circuit 31 is not used.
[0151] However, as described above, the 4n order higher harmonic
component appears when the phase shift quantity is not held to be
90.degree.. In fact, various frequency components act on the mixer
22 of the doubler circuit 2. In this case, the output frequencies
of the respective stages of doubler circuits are as follows.
[0152] First Stage: 81.425 MHz, 162.85 MHz, 244.275 MHz, 325.7 MHz,
407.125 MHz, . . .
[0153] Second Stage: 162.85MHz, 325.7MHz, 488.55MHz, 651.4MHz,
814.25 MHz, (caused by 81.425 MHz) . . .
[0154] 325.7 MHz, 651.4 MHz, 977.1 MHz, 1302.8 MHz, 1628.5 MHz, . .
. (caused by 162.85 MHz)
[0155] 488.55 MHz, 977.1 MHz, 1465.65 MHz, 1954.2 MHz, . . .
(caused by 244.275 MHz)
[0156] 651.4 MHz, 1302.8 MHz, 1954.2 MHz, 2605.6 MHz, 3257 MHz, . .
. (caused by 325.7 MHz)
[0157] 814.25 MHz, 1628.5 MHz, 2442.75 MHz, 3257 MHz, . . . (caused
by 407.125 MHz)
[0158] 81.425 MHz, 162.85 MHz, 244.275 MHz, 325.7 MHz, . . .
(interaction between higher harmonics in the first stage)
[0159] Third Stage: 325.7 MHz, 651.4 MHz, 977.1 MHz, 1302.8 MHz,
1628.5 MHz, . . . (caused by 162.85 MHz)
[0160] 488.55 MHz, 977.1 MHz, 1465.65 MHz, 1954.2 MHz, . . .
(caused by 244.275 MHz)
[0161] 651.4 MHz, 1302.8 MHz, 1954.2 MHz, 2605.6 MHz, 3257 MHz, . .
. (caused by 325.7 MHz)
[0162] 814.25 MHz, 1628.5 MHz, 2442.75 MHz, 3257 MHz, . . . (caused
by 407.125 MHz)
[0163] 977.1MHz, 1954.2MHz, 2931.3MHz, 3908.4MHz,4885.5 MHz, . . .
(caused by 488.55 MHz)
[0164] 81.425 MHz, 162.85 MHz, 244.275 MHz, 325.7 MHz, . . .
(interaction between higher harmonics in the second stage)
[0165] Thus, frequency components which are multiples of 81.425 MHz
remain in the output of the third stage which is the final stage.
That is, frequencies adjacent to the finally required frequency of
325.7 MHz are 244.275 MHz and 407.125 MHz, and the difference
therebetween is only 81.425 MHz, so that it is difficult to remove
these frequencies.
[0166] The reason for this is that the frequency components which
are multiples of 81.425 MHz are left in the output of the first
stage. For example, if a filter circuit 31 for transmitting only a
frequency of 81.425 MHz is provided in the output of the first
stage to remove other frequency components, the output frequency of
the respective stages are as follows.
[0167] First Stage: 81.425 MHz
[0168] Second Stage: 162.85MHz, 325.7MHz, 488.55MHz, 651.4MHz,
814.25 MHz, . . .
[0169] Third Stage: 325.7 MHz, 651.4 MHz, 977.1 MHz, 1302.8 MHz,
1628.5 MHz, . . . (caused by 162.85 MHz)
[0170] 651.4 MHz, 1302.8 MHz, 1954.2 MHz, 2605.6 MHz, 3257 MHz, . .
. (caused by 325.7 MHz)
[0171] 814.25 MHz, 1628.5 MHz, 2442.75 MHz, 3257 MHz, . . . (caused
by 407.125 MHz)
[0172] 977.1 MHz, 1954.2 MHz, 2931.3 MHz, 3908.4 MHz, 4885.5 MHz, .
. . (caused by 488.55 MHz)
[0173] 162.85 MHz, 325.7 MHz, 488.55 MHz, 651.4 MHz, . . .
(interaction between higher harmonics in the second stage)
[0174] Thus, the frequency component of multiple number of 81.425
MHz remains to the third stage output, which is the last stage.
That is, the frequencies adjacent to the frequency of 325.7 MHz
necessary finally are 244.275 MHz and 407.125 MHz. Because the
difference between these frequencies is only 81.425 MHz, it is
difficult to remove these frequency components.
[0175] The reason why the frequency difference becomes 81.425 MHz
is because the frequency component of multiple number of 81.425 MHz
is included to the output of the first stage. For example, when the
filter circuit 31 for passing only 81.425 MHz is connected to the
output of the first stage to remove the other frequency components,
the output frequency of the respective stages are as follows.
[0176] First Stage: 81.425 MHz
[0177] Second Stage: 162.85 MHz, 325.7MHz, 488.55MHz, 651.4MHz,
814.25 MHz, . . . (caused by 81.425 MHz)
[0178] Third Stage: 325.7 MHz, 651.4 MHz, 977.1 MHz, 1302.8 MHz,
1628.5 MHz, . . . (caused by 162.85 MHz)
[0179] 651.4 MHz, 1302.8 MHz, 1954.2 MHz, 2605.6 MHz, 3257 MHz, . .
. (caused by 325.7 MHz)
[0180] 814.25 MHz, 1628.5 MHz, 2442.75 MHz, 3257 MHz, . . . (caused
by 407.125 MHz)
[0181] 977.1 MHz, 1954.2 MHz, 2931.3 MHz, 3908.4 MHz, 4885.5 MHz, .
. . (caused by 488.55 MHz)
[0182] 162.85 MHz, 325.7 MHz, 488.55 MHz, 651.4 MHz, . . .
(interaction between higher harmonics in the second stage)
[0183] Thus, the filter circuit 31 is connected to the output
terminal of the first stage doubler circuit 2, frequencies adjacent
to 325 MHz are 162.85 MHz and 488.55 MHz, and the difference
therebetween is 162.85 MHz, so that it is easy to remove these
frequencies.
[0184] If the filter circuit 31 for transmitting only a frequency
of 162.85 MHz is also provided in the output of the second stage
doubler circuit 2, the output frequency of the respective stages
are as follows.
[0185] First Stage: 81.425 MHz
[0186] Second Stage: 162.85 MHz
[0187] Third Stage: 325.7 MHz, 651.4 MHz, 977.1 MHz, 1302.8 MHz,
1628.5 MHz, . . . (caused by 162.85 MHz)
[0188] Thus, the undesired higher harmonic components outputted
from the third stage are greatly removed, and the frequency
adjacent to 325 MHz is 651.4 MHz, so that the undesired higher
harmonic components can be sufficiently removed.
[0189] The above described filter circuit 31 has a low-pass or
band-pass construction for removing higher harmonics, and must be
capable of optionally controlling frequency characteristics in
accordance with the variation in source oscillation frequency.
[0190] For example, the variation in source oscillation frequency
means a case where a system is intended to be used at a frequency
which varies due to the difference in system to be used, and a case
where the source oscillation frequency slightly varies due to
variation of elements, temperature characteristics and so
forth.
[0191] In order to realize such a filter circuit 31, there is
considered a filter circuit shown in, e.g., FIG. 5. The filter
circuit 31 of FIG. 5 is a secondary low-pass filter circuit which
comprises: a variable resistor R3, the resistance value of which is
variably controlled by the quantity of current flowing through a
current source 45; a variable resistor R4, the resistance value of
which is variably controlled by the quantity of current flowing
through a current source 46; amplifiers 47 and 48; and capacitors
C3 and C4.
[0192] In FIG. 5, the dc component of the output of the mixer 22 of
the first stage doubler circuit 2 is supplied to the current
source. If the current quantity of the current source varies in
accordance with the change of the dc component of the output of the
mixer 22, resistance value of the resistor 30 can be varied. This
is based on the same concept as that of the resistors R1 and R2 of
the CR phase shifter circuit shown in FIG. 4.
[0193] In the second preferred embodiment, the dc component of the
output of the mixer 22 is controlled so that the phase shift
quantity based on the CR phase shifter circuit shown in FIG. 4 is
actually 90.degree.. That is, this means that the value of
resistance of the CR phase shifter circuit settles in such a value
that the phase shift quantity is 90.degree. even if the source
oscillation frequency is varied.
[0194] If the filter circuit 31 comprises the resistors R3 and R4
which have the same constructions as those of the resistors R1 and
R2 which are used for the CR phase shifter circuit of FIG. 4 and if
the filter circuit 31 is controlled by control signals of the CR
phase shifter circuit, the value of resistance settles in the value
of resistance capable of always shifting the phase of the source
oscillation frequency by 90.degree.. Therefore, if this value is
inversely operated to set the capacity of the capacitor so as to
decide the frequency characteristics of the filter circuit 31, it
is possible to form the filter circuit 31 following the variation
in source oscillation frequency.
[0195] Thus, in the second preferred embodiment, the phase shift
adjusting circuit 32 is provided for monitoring the output of the
mixer 22, and the displacement of the phase shift can be corrected
by controlling the phase shift quantity of the 90.degree. phase
shifter circuit so that the dc component is always zero. Therefore,
even if the phase shift quantity is shifted from 90.degree. due to
the variation in element and temperature change, the phase shift
quantity can be immediately adjusted, so that the dc component of
the output of the mixer 22 can be always zero.
[0196] In addition, since the filter circuit 31 is provided between
the stages of the doubler circuits 2, it is possible to surely
inhibit the occurrence of undesired higher harmonics, so that
higher harmonic noises are not radiated to the outside of the IC
including the receiver in this preferred embodiment. Therefore, it
is not required to provide shielding for the frequency multiplier
circuit unlike conventional devices, and it is not required to
spatially insure the distance between the frequency multiplier
circuit and the mixer 22, so that it is possible to easily design
the circuit and to miniaturize the circuit.
Third Preferred Embodiment
[0197] In the third preferred embodiment of a frequency multiplier
circuit according to the present invention, the constructions of a
90.degree. phase shifter circuit 21 and a filter circuit 31 are
different from those in the second preferred embodiment.
[0198] FIG. 6 is a circuit diagram showing the detailed
construction of the third preferred embodiment of a 90.degree.
phase shifter circuit 21a according to the present invention. The
90.degree. phase shifter circuit 21a of FIG. 6 is a CR phase
shifter circuit using a semiconductor element (transistor). In the
90.degree. phase shifter circuit 21a, two stages of 45.degree.
phase shifting parts (first and second phase shifting parts) 60 for
shifting a phase by 45.degree. are cascade-connected to each
other.
[0199] The 45.degree. phase shifting parts 60 of FIG. 6 comprises:
transistors Q1 and Q2, to the base terminal of which the output of
a reference oscillator 41 is supplied; a capacitor C5 which is
provided between the emitter terminals of the transistors Q1 and
Q2; and current sources 61 and 62 which are connected to the
emitter terminals of the transistors Q1 and Q2, respectively. The
current supplied from the current sources 61 and 62 is controlled
by the phase shift adjusting circuit 32 of FIG. 3.
[0200] The resistance R of the p-n junction between the base and
emitter of the transistors Q1 and Q2 viewed from the emitter side
is R=VT/I assuming that the current flowing through the p-n
junction is I, so that the resistance R can be varied by varying I.
That is, the frequency characteristics can be varied by controlling
the current flowing through the transistors Q1 and Q2. Furthermore,
VT is expressed by VT=kT/q wherein k is Boltzmann's constant, T is
an absolute temperature and q is the quantity of charges of
electrons, and VT is about 26 mV at ordinary temperatures.
[0201] The current I flowing through the transistors Q1 and Q2 is
determined by the current supplied from the current sources 61 and
62. If the current quantity of the current sources 61 and 62 is
controlled by the dc component of the output of the mixer 22 of
FIG. 3, the phase shift quantity can be adjusted so that the dc
component of the output of the mixer 22 is always 0.
[0202] In the circuit of FIG. 6, the emitter resistance of the
transistors Q1 and Q2 is adjusted by the current quantity of the
current sources 61 and 62, and the current quantity of the current
sources 61 and 62 is varied in accordance with the change of the dc
component of the output of the mixer 22. Specifically, the current
quantity of the current sources 61 and 62 is varied so that the dc
component of the output of the mixer 22 decreases. Thus, the
90.degree. phase shifter circuit 21a can be controlled so that the
dc component of the output of the mixer 22 is always 0, so that the
phase shift quantity can be maintained to be 90.degree.
[0203] However, in an actual circuit, the phase shift quantity is
not always 90.degree. due to the variation in element and
temperature conditions, and various frequency components act on the
mixer of the doubler circuit 2. Because of this, the filter circuit
31 of FIG. 3 has to be constituted of a low-pass or band-pass
construction for removing higher harmonics, and must be capable of
optionally controlling frequency characteristics in accordance with
the variation in source oscillation frequency.
[0204] For example, the variation in source oscillation frequency
means a case of intending to use the frequency different in
accordance with the used system different from each other, and a
case where the source oscillation frequency slightly varies due to
the variation in elements, temperature characteristics and so
forth.
[0205] As a filter circuit 31 meeting such requirements, a circuit
shown in FIG. 7 is considered. The filter circuit 31 of FIG. 7
comprises: transistors (first and second variable impedance
elements) Q3 and Q4 capable of varying a base-to-emitter
resistance; capacitors (first capacitor elements) C6 and C7 which
are provided between output terminals OUT1 and OUT2; a transistor
(first transistor) Q5 for controlling the voltage of the output
terminal OUT1 in accordance with a base-to-emitter current of the
transistor Q4; a transistor (second transistor) Q6 for controlling
the voltage of the output terminal OUT2 in accordance with a
base-to-emitter current of the transistor Q3; a current source 63
which is connected between the emitter and ground terminal of the
transistor Q5; a current source 64 which is connected between the
emitter and ground terminal of the transistor Q6; and capacitors
(second capacitor elements) C8 and C9 which are connected to the
emitters of the transistors Q5 and Q6.
[0206] Between the output terminals OUT1 and OUT2 and between the
emitters of the transistors Q5 and Q6, the two capacitors (C6, C7)
and the two capacitors (C8, C9) are connected in series,
respectively. These capacitors are provided so as to be consistent
to the small-signal equivalent circuit diagram of FIG. 8 which will
be described later, and the number of the capacitors may be
one.
[0207] The current passing through the current sources 63 and 64 is
controlled by the output dc component of the mixer 22 in the
doubler circuit 2 of FIG. 3. By changing the current passing
through the current sources 63 and 64, it is possible to change the
emitter resistor of the transistors Q3, Q4, Q5 and Q6. This is the
same conception as the resistor of the above CR phase shifter
circuit.
[0208] It has been described above that the dc component of the
output of the mixer 22 in the double circuit 2 is controlled so
that the phase shift quantity based on the CR phase shifter circuit
is 90.degree.. That is, this means that the value of resistance of
the CR phase shifter circuit always settles in such a value of
resistance that the quantity can be phase-shifted by 90.degree.
even if the source oscillation frequency is varied on various
conditions.
[0209] If the filter circuit 31 comprises an emitter resistor which
has the same construction as that of the emitter resistor of the
transistor in the CR phase shifter circuit and if the filter
circuit 31 is controlled by control signals of the CR phase shifter
circuit, the value of resistance settles in the emitter resistance
capable of always shifting the phase of the source oscillation
frequency by 90.degree.. Therefore, if this value is inversely
operated to set the capacity of the capacitor so as to decide the
frequency characteristics of the filter circuit 31, it is possible
to form the filter circuit 31 following the variation in source
oscillation frequency.
[0210] FIG. 8 is a small-signal equivalent circuit diagram of the
filter circuit 31 of FIG. 7. That is, FIG. 8 shows a laterally
symmetric circuit wherein the capacitors C6 =C7, C8=C9 and the
current source 63=64 in the filter circuit 31 of FIG. 7.
[0211] In FIG. 8, the emitter resistors of the transistors Q3, Q4
and transistors Q5, Q6 are expressed by variable resistors (first
and second variable impedance elements) re, and the transistors Q5,
Q6 are expressed by a buffer 81. Since the base and collector of
the transistors Q5, Q6 are crossed, the same current as the output
current Io of the buffer 81 flows through a constant current source
(current supply circuit) 82. Moreover, the capacitors C6, C7 of
FIG. 7 are expressed by a capacitor (first capacitor element) C11,
and the capacitors C8, C9 are expressed by a capacitor C12.
[0212] The transfer function T(s) of the small-signal equivalent
circuit of FIG. 8 is described as expression (7):
T(s)=(1+s.times.C12.times.re)/(1-(.omega..times.re) 2.times.C11
.times.C12+s.times.(C11.times.re+C12.times.re-C12.times.re) (7)
[0213] FIG. 9 is a graph expressed by expression (7), wherein the
axis of abscissas denotes frequency (standardized at the central
frequency) and the axis of ordinates denotes amplitude (expressed
by logarithm). In the small-signal equivalent circuit diagram of
FIG. 8, Q is determined by the ratio C11/C12 of the capacitance C11
to the capacitance C12, and Q is high when the value of C11/C12 is
small.
[0214] FIG. 9 shows characteristics in the cases of C11/C12=0.44
and C11/C12=0.25. By setting Q to be an appropriate value, the
quantity of attenuation of adjacent undesired frequencies can be
adjusted.
[0215] FIG. 10 shows a filter circuit 31 wherein the transistors Q3
and Q4 of FIG. 7 are Darlington-connected. The resistance of the
input side viewed from the emitters of the transistors Q3 and Q4 is
2.times.re, and a linearly operation range is .+-.2VT (about .+-.52
mV) in differential.
[0216] FIG. 11 shows a filter circuit 31 used for an actual LSI or
the like. The dc voltage error generated by the filter circuit 31
of FIG. 11 is usually about 1 mV, and the required signal level
must be sufficiently higher than the dc error voltage. The filter
circuit 31 of FIG. 11 is characterized in that a limiter amplifier
(first limiter amplifier) 71 is provided between the input terminal
and transistors Q3, Q4 of FIG. 7.
[0217] In the filter circuit 31 of FIG. 11, a linearly operating
range is .+-.2 VT (about +52 mV), and is not sufficiently greater
than the dc error voltage 1 mV. Therefore, in order to obtain an
operating range which is sufficiently greater than the dc error
voltage, it is required to operate the filter circuit 31 in a
non-linear range. Since the dc error voltage should be 1% or less,
the input signal level should be usually 100 mV. However, when the
filter circuit 31 is operated in a non-linear range, the frequency
characteristics of the filter circuit 31 are varied by the input
signal level, so that the limiter amplifier 71 of FIG. 11 is
required.
[0218] The frequency characteristics of the filter circuit 31 of
FIG. 11 must be controlled in accordance with the phase shift
quantity of the 90.degree. phase shifter circuit 21a. However, when
there is a fixed phase shift quantity based on a limiter amplifier
26 provided in the 90.degree. phase shifter circuit 21a, the
frequency characteristics of the filter circuit 31 are shifted by a
value corresponding to the fixed phase shift quantity. This means
that the frequency characteristics of the filter circuit 31 can not
faithfully follow the phase shift quantity of the 90.degree. phase
shifter circuit 21a if the source oscillation frequency varies, so
that required signals are attenuated.
[0219] Therefore, in order to cancel the fixed phase shift quantity
caused by the limiter amplifier 26, the filter circuit 31 of FIG.
11 is provided with a fixed resistor (first impedance element) R5
between the emitter of the transistor Q3 and the collector of the
transistor Q5, a fixed resistor (second impedance element) R6
between the emitter of the transistor Q4 and the collector of the
transistor Q6, a fixed resistor (third impedance element ) R7
between the emitter of the transistor Q5 and the current source 63,
and a fixed resistor (fourth impedance element) R8 between the
emitter of the transistor Q6 and the resistor R8. Thus, the fixed
phase shift quantity caused by the limiter amplifier 26 is
canceled, so that it is possible to realize the filter circuit 31
faithfully following the phase shift quantity of the 90.degree.
phase shifter circuit.
[0220] The values of resistance of the fixed resistors R7 and R8
are obtained as follows. Assuming that the fixed phase shift
quantity of the 90.degree. phase shifter circuit 21a (two
45.degree. phase shifter circuits) is .alpha. and the variable
phase shift quantity is .beta.(.alpha.+.beta.=45.degree.) in a
certain frequency, the value R of resistance of the fixed resistors
R5 through R8 is obtained by expression (6):
R:re=.alpha.:.beta. (8)
[0221] wherein re and .beta. are variable and controlled in inverse
proportion to a constant current I. If expression (8) is
transformed, expression (9) is obtained.
R=(.alpha./.beta.).times.re (9)
[0222] The fixed resistors R5 and R6 are expressed by an expression
wherein 2re is substituted for re in expression (9).
[0223] If the limiter amplifier 71 of FIG. 11 is provided in the
filter circuit 31, the linearly operating range is .+-.2VT (about
.+-.52 mV) which is not sufficiently greater than the dc error
voltage of 1 mv. Therefore, in order to obtain a sufficiently
greater operating range than the dc error voltage, it is required
to operate the filter circuit 31 in a non-linear range. Since the
dc error voltage should be 1% or less, the input signal level
should be usually 100 mV. However, when the filter circuit 31 is
operated in the non-linear range, it is required to provide the
limiter amplifier 71 since the frequency characteristics of the
filter circuit 31 is varied by the input signal level.
[0224] FIG. 12 is a circuit diagram of a 90.degree. phase shifter
circuit 21a having a limiter amplifier 26. By this circuit, it is
possible to obtain a sufficiently great input signal level with
respect to the dc voltage error.
[0225] Thus, in this preferred embodiment, in order to cancel the
fixed phase shift quantity, which is caused by the limiter
amplifier 26 of the 90.degree. phase shifter 21a, by the resistors
R6 through R8 provided in the filter circuit 31, it is possible to
realize the filter circuit 31 capable of controlling the frequency
characteristics faithfully following the phase shift quantity of
the 90.degree. phase shifter circuit 21a. Thus, even if adjacent
undesired high frequencies are generated, the filter circuit 31 can
attenuate undesired frequencies.
[0226] While FIG. 3 has shown the local oscillator circuit 14b
having both of the filter circuit 31 and the phase shift adjusting
circuit 32, a local oscillator circuit 14b having a filter circuit
31 and no phase shift adjusting circuit 32 as shown in FIG. 13, and
a local oscillator circuit 14b having a phase shift adjusting
circuit 32 and no filter circuit 31 as shown in FIG. 14 are
considered.
[0227] In the case of the construction of FIG. 13, undesired higher
harmonic components can be removed by the filter circuit 31
although the phase shift quantity of the 90.degree. phase shifter
circuit 21a can not be adjusted. In the case of the construction of
FIG. 14, the phase shift quantity of the 90.degree. phase shifter
21a can be adjusted although higher harmonic components can not be
removed by the filter circuit 31. In either case, the circuit
construction can be more simplified than that in FIG. 3.
Fourth Preferred Embodiment
[0228] As described in the second preferred embodiment, undesired
frequency components appear if the phase shift quantity in the
90.degree. phase shifter circuit 21 is not correctly held to be
90.degree.. The signal level of the undesired frequency components
is doubled every time passing through the doubler circuit 2.
[0229] That is, assuming that the signal level of a required
frequency is 0 dB, the signal level of adjacent undesired
frequencies is increased by 6 dB every time passing through one
stage doubler circuit 2. Because of this, the required frequency is
easily interfered by the undesired frequencies, and the receiving
sensitivity deteriorates, so that communication quality
deteriorates. Therefore, it is difficult to realize
commercialization of products.
[0230] The cause of the occurrence of undesired frequency
components from the doubler circuits 2 will be described below. The
mixer 22 has two input terminals. If signals f1 and f2 are inputted
to these input terminals, the mixer 22 outputs a frequency signal
of .vertline.f1.+-.f2.vertline.. If the signals f1 and f2 contain
even order distorted components 2n.multidot.f (n is an integer
which is 0 or more), the mixer 22 outputs a frequency signal of
(2n.multidot.f) .+-.f=(2n.+-.1).multidot.f. Therefore, the
frequency component of (2n+1).multidot.f remains in the output of
the doubler circuit 2.
[0231] If the phase difference between input signals of the mixer
22 is shifted from 90.degree., a frequency component of
4.multidot.f remains in the output signal of the mixer 22. If the
output of the mixer 22 is inputted directly to the phase shift
adjusting circuit as shown in FIG. 3, the phase shift adjusting
circuit itself generates a DC offset by the frequency component of
4.multidot.f included in the output signal of the mixer 22, so that
it is difficult to remove the DC offset.
[0232] For example, if the output signal of the mixer 22 contains a
frequency component of 2.multidot.f and a frequency component of
4.multidot.f, a dc component is generated by a tertiary
intermodulation as expressed by expression (10).
4.multidot.f-2.multidot.f.times.2=0 (DC) (10)
[0233] Thus, the phase shift can not be maintained to be correctly
90.degree., and the frequency component of 4.multidot.f contained
in the output of the mixer 22 can not be removed.
[0234] Also, if two input signals to the mixer 22 contain higher
harmonic components other than the above described components,
frequency components which are the sum of and difference between
these frequency components are generated in the mixer 22 to be
spurious. If this spurious is generated in the first stage doubler
circuit 2, undesired frequency components are increased by 6 dB in
the respective stages of doubler circuits 2. However, the
construction of FIG. 3 can not remove such undesired frequency
components.
[0235] The fourth preferred embodiment which will be described
later is characterized in that spurious contained in the source
oscillation signal from the source oscillator circuit 1 is removed,
and the distorted component contained in the input signal of the
mixer 22 is removed, and the distorted component contained in the
output signal of the mixer 22 is removed.
[0236] FIG. 15 is a block diagram of the fourth preferred
embodiment of a receiver including a frequency multiplier circuit
according to the present invention. The receiver of FIG. 15 has the
same construction as that in FIG. 3, except that the internal
construction of the doubler circuit in the local oscillator circuit
14 is different from that in FIG. 3.
[0237] While three stages of doubler circuits 2 are connected in
FIG. 15, the number of stages of doubler circuits 2 to be connected
is not particularly limited.
[0238] Among the three stages of doubler circuits 2 of FIG. 15,
only the construction of the first stage doubler circuit 2 is
different. FIG. 16 is an enlarged block diagram of the internal
construction of the first stage doubler circuit 2. As shown in FIG.
16, the first stage doubler circuit 2 comprises: a limiter
amplifier (first waveform shaping circuit) 81 for shaping the
waveform of a source oscillation signal from the source oscillation
circuit 1; an offset cancel circuit 82 for removing a DC offset,
which is contained in the output of the limiter amplifier 81, to
feed the output back to the input side of the limiter amplifier 81;
a 90.degree. phase shifter circuit 21 for shifting the phase of the
output signal of the limiter amplifier 81 by 90.degree.; a limiter
amplifier (fourth waveform shaping circuit) 83 for shaping the
waveform of the output of the 90.degree. phase shifter circuit 21;
a limiter amplifier (third waveform shaping circuit) 84 for shaping
the waveform of the output of the limiter amplifier 81; and a mixer
22 for generating a doubled signal on the basis of the output
signals of the limiter amplifiers 83 and 84. After the output of
the mixer 22 is inputted to the limiter amplifier (second waveform
shaping circuit) 85 to be waveform-shaped to be inputted to the
phase shift adjusting circuit 32 to remove a DC offset
therefrom.
[0239] The doubler circuits 2 other than the first stage in FIG. 15
have a construction wherein the limiter amplifier 81 and the offset
cancel circuit 82 are omitted from the first stage doubler
circuit.
[0240] The limiter amplifier 81 is designed to remove the even
order distorted components contained in the source oscillation
signal from the source oscillator circuit 1, and the offset cancel
circuit 82 is designed to remove the DC offset contained in the
output of the limiter amplifier 81. Thus, a complete rectangular
wave having a duty ratio of 50% is inputted to the 90.degree. phase
shifter circuit 21.
[0241] Since the above described construction of FIG. 3 can not
remove the even order frequency components contained in the source
oscillation signal from the source oscillator circuit 1, there is
the possibility that odd order ((2n+1).times.f) spurious of
multiplied output may be generated in the output of the mixer 22.
However, since the construction of FIG. 15 is designed to carry out
a multiplication processing after changing the source oscillation
signal to a complete rectangular wave having a duty ratio of 50%,
spurious is not generated in the output of the mixer 22.
[0242] FIG. 17 is a circuit diagram showing the detailed
construction of the phase shift adjusting circuit of FIG. 16. The
offset cancel circuit 82 of FIG. 17 comprises: a differential
amplifier having transistors Q21 and Q22 for comparing offset
voltages of differential input signals, and a current source 86; a
current mirror circuit having transistors (Q23, Q24), (Q25, Q26),
(Q27, Q28) connected to the differential amplifier; a capacitor C21
for removing ac components from the output of the differential
amplifier; and a transistor Q29 for current-outputting the output
of the differential amplifier. The capacitor C21 and the transistor
Q28 constitute a low-pass filter.
[0243] FIG. 18 is a circuit diagram showing the detailed
construction of the limiter amplifier of FIG. 16. The limiter
amplifier of FIG. 18 comprises: a differential amplifier having
transistors Q30 and Q31, resistors R21 and R22 and a current source
87; capacitors C22 and C23 connected to the resistors R21 and R22
in parallel, respectively; and an emitter follower circuit having
transistors Q32 and Q33 connected to the output of the differential
amplifier. The capacitors C22 and C23 and the resistors R21 and R22
constitute a low-pass filter.
[0244] The low-pass filters of FIGS. 17 and 18 are not always
essential constructions, but it is possible to reduce higher order
spurious by providing the low-pass filters.
[0245] If the phase shift quantity of the 90.degree. phase shifter
circuit 21 is shifted from 90.degree. in the doubler circuit 2 of
FIG. 16, a frequency component of 4.multidot.f appears in the
output of the mixer 22. This frequency component is changed to a DC
offset by the limiter amplifier 85, and the DC offset is removed by
the phase shift adjusting circuit 32.
[0246] If the output of the mixer 22 contains an amplitude
distorted component, the distorted component is changed to a DC
component by the limiter amplifier 85. Therefore, the distorted
component is not inputted to the phase shift adjusting circuit 32,
and no tertiary intermodulation is generated.
[0247] Thus, even if the signal from the source oscillator circuit
1 contains even order distorted components, if the DC offset
contained in the output of the mixer 22 is removed by the limiter
amplifier 85, it is possible to obtain a complete rectangular wave
having a duty ratio of 50%, so that it is possible to remove even
order components (2n.times.f (n=0, 1, 2, 3, . . . ) of the output.
That is, in the construction of FIG. 3, even order components exist
in the output signal of the source oscillator circuit 1, and if the
components are inputted to the mixer 22, odd order ((2n+1).times.f)
spurious of multiplied output is generated in the output signal of
the source oscillator circuit 1, whereas in the construction of
FIG. 15, it is possible surely remove spurious.
[0248] If two input signals to the mixer 22 have the same waveform
and contain tertiary spurious components, one of the input signals
contains frequency components of f(0.degree.) and 3f(0.degree.),
and the other input signal contains frequency components of
f(90.degree.) and 3f((270.degree.)).
[0249] If signals of these frequency components are inputted to the
mixer 22, eight kinds of frequency components which are the sum of
and difference between the respective frequency components appear.
Combinations generated from quadruple frequencies among the eight
kinds of frequency components are the following two kinds of
frequency components.
f(90.degree.).times.3.multidot.f(0.degree.).fwdarw.4.multidot.f(90.degree.-
)
f(0.degree.).times.3.multidot.f(270.degree.).fwdarw.4.multidot.f(270.degre-
e.)
[0250] Since the phases of the two kinds of signals are different
from each other by 180.degree., these signals are canceled out, so
that the frequency component of 4.multidot.f disappears.
[0251] This means that the frequency component of 4.multidot.f can
be canceled when two input signals to the mixer 22 have the same
waveform, i.e., only when two input signals to the mixer 22 have
the same level as that of the phase of the tertiary component. In
this preferred embodiment, it is possible to cancel the frequency
component of 4.multidot.f by previously shaping a signal, which is
inputted to the mixer 22, by means of the limiter amplifiers 83 and
84.
[0252] There are the following frequency components of
4.multidot.f.
(5.multidot.f)-f.fwdarw.4.multidot.f
(7.multidot.f)-(3.multidot.f) 4.multidot.f
[0253] It is difficult to cancel high frequency components such as
5.multidot.f and 7.multidot.f. Therefore, in this preferred
embodiment, low-pass filters are provided in the limiter amplifiers
81 and 83 through 85 for attenuating high order components.
[0254] Thus, in this preferred embodiment, the distorted components
contained in the input signals of the doubler circuits 2 and the
output signals of the 90.degree. phase shifter circuit 21 are
changed to DC offsets by the limiter amplifiers 83 and 84 and then
inputted to the mixer 22. Therefore, even if the input signals of
the mixer 22 contain even order components, it is possible to
inhibit the occurrence of odd order ((2n+1).times.f) spurious
components of multiplied outputs passing though the output of the
mixer 22.
[0255] In addition, similarly to the filter circuit 31 shown in
FIG. 3, a band-pass filter may be provided between the mixer 22 and
the limiter amplifier 85 although this is not shown in FIG. 15.
Thus, it is possible to remove spurious contained in the output of
the mixer 22. Even if spurious is generated in the band-pass filter
itself, it is possible to remove the spurious by the subsequent
stage limiter amplifier 85 and offset cancel circuit 82.
[0256] While the present invention has been disclosed in terms of
the preferred embodiment in order to facilitate better
understanding thereof, it should be appreciated that the invention
can be embodied in various ways without departing from the
principle of the invention. Therefore, the invention should be
understood to include all possible embodiments and modification to
the shown embodiments which can be embodied without departing from
the principle of the invention as set forth in the appended
claims.
* * * * *