U.S. patent application number 09/919926 was filed with the patent office on 2001-11-22 for semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop.
Invention is credited to Ogawa, Katsuhisa, Ohmi, Tadahiro, Shibata, Tadashi.
Application Number | 20010043101 09/919926 |
Document ID | / |
Family ID | 16021200 |
Filed Date | 2001-11-22 |
United States Patent
Application |
20010043101 |
Kind Code |
A1 |
Ogawa, Katsuhisa ; et
al. |
November 22, 2001 |
Semiconductor integrated circuit, delay-locked loop having the same
circuit, self-synchronizing pipeline type system,
voltage-controlled oscillator, and phase-locked loop
Abstract
The problem of increase in jitter amounts against increase in
delay amounts is solved by a circuit wherein a signal input
terminal is connected through a first capacitor to an input
terminal of a sense amplifier, a control input terminal is
connected through a second capacitor to the input terminal of the
sense amplifier, and a common connection point between the input
terminal of the sense amplifier and the first and second capacitors
is a floating node, and wherein a signal applied through the signal
input terminal to the input terminal of the sense amplifier is
vertically shifted by a control signal applied to the control input
terminal, at least, near a determination threshold of the sense
amplifier, thereby controlling a delay amount of an output.
Inventors: |
Ogawa, Katsuhisa; (Tokyo,
JP) ; Ohmi, Tadahiro; (Sendai-shi, JP) ;
Shibata, Tadashi; (Tokyo, JP) |
Correspondence
Address: |
FITZPATRICK CELLA HARPER & SCINTO
30 ROCKEFELLER PLAZA
NEW YORK
NY
10112
US
|
Family ID: |
16021200 |
Appl. No.: |
09/919926 |
Filed: |
August 2, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09919926 |
Aug 2, 2001 |
|
|
|
09110013 |
Jul 2, 1998 |
|
|
|
Current U.S.
Class: |
327/158 |
Current CPC
Class: |
H03K 3/0315 20130101;
H03L 7/0812 20130101; H03L 2207/06 20130101; H03L 7/0995 20130101;
H03K 2005/00045 20130101; H03K 3/354 20130101; H03K 5/133
20130101 |
Class at
Publication: |
327/158 |
International
Class: |
H03L 007/06 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 2, 1997 |
JP |
9-176867 |
Claims
What is claimed is:
1. A semiconductor integrated circuit comprising a circuit unit,
said circuit unit comprising: an NMOS transistor and a PMOS
transistor connected to each other between gate terminals thereof
and between drain terminals thereof; and first and second capacitor
means connected in parallel at one terminal of each capacitor means
to the gate electrodes of the NMOS transistor and the PMOS
transistor connected to each other, the other terminal of the first
capacitor means being an input terminal and the other terminal of
the second capacitor means being a control terminal; wherein a
source terminal of said NMOS transistor is a ground terminal, a
source terminal of said PMOS transistor is a power-supply terminal,
and the drain terminals of the NMOS transistor and the PMOS
transistor connected to each other are an output terminal.
2. The semiconductor integrated circuit according to claim 1,
further comprising an inverter connected to the output terminal of
said circuit unit.
3. The semiconductor integrated circuit according to claim 1,
comprising a plurality of said circuit units and a plurality of
inverters respectively connected to output terminals of said
circuit units, wherein an output terminal of each said inverter is
connected to an input terminal of each said circuit unit.
4. The semiconductor integrated circuit according to claim 3,
wherein the control terminals of the circuit units are connected to
each other.
5. The semiconductor integrated circuit according to claim 3,
wherein an output of an inverter associated with the circuit unit
of the final stage out of the output terminals of the inverters to
the circuit units is a final output terminal.
6. The semiconductor integrated circuit according to claim 1,
comprising a plurality of said circuit units, wherein an output
terminal of each said circuit unit is connected to an input
terminal of a circuit unit of a next stage.
7. The semiconductor integrated circuit according to claim 6,
wherein the control terminals of the circuit units of odd stages
are connected to each other and the control terminals of the
circuit units of even stages are connected to each other.
8. The semiconductor integrated circuit according to claim 6,
comprising an odd number of said circuit units.
9. The semiconductor integrated circuit according to claim 7,
comprising an odd number of said circuit units.
10. The semiconductor integrated circuit according to claim 1,
wherein the one terminals of said first and second capacitor means
are connected through a current mirror circuit to the gate
electrodes of the NMOS transistor and the PMOS transistor.
11. The semiconductor integrated circuit according to claim 1,
wherein a connection point between the one terminals of the first
and second capacitor means and the gate electrodes of the NMOS
transistor and the PMOS transistor is in a floating state.
12. The semiconductor integrated circuit according to claim 1,
comprising a first transistor whose gate electrode is connected to
the one terminals of the first and second capacitor means; a second
transistor whose source terminal is connected to a source terminal
of the first transistor; a third transistor whose drain terminal is
connected to a drain terminal of the first transistor, said third
transistor having a gate terminal and the drain terminal shorted; a
fourth transistor forming a current mirror circuit with the third
transistor; a fifth transistor whose drain terminal is connected to
a drain terminal of the second transistor, said fifth transistor
having a gate terminal and the drain terminal shorted; a sixth
transistor forming a current mirror circuit with the fifth
transistor; a seventh transistor whose drain terminal is connected
to a drain terminal of the sixth transistor, said seventh
transistor having the drain terminal and a gate terminal shorted;
and an eighth transistor forming a current mirror circuit with the
seventh transistor; wherein a drain terminal of the fourth
transistor and a drain terminal of the eighth transistor are
connected to each other to be connected to the gate electrodes of
said NMOS transistor and said PMOS transistor.
13. The semiconductor integrated circuit according to claim 12,
wherein the source terminal of the first transistor is a terminal
connected to a low voltage supply whose one terminal is grounded,
source terminals of the third, fourth, fifth, and sixth transistors
are terminals connected to a power supply to which said PMOS
transistor is connected, and source terminals of the seventh and
eighth transistors are ground terminals.
14. The semiconductor integrated circuit according to claim 13,
wherein said first, second, seventh, and eighth transistors are
NMOS transistors and said third, fourth, fifth, and sixth
transistors are PMOS transistors.
15. A delay-locked loop comprising: a semiconductor integrated
circuit comprising a circuit unit, said circuit unit comprising an
NMOS transistor and a PMOS transistor connected to each other
between gate terminals thereof and between drain terminals thereof,
and first and second capacitor means connected in parallel at one
terminal of each capacitor means to the gate electrodes of the NMOS
transistor and the PMOS transistor connected to each other, the
other terminal of the first capacitor means being an input terminal
and the other terminal of the second capacitor means being a
control terminal, wherein a source terminal of said NMOS transistor
is a ground terminal, a source terminal of said PMOS transistor is
a power-supply terminal, and the drain terminals of the NMOS
transistor and the PMOS transistor connected to each other are an
output terminal; a phase comparator to which a reference clock and
an output from the output terminal of said semiconductor integrated
circuit are input; and a low-pass filter to which a phase
difference resulting from comparison in said phase comparator is
input; wherein an output of said lower-pass filter is input to the
control terminal of said semiconductor integrated circuit.
16. The delay-locked loop according to claim 15, further comprising
an inverter connected to the output terminal of said circuit unit
of the semiconductor integrated circuit.
17. The delay-locked loop according to claim 15, comprising a
plurality of said circuit units of the semiconductor integrated
circuit and a plurality of inverters respectively connected to
output terminals of said circuit units, wherein an output terminal
of each said inverter is connected to an input terminal of each
said circuit unit.
18. The delay-locked loop according to claim 17, wherein the
control terminals of the circuit units of the semiconductor
integrated circuit are connected to each other.
19. The delay-locked loop according to claim 17, wherein an output
of an inverter associated with the circuit unit of the final stage
out of the output terminals of the inverters to the circuit units
of the semiconductor integrated circuit is a final output
terminal.
20. The delay-locked loop according to claim 15, comprising a
plurality of said circuit units of the semiconductor integrated
circuit, wherein an output terminal of each said circuit unit is
connected to an input terminal of a circuit unit of a next
stage.
21. The delay-locked loop according to claim 20, wherein the
control terminals of the circuit units of odd stages of the
semiconductor integrated circuit are connected to each other and
the control terminals of the circuit units of even stages thereof
are connected to each other.
22. The delay-locked loop according to claim 20, comprising an odd
number of said circuit units of the semiconductor integrated
circuit.
23. The delay-locked loop according to claim 21, comprising an odd
number of said circuit units of the semiconductor integrated
circuit.
24. The delay-locked loop according to claim 15, wherein the one
terminals of said first and second capacitor means of the
semiconductor integrated circuit are connected through a current
mirror circuit to the gate electrodes of the NMOS transistor and
the PMOS transistor.
25. The delay-locked loop according to claim 15, wherein a
connection point between the one terminals of the first and second
capacitor means of the semiconductor integrated circuit and the
gate electrodes of the NMOS transistor and the PMOS transistor
thereof is in a floating state.
26. The delay-locked loop according to claim 15, comprising a first
transistor whose gate electrode is connected to the one terminals
of the first and second capacitor means of the semiconductor
integrated circuit; a second transistor whose source terminal is
connected to a source terminal of the first transistor; a third
transistor whose drain terminal is connected to a drain terminal of
the first transistor, said third transistor having a gate terminal
and the drain terminal shorted; a fourth transistor forming a
current mirror circuit with the third transistor; a fifth
transistor whose drain terminal is connected to a drain terminal of
the second transistor, said fifth transistor having a gate terminal
and the drain terminal shorted; a sixth transistor forming a
current mirror circuit with the fifth transistor; a seventh
transistor whose drain terminal is connected to a drain terminal of
the sixth transistor, said seventh transistor having the drain
terminal and a gate terminal shorted; and an eighth transistor
forming a current mirror circuit with the seventh transistor;
wherein a drain terminal of the fourth transistor and a drain
terminal of the eighth transistor are connected to each other to be
connected to the gate electrodes of said NMOS transistor and said
PMOS transistor.
27. The delay-locked loop according to claim 26, wherein the source
terminal of the first transistor of the semiconductor integrated
circuit is a terminal connected to a low voltage supply whose one
terminal is grounded, source terminals of the third, fourth, fifth,
and sixth transistors are terminals connected to a power supply to
which said PMOS transistor is connected, and source terminals of
the seventh and eighth transistors are ground terminals.
28. The delay-locked loop according to claim 27, wherein said
first, second, seventh, and eighth transistors of the semiconductor
integrated circuit are NMOS transistors and said third, fourth,
fifth, and sixth transistors are PMOS transistors.
29. A self-synchronizing pipeline type system comprising: a
semiconductor integrated circuit comprising a circuit unit, said
circuit unit comprising an NMOS transistor and a PMOS transistor
connected to each other between gate terminals thereof and between
drain terminals thereof, and first and second capacitor means
connected in parallel at one terminal of each capacitor means to
the gate electrodes of the NMOS transistor and the PMOS transistor
connected to each other, the other terminal of the first capacitor
means being an input terminal and the other terminal of the second
capacitor means being a control terminal, wherein a source terminal
of said NMOS transistor is a ground terminal, a source terminal of
said PMOS transistor is a power-supply terminal, and the drain
terminals of the NMOS transistor and the PMOS transistor connected
to each other are an output terminal; an input latch; a signal
processing logic circuit; an output latch; and first and second
handshake circuits; wherein digital input data and an output from
the first handshake circuit are input to said input latch, data
from said input latch is input to said signal processing logic
circuit, an output from said signal processing logic circuit and an
output from said second handshake circuit are input to the output
latch, a clock signal output from the first handshake circuit is
input to the control terminal of said semiconductor integrated
circuit, and an output from said semiconductor integrated circuit
is input to the second handshake circuit.
30. The system according to claim 29, further comprising an
inverter connected to the output terminal of said circuit unit of
the semiconductor integrated circuit.
31. The system according to claim 29, comprising a plurality of
said circuit units of the semiconductor integrated circuit and a
plurality of inverters respectively connected to output terminals
of said circuit units, wherein an output terminal of each said
inverter is connected to an input terminal of each said circuit
unit.
32. The system according to claim 31, wherein the control terminals
of the circuit units of the semiconductor integrated circuit are
connected to each other.
33. The system according to claim 31, wherein an output of an
inverter associated with a circuit unit of the final stage out of
the outputs of the inverters to the circuit units of the
semiconductor integrated circuit is a final output terminal.
34. The system according to claim 29, comprising a plurality of
said circuit units of the semiconductor integrated circuit, wherein
an output terminal of each said circuit unit is connected to an
input terminal of a circuit unit of a next stage.
35. The system according to claim 34, wherein the control terminals
of the circuit units of odd stages of the semiconductor integrated
circuit are connected to each other and the control terminals of
the circuit units of even stages thereof are connected to each
other.
36. The system according to claim 34, comprising an odd number of
said circuit units of the semiconductor integrated circuit.
37. The system according to claim 35, comprising an odd number of
said circuit units of the semiconductor integrated circuit.
38. The system according to claim 29, wherein the one terminals of
said first and second capacitor means of the semiconductor
integrated circuit are connected through a current mirror circuit
to the gate electrodes of the NMOS transistor and the PMOS
transistor.
39. The system according to claim 29, wherein a connection point
between the one terminals of the first and second capacitor means
of the semiconductor integrated circuit and the gate electrodes of
the NMOS transistor and the PMOS transistor thereof is in a
floating state.
40. The system according to claim 29, comprising a first transistor
whose gate electrode is connected to the one terminals of the first
and second capacitor means of the semiconductor integrated circuit;
a second transistor whose source terminal is connected to a source
terminal of the first transistor; a third transistor whose drain
terminal is connected to a drain terminal of the first transistor,
said third transistor having a gate terminal and the drain terminal
shorted; a fourth transistor forming a current mirror circuit with
the third transistor; a fifth transistor whose drain terminal is
connected to a drain terminal of the second transistor, said fifth
transistor having a gate terminal and the drain terminal shorted; a
sixth transistor forming a current mirror circuit with the fifth
transistor; a seventh transistor whose drain terminal is connected
to a drain terminal of the sixth transistor, said seventh
transistor having the drain terminal and a gate terminal shorted;
and an eighth transistor forming a current mirror circuit with the
seventh transistor; wherein a drain terminal of the fourth
transistor and a drain terminal of the eighth transistor are
connected to each other to be connected to the gate electrodes of
said NMOS transistor and said PMOS transistor.
41. The system according to claim 40, wherein the source terminal
of the first transistor of the semiconductor integrated circuit is
a terminal connected to a low voltage supply whose one terminal is
grounded, source terminals of the third, fourth, fifth, and sixth
transistors are terminals connected to a power supply to which said
PMOS transistor is connected, and source terminals of the seventh
and eighth transistors are ground terminals.
42. The system according to claim 41, wherein said first, second,
seventh, and eighth transistors of the semiconductor integrated
circuit are NMOS transistors and said third, fourth, fifth, and
sixth transistors are PMOS transistors.
43. A voltage-controlled oscillator comprising: a plurality of
circuit units, each said circuit unit comprising an NMOS transistor
and a PMOS transistor connected to each other between gate
terminals thereof and between drain terminals thereof, and first
and second capacitor means connected in parallel at one terminal of
each capacitor means to the gate electrodes of the NMOS transistor
and the PMOS transistor connected to each other, the other terminal
of the first capacitor means being an input terminal and the other
terminal of the second capacitor means being a control terminal,
wherein a source terminal of said NMOS transistor is a ground
terminal, a source terminal of said PMOS transistor is a
power-supply terminal, and the drain terminals of the NMOS
transistor and the PMOS transistor connected to each other are an
output terminal; wherein an output terminal of each said circuit
unit is connected to an input terminal of a circuit unit of a next
stage, an input terminal of the circuit unit of the first stage is
connected to an output terminal of the circuit unit of the final
stage, the control terminals of the circuit units of the first
stage and the final stage are connected to each other, and the
control terminals of the circuit units except for the first stage
and the final stage are connected to each other.
44. A phase-locked loop comprising: a voltage-controlled oscillator
comprising a plurality of circuit units, each said circuit unit
comprising an NMOS transistor and a PMOS transistor connected to
each other between gate terminals thereof and between drain
terminals thereof, and first and second capacitor means connected
in parallel at one terminal of each capacitor means to the gate
electrodes of the NMOS transistor and the PMOS transistor connected
to each other, the other terminal of the first capacitor means
being an input terminal and the other terminal of the second
capacitor means being a control terminal, wherein a source terminal
of said NMOS transistor is a ground terminal, a source terminal of
said PMOS transistor is a power-supply terminal, and the drain
terminals of the NMOS transistor and the PMOS transistor connected
to each other are an output terminal, and wherein an output
terminal of each said circuit unit is connected to an input
terminal of a circuit unit of a next stage, an input terminal of
the circuit unit of the first stage is connected to an output
terminal of the circuit unit of the final stage, the control
terminals of the circuit units of the first stage and the final
stage are connected to each other, and the control terminals of the
circuit units except for the first stage and the final stage are
connected to each other; a phase comparator to which a signal of a
frequency fO is input; and a low-pass filter to which an output
from said phase comparator is input; wherein an output from said
low-pass filter is input to the control terminal of said
voltage-controlled oscillator and an output from said
voltage-controlled oscillator is input to said phase
comparator.
45. A semiconductor integrated circuit wherein a signal input
terminal is connected through first capacitor means to an input
terminal of a sense amplifier and a control input terminal is
connected through second capacitor means to the input terminal of
said sense amplifier, wherein a common connection point between the
input terminal of said sense amplifier and said first and second
capacitor means is a floating node, and wherein a signal applied
through said signal input terminal to the input terminal of said
sense amplifier is vertically shifted by a control signal applied
to said control input terminal, at least, near a determination
threshold of said sense amplifier, thereby controlling a delay
amount of an output.
46. The semiconductor integrated circuit according to claim 45,
wherein said sense amplifier has a buffer function, wherein a
plurality of said semiconductor integrated circuits are connected
in series so that an output terminal of a semiconductor integrated
circuit of a preceding stage is connected to a signal input
terminal of a semiconductor integrated circuit of a next stage, the
control input terminals of the all semiconductor integrated
circuits connected in series being connected to each other, and
wherein a signal is applied to the signal input terminal of the
first stage out of the semiconductor integrated circuits connected
in series and the output terminal of the semiconductor integrated
circuit of the final stage is a signal output terminal.
47. The semiconductor integrated circuit according to claim 45,
wherein said sense amplifier has an inverter function, wherein a
plurality of said semiconductor integrated circuits are connected
in series so that an output terminal of a semiconductor integrated
circuit of a preceding stage is connected to a signal input
terminal of a semiconductor integrated circuit of a next stage, the
control input terminals of the semiconductor integrated circuits of
odd stages out of said plurality of semiconductor integrated
circuits connected in series are connected to each other, and the
control input terminals of the semiconductor integrated circuits of
even stages are connected to each other, and wherein a signal is
applied to the signal input terminal of the first stage out of the
semiconductor integrated circuits connected in series and the
output terminal of the semiconductor integrated circuit of the
final stage is a signal output terminal.
48. The semiconductor integrated circuit according to claim 47,
wherein control voltages changing in opposite directions to each
other are applied to the control input terminals of the
semiconductor integrated circuits of said odd stages and to the
control input terminals of the semiconductor integrated circuits of
said even stages.
49. The semiconductor integrated circuit according to claim 45,
wherein said sense amplifier is comprised of a complementary MOS
inverter.
50. The semiconductor integrated circuit according to claim 45,
wherein said sense amplifier is a comparator having an input stage
of a differential amplifier comprised of MOS transistors.
51. The semiconductor integrated circuit according to claim 50,
wherein an input-output relation of said comparator is an inverting
relation.
52. The semiconductor integrated circuit according to claim 50,
wherein an input-output relation of said comparator is a
non-inverting relation.
53. The semiconductor integrated circuit according to claim 49,
wherein the MOS transistor forming said sense amplifier and the
first and second capacitor means are comprised of a transistor
wherein a floating electrode is formed through a first gate
insulating film on a channel region between source and drain
regions spaced from each other on a semiconductor substrate and
wherein two gate electrodes electrically insulated from each other
are formed through a second gate oxide film on said floating gate
electrode.
54. A voltage control delay line comprising the semiconductor
integrated circuit as set forth in claim 45, wherein a delay amount
of an output pulse is controlled by controlling a pulse applied to
said signal input terminal by said control input terminal.
55. A delay-locked loop comprising the voltage control delay line
as set forth in claim 54.
56. A self-synchronizing pipeline type system comprising the
voltage control delay line as set forth in claim 54.
57. A voltage-controlled oscillator wherein an odd number of
semiconductor integrated circuits as set forth in claim 47 are
connected in series and a final output terminal is connected to the
signal input terminal of the first stage, thereby forming an
oscillation loop, and wherein an oscillation frequency is
controlled by control signals supplied through the control input
terminals of the semiconductor integrated circuits of odd stages
and through the control input terminals of the semiconductor
integrated circuits of even stages.
58. A phase-locked loop comprising the voltage-controlled
oscillator as set forth in claim 57.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor integrated
circuit and, more particularly, to a semiconductor integrated
circuit including a variable delay circuit and to a voltage control
delay line, a delay-locked loop, a self-synchronizing pipeline type
digital system, a voltage-controlled oscillator, and a phase-locked
loop, constructed using the mentioned semiconductor integrated
circuit.
[0003] 2. Related Background Art
[0004] With present progress in the speed-up technology of LSI
there are commercially available microprocessors operating at
several hundred MHz and LSI for communication in several GHz band.
The high-frequency clock synchronization technology is essential to
development of the speed-up technology of these. Increase in the
accuracy and speed of voltage control variable delay circuits is
important as the core of the pulse synchronization control
technology of PLL, DLL, and so on. A voltage control variable delay
circuit is illustrated in FIG. 1. A CMOS inverter is constructed of
an NMOS transistor 82 and a PMOS transistor 81, a gate terminal of
each transistor being connected to input terminal 1 and a source
terminal of each transistor being connected to an input of inverter
88. An NMOS transistor 83 having a first control terminal 86 as a
gate terminal is connected between the ground potential 4 and a
source terminal of the NMOS transistor 82, and a PMOS transistor 84
having a second control terminal 85 as a gate terminal is connected
between a power-supply voltage 3 and a source terminal of the PMOS
transistor 81. In this setup, control voltages of the control
terminals 85, 86 are changed, so as to change conductances of the
PMOS transistor 84 and NMOS transistor 83, thereby controlling a
delay of a pulse appearing at output terminal 2.
[0005] The voltage control variable delay circuit illustrated in
FIG. 1, however, had the problem of increase in jitter amounts
caused by the differences of delay amounts. This problem will be
explained using FIGS. 2, 3, and 4. FIG. 2 is a time chart during
the pulse delay control of the circuit shown in FIG. 1. Numeral 89
designates an input signal applied to the input terminal 1 and a
waveform at node 87 varies as indicated by 90, 91, 92 while its
slewing rate is controlled by the voltages applied to the terminals
85, 86. This waveform is binarized by logic threshold 96 of the
inverter 88 whereby a delay is generated. Increase of the delay of
output can be realized by controlling the slewing rate from the
waveform 90 to 92 of FIG. 2, thereby achieving the variable delay
circuit having delay amounts D1, D2, D3 from output waveforms 93,
94, 95 corresponding to the waveforms 90, 91, 92.
[0006] FIG. 3 is a diagram for explaining a jitter amount in the
case of the waveform 90 and FIG. 4 is a diagram for explaining a
jitter amount in the case of the waveform 92. In practical
circuits, noise signal 97 consisting of thermal noise of the
circuit and external noise etc. is superimposed on the both
waveforms. In the case of the delay time D1, when the CMOS inverter
88 of the next stage binarizes the signal by the logic threshold 96
and supposing the noise density of the noise signal 97 is of a
Gaussian distribution as shown in FIG. 3, a jitter 98 having the
width of J1 appears. When the controlled delay time is changed to
D3, so as to lower the slewing rate, the signal and noise width
across the logic threshold 96 increases as shown in FIG. 4, and
thus the jitter increases to a jitter 99 having the width of J2.
Since at least the thermal noise of the circuit is normally present
in signals, when the delay is controlled by the above-stated
method, the larger the delay, the larger the jitter which is
fluctuation along the time-base direction.
SUMMARY OF THE INVENTION
[0007] The present invention has been accomplished in view of the
above point to be improved, and an object of the present invention
is to provide a semiconductor integrated circuit including a delay
circuit without change in the jitter against change in the delay of
signal.
[0008] Another object of the present invention is to provide a
semiconductor integrated circuit that has no dependence of increase
or decrease of the jitter on change in the delay, that can achieve
low jitter characteristics, that has enhanced high-frequency clock
synchronization accuracy, and that permits higher-speed clock
control.
[0009] Still another object of the present invention is to provide
a semiconductor integrated circuit having a number of circuit units
for carrying out the voltage control delay, connected in series,
the semiconductor integrated circuit being capable of changing the
delay in a wide dynamic range of delay-variable region and the
semiconductor integrated circuit being capable of configuring a PLL
or DLL loop having pulling characteristics of a wide range or a
delay line having a wide variable range.
[0010] A further object of the present invention is to provide a
delay-locked loop, a self-synchronizing pipeline type system, a
voltage-controlled oscillator, and a phase-locked loop, each having
the aforementioned semiconductor integrated circuit.
[0011] Another object of the present invention is to provide a
semiconductor integrated circuit comprising a circuit unit, the
circuit unit comprising:
[0012] an NMOS transistor and a PMOS transistor connected to each
other between gate terminals thereof and between drain terminals
thereof; and
[0013] first and second capacitor means connected in parallel at
one terminal of each capacitor means to the gate electrodes of the
NMOS transistor and the PMOS transistor connected to each other,
the other terminal of the first capacitor means being an input
terminal and the other terminal of the second capacitor means being
a control terminal;
[0014] wherein a source terminal of the NMOS transistor is a ground
terminal, a source terminal of the PMOS transistor is a
power-supply terminal, and the drain terminals of the NMOS
transistor and the PMOS transistor connected to each other are an
output terminal.
[0015] Still another object of the present invention is to provide
a delay-locked loop comprising:
[0016] a semiconductor integrated circuit comprising a circuit
unit, the circuit unit comprising
[0017] an NMOS transistor and a PMOS transistor connected to each
other between gate terminals thereof and between drain terminals
thereof, and
[0018] first and second capacitor means connected in parallel at
one terminal of each capacitor means to the gate electrodes of the
NMOS transistor and the PMOS transistor connected to each other,
the other terminal of the first capacitor means being an input
terminal and the other terminal of the second capacitor means being
a control terminal,
[0019] wherein a source terminal of the NMOS transistor is a ground
terminal, a source terminal of the PMOS transistor is a
power-supply terminal, and the drain terminals of the NMOS
transistor and the PMOS transistor connected to each other are an
output terminal;
[0020] a phase comparator to which a reference clock and an output
from the output terminal of the semiconductor integrated circuit
are input; and
[0021] a low-pass filter to which a phase difference resulting from
comparison in the phase comparator is input;
[0022] wherein an output of the lower-pass filter is input to the
control terminal of the semiconductor integrated circuit.
[0023] A further object of the present invention is to provide a
self-synchronizing pipeline type system comprising:
[0024] a semiconductor integrated circuit comprising a circuit
unit, the circuit unit comprising
[0025] an NMOS transistor and a PMOS transistor connected to each
other between gate terminals thereof and between drain terminals
thereof, and
[0026] first and second capacitor means connected in parallel at
one terminal of each capacitor means to the gate electrodes of the
NMOS transistor and the PMOS transistor connected to each other,
the other terminal of the first capacitor means being an input
terminal and the other terminal of the second capacitor means being
a control terminal,
[0027] wherein a source terminal of the NMOS transistor is a ground
terminal, a source terminal of the PMOS transistor is a
power-supply terminal, and the drain terminals of the NMOS
transistor and the PMOS transistor connected to each other are an
output terminal;
[0028] an input latch;
[0029] a signal processing logic circuit;
[0030] an output latch; and
[0031] first and second handshake circuits;
[0032] wherein digital input data and an output from the first
handshake circuit are input to the input latch, data from the input
latch is input to the signal processing logic circuit, an output
from the signal processing logic circuit and an output from the
second handshake circuit are input to the output latch, a clock
signal output from the first handshake circuit is input to the
control terminal of the semiconductor integrated circuit, and an
output from the semiconductor integrated circuit is input to the
second handshake circuit.
[0033] A further object of the present invention is to provide a
voltage-controlled oscillator comprising:
[0034] a plurality of circuit units, each the circuit unit
comprising
[0035] an NMOS transistor and a PMOS transistor connected to each
other between gate terminals thereof and between drain terminals
thereof, and
[0036] first and second capacitor means connected in parallel at
one terminal of each capacitor means to the gate electrodes of the
NMOS transistor and the PMOS transistor connected to each other,
the other terminal of the first capacitor means being an input
terminal and the other terminal of the second capacitor means being
a control terminal,
[0037] wherein a source terminal of the NMOS transistor is a ground
terminal, a source terminal of the PMOS transistor is a
power-supply terminal, and the drain terminals of the NMOS
transistor and the PMOS transistor connected to each other are an
output terminal;
[0038] wherein an output terminal of each the circuit unit is
connected to an input terminal of a circuit unit of a next stage,
an input terminal of the circuit unit of the first stage is
connected to an output terminal of the circuit unit of the final
stage, the control terminals of the circuit units of the first
stage and the final stage are connected to each other, and the
control terminals of the circuit units except for the first stage
and the final stage are connected to each other.
[0039] A further object of the present invention is to provide a
phase-locked loop comprising:
[0040] a voltage-controlled oscillator comprising
[0041] a plurality of circuit units, each the circuit unit
comprising
[0042] an NMOS transistor and a PMOS transistor connected to each
other between gate terminals thereof and between drain terminals
thereof, and
[0043] first and second capacitor means connected in parallel at
one terminal of each capacitor means to the gate electrodes of the
NMOS transistor and the PMOS transistor connected to each other,
the other terminal of the first capacitor means being an input
terminal and the other terminal of the second capacitor means being
a control terminal,
[0044] wherein a source terminal of the NMOS transistor is a ground
terminal, a source terminal of the PMOS transistor is a
power-supply terminal, and the drain terminals of the NMOS
transistor and the PMOS transistor connected to each other are an
output terminal, and
[0045] wherein an output terminal of each the circuit unit is
connected to an input terminal of a circuit unit of a next stage,
an input terminal of the circuit unit of the first stage is
connected to an output terminal of the circuit unit of the final
stage, the control terminals of the circuit units of the first
stage and the final stage are connected to each other, and the
control terminals of the circuit units except for the first stage
and the final stage are connected to each other;
[0046] a phase comparator to which a signal of a frequency fO is
input; and
[0047] a low-pass filter to which an output from the phase
comparator is input;
[0048] wherein an output from the low-pass filter is input to the
control terminal of the voltage-controlled oscillator and an output
from the voltage-controlled oscillator is input to the phase
comparator.
[0049] A further object of the present invention is to provide a
semiconductor integrated circuit wherein a signal input terminal is
connected through first capacitor means to an input terminal of a
sense amplifier and a control input terminal is connected through
second capacitor means to the input terminal of the sense
amplifier,
[0050] wherein a common connection point between the input terminal
of the sense amplifier and the first and second capacitor means is
a floating node, and wherein a signal applied through the signal
input terminal to the input terminal of the sense amplifier is
vertically shifted by a control signal applied to the control input
terminal, at least, near a determination threshold of the sense
amplifier, thereby controlling a delay amount of an output.
[0051] A further object of the present invention is to provide a
semiconductor integrated circuit which is the above-described
semiconductor integrated circuit, wherein the sense amplifier has a
buffer function, wherein a plurality of the semiconductor
integrated circuits are connected in series so that an output
terminal of a semiconductor integrated circuit of a preceding stage
is connected to a signal input terminal of a semiconductor
integrated circuit of a next stage, the control input terminals of
the all semiconductor integrated circuits connected in series being
connected to each other, and
[0052] wherein a signal is applied to the signal input terminal of
the first stage out of the semiconductor integrated circuits
connected in series and the output terminal of the semiconductor
integrated circuit of the final stage is a signal output
terminal.
[0053] A further object of the present invention is to provide a
semiconductor integrated circuit which is the above-described
semiconductor integrated circuit, wherein the sense amplifier has
an inverter function,
[0054] wherein a plurality of the semiconductor integrated circuits
are connected in series so that an output terminal of a
semiconductor integrated circuit of a preceding stage is connected
to a signal input terminal of a semiconductor integrated circuit of
a next stage, the control input terminals of the semiconductor
integrated circuits of odd stages out of the plurality of
semiconductor integrated circuits connected in series are connected
to each other, and the control input terminals of the semiconductor
integrated circuits of even stages are connected to each other,
and
[0055] wherein a signal is applied to the signal input terminal of
the first stage out of the semiconductor integrated circuits
connected in series and the output terminal of the semiconductor
integrated circuit of the final stage is a signal output
terminal.
[0056] Further, the present invention provides a circuit wherein
many stages of the above-stated semiconductor integrated circuit
units are connected in series whereby the circuit is provided with
a variable delay in a wide dynamic range of delay variable region;
PLL and DLL loops with pulling characteristics of a wide range and
a delay line with a wide variable range can be constructed thereby;
because the delay value can be controlled by the level shift of
waveform, the control characteristics with good linearity can be
assured and accurate control can be performed, thus providing the
circuit suitable for a system requiring high-accuracy and
low-jitter delay control, such as a clock doubler circuit of CPU or
a delay line for handshake in a self-synchronizing pipeline signal
processing system.
BRIEF DESCRIPTION OF THE DRAWINGS
[0057] FIG. 1 is a schematic circuit diagram for explaining an
example of the voltage control variable delay circuit;
[0058] FIG. 2 is a time chart for explaining an example of
waveforms during the pulse delay control in the circuit of FIG.
1;
[0059] FIG. 3 and FIG. 4 are diagrams for explaining respective
jitter amounts in the circuit of FIG. 1;
[0060] FIG. 5 is a schematic circuit diagram for explaining a
semiconductor integrated circuit unit including the variable delay
circuit of the present invention;
[0061] FIG. 6 is a time chart for explaining the pulse delay
control in the circuit of FIG. 5;
[0062] FIG. 7 is a diagram for explaining a jitter amount in the
circuit of FIG. 5;
[0063] FIG. 8 is a conceptual drawing for explaining an example of
a multi-input MOS transistor having a floating gate electrode;
[0064] FIG. 9 is a schematic circuit diagram for explaining an
example of a voltage control delay line in the semiconductor
integrated circuit of the present invention;
[0065] FIG. 10 is a schematic circuit diagram for explaining
another example of the voltage control delay line in the
semiconductor integrated circuit of the present invention;
[0066] FIG. 11 is a schematic circuit diagram for explaining
another example of the voltage control delay line in the
semiconductor integrated circuit of the present invention;
[0067] FIG. 12 is a conceptual drawing for explaining another
example of the multi-input MOS transistor having the floating gate
electrode;
[0068] FIG. 13 is a conceptual drawing of an MOS transistor having
capacitive couplings of two inputs;
[0069] FIG. 14 is a schematic block diagram for explaining an
example of the delay-locked loop of the present invention;
[0070] FIG. 15 is a schematic block diagram for explaining an
example of the self-synchronizing pipeline type system of the
present invention;
[0071] FIG. 16 is a schematic circuit diagram for explaining an
example of the voltage-controlled oscillator of the present
invention; and
[0072] FIG. 17 is a schematic block diagram for explaining an
example of the phase-locked loop of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0073] The embodiments of the present invention will be described
in detail by reference to the drawings.
[0074] [First Embodiment]
[0075] FIG. 5 is a circuit diagram to show the first embodiment of
the present invention. In FIG. 5, first capacitor 6 and second
capacitor 5 are connected in parallel to a gate common connection
point which is an input terminal of a first inverter composed of an
NMOS transistor 8 and a PMOS transistor 9 connected to each other
between their gate terminals and between their drain terminals,
whereby a floating node is created there. An input terminal 1 is
connected to the other terminal of the first capacitor 6 and an
input pulse signal Vin is applied thereto. A control terminal 10 is
connected to the other terminal of the second capacitor 5 and a
control signal Vc is applied thereto. The source terminal of the
NMOS transistor 8 is connected to the ground potential 4 and the
source terminal of the PMOS transistor 9 is connected to the
power-supply voltage 3. A node 7, which is an output of the first
inverter, is connected to an input of second inverter 11 and a
final waveform is taken out of the output terminal 2.
[0076] FIG. 6 is a time chart of waveforms during the pulse delay
control in the present invention. Numeral 12 designates the input
pulse Vin applied to the input terminal 1. The input terminal of
the first inverter is connected to Cin of the first capacitor 6 and
to Cc of the second capacitor 5 to form the floating node. When the
initial charge at the floating node is assumed to be set at 0, the
input pulse applied to Cin of the first capacitor 6 undergoes a
level shift by the control voltage Vc applied to Cc of the second
capacitor 5. Since the floating node comes to have a potential
resulting from capacitance division of Vin and Vc by Cin and Cc,
the potential at the floating node is linearly shifted by
Vc.multidot.Cc/(Cin+Cc) by increasing or decreasing the potential
of Vc. The amplitude of the input pulse Vin is attenuated by the
capacitance division of Vin.multidot.Cin/(Cin+Cc), so that an
attenuated pulse appears at the floating node. Although the
amplitude is attenuated, the frequency characteristics do not vary,
so as to keep rise and fall edges of waveform as they are.
Therefore, the inclination of the rise and fall edges of waveform
does not vary even with the level shift of the floating node by the
control voltage Vc. Numerals 13 to 15 of FIG. 6 indicate changes at
the floating node when the control voltage Vc is changed from the
ground potential to the power-supply potential. As the control
voltage Vc increases, the waveform at the floating node also
raises, so as to change the position where the waveform intersects
with the logic threshold 16 of the first inverter in the time-base
direction. This causes a change of delay between the waveforms at
the node 7 and at the output terminal 2 against the input pulse
Vin. Numerals 17 to 19 of FIG. 6 indicate outputs 2 of the second
inverter 11. The waveform 13 corresponds to the waveform 19, the
waveform 14 to the waveform 18, and the waveform 15 to the waveform
17. While the control voltage Vc is changed from the ground
potential to the power-supply potential, the delay time of output
varies from D3' via D2' to D1'.
[0077] FIG. 7 is a diagram for explaining a jitter amount of the
waveforms 13 to 15 according to the present invention. A noise
signal 20 including the thermal noise of the circuit and the
external noise etc. is superimposed on the waveforms. When the
first inverter binarizes the waveforms 13 to 15 at the floating
node by the logic threshold 16, supposing the noise density of the
noise signal 20 is of the Gaussian distribution as shown in FIG. 7,
a jitter 21 having the width of J appears. The slewing rate of the
waveforms at the floating node is constant even with the change in
the controlled delay time as D3', D2', and D1' in order, so that
the jitter is constant regardless of the delay time.
[0078] The present embodiment is so arranged that the slewing rate
is kept constant and that the delay is changed by the level shift
of input waveform near the logic threshold of the first inverter,
whereby the voltage-controlled delay circuit can be configured
without increase of the jitter against change of the delay, thus
realizing the higher-speed clock technology with improved
high-frequency clock synchronization accuracy.
[0079] The capacitors 5, 6, NMOS transistor 8, and PMOS transistor
9, shown in FIG. 5, can be constructed of a multi-input MOS
transistor having a floating gate electrode (this is also the case
in the subsequent embodiments). This multi-input MOS transistor can
be realized by the two-layer polysilicon CMOS processes and the
like.
[0080] FIG. 8 is a conceptual diagram to show the two-input MOS
transistor having the floating gate electrode.
[0081] P-well regions are formed in an n-type semiconductor
substrate, and the source region and drain region of NMOS
transistor and the source region and drain region of PMOS
transistor are formed in the p-well region and the n-type
semiconductor substrate. In FIG. 8, numeral 102 denotes the NMOS
transistor, 104 the PMOS transistor, 100 the source region of the
NMOS transistor 102, 105 the source region of the PMOS transistor
104, and 103 the drain regions connected to each other.
[0082] A first gate insulating film is provided on the channels
between the drain region and the source region of the NMOS and PMOS
transistors spaced from each other, and a floating gate electrode
(control electrode) 106 of first polycrystal silicon is formed in
common connection through the first gate insulating film. Input
gate electrodes 107, 108 of second polycrystal silicon are formed
through a second gate oxide film on this floating gate electrode
106. Each input gate electrode 107, 108 is connected to the
terminal 10, 1, respectively. Achieved in this way is the
multi-input device having the capacitive couplings of C1 (Cin) and
C2 (Cc) to the floating gate electrode 106.
[0083] When N input gate electrodes (N=2 herein) capacitively
coupled with the floating gate electrode 106 are formed as
described above, the potential of the floating gate electrode 106
is given by a weighted average of input voltages applied to the
many input gates, and the transistor is switched on or off by
whether the weighted average surpasses the threshold of the
transistor. Since this is similar to the operation of neuron which
is a basic constituent unit of the brain of organism, this is
called neuron MOS (hereinafter referred to as VMOS).
[0084] Let C1 be a capacitance established between the floating
gate electrode 106 and the input gate electrode 108, C2 be a
capacitance established between the floating gate electrode 106 and
the input gate electrode 107, V1 be a voltage applied to the input
terminal 108, and V2 be a voltage applied to the input terminal
107. Then the potential .PHI.F of the floating gate electrode 106
is expressed by the following equation.
.PHI.F=(C2.multidot.V2+C1.multidot.V1)/(C2+C1)
[0085] As described above, the potential .PHI.F of the floating
gate electrode 106 is the weighted average, and this weighted
average is determined by the capacitive coupling ratio of the
voltages.
[0086] [Second Embodiment]
[0087] FIG. 9 is a circuit diagram to show the second embodiment of
the present invention. FIG. 9 illustrates a circuit in which N
units of the voltage control delay circuits of the present
invention are connected in series, wherein the voltage control
delay circuit of the first stage is composed of the same components
of numerals 1 to 11 in the first embodiment and wherein the second
stage, . . . , the N-th stage also have the same circuit
configuration. For convenience' sake of description, the circuits
of the third stage to the (N--1)th stage are omitted. In each
voltage control delay circuit, a capacitor 6, 22, 27 composes the
first capacitor means and a capacitor 5, 23, 28 composes the second
capacitor means.
[0088] As illustrated in FIG. 9, the output 2 of the voltage
control delay circuit of the first stage is connected to one
terminal of the capacitor 22, which is an input terminal of the
voltage control delay circuit of the second stage, and the other
terminal of the capacitor 22 is connected to an input terminal of a
third inverter comprised of a capacitor 23, an NMOS transistor 25,
and a PMOS transistor 24. The capacitor 23 is connected to the
delay control terminal 10. An output of the third inverter is input
to a fourth inverter 26 and an output 32 of the fourth inverter 26
is an output of the voltage control delay circuit of the second
stage to be connected to an input of the voltage control delay
circuit of the third stage. The same circuit connection continues
from the voltage control delay circuit of the third stage to the
voltage control delay circuit of the (N-1)th stage.
[0089] An output of the voltage control delay circuit of the
(N-1)th stage is connected to one terminal of the capacitor 27,
which is an input of the voltage control delay circuit of the N-th
stage, and the other terminal of the capacitor 27 is connected to
an input terminal of the (2N-1)th inverter comprised of a capacitor
28, an NMOS transistor 30, and a PMOS transistor 29. The capacitor
28 is connected to the delay control terminal 10. An output of the
(2N-1)th inverter is input to the (2N)th inverter 31 and an output
33 of the (2N)th inverter is a final output.
[0090] By the structure wherein the circuit units of the first
embodiment are connected in series and wherein. the respective
control terminals are connected to each other as described above,
the voltage control delay circuit can be constructed in a simple
form with a wide variable range and with good linearity with the
control voltage, and it becomes possible to realize PPL and DLL
loops with pulling characteristics of a wide range and a delay line
with a wide variable range while maintaining the high-speed
property.
[0091] [Third Embodiment]
[0092] FIG. 10 is a circuit diagram to show the third embodiment of
the present invention. FIG. 10 illustrates a circuit in which N
stages of the voltage control delay circuit units of the present
invention are connected in series, wherein the internal circuits
have the same configuration as the first stage, the second stage,
the (N-1)th stage, and the N-th stage. The present embodiment will
be described with N being odd, but the invention is not limited to
this. For convenience' sake of description, the circuits of the
third stage to the (N-2)th stage are omitted. In each voltage
control delay circuit, a capacitor 34, 38, 62, 42 composes the
first capacitor means and a capacitor 35, 39, 63, 43 composes the
second capacitor means.
[0093] As shown in FIG. 10, the input terminal 1 is connected to
one terminal of the capacitor 34, which is an input terminal of the
voltage control delay circuit of the first stage, and the other
terminal of the capacitor 34 is connected to an input terminal of a
first inverter consisting of a capacitor 35, an NMOS transistor 37,
and a PMOS transistor 36. The capacitor 35 is connected to a first
delay control terminal 66. An output of the first inverter becomes
an output of the voltage control delay circuit of the first stage
to be connected to one terminal of the capacitor 38, which is an
input of the voltage control delay circuit of the second stage, and
the other terminal of the capacitor 38 is connected to an input
terminal of a second inverter consisting of a capacitor 39, an NMOS
transistor 41, and a PMOS transistor 40. The capacitor 39 is
connected to a second delay control terminal 61. An output of the
second inverter becomes an output of the voltage control delay
circuit of the second stage to be connected to an input of the
voltage control delay circuit of the third stage. The same circuit
connection continues from the voltage control delay circuit of the
third stage to the voltage control delay circuit of the (N-2)th
stage. In the present embodiment the second capacitor means of the
circuit units of the odd stages are connected to the first delay
control terminal 66, while the second capacitor means of the
circuit units of the even stages are connected to the second delay
control terminal 61 An output of the voltage control delay circuit
of the (N-2)th stage is connected to one terminal of the capacitor
62, which is an input of the voltage control delay circuit of the
(N-1)th stage, and the other terminal of the capacitor 62 is
connected to an input terminal of the (N-1)th inverter consisting
of a capacitor 63, an NMOS transistor 65, and a PMOS transistor 64.
The capacitor 63 is connected to the second delay control terminal
61. An output of the (N-1)th inverter becomes an output of the
voltage control delay circuit of the (N-1)th stage to be connected
to one terminal of the capacitor 42, which is an input of the
voltage control delay circuit of the N-th stage, and the other
terminal of the capacitor 42 is connected to an input terminal of
the N-th inverter consisting of a capacitor 43, an NMOS transistor
45, and a PMOS transistor 44. The capacitor 43 is connected to the
first delay control terminal 66. An output of the N-th inverter is
a final output 46.
[0094] By the third embodiment wherein the voltage control delay
circuits are connected directly by only the one-stage inverters
through their floating nodes, wherein the control terminals of the
odd stages are connected to the first delay control terminal 66,
wherein the control terminals of the even stages are connected to
the second delay control terminal 61, and wherein the control
voltages of opposite phases to each other are applied to the
control terminals to control their delay amounts, the sensitivity
of delay to the control voltage can be controlled to the level
lower than in the second embodiment. Therefore, the voltage control
delay circuit can be constructed in a simple form with a narrow
variable range and with good linearity with the control voltage,
and it is possible to realize stable PLL and DLL loops resistant to
disturbance noise.
[0095] [Fourth Embodiment]
[0096] FIG. 11 is a circuit diagram to show the fourth embodiment
of the present invention. In FIG. 11 an input pulse Vin is applied
to the input terminal 1 and the input terminal 1 is connected
through first capacitor 48 to second capacitor 47 and to a gate
terminal of NMOS transistor 49. The other terminal of the second
capacitor 47 is connected to the control terminal 10 to which a
delay control signal Vc is applied. The source of NMOS transistor
49 is connected to the source of NMOS transistor 50, thus forming
an input differential stage. A low current source 51 is connected
between the source terminals connected to each other, and the
ground potential 4, to be a tail current of the input differential
stage. The drain terminal of the NMOS transistor 49 and the NMOS
transistor 50 composing the differential stage is connected to the
drain terminal of PMOS transistor 52 and PMOS transistor 54,
respectively. The drain terminal and gate terminal of the PMOS
transistor 52 and PMOS transistor 54 are shorted out. A common
connection point to short the drain and gate terminals of each of
the PMOS transistor 52 and PMOS transistor 54 is connected to the
gate of PMOS transistor 53 and PMOS transistor 55, respectively, to
compose first and second current mirror circuits. The drain
terminal of the PMOS transistor 55, which is an output of the
second current mirror circuit, is connected to NMOS transistor 56
having a common connection point to short the drain and gate
terminals, and this common connection point is connected to the
gate of NMOS transistor 57, whereby the NMOS transistor 56 and NMOS
transistor 57 compose the third current mirror circuit. The drain
terminal of the NMOS transistor 57, which is an output of the third
current mirror circuit, is connected to the drain terminal of the
PMOS transistor 53, which is an output of the first current mirror
circuit, and the common connection point between them is connected
to an input of a CMOS inverter composed of an NMOS transistor 59
and a PMOS transistor 58.
[0097] A drain common connection point of the NMOS transistor 59
and PMOS transistor 58 becomes an output of the CMOS inverter to be
connected to the output terminal 2. The gate terminal 60 of the
NMOS transistor 50 constituting the differential amplifier of the
input stage is fixed to the reference voltage Vref, and the gate
terminal of the NMOS transistor 49 is a floating node. The input
pulse Vin applied to the input terminal 1 is applied through the
first capacitor 48 to the floating node and undergoes a level shift
by the delay control signal Vc applied to the control terminal 10.
The present embodiment also realizes the control of the delay
occurring between the input and the output by the arrangement
wherein the binarizing position of the input pulse is changed by
the vertical level shift of waveform at the floating node by use of
the delay control signal Vc, as in the first embodiment. The
binarization result at this differential stage becomes a change of
each drain current of the NMOS transistor 49 and NMOS transistor 50
of the differential pair to be input to the first and second
current mirror circuits. Further, the output of the second current
mirror circuit is transmitted as a current change to the third
current mirror circuit to be converted to a voltage at the
connection point between the drain terminal of the PMOS transistor
53 being the output of the first current mirror circuit and the
drain terminal of the NMOS transistor 57 being the output of the
third current mirror circuit, and the voltage is shaped by the CMOS
inverter composed of the NMOS transistor 59 and PMOS transistor 58
to be outputted. This forms the voltage control delay circuit
capable of controlling the delay time of the output pulse by Vc
applied to the control terminal 10.
[0098] In the circuit configuration of the present embodiment, even
if the external noise is superimposed on the power-supply voltage
3, no external noise appears at each node of the circuit, because
each section of the circuit operates in the current mode; thus,
only the thermal noise produced in the circuit appears in the input
waveform binarized by the differential stage, so that the voltage
control delay circuit can be realized with low jitter
characteristics. The circuit is independent of the variable delay
amounts, thereby achieving the high-accuracy low-jitter clock
control in the several GHz band.
[0099] The capacitors 47, 48 and NMOS transistor 49, illustrated in
FIG. 11, can be constructed of a multi-input MOS transistor having
a floating gate electrode. This multi-input MOS transistor can be
achieved by the two-layer polysilicon CMOS processes or the
like.
[0100] FIG. 12 is a conceptual diagram to show the multi-input MOS
transistor having the floating gate electrode.
[0101] A first gate insulating film is provided on a channel
between the source (main electrode) 133 and the drain (main
electrode) 134 spaced from each other on a semiconductor substrate,
and a floating gate electrode (control electrode) 126 of first
polycrystal silicon is formed through the first gate insulating
film. N input gate electrodes 127, 128 to 129 of second polycrystal
silicon are formed through a second gate oxide film on the floating
gate electrode 126. The input gate electrode 127, 128 to 129 is
connected each to input terminal 130, 131 to 132. In this way the
multi-input device can be constructed with capacitive couplings of
C1, C2 to Cn to the floating gate electrode 126.
[0102] When the N input gate electrodes 127, 128 to 129
capacitively coupled with the floating gate electrode 126 are
formed as described, the potential of the floating gate electrode
126 is a weighted average of input voltages applied to the many
input gates. The transistor is turned on or off by whether the
weighted average surpasses the threshold of the transistor. Since
this is similar to the operation of the neuron being a fundamental
constituent unit of the brain of organism, this is called the
neuron MOS (hereinafter referred to as VMOS).
[0103] FIG. 13 is a conceptual drawing to show the VMOS having
capacitive couplings of two inputs, which can be employed in the
present embodiment. The VMOS shown in FIG. 13 is composed of drain
140 and source 141, floating gate electrode 135, input gate
electrodes 136, 137, and input terminals 138, 139 connected to the
input gate electrodes 136, 137. Now, let Cox be a capacitance
established between the floating gate electrode 135 and the input
gate electrode 136, Coy be a capacitance established between the
floating gate electrode 135 and the input gate electrode 137, Vox
be the voltage applied to the input terminal 138, and Voy be the
voltage applied to the input terminal 139. Then the potential
.PHI.F of the floating gate electrode 135 is expressed by the
following equation.
.PHI.F=(Cox.multidot.Vox+Coy.multidot.Voy)/(Cox+Coy)
[0104] As described above, the potential .PHI.F of the floating
gate electrode 135 is the weighted average, and this weighted
averaged is determined by the capacitive coupling ratio of the
voltages.
[0105] [Fifth Embodiment]
[0106] FIG. 14 is a block diagram to show an embodiment of the
delay-locked loop according to the present invention. In FIG. 14,
numeral 204 designates a reference clock to be a reference, and 203
an input clock controlled in the present embodiment. An output
clock 205 passing through a voltage control delay line 200
constructed according to the present invention is phase-compared
with the reference clock 204 by phase comparator 202, and a phase
error between them is supplied through low-pass filter 201 to the
control terminal of the voltage control delay line 200, thus
forming a closed loop. This is a delay-locked loop for
automatically controlling the delay of the voltage control delay
line 200 so as to cancel the phase difference between the input
clock 203 and the output clock 205.
[0107] When the present invention is applied to the voltage control
delay line 200, the circuit can obtain the output clock 205 with
little error from the reference clock.
[0108] [Sixth Embodiment]
[0109] FIG. 15 is a block diagram to show an embodiment of the
self-synchronizing pipeline type digital system of the present
invention.
[0110] In FIG. 15, numeral 300 denotes digital input data, 301 an
input latch, 302 a signal processing logic circuit, 303 an output
latch, 304 a digital output signal, 305, 306 handshake circuits,
and 307 the voltage control delay line according to the present
invention.
[0111] An output from the signal processing logic circuit of a
preceding stage is supplied to the input data 300 to be latched at
the input latch 301. Thereafter, the signal is transferred to the
output latch 303 after a lapse of the delay T.sub.D1 of the signal
processing logic circuit 302. Namely, the timing of latching at the
output latch has a time delay of T.sub.D1 from that at the input
latch 301. If the input latch clock 308 and output latch clock 309
are the same timing, a malfunction will occur, because the timing
of latching at the output latch has the delay of T.sub.D1.
[0112] In order to prevent it, a clock having the same phase as the
input latch clock 308 is input through the voltage control delay
line 307 to the handshake circuit 306, and a signal having the same
phase as it becomes the output latch clock 309. When the delay
amount of the voltage control delay line 307 is set to the delay
amount T.sub.D1 of the signal processing logic circuit by the
control signal 313, the timing can be matched between the input
signal 314 and the output latch clock 309 to the output latch 303.
This can realize a high-speed pipeline synchronization system. The
self-synchronizing pipeline type digital system can be realized by
generating the control signal 313 in accordance with the delay
amount of the signal processing logic circuit 302.
[0113] [Seventh Embodiment]
[0114] FIG. 16 is a block diagram to show an embodiment of the
voltage-controlled oscillator according to the present invention.
Since the same components as those in the circuit of the third
embodiment of the present invention shown in FIG. 10 operate in the
same manner, the description thereof will be omitted herein by
denoting them by the same reference symbols.
[0115] In FIG. 16, numeral 401 (the part surrounded by the dashed
line) represents a unit circuit of the voltage control delay line
which is the basis of the present embodiment. The present
embodiment is an example in which the odd number of unit circuits
401 are connected in series, a common drain terminal of PMOS
transistor 44 and NMOS transistor 45 of the final-stage output is
connected to input terminal capacitor 34, so as to form a positive
feedback loop, and the circuit self-oscillates. An oscillation
response is outputted to the terminal 400. The frequency of this
oscillation is controlled by the control terminals 61, 66, whereby
the voltage-controlled oscillator of low jitter can be
realized.
[0116] [Eighth Embodiment]
[0117] FIG. 17 is a block diagram to show an embodiment of the
phase-locked loop of the present invention. In FIG. 17, numeral 500
denotes a phase comparator, 501 a low-pass filter, and 502 the
voltage-controlled oscillator of Embodiment 7 (FIG. 16) described
above.
[0118] When an input signal of the frequency fO is input to 503,
the phase comparator 500 detects a phase difference thereof from
the output 504 of the voltage-controlled oscillator 502, and the
phase error is input through the low-pass filter 501 to the control
terminal of the voltage-controlled oscillator 502. The low-pass
filter 501 outputs signals of opposite phases by a differential
amplifier or the like, and the signals are input respectively to
the voltage control terminals 61, 66.
[0119] The voltage-controlled oscillator 502 locks the oscillation
frequency of output 504 at the input frequency of the input signal
503 so that the phase error of the phase comparator 500 becomes
.phi.. As described, the phase-locked loop of low jitter can be
formed by utilizing the voltage-controlled oscillator of the
present invention.
[0120] As detailed above, the present invention can provide the
voltage control delay circuit without increase (change) in the
jitter against change of the delay by the circuit configuration
wherein the input pulse and the control signal are added through
the capacitors at the floating node and wherein the input waveform
is level-shifted near the determination threshold of the sense
amplifier without changing the slewing rate of the input pulse; the
present invention can also realize elimination of the dependence of
increase and decrease of the jitter on change in the delay, thus
achieve the low jitter characteristics, enhance the high-frequency
clock synchronization accuracy, and permit higher-speed clock
control.
[0121] Further, the present invention achieves the variable delay
with a wide dynamic range of the delay variable region by the
configuration in which many voltage control delay circuits are
connected in series, and thus the present invention can be applied
to construction of PLL and DLL loops with pulling characteristics
of a wide range and a delay line with a wide variable range. Since
the delay amount can be controlled by the level shift of waveform,
the control characteristics with good linearity can be assured and
accurate control can be performed; therefore, high accuracy and
high speed can be achieved for the systems necessitating the
high-accuracy and low-jitter delay control, such as a clock doubler
circuit of CPU or a delay line for handshake in the
self-synchronizing pipeline signal processing system.
* * * * *