U.S. patent application number 09/901834 was filed with the patent office on 2001-11-15 for multiplexing of trim outputs on a trim bus to reduce die size.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Roohparvar, Frankie Fariborz.
Application Number | 20010042159 09/901834 |
Document ID | / |
Family ID | 22314649 |
Filed Date | 2001-11-15 |
United States Patent
Application |
20010042159 |
Kind Code |
A1 |
Roohparvar, Frankie
Fariborz |
November 15, 2001 |
Multiplexing of trim outputs on a trim bus to reduce die size
Abstract
An integrated circuit includes trim circuitry to control
operations of internal circuitry. The integrated circuit includes
multiplex circuitry for coupling the trim circuitry to internal
circuits via a trim bus in a manner which reduces die area. The
trim circuitry is controlled such that fuses used to control
different level and timing parameters are grouped together and
routed across the integrated circuit using the trim bus and
multiplex circuit.
Inventors: |
Roohparvar, Frankie Fariborz;
(Milpitas, CA) |
Correspondence
Address: |
SCHWEGMAN, LUNDBERG, WOESSNER & KLUTH
P.O. BOX 2938
MINNEAPOLIS
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
22314649 |
Appl. No.: |
09/901834 |
Filed: |
July 10, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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09901834 |
Jul 10, 2001 |
|
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09107062 |
Jun 30, 1998 |
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Current U.S.
Class: |
711/103 ;
365/185.01; 365/185.29; 365/185.33; 365/189.15 |
Current CPC
Class: |
G11C 16/20 20130101 |
Class at
Publication: |
711/103 ;
365/185.01; 365/185.29; 365/185.33; 365/189.01 |
International
Class: |
G06F 012/00 |
Claims
What is claimed is:
1. An integrated circuit comprising: trim circuitry which provides
output signals to control operations of internal circuitry, the
trim circuitry includes a plurality of non-volatile fuse adapted to
provide X trim signals; a trim bus selectively coupled to the trim
circuitry for routing the X trim signals across the integrated
circuit, the trim bus comprising Y interconnect lines, where Y is
greater than X; and multiplex circuitry for coupling a group of Y
trim signals selected from the X trim signals of the trim circuitry
to internal circuits via the trim bus.
2. The integrated circuit of claim 1 further comprising a control
circuit for controlling the multiplex circuitry to select the Y
trim signals from the X trim signals in response to an operational
state of the integrated circuit.
3. The integrated circuit of claim 1 wherein the multiplex
circuitry comprises a plurality of multiplex circuits for coupling
a group of Y trim signals selected from the X trim signals.
4. The integrated circuit of claim 1 wherein the integrated circuit
is a flash memory device and the multiplex circuitry comprises a
first multiplex circuit for coupling a group of Y trim signals
related to controlling word lines during high voltage operations
and settings which relate to sense amplifier operations.
5. The integrated circuit of claim 4 wherein the multiplex
circuitry comprises a second multiplex circuit for coupling a group
of Y trim signals related to sense amplifier outputs.
6. The integrated circuit of claim 1 wherein Y is at least three
times greater than X.
7. A flash memory device comprising: trim circuitry which provides
output signals to control operations of internal circuitry, the
trim circuitry includes a plurality of non-volatile memory cells
adapted to provide X trim signals; a trim bus selectively coupled
to the trim circuitry for routing the X trim signals across the
flash memory device, the trim bus comprising Y interconnect lines,
where Y is greater than X; and multiplex circuitry for coupling a
group of Y trim signals selected from the X trim signals of the
trim circuitry to internal circuits via the trim bus.
8. The flash memory device of claim 7 farther comprising a control
circuit for controlling the multiplex circuitry to select the Y
trim signals from the X trim signals in response to an operational
state of the memory device.
9. The flash memory device of claim 7 wherein the multiplex
circuitry comprises three multiplex circuits.
10. The flash memory device of claim 9 wherein the multiplex
circuitry comprises a first multiplex circuit for coupling a first
group of trim signals related to high voltage operations.
11. The flash memory device of claim 10 wherein the first group of
trim signals comprises: a three bit erase margin signal; a two bit
heal word line signal; a three bit program margin signal; a three
bit program word line signal; and a two bit soft program word line
signal.
12. The flash memory device of claim 9 wherein the multiplex
circuitry comprises a second multiplex circuit for coupling a
second group of trim signals related to sense amplifier
operations.
13. The flash memory device of claim 12 wherein the second group of
trim signals comprises: a two bit soft program margin signal trim
signal; a three bit sense amplifier verification level signal; a
three bit program pulse signal; a two bit heal pulse signal; and a
two bit heal erase pulse signal.
14. The flash memory device of claim 9 wherein the multiplex
circuitry comprises a third multiplex circuit for coupling a third
group of trim signals related to high current operations.
15. The flash memory device of claim 14 wherein the third group of
trim signals comprises: a three bit memory source voltage signal,
used during erase operations; a three bit line voltage signal, used
during programming operations; and a three bit line voltage signal,
used during soft programming operations.
16. The flash memory device of claim 7 wherein the multiplex
circuitry comprises overwrite circuitry for decoupling outputs of
the multiplex circuitry from the trim bus in response to a test
signal.
17. The flash memory device of claim 7 wherein the X trim signals
comprise 34 trim signals and the trim bus comprises nine
interconnect lines.
18. A method of reducing interconnect routing in a flash memory
device using non-volatile trim circuits, the method comprising:
providing trim signals from the non-volatile trim circuits;
selecting a predetermined number of the trim signals based upon an
operating state of the flash memory device; and multiplexing the
selected trim signals on common bus lines provided on the flash
memory device.
19. The method of claim 18 further comprising decoupling outputs of
multiplex circuitry from the common bus lines in response to a test
signal.
20. The method of claim 18 wherein the trim signals are multi-bit
signals.
Description
TECHNICAL FIELD OF THE INVENTION
[0001] The present invention relates generally to static
information storage and in particular the present invention relates
to multiplexing trim circuits.
BACKGROUND OF THE INVENTION
[0002] Also, many processor systems which operate with an
associated memory require a particular memory configuration to
operate properly. By way of example, some systems require a word
length of eight bits and some require sixteen bits. There are
conventional memory systems available which permit the end user to
control the word size to some degree. However, this somewhat
increases the complexity imposed upon the end user of the memory
since the end user must provide the necessary signals to the memory
for controlling the word length. As a further example, most
processor systems look to a certain portion of a memory for boot
data at power on. Such boot data is necessary for the processor to
function in system. The processor will be implemented to expect the
boot data to be at a specific memory address. Some processors
expect the boot data to be at the memory low addresses (bottom
boot) and some processors expect the boot data to be at the memory
high addresses (top boot). In order to provide capabilities for
different types of processor systems, it is possible to produce a
different memory system for each application. However, it is always
desirable to limit the number of different memory types which must
be manufactured.
[0003] It is desirable to have a memory system which can be fully
characterized after fabrication. See for example U.S. Pat. No.
5,627,784 entitled "Memory System Having Non-Volatile Data Storage
Structure for Memory Control Parameters and Method" which is
incorporated herein for a description of a memory which uses
non-volatile data storage units for controlling parameters of the
memory device. These non-volatile data storage units are typically
located in a common area on the integrated circuit and are coupled
to circuitry which is located throughout the integrated circuit.
The interconnect system is both complex and requires substantial
die area.
[0004] For the reasons stated above, and for other reasons stated
below which will become apparent to those skilled in the art upon
reading and understanding the present specification, there is a
need in the art for a memory which uses data storage units for
controlling parameters of the memory device and reduces die area by
multiplexing control signals.
SUMMARY OF THE INVENTION
[0005] The above mentioned problems with routing control signals
and other problems are addressed by the present invention and will
be understood by reading and studying the following
specification.
[0006] In particular, the present invention describes an integrated
circuit comprising trim circuitry which provides output signals to
control operations of internal circuitry. The trim circuitry
includes a plurality of non-volatile fuse adapted to provide X trim
signals. A trim bus is selectively coupled to the trim circuitry
for routing the X trim signals across the integrated circuit. The
trim bus comprises Y interconnect lines, where Y is greater than X.
Multiplex circuitry is provided for coupling a group of Y trim
signals selected from the X trim signals of the trim circuitry to
internal circuits via the trim bus.
[0007] Another aspect of the invention provides a flash memory
device comprising trim circuitry which provides output signals to
control operations of internal circuitry. The trim circuitry
includes a plurality of non-volatile memory cells adapted to
provide X trim signals. A trim bus is selectively coupled to the
trim circuitry for routing the X trim signals across the flash
memory device, the trim bus comprising Y interconnect lines, where
Y is greater than X. Further, multiplex circuitry is provided for
coupling a group of Y trim signals selected from the X trim signals
of the trim circuitry to internal circuits via the trim bus.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 is a block diagram of a flash memory incorporating
the present invention;
[0009] FIG. 2 is a more detailed illustration of the memory of FIG.
1;
[0010] FIG. 3 is a block diagram of an integrated circuit
incorporating the present invention;
[0011] FIG. 4 illustrates one embodiment of a multiplex
circuitry;
[0012] FIGS. 5A and 5B illustrates one embodiment of a high voltage
trim multiplex circuit;
[0013] FIGS. 6A and 6B illustrates one embodiment of a sense/pulse
trim multiplex circuit; and
[0014] FIGS. 7A and 7B illustrates one embodiment of a high current
trim multiplex circuit.
DETAILED DESCRIPTION OF THE INVENTION
[0015] In the following detailed description of the preferred
embodiments, reference is made to the accompanying drawings which
form a part hereof, and in which is shown by way of illustration
specific preferred embodiments in which the inventions may be
practiced. These embodiments are described in sufficient detail to
enable those skilled in the art to practice the invention, and it
is to be understood that other embodiments may be utilized and that
logical, mechanical and electrical changes may be made without
departing from the spirit and scope of the present inventions. The
following detailed description is, therefore, not to be taken in a
limiting sense, and the scope of the present invention is defined
only by the appended claims.
[0016] The present invention provides a memory which multiplexes
trim circuitry that controls parameters of the memory to reduce die
area. Prior to describing these features in greater detail, a brief
description of a flash memory of the present invention is
provided.
Flash Memory
[0017] FIG. 1 illustrates a block diagram of a Flash memory device
100 which is coupled to a flash controller 102. The memory device
has been simplified to focus on features of the memory which are
helpful in understanding the present invention. The memory device
100 includes an array of memory cells 104, FIG. 2. The memory cells
are preferably floating gate memory cells. The array is arranged in
rows and columns, with the rows arranged in blocks. The blocks
allow memory cells to be erased in large groups. Data, however, is
stored in the memory array in small data groups (byte or group of
bytes) and separate from the block structure. Erase operations are
performed on a large number of cells in parallel.
[0018] An x-decoder 108 and a y-decoder 110 are provided to decode
address signals provided on address lines A0-Ax 112. Address
signals are received and decoded to access the memory array 104. An
address buffer circuit 106 is provided to latch the address
signals. A y-select circuit 116 is provided to select a column of
the array identified with the y-decoder 110. Sense amplifier and
compare circuitry 118 is used to sense data stored in the memory
cells and verify the accuracy of stored data. Data input 120 and
output 122 buffer circuits are included for bi-directional data
communication over a plurality of data (DQ) lines with the
microprocessor 102. Command control circuit 114 decodes signals
provided on control lines from the microprocessor. These signals
are used to control the operations of the memory, including data
read, data write, and erase operations. Input/output control
circuit 124 is used to control the input and output buffers in
response to some of the control signals. The flash memory includes
a charge pump circuit 123 which generates a Vpp voltage used during
programming of the memory cells and other internal operations.
During write operations, Vpp is coupled to the memory cells for
providing appropriate write operation programming power. Charge
pump designs are known to those skilled in the art, and provides
power which is dependant upon an externally provided supply voltage
Vcc.
[0019] Latch circuitry 125 is provided in the memory for latching
locations of memory cells which are not successfully written to
during a memory write operation. The latch circuitry allows rewrite
operations, as described below, to be performed after a plurality
of separate memory write operations are performed.
[0020] As stated above, the Flash memory of FIGS. 1 and 2 has been
simplified to facilitate a basic understanding of the features of
the memory. A more detailed understanding of Flash memories is
known to those skilled in the art. It will be appreciated that more
than one Flash memory can be included in various package
configurations. For example, Flash memory cards can be manufactured
in varying densities using numerous Flash memories.
Trim Circuitry
[0021] FIG. 3 illustrates a block diagram of an integrated circuit
200, such as a memory device, incorporating the present invention.
The integrated circuit includes trim circuitry 202 which provides
output signals to control operations of internal circuitry. Because
the trim circuitry includes non-volatile memory it is best suited
for use in memory circuits and the trim circuitry is fabricated in
close proximity to a memory array. The integrated circuit includes
multiplex circuitry 204 for coupling the trim circuitry to internal
circuits 206 via a trim bus and control 208 in a manner which
reduces die area. That is, trim circuitry is controlled such that
fuses used to control different level and timing parameters are
grouped together and routed across the integrated circuit using the
trim bus and multiplex circuit.
[0022] A description of a memory device with control parameters
using non-volatile storage is described in U.S. Pat. No. 5,627,784
issued May. 6, 1997 and entitled "MEMORY SYSTEM HAVING NON-VOLATILE
DATA STORAGE STRUCTURE FOR MEMORY CONTROL PARAMETERS AND METHOD".
U.S. Pat. No. 5,682,345 issued Oct. 28, 1997, entitled
"NON-VOLATILE DATA STORAGE UNIT AND METHOD OF CONTROLLING SAME"
describes a non-volatile unit for storing control parameters. Each
of the above references are incorporated herein, and provide a
description of the trim fuses and there intended uses.
[0023] Referring to FIG. 4, control signals from the trim circuitry
are routed using multiplex circuits 210, 212 and 214. The control
signals in the integrated circuit memory device includes a three
bit bus, ErsMarg<3:1>, used to adjust the level of the
current of the sense amplifier for verifying if a cell is erased
properly. A two bit bus, HealWL<2:1>, is used to adjust a
voltage level of wordlines during a Heal operation after an erase
cycle. A three bit bus, PgMarg<3:1>, is used to adjust the
level of the current of the sense amplifier for verifying if a cell
is programmed properly. A three bit bus, PgmWL<3:1>, is used
to adjust the level of the voltage on a wordline during programming
operation. Likewise, SoftPWL<2:1> is a two bit bus used to
adjust the level of the voltage on a wordline during soft
programming operation. This operation is used to recover from
over-erased cells.
[0024] This first group of trim fuse outputs are all associated
with voltages related to wordlines during high voltage operations
and settings which relate to sense amplifier operations. It is
important to note that these trim settings are not required at the
same time. For example, high voltage operations may be performed
first, and then verification operations are performed to determine
if an operation was successful using the sense amplifiers.
Therefore, these fuse element outputs are placed on the same
bus.
[0025] A second group of trim circuit outputs include a two bit
bus, SPMarg<2:1>, used to set soft programming current levels
in the sense Amplifiers. A three bit bus, SenMarg<3:1>,
includes output of three fuse elements that are used to set the
level of verification of the sense amplifier during a normal read
operation. A three bit bus, PgmPls<3:1>, provides output of
three fuse elements that are used to set the duration of the
programming pulse. Likewise, a HealPls<2:1> bus provides
output of two fuse elements that are used to set the duration of a
heal pulse during a heal operation performs after an erase cycle to
recover from over-erasure. Finally, HErPls<2:1> provides
output of two fuse elements that are used to set the duration of
the erase operation after a Heal operation to recover any
inadvertently reduced margin of some erased cells. The above
described second set of trim element signals are mostly related to
sense amplifier outputs.
[0026] The third group of trim signals include a three bit bus,
ErsSrc<3:1>, used to set a voltage level on the sources of a
memory cells being erased. A three bit bus, PgmBL<3:1>, is
provided to set a voltage level on bit lines during a programming
operation, and a three bit bus, SoftPBL<3:1>, is provided to
set a voltage level on the bit lines during a soft programming
operation.
[0027] The multiplex circuitry 210, 212 and 214 of one embodiment
of the present invention routes the 34 control signals from the
trim circuitry over nine bus lines. Thus, where prior integrated
circuits required 34 metal lines routed around the integrated
circuit from the trim location to control different circuits, the
present invention uses nine lines.
[0028] FIGS. 5A and 5B illustrate one embodiment of a high voltage
trim multiplex circuit 210 used with the above described first
signal group. Seven control signals are used to couple the trim
fuses to an internal bus. The signals include an ActiveHV to
indicate when the memory is performing High voltage operations
within a program or erase operation. A HealCyc signal indicating
the performance of a Heal cycle of a memory erase operation. The
Program Margin Enable signal, PgMargE, signifies that any reading
of the memory array should be performed to verify that the cell has
sufficient programming margin. A PgmOp signal is used to indicated
that the memory is either in programming mode or pre-programming
mode within an erase operation. A SoftPgm signal indicates the
execution of a soft programming cycle used in over-erased memory
cell threshold recovery. An ErsCyc signal is provided which
signifies that the memory is in a cell erase cycle within an erase
operation. Finally, a TstOvrWrt signal is used to overwrite the
output of all the fuse elements to a known state.
[0029] The multiplex circuitry of FIG. 5A couples either the
PgmvWL<3:1>, HealWL<2:1>, SoftPWL<2:1>,
PgMarg<3:1>, or ErsMarg<3:1> trim output signal to the
high voltage bus. Each of the trim output signals is coupled to the
bus via isolation devices 220, or transistors, controlled by logic
circuits 222. The logic expression used to activate the isolation
devices for the PgmWL trim signals is:
{overscore ((PgmOP+ErsCyc)*ActiveHv*)}{double overscore
(Softpgm)}
[0030] The logic expression used to activate the isolation devices
for the HealWL trim signals is:
{overscore (ActiveHV*Healcyc)}
[0031] The logic expression used to activate the isolation devices
for the SoftPWL trim signals is /SoftPgm. The logic expression used
to activate the isolation devices for the PgMarg trim signals
is:
{double overscore ((ActiveHV+Softpgm))}{overscore (*PgmargE)}
[0032] The logic expression used to activate the isolation devices
for the ErsMarg trim signals is:
{double overscore ((ActiveHV+Softpgm))}{overscore (*)}{double
overscore (PgmargE)}
[0033] Because the HealWL<2:1> and SoftPWL<2:1> trim
signals are two bits, while the bus is three bits, one line of the
bus is coupled to ground by the appropriate isolation device. The
multiplex also includes a test overwrite circuit 224 which uses the
TstOvrWrt signal to couple the bus lines to a trim bus. Two
coupling logic circuits are illustrated; one using a NOR gate 226
and one using a NAND gate 228. When the TstOvrWrt signal is in a
low state, the bus lines are coupled to the trim bus. When the
TstOvrWrt signal is in a high state, the trim bus connections are
coupled low.
[0034] FIGS. 6A and 6B illustrate one embodiment of a sense/pulse
trim multiplex circuit 212 used with the above described second
signal group. Logic circuit 230 is provided to couple the signal
group to bus via isolation devices 231. In addition to some of the
above control signals, an additional control signal, SPMargE, is
used to indicate that currents read out of memory cells are for
soft program margin purposes. When the memory device is in an
active high voltage mode, the soft program margin signal trim
signals, SPMarg<2:1>, and the sense amplifier verification
level, SenMarg<3:1>, are not coupled to the sense/pulse bus.
Conversely, during the high voltage operation, the PgmOp, HealCyc,
and ErsCyc signals control the coupling of PgmPls<3:1>,
HealPls<2:1>, and HerPls<2:1> trim signals to the
sense/pulse bus, respectively.
[0035] The multiplex of FIG. 6B also includes a test overwrite
circuit 232 which uses the TstOvrWrt signal to couple the bus lines
to a trim bus. Bus lines one and three are coupled through a NAND
gate 234, and bus line 2 is coupled though a NOR gate 236. A
latching inverter 240 is provided to latch the third bus line.
[0036] FIGS. 7A and 7B illustrates a multiplex circuit 214 used to
couple either PgmBL<3:1>, ErsSrc<3:1>, or
SoftPBL<3:1> to a three bit high current bus. The multiplex
circuitry couples PgmBL<3:1> to the three bit bus in response
to a low ErsCyc and a low Softpgm signals via NOR gate 241 and
transfer circuitry 242. The ErsSrc<3:1> signal is coupled to
the bus when the ErsCyc signal is high via transfer circuit.
Finally, the SoftPBL<3:1> is coupled to the bus when the
Softpgm signal is high using transfer circuit. The multiplex of
FIG. 7B also includes a test overwrite circuit 244 which uses the
TstOvrWrt signal. Bus lines 1 and 3 (HCTrim<3,1>) are coupled
through NAND gate 246, and bus line 2 is coupled though NOR gate
248. Thus, when the TstOvrWrt signal is high bus line 2 is coupled
low, and bits lines 1 and 3 are coupled high. When the TstOvrWrt
signal is low, the bus data is not over written.
Conclusion
[0037] An integrated circuit has been described which includes trim
circuitry to control operations of internal circuitry. Because the
trim circuitry includes non-volatile memory it is well suited for
use in memory circuits. The integrated circuit includes multiplex
circuitry for coupling the trim circuitry to internal circuits via
a trim bus in a manner which reduces die area. The trim circuitry
is controlled such that fuses used to control different level and
timing parameters are grouped together and routed across the
integrated circuit using the trim bus and multiplex circuit.
[0038] Although specific embodiments have been illustrated and
described herein, it will be appreciated by those of ordinary skill
in the art that any arrangement which is calculated to achieve the
same purpose may be substituted for the specific embodiment shown.
This application is intended to cover any adaptations or variations
of the present invention. Therefore, it is manifestly intended that
this invention be limited only by the claims and the equivalents
thereof.
* * * * *