U.S. patent application number 09/832942 was filed with the patent office on 2001-11-15 for method of depositing dielectric.
Invention is credited to Wiggins, Claire Louise.
Application Number | 20010041460 09/832942 |
Document ID | / |
Family ID | 9889853 |
Filed Date | 2001-11-15 |
United States Patent
Application |
20010041460 |
Kind Code |
A1 |
Wiggins, Claire Louise |
November 15, 2001 |
Method of depositing dielectric
Abstract
This invention relates to a method of depositing dielectric on a
semiconductor substrate to form part of a capacitor. The method
includes reactive sputtering a metal oxide layer from a target of
metal onto the substrate wherein the support is biased to induce a
DC voltage across the depositing dielectric as it forms. The
voltage may be in the range of 200-300V.
Inventors: |
Wiggins, Claire Louise;
(Grantham, GB) |
Correspondence
Address: |
JONES VOLENTINE, L.L.C.
Suite 150
12200 Sunrise Valley Drive
Reston
VA
20191
US
|
Family ID: |
9889853 |
Appl. No.: |
09/832942 |
Filed: |
April 12, 2001 |
Current U.S.
Class: |
438/785 ;
257/E21.274; 438/466 |
Current CPC
Class: |
C23C 14/5853 20130101;
H01L 21/02323 20130101; C23C 14/5826 20130101; H01L 21/02266
20130101; C23C 14/0036 20130101; H01L 21/02183 20130101; H01L
21/31604 20130101; H01L 21/0234 20130101; C23C 14/083 20130101;
H01G 4/1254 20130101 |
Class at
Publication: |
438/785 ;
438/466 |
International
Class: |
H01L 021/326; H01L
021/479; H01L 021/31 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 14, 2000 |
GB |
0009139.7 |
Claims
1. A method of depositing dielectric on a semiconductor substrate
on a support to form part of a capacitor including reactive
sputtering a metal oxide layer from a target of the metal onto the
substrate characterised in that the support is biased to induce a
DC voltage across the depositing dielectric as it forms.
2. A method as claimed in claim 1 wherein the induced voltage is in
the range 200 to 300 volts.
3. A method as claimed in claim 1 or claim 2 wherein the support is
biased by means of an RF or pulsed DC power supply.
4. A method as claimed in claim 1 wherein the target is biased by
an RF or pulsed DC power supply.
5. A method as claimed in any one of the preceding claims further
including plasma oxidation of the oxide after or during
deposition.
6. A method as claimed in any one of the preceding claims wherein
the dielectric is deposited on a first electrode and discrete
second electrodes are deposited on the upper surface to define a
plurality of capacitors.
7. A method as claimed in claim 6 wherein the area of each second
electrode is less than 0.01 cm.sup.2.
8. A method as claimed in any one of the preceding claims wherein
the metal oxide is Tantalum Pentoxide.
Description
[0001] This invention relates to a method of depositing dielectric
on a semiconductor substrate to form part of a capacitor.
[0002] In order to reduce the size of capacitors required in
semiconductor devices the industry is moving towards the use of
high dielectric constant (k) materials. One particular favoured
material is Tantalum Pentoxide (Ta.sub.2O.sub.5) is a particularly
promising candidate with a dielectric constant of about 25. This
material can be deposited by various chemical and physical means,
but the most convenient for semiconductor work is active visual
vapour deposition. This process is well known in general and is for
example described in U.S. Pat. No. 5,111,355. From this it will be
seen that Tantalum is one of a class of materials in which the
oxide forms on the surface of the metal target and is sputtered
from the target, in contrast to other reactive processes where the
oxide or nitride is formed in flight or on the surface of the
substrate. Possibly because of this factor problems can arise from
a relatively high leakage current through the deposited layer. As
will be seen in U.S. Pat. No. 5,872,696 it is thought that this is
in part due to pin holes and in part due to the presence of
un-oxidised Tantalum atoms within the layer linking to form a
leakage path. In that Patent a reduction of the leakage current is
achieved by further anodisation of the Tantalum Pentoxide. This
reduces the pinholes and/or the conductive paths sufficiently to
allow large area capacitors to be formed. However, with small area
capacitors relatively high leakage currents (of the order of
>1.sup.-6 amps when 5 volts is applied against a layer of 100
.ANG. thickness of Tantalum Pentoxide).
[0003] The present invention consists in a method of depositing
dielectric on a semiconductor substrate on a support to form part
of a capacitor including reactive sputtering the metal oxide layer
from a target of the metal onto the substrate characterised in that
the support is bias to induce a DC voltage across the deposited
dielectric as it forms.
[0004] The induced voltage may be in the range of 200-300 volts and
to achieve this the support may be bias by means of an RF or pulse
DC power supply. The target may also be bias by an RV or pulse DC
power supply, the pulsed supply is preferred.
[0005] The method may further include the step of plasma oxidation
of the deposited oxide after or during deposition.
[0006] The dielectric layer may be deposited on the first electrode
and discrete second electrodes may be deposited on the upper
surface to define a plurality of capacitors. The area of each
second electrode may be less than 0.01 cm.sup.2 and capacitors have
been formed with second electrode areas of 0.008 cm.sup.2.
[0007] In a preferred embodiment the metal oxide is Tantalum
Pentoxide, but it is believed that the method will show
improvements with any metal oxide which is reactive sputtered from
the target.
[0008] Although the invention has been defined above it is to be
understood it includes any inventive combination of the features
set out above or in the following description.
[0009] The invention may be performed in various ways and a
specific embodiment will now be described, by way of example with
reference to the accompanying drawing which is a schematic
cross-section through an array of capacitors formed in accordance
with the invention.
[0010] The process of reactive sputtering is well known and is, for
example, described at pages 48 to 53, pages 107 to 109 in Thin Film
Processes edited by John L. Vossen and Werner Kern and published
1978 by Academic Press, Inc. This disclosure is herein incorporated
by reference. As has already been mentioned U.S. Pat. No. 5,872,696
specifically describes the reactive sputtering of Tantalum
Pentoxide.
[0011] As can be seen in the FIGURE the Applicants deposit a first
electrode 10, (typically of Titanium Nitride) onto the surface of a
substrate 11 and onto this they reactively sputter Tantalum
Pentoxide 12 to form a dielectric layer. Second electrodes are then
formed by depositing dots 13 of Titanium Nitride through an
aperture mask. Each dot then defines a single capacitor formed by
the respective dot 13 the underlying area of the first electrode 10
and the intermediate portion of dielectric 12.
[0012] In the Applicants set up the target electrode for the
reactive deposition was powered by pulsed DC.
[0013] Two experiments were then run on identical ("same lot")
wafers using the following conditions except that in one part of
the experiment the support on which the substrate sits was not
biased, whereas in the second experiment it was biased as
indicated:
[0014] Test Structure
[0015] Lower electrode TiN
[0016] Dielectric Ta.sub.2O.sub.5 generally 100 .ANG. to 100 .ANG.
thick, typically 500 .ANG. through different applications may
require 1 micron thickness and the result reported below was for
100 .ANG.. In general thinner layers are preferred.
[0017] Upper electrode For testing of the dielectric a TiN layer is
deposited through an aperture mask to define capacitance dots of
area 0.008 cm.sup.2.
[0018] Experimental Process
[0019] Reactive Deposition of 600 .ANG. Tantalum Pentoxide Target
power 2 kw DC, pulsed at 1000 kHz with a pulse width of 4000
nanoseconds
1 Argon flow 50 sccm Oxygen flow 40 sccm Platen temperature
300.degree. C.
[0020] Platen bias power 600 W 13.65 mhz RF inducing 270 v dc
bias
[0021] Process time 150 seconds
[0022] Wafer size: 150 mm silicon
[0023] Plasma Oxidation of the Tantalum Pentoxide Deposited as
above
[0024] Oxygen flow 200 sccm
[0025] Inductive coil power 500 watts, `soft started` at 400 watts
then increased 1 minute process Power density is an important
characteristic and for different size wafers and chambers other
power levels would be appropriate and can be determined
experimentally.
[0026] The capacitance dots 13 were probed under the application of
5 volts and the leakage current measured. The batch of capacitors
which had been formed without biasing the support had a leakage
current >1.sup.-6 amps whereas those formed under the bias
conditions had a leakage current of <1.sup.-8 amps. In each case
the thickness of the Tantalum Pentoxide was 100 .ANG..
[0027] It will be noted that in each case the anodising step of
U.S. Pat. No. 5,872,696 was carried out, but the leakage current
was substantially improved under bias conditions. This strongly
suggests that quite a different process is occurring in the
Applicants invention and it is believed that this may result in an
improved density in the deposited layer. It will be appreciated
that the orders of magnitude improvement in leakage current means
that the Applicants have found a way of significantly improving the
performance of capacitors of this type.
* * * * *