U.S. patent application number 09/900148 was filed with the patent office on 2001-11-15 for semiconductor memory device and method of manufacturing the same.
Invention is credited to Aoki, Masami.
Application Number | 20010041405 09/900148 |
Document ID | / |
Family ID | 12757693 |
Filed Date | 2001-11-15 |
United States Patent
Application |
20010041405 |
Kind Code |
A1 |
Aoki, Masami |
November 15, 2001 |
Semiconductor memory device and method of manufacturing the
same
Abstract
A semiconductor memory device comprises a memory cell region
having an array of plurality of memory cells, and a peripheral
circuit region to which a bit line connected to a predetermined
number of the memory cells in the memory cell region is extended
and connected, the bit line in the memory cell region and the bit
line in the peripheral circuit region having substantially the same
upper surface height.
Inventors: |
Aoki, Masami; (Fishkill,
NY) |
Correspondence
Address: |
BANNER & WITCOFF
1001 G STREET N W
SUITE 1100
WASHINGTON
DC
20001
US
|
Family ID: |
12757693 |
Appl. No.: |
09/900148 |
Filed: |
July 9, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09900148 |
Jul 9, 2001 |
|
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09030248 |
Feb 25, 1998 |
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Current U.S.
Class: |
438/254 ;
257/306; 257/775; 257/E21.583; 257/E21.657; 257/E21.658;
257/E21.66; 257/E27.087; 438/211; 438/241 |
Current CPC
Class: |
H01L 27/10894 20130101;
H01L 27/10885 20130101; H01L 27/10811 20130101; H01L 27/10888
20130101; H01L 2924/0002 20130101; H01L 21/7684 20130101; H01L
2924/00 20130101; H01L 2924/0002 20130101 |
Class at
Publication: |
438/254 ;
257/306; 257/775; 438/241; 438/211 |
International
Class: |
H01L 021/8242; H01L
021/8238; H01L 027/108; H01L 029/76; H01L 029/94; H01L 031/119;
H01L 023/48; H01L 023/52; H01L 029/40 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 28, 1997 |
JP |
9-046810 |
Claims
1. A semiconductor memory device comprising: a memory cell region
having an array of plurality of memory cells; and a peripheral
circuit region to which a bit line connected to a predetermined
number of the memory cells in the memory cell region is extended
and connected; the bit line in the memory cell region and the bit
line in the peripheral circuit region having substantially the same
upper surface height.
2. The semiconductor memory device according to claim 1, further
comprising plug electrodes through which the bit line is connected
to the memory cell region and the peripheral circuit region, the
plug electrodes being connected respectively to the memory cell
region and the peripheral circuit region each via a barrier layer
formed of a first conducting material.
3. The semiconductor memory device according to claim 2, further
comprising contact electrodes respectively interposed between the
plug electrodes and the bit line, a periphery of each of the
contact electrodes being covered with SiN.
4. The semiconductor memory device according to claim 1, wherein
the memory cell region has a plurality of capacitors each having a
storage electrode, a plate electrode, and a capacitor insulating
film interposed therebetween, the capacitor insulating film being
extending to the peripheral circuit region.
5. The semiconductor memory device according to claim 2, wherein
the memory cell region has a plurality of MOS transistors and an
insulating film formed on the MOS transistors, and the barrier
layer is formed of the first conducting material along an inner
wall of a contact hole formed in the insulating film.
6. The semiconductor memory device according to claim 2, wherein
one of the plug electrodes is formed of the barrier layer and a
second conducting film buried in the contact hole with the barrier
layer interposed therebetween.
7. The semiconductor memory device according to claim 6, further
comprising contact electrodes formed on each space between the plug
electrodes and bit line.
8. A semiconductor memory device comprising: a semiconductor
substrate; a plurality of MOS transistors respectively formed in a
memory cell region and in a peripheral circuit region on said
semiconductor substrate, each of the MOS transistors having
source/drain regions; a first interlayer insulating film formed
over an entire surface of the semiconductor substrate including the
MOS transistors; a plurality of capacitors formed in a plurality of
first contact holes which are formed in the first interlayer
insulating film of the memory cell region in such a way that one of
the source/drain regions is exposed therein, each of the capacitors
being formed at least on an inner wall portion of a corresponding
one of the first contact holes and having a storage electrode
formed of a first conducting material and a plate electrode formed
on the storage electrode with a capacitor insulating film
interposed therebetween; a first plug electrode formed in each of a
plurality of second contact holes formed in the first interlayer
insulating film of the memory cell region in such a way that the
other of the source/drain regions is exposed therein, the first
plug electrode being formed by burying a second conducting material
in each of the second contact holes interposing a barrier layer of
a first conducting material formed at least on an inner wall of
each of the second contact holes; a second plug electrode formed in
each of a plurality of third contact holes formed in the first
interlayer insulating film of the peripheral circuit region in such
a way that either one of the source/drain regions is exposed
therein, the second plug electrode being formed by burying the
second conducting material in each of the third contact holes
interposing the barrier layer of the first conducting material
formed at least on an inner wall of each of the third contact
holes; a second interlayer insulating film formed over an entire
surface of the first interlayer insulating film; a first and a
second contact electrode respectively formed on the first and the
second plug electrode, in a fourth and a fifth contact hole formed
in the second interlayer insulating film in such a way that the
first and the second plug electrode are exposed therein,
respectively; and a plurality of bit lines respectively connected
to the first and the second contact electrode, formed on the second
interlayer insulating film.
9. The semiconductor memory device according to claim 8, wherein a
bit line connecting portion in the peripheral circuit region is
formed of the second plug electrode and the second contact
electrode.
10. The semiconductor memory device according to claim 8, wherein
the plate electrode is formed only along an surface of the
capacitor insulating film.
11. The semiconductor memory device according to claim 8, wherein
each of the fourth and the fifth contact hole has a side-wall
insulating film formed on an inner wall thereof.
12. A method of manufacturing a semiconductor memory device
comprising the steps of: forming MOS transistors both in a memory
cell region and in a peripheral circuit region formed on a
semiconductor substrate; forming an interlayer insulating film over
an entire surface of the semiconductor substrate including the MOS
transistors; and forming a barrier layer of a bit line connecting
portion and a storage electrode of a capacitor by use of the same
conducting material simultaneously in the interlayer insulating
film.
13. The method of manufacturing a semiconductor device according to
claim 12, wherein the step of forming the storage electrode
includes a step of forming a layer of a first conducting material
at least along an inner wall of a contact hole for the storage
electrode which is connected to one of source/drain regions of each
of the MOS transistors.
14. The method of manufacturing a semiconductor memory device
according to claim 13, wherein the step of forming the barrier
layer include a step of forming a layer of the first conducting
material at least along an inner wall of contact holes for a first
and a second plug electrode formed in the interlayer insulating
film and connecting to the other of the source/drain regions of
each of the MOS transistors.
15. The method of manufacturing a semiconductor memory device
according to claim 12, further comprising a step of forming a
plurality of bit lines each to be connected to the barrier layer in
the interlayer insulating film in such a way that an upper surface
of each of the bit lines is set at the same height, after the step
of forming the barrier layer of the bit line connecting
portion.
16. A method of manufacturing a semiconductor memory device
comprising the steps of: forming MOS transistors both in a memory
cell region and in a peripheral circuit region formed on a
semiconductor substrate; forming a first interlayer insulating film
over an entire surface of the semiconductor substrate after the
step of forming the MOS transistors; flattening a surface of the
first interlayer insulating film; removing the first interlayer
insulating film selectively to form a contact hole for a storage
electrode and contact holes for a first and a second plug
electrode; forming a storage electrode and a barrier layer by use
of a first conducting material at least on inner walls of the
contact holes for the first and the second plug electrode,
respectively; burying a dummy film in the contact holes for the
first and the second plug electrode; removing the dummy film buried
in the contact holes for the first and the second plug electrode
other than the dummy film buried in the contact hole for the
storage electrode; forming the first and the second plug electrode
by burying a second conducting material in the contact holes for
the first and the second plug electrode from which the dummy film
is removed; removing the dummy film buried in the contact hole for
the storage electrode; forming a capacitor insulating film along an
surface of the storage electrode; forming a capacitor by providing
a plate electrode in the contact hole for the storage electrode
interposing the capacitor insulating film; forming a second
interlayer insulating film over an entire surface of the substrate;
flattening an surface of the interlayer insulating film; removing
the second interlayer insulating film selectively to form contact
holes for a first and a second contact electrode to be connected to
the first and the second plug electrode, respectively; and forming
a bit line on the second interlayer insulating film simultaneously
with the first and the second contact electrode which connect the
bit line to the first and the second plug electrode.
17. The method of manufacturing a semiconductor memory device
according to claim 16, wherein a bit line connecting portion in the
memory cell region is formed of the first plug electrode and the
first contact electrode.
18. The method of manufacturing a semiconductor memory device
according to claim 16, wherein a bit line connecting portion in the
peripheral circuit region is formed of the second plug electrode
and the second contact electrode.
19. The method of manufacturing a semiconductor memory device
according to claim 16, wherein the plate electrode is provided only
along an surface of the capacitor insulating film.
20. The method of manufacturing a semiconductor memory device
according to claim 16, further comprising a step of forming a
side-wall insulating film on each of inner walls of the contact
holes for the first and the second contact electrode after the
contact holes for the first and the second contact electrode are
formed.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a semiconductor memory
device and a method of manufacturing the same. More specifically,
the present invention relates to a semiconductor device for-DRAMs
(Dynamic Random Access Memories) which includes a memory cell array
and a peripheral circuit mounted together on the same chip.
[0002] Nowadays, memory cells (DRAM cells) having a stacked
capacitor have been developed for use in a 256M bit DRAM and an IG
bit DRAM. In most of the DRAM cells, the capacitor is formed after
a bit line is formed. Such a structure is called
"capacitor-over-bit-line (COB) structure".
[0003] The COB structure has a merit in that the capacitor can
occupy a large area since the capacitor is not influenced by the
formation of the bit line. However, the COB has demerits in that a
parasitic capacitance to the bit line is large, and in that it is
difficult to form the bit line by use of Al since a self-aligning
process is required for the bit line formation.
[0004] Because of the aforementioned demerits, the COB structure is
not well adapted to the chip (which will be a main-current DRAM
chip) consisting of a memory cell array and a peripheral logic
circuit (hereinafter referred to as "peripheral circuit") mounted
together on the same chip.
[0005] On the other hand, if another cell having a
bitline-over-capacitor structure (a capacitor is formed before the
bit line) is employed, the aforementioned problems can be overcome.
However, if the chip having a memory cell array and a peripheral
circuit mounted together thereon, is formed by using the
bit-line-over-capacitor structure, a stepped portion is undesirably
formed on an upper surface of an interlayer insulating film between
the memory cell region and the peripheral circuit region depending
upon the presence/absence of a capacitor.
[0006] FIGS. 1A-1C show an example of a DRAM having a memory cell
array and a peripheral circuit mounted on the same chip and formed
by using a cell having the bit-line-over-capacitor structure. In
the DRAM shown in these figures, a memory cell region is shown on
the left side (101a) of the device and a peripheral circuit region
is shown on the right side (101b).
[0007] To describe the DRAM more specifically referring to FIG. 1C,
a device formation region is surrounded by a field oxidation film
102 which is formed on a silicon substrate 101. In the device
formation region, a plurality of MOS transistors each consisting of
a gate electrode 103 and source/drain regions 104, are formed. The
memory cell region 101a is thus formed. In the memory cell region,
a stacked capacitor is formed. The stacked capacitor is formed of a
storage node electrode 105, a capacitor insulating film 106, and a
plate electrode 107. The storage node electrode 105 is electrically
connected to one of the source/drain regions 104 of each of the MOS
transistors.
[0008] Corresponding to the other source/drain region 104, a bit
line contact 110 is formed which is connected to a bit line 109
formed on an interlayer insulating film 108.
[0009] In the peripheral circuit region 101b, a gate electrode
contact 111 to be connected to the bit line 109 is formed in
correspondence with the gate electrode 103 formed on the field
oxidation film 102.
[0010] Furthermore, a diffusion layer contact 112 to be connected
to the bit line 109 is formed corresponding to one of the
source/drain regions 104 of the MOS transistor which is formed on
the field region.
[0011] However, the DRAM thus constructed has a problem. Since the
interlayer insulating film 108 is formed over an entire surface
after the stacked capacitor is formed in the memory cell portion,
as shown in FIG. 1B, a stepped portion 120 is formed in the upper
surface of the interlayer insulating film 108 between the memory
cell region 101a and the peripheral circuit region 101b depending
upon the presence or absence of the capacitor (see FIG. 1C). It is
therefore difficult to pattern the bit line 109 with a high
accuracy. As mentioned above, the DRAM of a the
bit-line-over-capacitor structure has a problem in that the memory
cell region is not well-matched with the peripheral circuit
region.
BRIEF SUMMARY OF THE INVENTION
[0012] An object of the present invention is to provide a
semiconductor memory device including a memory cell region and a
peripheral circuit region mounted on the same chip, both being
matched excellently without a stepped portion which is usually
formed in an upper interlayer insulating film between the memory
cell region and the peripheral circuit region depending upon the
presence and absence of a capacitor.
[0013] To attain the object, the semiconductor memory device
according to a first aspect of the present invention comprises:
[0014] a memory cell region having an array of a plurality of
memory cells; and
[0015] a peripheral circuit region to which a bit line connected to
a predetermined number of the memory cells of the memory cell
region is extended and connected;
[0016] the bit line in the memory cell region and the bit line in
the peripheral circuit region having substantially the same upper
surface height.
[0017] The semiconductor memory device according to a second aspect
of the present invention comprises
[0018] a semiconductor substrate;
[0019] a plurality of MOS transistors respectively formed in a
memory cell region and in a peripheral circuit region on the
semiconductor substrate, each of the MOS transistors having
source/drain regions;
[0020] a first interlayer insulating film formed over an entire
surface of the semiconductor substrate including the MOS
transistors;
[0021] a plurality of capacitors formed in a plurality of first
contact holes which are formed in the first interlayer insulating
film of the memory cell region in such a way that one of the
source/drain regions is exposed therein, each of the capacitors
being formed at least on an inner wall portion of a corresponding
one of the first contact holes and having a storage electrode
formed of a first conducting material and a plate electrode formed
on the storage electrode with a capacitor insulating film
interposed therebetween;
[0022] a first plug electrode formed in each of a plurality of
second contact holes formed in the first interlayer insulating film
of the memory cell region in such a way that the other of the
source/drain regions is exposed therein; the first plug electrode
being formed by burying a second conducting material in each of the
second contact holes interposing a barrier layer of a first
conducting material formed at least on an inner wall of each of the
second contact holes;
[0023] a second plug electrode formed in each of a plurality of
third contact holes formed in the first interlayer insulating film
of the peripheral circuit region in such a way that either one of
the source/drain regions is exposed therein, the second plug
electrode being formed by burying the second conducting material in
each of the third contact holes interposing a barrier layer of the
first conducting material formed at least on an inner wall of each
of the third contact holes;
[0024] a second interlayer insulating film formed over an entire
surface of the first interlayer insulating film;
[0025] a first and a second contact electrode respectively formed
on the first and the second plug electrode, in a fourth and a fifth
contact hole formed in the second interlayer insulating film in
such a way that the first and the second plug electrode are exposed
therein, respectively; and
[0026] a plurality of bit lines respectively connected to the first
and the second contact electrode, and formed on the second
interlayer insulating film.
[0027] The method of manufacturing a semiconductor memory device
according to a third aspect of the present invention comprises the
steps of:
[0028] forming MOS transistors both in a memory cell region and in
a peripheral circuit region formed on a semiconductor
substrate;
[0029] forming an interlayer insulating film over an entire surface
of the semiconductor substrate including the MOS transistors;
and
[0030] forming a barrier layer of a bit line connecting portion and
a storage electrode of a capacitor by use of the same conducting
material simultaneously in the interlayer insulating film.
[0031] The method of manufacturing a semiconductor memory device
according to a fourth aspect of the present invention comprises the
steps of:
[0032] forming MOS transistors both in a memory cell region and in
a peripheral circuit region formed on a semiconductor
substrate;
[0033] forming a first interlayer insulating film over an entire
surface of the semiconductor substrate after the step of forming
the MOS transistors;
[0034] flattening a surface of the first interlayer insulating
film;
[0035] removing the first interlayer insulating film selectively to
form a contact hole for a storage electrode and contact holes for a
first and a second plug electrode;
[0036] forming a storage electrode and a barrier layer by use of a
first conducting material at least on inner walls of the contact
holes for the first and the second plug electrode,
respectively;
[0037] burying a dummy film in the contact holes for the first and
the second plug electrode;
[0038] removing the dummy film buried in the contact holes for the
first and the second plug electrode other than the dummy film
buried in the contact hole for the storage electrode;
[0039] forming the first and the second plug electrode by burying a
second conducting material in the contact holes for the first and
the second plug electrode from which the dummy film is removed;
[0040] removing the dummy film buried in the contact hole for the
storage electrode;
[0041] forming a capacitor insulating film along an surface of the
storage electrode;
[0042] forming a capacitor by providing a plate electrode in the
contact hole for the storage electrode interposing the capacitor
insulating film;
[0043] forming a second interlayer insulating film over an entire
surface of the substrate;
[0044] flattening an surface of the interlayer insulating film;
[0045] removing the second interlayer insulating film selectively
to form contact holes for a first and a second contact electrode to
be connected to the first and the second plug electrode,
respectively; and
[0046] forming a bit line on the second interlayer insulating film
simultaneously with the first and the second contact electrode
which connect the bit line to the first and the second plug
electrode.
[0047] According to the semiconductor memory device and the method
of manufacturing the semiconductor memory device of the present
invention, the process for forming the memory cell region having a
stacked capacitor of a bit-line on capacitor structure can be
easily matched with the process for forming the peripheral circuit
region. By virtue of this, it is possible to improve the
fine-patterning processability of the DRAM which consists of the
memory cell region and the peripheral circuit region mounted on the
same chip, without performing a particular flattening step of the
interlayer insulating film.
[0048] Additional object and advantages of the invention will be
set forth in the description which follows, and in part will be
obvious from the description, or may be learned by practice of the
invention. The object and advantages of the invention may be
realized and obtained by means of the instrumentalities and
combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0049] The accompanying drawings, which are incorporated in and
constitute a part of the specification, illustrate presently
preferred embodiments of the invention, and together with the
general description given above and the detailed description of the
preferred embodiments given below, serve to explain the principles
of the invention.
[0050] FIGS. 1A-1C are schematic sectional views of a conventional
DRAM for explaining a manufacturing process thereof and
accompanying problems;
[0051] FIG. 2A is a schematic plan view of a gist portion of a DRAM
according to a first embodiment of the present invention having-a
memory cell region of a bit-line-over-capacitor structure and a
peripheral circuit region mounted on the same chip;
[0052] FIG. 2B is a cross sectional view of the DRAM taken along a
line 2B-2B of FIG. 2A;
[0053] FIGS. 3-11 are schematic sectional views of the DRAM for
explaining a method of manufacturing the DRAM according to the
first embodiment, stepwise;
[0054] FIG. 12 is a schematic sectional view of a gist portion of a
DRAM according to a second embodiment of the present invention;
and
[0055] FIG. 13 is a schematic sectional view of a gist portion of a
DRAM according to a third embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0056] Now, embodiments of the present invention will be explained
with reference to the accompanying drawings.
First Embodiment
[0057] FIGS. 2A and 2B show schematic structures of a DRAM
according to a first embodiment of the present invention, which is
characterized by having a memory cell region and a peripheral
circuit region mounted on the same chip. More precisely, FIG. 2A is
a plan view of a gist portion of the DRAM, showing its layout (1/2
pitch, 8F.sup.2(F represents a minimum design rule)). FIG. 2B is a
cross sectional view of a gist portion of the DRAM taken along a
line 2B-2B of FIG. 2A. The memory cell region is shown on the left
side (11A) and the peripheral circuit region is shown on the right
side (11B) of FIG. 2B.
[0058] The DRAM includes the memory cell region (DRAM cell) 11A
having a stacked capacitor of the bit-on-capacitor structure and
the peripheral circuit (logic circuit) region 11B mounted together
on a chip formed of a P-type silicon substrate (semiconductor
substrate) 11, as shown in FIG. 2B.
[0059] More precisely, as shown in FIG. 2B, in the memory cell
region 11A, the field oxidation film 12 (device isolation film) is
formed selectively in the surface of the P-type silicon substrate
11. Gate electrodes 17 are selectively formed on a memory cell
region 13a surrounded by the field oxidation film 12 with a gate
oxidation film 14 interposed therebetween. Each of the gate
electrodes 17 is formed by stacking polycrystalline silicon 15 and
an electrode material 16 such as tungsten polycide or titanium
silicide.
[0060] On the upper portion and side portions of each gate
electrode 17, a silicon nitride film 18 is formed.
[0061] In the surface of the p-type silicon substrate 11 between
gate electrodes 17, source/drain regions 19 are formed of an N-
type diffusion layer. In this way, a plurality of N-type MOS
transistors are constructed.
[0062] On the entire surface of the p-type silicon substrate 11
including the surfaces of the MOS transistors, a first interlayer
insulating film 21 made of SiO.sub.2 (silicon oxide) is formed, as
shown in FIG. 2B.
[0063] In the first interlayer insulating film 21, a bit line plug
(a first plug electrode) 31 constituting the bit line connecting
portion is formed corresponding to one (drain) of the source/drain
regions 19 of the MOS transistor.
[0064] The bit line plug 31 is formed of a barrier layer 32 formed
along an inner wall of, for example, the first plug electrode
contact hole 31a and a second conducting material 33 buried in a
space surrounded by the barrier layer 32. The barrier layer is a
stacked film of Ti(titanium)-TiN(titanium nitride) (first
conducting material). As the second conducting material 33, for
example, W is used.
[0065] On the bit line plug 31, a bit line contact (first contact
electrode) 51 is formed for connecting the bit line 41, as shown in
FIGS. 2A and 2B. The bit line connecting portion is constituted of
the bit line contact 51 and the bit line plug 31.
[0066] The bit line contact 51 is constituted of an insulating film
52 formed along an inner wall of the first contact electrode
contact hole 51a and a wiring material buried in the space
surrounded by the insulating film 52. The insulating film 52 is
formed of SiN (silicon nitride). As the wiring material, for
example, W (tungsten), aluminium (Al) or copper (Cu) which is used
for the bit line 41, is employed.
[0067] In the portion of the first interlayer insulating film 21
corresponding to the other (source) of the source/drain regions 19
of the MOS transistor, a capacitor 61 is formed as shown in FIG.
2B.
[0068] The capacitor 61 consists of a storage electrode 62 and a
plate electrode 64 which is buried in the storage electrode 62 with
a capacitor insulating film (Ta.sub.2O.sub.5 (tantal oxide) film)
63 interposed therebetween. The storage electrode 62 is a stacked
film of Ti and TiN (first conducting material) formed along an
inner wall of a storage electrode contact hole 61a. Note that the
capacitor insulating film may be an NO film or an ONO film.
[0069] A second interlayer insulating film 22 (SiO.sub.2) is formed
on the plate electrode 64. A bit line 41 is formed of the wiring
material (such as W or an Al alloy) on the second interlayer
insulating film 22.
[0070] On the other hand, as shown in the peripheral circuit region
11B (13b) of the FIG. 2B, a gate electrode 17 is selectively formed
not only on the field oxidation film 12 (selectively formed on the
surface of the P-type silicon substrate 11) but also in the field
region 13c excluding the field oxidation film 12, with the gate
oxidation film 14 interposed therebetween. The gate electrode 17 is
a stacked film formed of the polycrystalline silicon 15 and the
electrode material 16.
[0071] On the upper portion and side portions of the gate electrode
17, the silicon nitride film 18 is formed.
[0072] The source/drain regions 19 are formed of an N- type
diffusion layer in the surface of the p-type silicon substrate 11
on both sides of each of gate electrodes 17. In this manner, a
plurality of N-type MOS transistors are formed.
[0073] Over the entire surface of the P-type silicon substrate 11
including the surfaces of the MOS transistors, the first interlayer
insulating film 21 (SiO.sub.2) is formed, as shown in FIG. 2B.
[0074] In the first interlayer insulating film 21, a diffusion
layer plug (second plug electrode) 71 is formed which constitutes a
bit-line connecting portion (a first peripheral contact) to be
connected to the bit line 41 in correspondence with one (drain) of
the source/drain regions 19 of the MOS transistor.
[0075] The diffusion layer plug 71 is formed of the barrier layer
32 formed along an inner wall of the second plug electrode contact
hole 71a, and a second conducting material 33 (such as W) buried in
the space surrounded by the barrier layer 32, as shown in FIG. 2B.
The barrier layer 32 is formed of a stacked film formed of Ti--TiN
(the first conducting material).
[0076] On the gate electrode 17 formed on the field oxidation film
12, a gate electrode plug (second plug electrode) 81 is formed as
shown in FIG. 2B. The gate electrode plug constitutes a bit line
connecting portion (a second peripheral contact).
[0077] The gate electrode plug 81 is formed of the barrier layer 32
formed along an inner wall of the second plug electrode contact
hole 81a and the second conducting material 33 (such as W) buried
in the space surrounded by the barrier layer 32. The barrier layer
32 is formed of a stacked film formed of Ti--TiN (the first
conducting material).
[0078] On the diffusion layer plug 71 and the gate electrode plug
81, a bit line contact (second contact electrode) 91 to be
connected to the bit line 41 is formed, as shown in FIGS. 2A and
2B. The bit line connecting portion is formed of either the bit
line contact 91 in combination with the diffusion layer plug 71 or
the bit line contact 91 in combination with the gate electrode plug
81.
[0079] The bit line contact 91, as shown in FIG. 2B, is formed of a
SiN insulating film 52 formed along the inner wall of the second
contact electrode contact hole 91a and a wiring material buried in
a space surrounded by the SiN insulating film 52.
[0080] The second contact electrode contact hole 91a is formed
through the Ta.sub.2O.sub.5 film 63 and the second interlayer
insulating film 22. As the wiring material, for example, W or an Al
alloy (which is also used for the bit line 41) is used.
[0081] In the DRAM thus constituted, the bit line connecting
portion in the memory cell region 11A has the same surface height
as that of the peripheral circuit region 11B. Because of these
features, when the memory cell region 11A and the peripheral
circuit region 11B are mounted on the same chip, the formation
process for the memory cell region 11A can be more accurately
matched with that for the peripheral circuit region 11B.
[0082] To explain more specifically, in the memory cell region 11A
having a stacked capacitor of the bit-line-on capacitor structure,
the formation of the bit line plug 31 is made simultaneously with
the formation of the each of the plugs 71 and 81 of the peripheral
circuit region. In addition, the formation of the bit line contact
51 is made simultaneously with the formation of the bit line
contacts 91, 91 of the peripheral circuit region.
[0083] As mentioned above, the memory cell region (11A) formation
process can be easily matched with the peripheral circuit (11B)
formation process.
[0084] Hence, when the second interlayer insulating film 22 is
deposited, the stepped portion (which is usually caused by the
presence of the capacitor 61) is not formed on the upper surface of
the second interlayer insulating film 22 between the memory cell
region 11A and the peripheral circuit region 11B. As a result,
processing can be applied onto the flat surface, improving an
processing accuracy when the bit line 41 is patterned.
[0085] In addition, the barrier layer 32 of each of plugs 31, 71,
and 81 can be formed simultaneously with the storage node electrode
62 of the capacitor 61 after the first interlayer insulating film
21 is deposited. As a result, steps for forming the capacitor 61
can be reduced in number drastically.
[0086] After the transistor is formed, in particular, a full metal
process can be employed. To explain more specifically, a DRAM
consisting of the memory cell region 11A having a stacked capacitor
of the bit-line-over-capacitor structure and the peripheral circuit
region 11B mounted on the same chip, can be easily manufactured at
a low cost simply by adding steps of forming the capacitor
insulating film 63 and the plate electrode 64 to the process for
manufacturing a standard logic LSI.
[0087] Next, we will explain a process for manufacturing the DRAM
having the aforementioned structure.
[0088] As shown in FIG. 3, the field oxidation films 12 are
selectively formed on the surface of the P-type silicon substrate
11. Thereafter, the gate electrodes 17 are formed on the substrate
11 with the gate oxidation film 14 interposed therebetween. At the
same time, the source/drain regions 19 are separately formed in
spaces between the gate electrodes 17 in regions 13a and 13c. In
this way, a plurality of N-type MOS transistors are formed.
[0089] A nitride silicon film 18 is then formed on the upper
portion and side portions of each of the gate electrodes 17.
Thereafter, the first interlayer insulating film 21 (SiO.sub.2) is
formed in a thickness of about 300 to 1000 nm over the entire
surface by a CVD method and flattened by a CMP (Chemical Mechanical
Polishing) method.
[0090] Subsequently, a resist mask 23 is formed on the first
interlayer insulating film 21. The contact holes 31a, 61a, 71a and
81a are successively or simultaneously formed.
[0091] To explain more specifically, in the memory cell 11A, a
contact hole (first plug electrode contact hole) 31a for forming
the bit line plug 31 and a contact hole (storage electrode contact
hole) 61 for forming the capacitor 61 are separately formed through
the first interlayer insulating film 21.
[0092] On the other hand, in the peripheral circuit region 11B,
contact holes (second plug electrode contact holes) 71a and 81a for
forming the diffusion layer plug 71 and the gate electrode plug 81,
respectively, are formed.
[0093] After the resist mask 23 is removed, as shown in FIG. 4, a
Ti--TiN stacked film (first conducting material) 24 is deposited in
a thickness of about 10 to 50 nm on the bottom and side portions of
contact holes 31a, 61a, 71a, and 81a to form the barrier layer 32
or the storage electrode 62.
[0094] A dummy insulating film 25 is then deposited over the entire
surface so as to fill the contact holes 31a, 61a, 71a, and 81a. As
the dummy insulating film 25, a PSG (phospho-silicate glass) film,
a BPSG (boron-doped phospho silicate glass) film, or the like is
used.
[0095] The upper surface of the dummy insulating film 25 is then
flattened by a CMP method, as shown in FIG. 5. Subsequently, the
laminate film 24 present on the first interlayer insulating film 21
is removed by etchback.
[0096] Since the dummy insulating film 25 is buried in the contact
holes 31a, 61a, 71a and 81a, adverse effects such as a
polishing-agent deposition in the holes can be avoided during the
etchback.
[0097] In this process, the contact holes 31a, 71a and 81a are
filled with the barrier layer 32 and the dummy insulating film 25.
The contact hole 61a is filled with the storage node electrode 62
and the dummy insulating film 25.
[0098] As shown in FIG. 6, the dummy insulating film 25 buried in
the contact hole 31a (for the bit line plug 31), 71a (for the
diffusion layer plug 71), and 81a (for the gate electrode plug 81)
is removed by etching using the resist mask 26. As the etching
means used herein, a gaseous etching or liquid etching is
preferably employed. Isotropic etching is particularly preferably
employed.
[0099] Subsequently, as shown in FIG. 7, after the resist mask 26
is removed, the second conducting material 33 (W) is deposited over
the entire surface by a CVD method, followed by etching back by a
CMP method while keeping its flatness. As a result, the second
conducting material 33 is left only in the contact holes 31a, 71a
and 81a, forming the bit line plug 31, the diffusion layer plug 71
and gate electrode plug 81, separately.
[0100] Thereafter, as shown in FIG. 8, the dummy insulating film 25
buried in the contact hole 61a (for the capacitor 61) is removed by
etching using a resist mask (not shown), in the same manner as
mentioned above.
[0101] As shown in FIG. 9, after the resist mask is removed, the
capacitor insulating film 63 (e.g, Ta.sub.2O.sub.5) is formed in a
thickness of about 5 to 25 angstroms {in terms of an oxide film}
over the entire surface. Then, the plate electrode 64 (such as W)
is deposited on the Ta.sub.2O.sub.5 film 63 to fill only the
contact hole 61a. In this way, the capacitor 61 is formed.
[0102] Subsequently, as shown in FIG. 10, after the second
interlayer insulating film 22 is formed over the entire surface,
contact holes 51a, 91a and 91a (serving as the first and second
contact electrode contact holes) are separately formed by use of a
resist mask 27 to form the bit line contacts 51, 91 and 91.
[0103] After the resist film 27 is removed as shown in FIG. 11, for
example, SiN is deposited over the entire surface in a thickness of
about 10 to 50 nm, and etched by RIE in such a way that the SiN
film remains on side walls of each of the contact holes. In this
manner, an insulating film 52 is formed.
[0104] Afterward, a wiring material (such as W or an Al alloy) is
deposited on the second interlayer insulating film 22 and
patterned.
[0105] In the aforementioned steps, the formation of the bit line
contacts 51, 91 and 91 having the wiring material buried in each of
contact holes 51a, 91a and 91a, and the formation of the bit line
41 to be connected to the bit line contacts 51, 91 and 91 are
completed. As a result, the DRAM is accomplished including the
memory cell region 11A and the peripheral circuit region 11B
mounted together on the same chip, as shown in FIGS. 2A and 2B.
[0106] As mentioned above, the bit line connecting portion in the
memory cell region has the same surface height and the same
construction as those of the bit line connecting portion in the
peripheral circuit region.
[0107] By virtue of this, each bit line plug and bit line contact
in the memory cell region and the peripheral circuit region can be
formed simultaneously in the same process. Hence, a full metal
process for forming the bit line of Al can be employed. In this
way, the process for manufacturing the memory cell region having a
stacked capacitor of the bit-line-over-capacitor structure can be
matched with the process for manufacturing the peripheral circuit
formation. Hence, in the case where the memory cell region and the
peripheral circuit region are mounted on the same chip, the memory
cell region can be easily matched with the peripheral circuit
region. As a result, no stepped portion is formed on the upper
surface of the interlayer insulating film regardless the presence
or absence of a capacitor.
[0108] In particular, if the height of the storage electrode is
increased to obtain a requisite storage capacitance, the height of
the upper surface of the plug is accordingly increased. As a
result, processing can be always applied to a flat surface. Hence,
a micro patterning required for a bit line patterning can be made
more accurately without a particular flattening step.
[0109] The storage electrode of the capacitor is formed
simultaneously with the barrier layer of each plug. The first
conducting material for use in forming the barrier layer may be
used in forming the storage electrode of a capacitor. Accordingly,
the number of the steps for forming the capacitor can be reduced
drastically.
[0110] According to the DRAM constructed in the above, since an MIM
(metal-insulator-metal) type capacitor can be formed easily, the
performance of the capacitor insulating film can be fully
presented.
[0111] In this embodiment, the bit line 41 in the peripheral
circuit region is described as the bit line extended from the
memory cell region, as an example. It is noted that the bit line 41
in the peripheral circuit region includes wires formed in the same
wiring layer as the bit line 41 formed in the memory cell
region.
Second Embodiment
[0112] The first embodiment of the present invention has been
explained taking the case as an example, in which the capacitor
insulating film (Ta.sub.2O.sub.5) 63 is formed on the storage node
electrode 62. However, the present invention is not limited to this
case. For example, a film 28 of Pt (platinum), Ru (ruthenium), or
RuO.sub.2 (ruthenium oxide) may be further layered at least on the
storage electrode 62, as shown in FIG. 12.
[0113] The film 28 is easily formed by depositing the laminate film
24, the film 28, and the dummy insulating film 25 on the entire
surface in the order mentioned and removing them in such a way that
they remain only in the contact holes 31a, 61a, 71a, and 81a.
[0114] In the DRAM of this type, a film, such as a BSTO
(Ba.sub.xSr.sub.1-x TiO.sub.3 (barium strontium titanate) film
having a dielectric constant higher than that of the
Ta.sub.2O.sub.5 film 63, may be used as the capacitor insulating
film.
Third embodiment
[0115] Other than the case where the storage electrode contact hole
61a is filled up with the plate electrode 64 interposing the
capacitor insulating film (Ta.sub.2O.sub.5) 63, the plate electrode
64' may be provided only along the Ta.sub.2O.sub.5 film 63, as
shown in FIG. 13.
[0116] In the DRAM thus constructed, if the plate electrode 64' is
formed thin, the parasitic capacitance of the contact portion can
be further reduced.
[0117] In the DRAM according to the third embodiment of the present
invention, the film 28 (Pt, Ru, RuO.sub.2 or the like) may be
interposed at least between the storage node electrode 62 and the
capacitor insulating film, and the BSTO film may be employed as the
capacitor insulating film, in the same manner as in the second
embodiment.
[0118] The present invention can be applied not only to the case
where the storage electrode 62 is formed in the storage electrode
contact hole 61a but also the case where at least an upper portion
of the capacitor is formed cylindrically. Furthermore, individual
material, film thickness, conducting type may be appropriately
modified.
[0119] As detailed in the foregoing, the present invention can
provide a semiconductor memory device having the memory cell region
and the peripheral circuit region excellently matched without
forming a stepped portion on the upper surface of the interlayer
insulating film, regardless the presence or absence of a capacitor,
in the case where the memory cell region and the peripheral circuit
region are mounted together on the same chip. At the same time, the
method of manufacturing such a semiconductor device can be
provided.
[0120] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalent.
* * * * *