U.S. patent application number 09/909282 was filed with the patent office on 2001-11-15 for digital to analog converter with reduced ringing.
Invention is credited to Bult, Klaas, Lin, Chi-Hung.
Application Number | 20010040520 09/909282 |
Document ID | / |
Family ID | 25438742 |
Filed Date | 2001-11-15 |
United States Patent
Application |
20010040520 |
Kind Code |
A1 |
Bult, Klaas ; et
al. |
November 15, 2001 |
Digital to analog converter with reduced ringing
Abstract
Binary indications are converted to an analog representation
with significant reductions in ringing at the transitions between
successive binary indications and in the period during each binary
indication. The binary indications are disposed in a row-and-column
matrix to provide a thermometer code. The converter includes
pluralities of decoders and latches, each decoder being associated
with an individual latch. Each decoder responds to binary
indications of an individual row and an individual column and the
next column to produce a latched pair of output indications,
inverted relative to each other, in synchronism with a clock
signal. The production of the latched outputs in synchronism with
the clock signal inhibits ringing in the period during each binary
indication. Each pair of inverted latch outputs is respectively
introduced to a differential amplifier, formed from MOS transistors
of the p type, in an individual one of a plurality of current
sources. Each differential amplifier has a pair of branches each
responsive to the paired inverted outputs from the associated latch
in an opposite relationship to that of the other branch. The p type
transistors in each differential amplifier inhibit ringing in such
amplifier at the transitions between the successive binary
indications. Each branch in each differential amplifier is
connected to a resistor common to the corresponding branches in the
other differential amplifiers. Such branches pass through such
resistor a current dependent upon the cumulative current through
such branches. This cumulative current provides the analog
representation.
Inventors: |
Bult, Klaas; (Dana Point,
CA) ; Lin, Chi-Hung; (Los Angeles, CA) |
Correspondence
Address: |
CHRISTIE, PARKER & HALE, LLP
350 WEST COLORADO BOULEVARD
SUITE 500
PASADENA
CA
91105
US
|
Family ID: |
25438742 |
Appl. No.: |
09/909282 |
Filed: |
July 19, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09909282 |
Jul 19, 2001 |
|
|
|
09753874 |
Jan 3, 2001 |
|
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Current U.S.
Class: |
341/144 |
Current CPC
Class: |
H03M 1/0682 20130101;
H03M 1/685 20130101; H03M 1/0624 20130101; H03M 1/0872 20130101;
H03M 1/747 20130101 |
Class at
Publication: |
341/144 |
International
Class: |
H03M 001/66 |
Claims
1. In combination for converting binary indications of a value to
an analog representation of the value, means for providing binary
indications of the value, means for providing a clock signal, a
plurality of decoding and latching circuits each responsive to an
individual one of the binary indications for latching such
individual one of the binary indications without any ringing at
times between the transitions of such binary indications, a
plurality of current sources each responsive to the latched binary
indications from an individual one of the decoding and latching
circuits for producing an analog current representative of the
latched binary indications from the individual one of the decoding
and latching circuits without any ringing at the transitions
between such binary indications, and means for combining the
currents from the current sources in the plurality to provide the
analog representation of the value.
2. In a combination as set forth in claim 1, each of the current
sources being formed from MOS transistors of the p type to inhibit
any ringing of the current sources at the transitions of the binary
indications.
3. In a combination as set forth in claim 1, the current sources
including a reference path for establishing reference voltages for
introduction to the current sources in the plurality to control the
operation of the current sources in producing the analog currents
representative of the latched binary indications from the decoding
and latching circuits.
4. In a combination as set forth in claim 1, each of the current
sources including first and second branches, each branch in each
current source constituting a duplicate of the other branch in such
current source and each having first and second transistors and an
output transistor connected to the first and second transistors,
the first and second transistors in the first branch in each
current source being respectively responsive to the binary
indications of 0 and 1 for the individual one of the latched
indications and the first and second transistors in the second
branch in each current source being respectively responsive to the
binary indications of 1 and 0 for the individual one of the latched
indications.
5. In a combination as set forth in claim 1, each branch in each
current source including a third transistor connected to the first
and second transistors for providing an output current dependent
upon the binary indications introduced to the first and second
transistors of such branch.
6. In a combination as set forth in claim 4, the first and second
and third transistors in each of the first and second branches
being CMOS transistors of the p-type.
7. In a combination as set forth in claim 3, each of the current
sources including first and second branches, each branch in each
current source constituting a duplicate of the other branch in such
current source and each having first and second transistors and an
output transistor connected to the first and second transistors,
the first and second transistors in the first branch in each
current source being respectively responsive to the binary
indications of 0 and 1 for the individual one of the latched
indications and the first and second transistors in the second
branch in each current source being respectively responsive to the
binary indications of 1 and 0 for the individual one of the latched
indications, each branch in each current source including a third
transistor connected to the first and second transistors for
providing an output current dependent upon the binary indications
introduced to the first and second transistors of such branch, the
first and second and third transistors in each of the first and
second branches being CMOS transistors of the p-type.
8. In combination for converting binary indications of a value to
an analog representation of the value, first means for providing
binary indications of the value, second means responsive to the
binary indications of the value for decoding and latching such
binary indications without any ringing at any time in the time
period during the binary indications, third means responsive to the
latched indications from the second means for producing currents
representative of such latched indications without any ringing at
the transitions between such latched indications, and fourth means
for combining the currents from the third means to provide the
analog representations.
9. In a combination as set forth in claim 8, the binary indications
being provided by cells in a matrix relationship of rows and
columns, and the second means including a plurality of decoders
each responsive to an individual one of the cells defined by an
individual one of the combination of rows and an individual one of
the columns and each responsive to the binary indication of the
next column to provide the latched determination of the binary
indication from the individual one of the cells.
10. In a combination as set forth in claim 9, means for providing a
clock signal, and the second means including a plurality of latches
each responsive to the clock signal and to the output from an
associated one of the decoders to provide the latched determination
of the binary indication in the associated one of the decoders.
11. In a combination as set forth in claim 8, the binary
indications by provided by cells in a matrix relationship of row
and columns, means for providing a clock signal, the second means
being responsive to the binary indications from an individual one
of the cells for decoding and latching such binary indications in
synchronism with the clock signal and without any ringing at any
time in the time period during such binary indications.
12. In a combination as set forth in claim 8, the binary
indications by provided by cells in a matrix relationship of rows
and columns, each of the current sources being constructed from a
plurality of transistors each constituting a CMOS transistor of the
p type to prevent any ringing at such transistor at the transitions
between the binary indications from the cells.
13. In a combination as set forth in claim 8 wherein the binary
indications being provided by cells in a matrix relationship of
rows and columns, the third means includes a plurality of
differential amplifiers each responsive to the decoding and
latching of the binary indications from an individual one of the
cells and to the inverse of such binary indications from such
individual one of the cells for producing currents representative
of such decoding and latching without any ringing at the
transitions between such binary indications.
14. In a combination as set forth in claim 15 wherein each of the
differential amplifiers is formed from a plurality of transistors
each constituting a MOS transistor of the p type.
15. In a combination as set forth in claim 9, means for providing a
clock signal, and the second means including a plurality of latches
each responsive to the clock signal and to the output from an
associated one of the decoders to provide the latched determination
of the binary indication in the associated one of the decoders,
each of the current sources being constructed from a plurality of
transistors each constituting a CMOS transistor of the p type to
prevent any ringing at such transistor at the transitions between
the binary indications from the cells, each of the differential
amplifiers is formed from a plurality of transistors each
constituting a MOS transistor of the p type.
16. In combination for converting binary indications of a value to
an analog representation of the value, means for providing binary
indications of the value, a plurality of decoding means each
including a first terminal and a second terminal and each
responsive to an individual one of the binary indications and to
the inverse of such individual one of the binary indications for
producing on the first terminal a voltage representative of the
individual one of the binary indications and for producing an
inverse of such voltage on the second terminal, means for providing
a clock signal, and a plurality of latching means each responsive
to the clock signal and to the voltage on the first terminal for
the individual one of the binary indications and the inverse
voltage on the second terminal for the individual one of the binary
indications for latching such voltage and the inverse of such
voltage.
17. In a combination as set forth in claim 16, each of the decoding
means in the plurality providing binary indications of an
individual position represented by an individual one of a plurality
of rows in a matrix relationship and by an individual one of a
plurality of columns in the matrix relationship.
18. In a combination as set forth in claim 16, each of the decoding
means in the plurality being represented by means common to an
individual one of a plurality of rows in a matrix relationship and
common to an individual one of a plurality of columns in the matrix
relationship and by the column higher in the matrix relationship
than the individual one of the plurality of columns.
19. In a combination as set forth in claim 16, each of the decoding
means including a first circuit responsive to the individual one of
the binary indications for producing a first voltage representative
of the individual one of the binary indications and including a
second circuit responsive to the inverse of the individual one of
the binary indications for producing a second voltage
representative of the inverse of the individual one of the binary
indications, and each of the latching means having first and second
circuits cross connected to each other in a latched relationship to
produce a first latched output from one of the first and second
circuits and a second latched output from the other one of the
first and second circuits, the second latched output being the
inverse of the first latched output, the first circuit in each of
the latching means being connected in circuitry with the clock
signal means and the first circuit in an individual one of the
decoding means to produce a first latched output in such circuitry
and the second circuit in each of the latching means being
connected in circuitry with the clock signal means and the second
circuit in such individual one of the decoding means to produce in
such circuitry a second latched output inverse to the first latched
output.
20. In a combination as set forth in claim 16, a plurality of
current means each having first and second branches connected in a
differential relationship, the first and second branches in each of
the current means being respectively responsive to the first and
second latched outputs in an individual one of the latching means
to provide a current through such current means in accordance with
the values of the first and second latched outputs in the
individual one of the latching means.
21. In a combination as set forth in claim 20, each of the decoding
means in the plurality providing binary indications of an
individual position represented by an individual one of a plurality
of rows in a matrix relationship and by an individual one of a
plurality of columns in the matrix relationship, each of the
decoding means in the plurality being represented by means common
to an individual one of a plurality of rows in a matrix
relationship and common to an individual one of a plurality of
columns in the matrix relationship and by the column higher in the
matrix relationship than the individual one of the plurality of
columns, each of the decoding means including a first circuit
responsive to the individual one of the binary indications for
producing a first voltage representative of the individual one of
the binary indications and including a second circuit responsive to
the inverse of the individual one of the binary indications for
producing a second voltage representative of the inverse of the
individual one of the binary indications, and each of the latching
means having first and second circuits cross connected to each
other in a latched relationship to produce a first latched output
from one of the first and second circuits and a second latched
output from the other one of the first and second circuits, the
second latched output being the inverse of the first latched
output, the first circuit in each of the latching means being
connected in circuitry with the clock signal means and the first
circuit in an individual one of the decoding means to produce a
first latched output in such circuitry and the second circuit in
each of the latching means being connected in circuitry with the
clock signal means and the second circuit in such individual one of
the decoding means to produce in such circuitry a second latched
output inverse to the first latched output.
22. In combination for converting binary indications of a value to
an analog representation of the value, first means for providing
binary indications of the value, second means for providing a clock
signal, a plurality of circuits each providing decoding and
latching and each responsive to an individual one of the binary
indications and to the clock signal for decoding the individual one
of the binary indications in synchronism with the clock signal and
for latching such decoding to provide a first latched output
representing such individual one of the binary indications and to
provide a second latched output representing the inverse of such
individual one of the binary indications, the first and second
latched outputs inhibiting any ringing in the period of such
individual one of the binary indications, an output impedance, and
a plurality of current sources each responsive to the first and
second latched outputs from an individual one of the decoding and
latching circuits and each constructed to pass a current through
the output impedance, without any ringing at the transition at the
individual one of the binary indications, in accordance with the
relative characteristics of the first and second latched
outputs.
23. In a combination as set forth in claim 22, each of the current
sources including a differential amplifier having first and second
branches, each of the first and second branches in the differential
amplifier in each of the current sources being responsive in a
first relationship to the first and second latched outputs and the
other one of the first and second branches in the differential
amplifier in each of the current sources being responsive to the
first and second latched outputs in a second relationship opposite
to the first relationship.
24. In a combination as set forth in claim 23, each of the branches
in each of the current sources being formed from a plurality of p
transistors.
25. In a combination as set forth in claim 23, each of the branches
in each of the current sources including first and second
transistors, the first and second transistors in the first branch
in each of the current sources being responsive to the first and
second latched outputs in a first relationship of such latched
output, and the first and second transistors in the second branch
in each of the current sources being responsive to the second and
first latched outputs in a second relationship of such latched
outputs opposite to the first relationship of such latched
outputs.
26. In a combination as set forth in claim 25, each of the branches
in each of the current sources including a third transistor
connected to the first and second transistors in such branch to
provide an output current in such third transistor dependent upon
the relative characteristics of the first and second latched
outputs introduced to such branch.
27. In combination in a current source for converting a binary
representation of a value to an analog representation of the value,
first means for providing the binary representation, second means
for providing the inverse of the binary representation, a
differential amplifier formed from a plurality of MOS transistors
of the p type and having a pair of branches, third means for
introducing the binary representations from the first and second
means to the first branch in a first relationship to provide at
first particular times an output current dependent upon the binary
representation from the first means and the inverse of the binary
representation from the second means, and fourth means for
introducing the binary representations from the first and second
means to the second branch in a second relationship inverse to the
first relationship to provide an output current at the times other
than the first particular times.
28. In a combination as set forth in claim 27, each of the first
and second branches being responsive to the binary indications of
an individual one of cells in a matrix relationship, each of the
branches including first and second transistors, the first and
second transistors in the first branch for each individual one of
the cells in the matrix relationship being respectively responsive
to the binary representations from the first and second means for
such cell to provide for the production of an output current from
the first branch at the first particular times and the second
branch for each individual one of the cells in the matrix
relationship being respectively responsive to the binary
representations from the first and second means, in an inverse
relationship to the response of the first branch for such cell to
the first and second binary representations for such cell, to
provide for the production of an output current from the second
branch at times other than the first particular times.
29. In a combination as set forth in claim 28, each of the branches
for each individual one of the cells in the matrix relationship
including a third transistor, the third transistor in the first
branch being connected to the first and second transistors in the
first branch to provide the output current upon the occurrence of a
particular relationship between the binary representations
introduced from the first and second means to such branch, the
third transistor in the second branch for each individual one of
the cells in the matrix relationship being connected to the first
and second transistors in the second branch to provide an output
current in the second branch upon the occurrence of the
relationship, inverse to the particular relationship, between the
binary representations introduced from the first and second means
to such branch.
30. In a combination as set forth in claim 29, the first and second
transistors in the first branch being connected in a series
relationship and having a common terminal, the first and second
transistors in the second branch being connected in a series
relationship and having a common terminal, means for connecting the
third transistor in the first branch to the terminal common to the
first and second transistors in the first branch, means for
connecting the third transistor in the second branch to the
terminal common to the first and second transistors in the second
branch.
31. In a combination as set forth in claim 30, a first resistor
connected to the third transistor in the first branch to receive
the current flowing through such transistor, a second resistor
connected to the third transistor in the second branch to receive
the current flowing through such transistor.
32. In a combination as set forth in claim 31, the first resistor
being connected to the third transistor for each of the first
branches for the cells in the matrix relationship, the second
resistor being connected to the third transistor for each of the
second branches for the cells in the matrix relationship.
33. In combination for converting binary indications of a value
into an analog representation of the value, first means for
providing the binary indications of the value, each of the binary
indications occurring in a finite time interval and having
transitions at the beginning and end of the finite time interval,
second means for providing a plurality of first outputs each
representative of an individual one of the binary indications of
the value, third means for providing a plurality of second outputs
each inverse to an individual one of the first outputs, an output
impedance, and a plurality of current sources each responsive to
the first and second outputs from an individual one of the binary
indications of the value and each constructed to pass a current
through the output impedance, without any ringing at the
transitions at the individual one of the binary indications, in
accordance with the characteristics of the first and second outputs
from such individual one of the binary indications.
34. In a combination as set forth in claim 33, each of the current
sources including a differential amplifier having first and second
branches each having a construction corresponding to the
construction of the other branch in the current source, each of the
first and second branches in each of the current sources having
first and second transistors, the first and second transistors in
each of the first branches being respectively responsive to the
first and second outputs and the first and second transistors in
each of the second branches being respectively responsive to the
second and first outputs.
35. In a combination as set forth in claim 34, each of the first
and second transistors in each of the branches constituting a MOS
transistor of the p type to eliminate any ringing at the
transitions at the individual ones of the binary indications.
36. In a combination as set forth in claim 34, each of the first
and second transistor including a third transistor connected to the
first and second transistors in such branch to provide an output
current dependent upon the introduction of the first and second
outputs to the particular ones of the first and second transistors
in such branch.
37. In a combination as set forth in claim 36, each of the first,
second and third transistors in each of the branches constituting a
MOS transistor of the p-type to eliminate any ringing at the
transitions at the individual ones of the binary indications.
Description
[0001] This invention relates to digital-to-analog converters. More
particularly, the invention relates to digital-to-analog converters
in which a plurality of binary indications representing a value are
converted to an analog current or an analog voltage representing
the value without any ringing during the binary indications or at
the transitions between successive binary indications.
BACKGROUND OF THE INVENTION
[0002] Most parameters such as measurements of temperature,
humidity and pressure are analog. For example, the use of a mercury
thermometer to measure the temperature of a patient is analog since
the temperature is measured by the rise of a mercury column.
However, temperature may also be indicated digitally. For example,
an indication of a temperature of "98.6" may be provided digitally
by providing three separate indications of "9", "8" and "6".
[0003] Generally, when parameters such as temperature or pressure
are measured on an analog basis and these measurements are used to
provide calculations for controlling the operation of a system in
which the values of temperature and pressure are regulated, the
analog values are converted to digital values for providing the
calculations. The calculations are then converted to digital values
to provide the regulation of the parameters such as temperature and
pressure.
[0004] Integrated circuit chips are generally provided for
converting digital indications of a value to an analog
representation of the value. Preferably this conversion is provided
in as short a time (or as high a frequency) as possible. Minimizing
the time for the conversion is desirable because it provides for an
enhanced regulation of the values of parameters such as pressure
and temperature.
[0005] Integrated circuit chips have been progressively provided
through the years with decreased micron size. In other words, the
thickness of the electrical leads connecting the different
components in the electrical circuitry on the integrated circuit
chip has been progressively decreased through the years. For
example, the micron size of the electrical leads on an integrated
circuit chip have progressively decreased in size during the past
ten (10) years from approximately two (2) microns to approximately
one half micron (0.5.mu.) or less. Decreases in micron size have
produced corresponding increases in the frequency at which the
electrical circuits on the integrated circuit chip are able to
operate. For example, electrical circuits made from CMOS technology
on an integrated circuit chip are now able to operate at
frequencies in the order of several hundred megahertz in comparison
to frequencies less than one hundred megahertz (100 Mhz) ten years
ago.
[0006] Digital-to-analog converters have problems of ringing,
particularly when they operate at high frequencies. The ringing
occurs during the period of each of the binary indications. The
ringing also occurs at the transitions between successive ones of
the binary indications. The ringing obscures the generation of the
analog current or analog voltage which represents the cumulative
value of the binary indications. The ringing becomes pronounced
because of the high frequencies at which the digital-to-analog
converters operate. As previously indicated, these high frequencies
are provided because of the progressive decrease in the micron size
of the electrical leads, and the progressive decrease in the
dimensions of devices such as transistors, in the integrated
circuit chips.
BRIEF DESCRIPTION OF THE INVENTION
[0007] In one embodiment of the invention, binary indications are
converted to an analog representation with significant reductions
in ringing at the transitions between successive binary indications
or in the period during each binary indication. The binary
indications are disposed in a row-and-column matrix to provide a
thermometer code. The converter includes pluralities of decoders
and latches, each decoder being associated with an individual
latch. Each decoder responds to binary indications of an individual
row and an individual column and the next column to produce a
latched pair of output indications, inverted relative to each
other, in synchronism with a clock signal.
[0008] The production of the latched outputs in synchronism with
the clock signal inhibits ringing in the period during each binary
indication. Each pair of inverted latch outputs is respectively
introduced to a differential amplifier, formed from MOS transistors
of the p type, in an individual one of a plurality of current
sources. Each differential amplifier has a pair of branches each
responsive to the paired inverted outputs from the associated latch
in an opposite relationship to that of the other branch.
[0009] The p type transistors in each differential amplifier
inhibit ringing in such amplifier at the transitions between the
successive binary indications. Each branch in each differential
amplifier is connected to a resistor common to the corresponding
branches in the other differential amplifiers. Such branches pass
through such resistor a current dependent upon the cumulative
current through such branches. This cumulative current provides the
analog representation.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In the drawings:
[0011] FIG. 1 is a general block diagram of digital-to-analog
converters of the prior art;
[0012] FIG. 2 is a circuit diagram of circuitry of the prior art,
such circuitry being used in the block diagram of FIG. 1 for
providing a binary-to-thermometer decoding of a plurality of binary
indications,
[0013] FIG. 3 is a circuit diagram of circuitry of the prior art,
such circuitry being used in the block diagram of FIG. 1 for
providing a binary-to-thermometer decoding of a binary indications
in a plurality of cells when the cells are disposed in a matrix
relationship;
[0014] FIG. 4 is an example of binary indications in cells disposed
in a matrix relationship for decoding by the circuitry shown in
FIG. 3;
[0015] FIG. 5 is a circuit diagram of a current source of the prior
art for use in the block diagram of FIG. 1 for converting a binary
indication in a cell to an analog representation;
[0016] FIG. 6 is a schematic diagram showing inductances which are
produced in the converter of FIG. 1 and which affect the operation
of such converter;
[0017] FIG. 7 provides curves showing ringing (oscillatory signals)
produced in the prior art converter shown in FIG. 1 and the
elimination of ringing in the digital-to-analog converter of this
invention;
[0018] FIG. 8 is a circuit diagram of a latch of the prior art for
use in the block diagram of FIG. 1;
[0019] FIG. 9 is a circuit diagram of a decoder and latch which is
included in the digital-to-analog converter of this invention for
decoding and latching a binary indication in a cell in a matrix
relationship without any ringing during the occurrence of such
binary indication; and
[0020] FIG. 10 is a circuit diagram of a current source which is
included in the digital-to-analog converter of this invention for
converting the latched binary indication in FIG. 9 for a cell in a
matrix relationship to a corresponding analog current or voltage
without any ringing at the transitions between successive binary
indication.
DETAILED DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 is a block diagram of a digital-to-analog converter,
general indicated at 10, of the prior art. The converter includes
three (3) blocks: a decoder 12, a latch 14 and a current source 16.
The decoder 12 receives binary indications, preferably in a
thermometer code, from a plurality of cells and provides signals
(currents or voltages) representative of these binary indications.
The latch 14 produces latched outputs representative of the
currents or voltages produced by the decoder 12. The current source
16 produces currents representative of the latched outputs from the
different cells and accumulates these currents in an output
impedance for the binary indications from the different cells to
provide in the output impedance a current representing the analog
value.
[0022] FIG. 2 is a circuit diagram of binary-to-thermometer
converter generally indicated at 20. The circuitry 20 includes a
first line 22 and a second line 24. A plurality of switches 26a-26p
is provided. Each of the switches 26a-26p has a first stationary
contact connected to the line 22 and a second stationary contact
connected to the line 24. Each of the switches 26a-26p has a
contact 28a-28p movable between the lines 22 and 24. For example,
the contact 28a may be continuous with the line 22 for a binary
value of 1 and may be continuous with the line 24 for a binary
value of 0.
[0023] When the movable contact of a switch such as the movable
contact 28a of the switch 26a establishes continuity with the line
24, a continuous circuit is established which includes a resistor
30, the line 24, the movable contact of the switch and a line such
as a line 32a. This is true for the switches 26a-26j in FIG. 2. In
this way, the resistor 30 receives the current cumulatively flowing
through the switches 26a-26j in FIG. 2. This cumulative current may
be considered to represent an inverse of the analog value of the
binary indications from the cells in FIG. 2.
[0024] When the movable contact of a switch such as the movable
contact 28k of the switch 26k is continuous with the line 22, a
continuous circuit is established through a circuit including a
resistor 34, the line 22, the switch 26k and a source 36k of a
substantially constant current. This is true of the switches
26k-26p in FIG. 2. In this way, the resistor 30 receives the
current cumulatively flowing through the switches 26k-26p in FIG.
2. This cumulative current may be considered to represent the
analog value of the binary indications in FIG. 2.
[0025] FIG. 3 indicates a decoder for use with the matrix
relationship shown in FIG. 3 to decode the binary indications of
one of the cells in the matrix relationship. A similar decoder is
provided for each of the other cells in the matrix relationship.
The decoder shown in FIG. 3 includes a line 40 for providing a
positive voltage such as five (5) volts and a line 42 for providing
a voltage such as ground. The lines 40 and 42 are also respectively
designated as "V.sub.ddd" and "V.sub.sdd" where the last letter in
the sub-designation indicates a digital circuit. Three (3)
transistors 44, 46 and 48, all preferably CMOS transistors of the p
type, are connected between the line 40 and a data line 50 for the
particular cell.
[0026] The gate of the transistor 44 receives a voltage
representative of the binary indication of the row in which the
particular cell is disposed. The gate of the transistor 46 receives
a voltage representative of the binary indication of the column in
which the particular cell is disposed. The gate of the transistor
48 receives a voltage representative of the binary indications in
the next column. If all of the cells in the next column have a
binary indication of "0", the gate of the transistor 48 receives a
low voltage. Otherwise, the gate of the transistor 48 receives a
high voltage. The sources of the transistors 44 and 46 are common
line with the line 40. The drain of the transistor 42 has a
connection with the line 50. The drains of the transistors 44 and
46 and the source of the transistor 48 are common.
[0027] Transistors 52, 54 and 56, all preferably CMOS transistors
of the N type, are disposed between the data line 50 and the ground
line 42. The drains of the transistors 52 and 56 are connected to
the data line 50. The source of the transistor 52 and the drain of
the transistor 54 have a common connection. The sources of the
transistors 54 and 56 are common with the ground line 42. The gate
of the transistor 52 receives the binary indication representing
the row in which the particular cell is disposed, and the gate of
the transistor 54 receives the binary indication representing the
column in which the particular cell is disposed. A binary
indication representing the next column is introduced to the gate
of the transistor 56.
[0028] When binary indications of 0 are introduced to the gates of
the transistors 44, 46 and 48, these transistors become conductive.
As a result, a high voltage is produced on the line 50 to indicate
a binary value of "0" for a cell. When high voltages are introduced
to the gates of the transistors 52, 54 and 56, all of these
transistors become conductive. This cause a low voltage to be
produced on the line 50 to indicate a binary "1".
[0029] The voltage on the line 50 in FIG. 3 is introduced to a pair
of lines 60 and 62 in FIG. 5, which shows a current source
generally indicated at 63 of the prior art. These lines are
respectively designated as "lan" and "lap" where the "n" in "lan"
indicates "negative" and the "p" in "lap" indicates "positive". The
lines 60 and 62 in FIG. 5 are respectively introduced to the gates
of a pair of transistors 64 and 66, both preferably CMOS transistor
of the n type. The drains of the transistors 64 and 66 are
respectively connected to first terminals of resistors 68 and 70,
the second terminals of which are common with a line 71 providing a
positive voltage. The line 71 is also designated as V.sub.dda where
"a" indicates an analog voltage.
[0030] The drains of the transistors 64 and 66 are common with the
drain of a transistor 72. The gate of the transistor 72 receives a
constant bias voltage on a line 74. The source of the transistor 72
and the drain of a transistor 76 are common. A constant bias
voltage on a line 80 is applied to the gate of the transistor 76.
The source of the transistor 76 is connected to a line 81. The line
81 is also designated as "V.sub.ssa" where "a" indicates an analog
circuit.
[0031] The current source 63 is provided for one of the cells in
the matrix relationship shown in FIG. 4. It will be appreciated
that a corresponding current source is provided for each individual
one of the cells in the matrix relationship. However, the resistors
68 and 70 are common to all of the current cells in the matrix
relationship. The resistor accordingly provides an analog current
representing the analog value of the binary indications introduced
to the cells in the matrix relationship.
[0032] The voltage on the gate of one of the transistors 64 and 66
represents an inverse value of the voltage produced on the line 50
in FIG. 3. Because of this, only one of the transistors 64 and 66
is conductive at any instant. For example, when the transistor 66
is conductive, current flows through a circuit including the line
71, the resistor 70, the transistor 66, the transistor 72, the
transistor 76 and the line 81.
[0033] The transistor 76 is biased at its gate by the voltage on
the line 80 so that the current through the circuit described in
the previous sentence is substantially constant. The transistor 72
is biased at its gate by the voltage on the line 74 so that a high
impedance is produced in the circuit. This high impedance is
provided to compensate for the fact that the resistors 68 and 70
receive currents from a number of current sources and that the
number of current sources connected to each individual one of the
resistors 68 and 70 at any instant may vary dependent upon the
values of the voltages applied to each individual one of the
transistors 64 and 66 in the different current sources.
[0034] FIG. 4 indicates a matrix relationship for a decoder. In a
matrix relationship, the binary indications are disposed in rows
and columns. In this relationship, progressive binary indications
of "1" are provided for the successive cells downwardly in the
first column from the top of the column and in the first two (2)
rows of the second column. All of the other indications for the
cells in the matrix relationship are a binary "0". In this matrix
relationship, if the value of the binary indications in the matrix
relationship were to be increased by an integer, the cell in the
third row in the second column would become a binary "1" instead of
a binary "0".
[0035] FIG. 6 indicates the inductances provided in the converters
of the prior art. Similar inductances exist in the converters of
this invention. These inductances result from bond wires and leads
from chip packages. For example, an inductance 84 may be provided
between a line 82 providing a positive voltage designated as
V.sub.dd and the line 71 providing a positive voltage designated as
V.sub.dda for the analog circuitry. The inductance may be
approximately five (5) nanohenries for each cell. Assuming that
there are approximately sixty (60) cells, the cumulative inductance
may be as high as three hundred (300) nanohenries. Similarly an
inductance of approximately three hundred (300) nanohenries may be
provided on a cumulative basis between the voltage V.sub.dd on the
line 82 and a digital voltage V.sub.ddd for the digital circuits.
Similar inductances are provided between the voltage V.sub.ssa on
the line 81 for the analog circuits and a voltage V.sub.ss on a
line 83 and between a voltage V.sub.ssd on a line 85 for the
digital circuits and the voltage V.sub.ss on the line 83.
[0036] The inductances shown in FIG. 6 combine with stray
capacitances in the converters of the prior art to produce ringing
in the converters. Such ringing constitutes oscillatory signals at
a frequency dependent upon the values of the inductances shown in
FIG. 6 and the stray capacitances in the converter. Such
inductances would also produce ringing in the circuits of this
invention if the features of this invention were not included.
[0037] FIG. 7 provides two (2) voltage waveforms on a schematic
basis. The upper diagram in FIG. 7 represents a voltage waveform 90
of the prior art. It shows that ringing 92 (oscillatory signals)
occurs at the beginning of the signal produced by one of the
current sources 63 shown in FIG. 5. Ringing 94 also occurs at the
middle of the signal from the current source 63. The bottom
waveform in FIG. 7 shows a waveform 96 produced by the circuitry
shown in FIGS. 9 and 10 and constituting one embodiment of the
invention. As will be seen, the ringing shown in the waveform 90
has been eliminated in the waveform 96.
[0038] FIG. 8 shows a latch, generally indicated at 100, of the
prior art. The latch includes the voltage V.sub.ddd and the voltage
V.sub.ssd on the line 85 (both also shown in FIG. 6) and the data
voltage on the data line 50 in FIG. 3 and the inverse ({overscore
(data)}) of this voltage on a line 102. The data voltage on the
line 50 is introduced to the gate of a transistor 104, the source
of which receives the voltage V.sub.ssd on the line 85. The drain
of the transistor 104 and the source of a transistor 106 are
common. A clock signal on a line 105 is introduced to the gate of
the transistor 106 and the drain of the transistor 106 is connected
to the lan line 60 also shown in FIG. 5. The transistors 104 and
106 may be CMOS transistors of the n-type.
[0039] Transistors 108 and 110 may also be CMOS transistors of the
n-type. The source of the transistor 106 may be common with the
V.sub.ssd line 85. The gate of the transistor 106 receives the
{overscore (data)} binary information on the line 102. A connection
is made from the drain of the transistor 106 to the source of the
transistor 108. The gate of the transistor 108 receives the clock
62 signal 105 also shown in FIG. 5.
[0040] The line 60 is connected to the drains of transistors 110
and 112 and to the gates of transistors 114 and 116. The
transistors 110 and 114 may be CMOS transistors of the p type and
the transistors 112 and 114 may be transistors of the n-type. In
like manner, the voltage on the line 62 is introduced to the drains
of the transistors 114 and 116 and to the gates of the transistors
110 and 112. The sources of the transistors 110 and 114 are
connected to the V.sub.ddd line also shown in FIG. 6. A connection
is made from the sources of the transistors 112 and 116 to the
V.sub.ssd line 85 also shown in FIG. 6.
[0041] Assume that the data line 50 is positive and that the
{overscore (data)} line 102 is negative. This will cause current to
flow through a circuit including the lan line 60 and the
transistors 106 and 104 when a clock signal appears on the line
105. This causes a low voltage to be produced on the line 60. This
low voltage causes the transistor 114 to become conductive and a
high voltage to be produced on the drain of the transistor. This
high voltage is introduced to the gate of the transistor 112. The
resultant flow of current through the transistor 112 causes a low
voltage to be produced on the drain of the transistor and to be
introduced to the gate of the transistor 114 to make the transistor
114 even more conductive. The resultant high voltage is introduced
to the lap line 62 to latch the lap line to a positive voltage. In
like manner, the lan line 60 becomes latched to a negative
voltage.
[0042] In like manner, when the data line 50 is negative and the
{overscore (data)} line 52 is positive, the lan line 60 is latched
to a positive voltage and the lap line 62 is latched to a negative
voltage. This results from the state of conductivity in the
transistors 110 and 116 and the states of non-conductivity in the
transistor 114 and 112.
[0043] FIG. 9 shows circuitry, generally illustrated at 129,
included in one embodiment of the invention. The circuitry shown in
FIG. 9 combines the functions of decoding and latching. Such
circuitry includes a latch formed from the transistors 110, 112,
114 and 116 in a manner similar to that described in connection
with the prior art embodiment shown in FIG. 8. Such circuitry also
includes decoding circuitry including a lan line 130 and a lap line
132 which provide signal outputs inverse to each other. The output
on the lan line 130 is inverted as at 131 to provide a lan signal
on a line 133. The lan line 130 is connected to the drains of the
transistor 110 and of a CMOS transistor 134, preferably of the
n-type. The transistor 134 receives a clock signal on its gate from
a line 135. The source of the transistor 134 has a common
connection with the drains of CMOS transistors 136, 138 and 139,
all preferably of the n-type.
[0044] The gate of the transistor 136 is common with the row
indication of an individual one of the cells in a matrix
arrangement. A connection is made from the source of the transistor
136 to the drain of a transistor 140 which is a CMOS transistor,
preferably of the n-type. The gate of the transistor 140 receives
the column indication of the individual one of the cells in the
matrix arrangement. The sources of the transistors 138 and 140 are
common with the V.sub.ssd line 85 also shown in FIG. 6. A binary
indication of the next column is introduced to the gates of the
transistors 138 and 139. The transistor 139 is included to provide
a symmetry between the transistors 136 and 139 and the transistors
138 and 140.
[0045] The output of the lap line 132 is inverted as at 135a to
provide a {overscore (lap)} signal on a line 137. The lap line 132
is connected to the drain of the transistor 114 and to the drain of
a transistor 142 which may be a CMOS transistor of the n-type. The
clock signal on the line 135 is applied to the gate of the
transistor 142. The source of the transistor 142 is common with the
drains of transistors 144 and 149 which may be CMOS transistors of
the n-type. A voltage representing the {overscore (next)}
{overscore (column)} in the cell is applied to the gates of the
transistors 144 and 149. The sources of the transistors 144 and 149
are applied to the drains of a pair of transistors 146 and 148,
both CMOS transistors of the n-type. The gates of the transistors
146 and 148 respectively receive the binary indications of the
{overscore (row)} and {overscore (column)} of the particular cell
in the matrix relationship shown in FIG. 4. The sources of the
transistors 146 and 148 are common with the V.sub.ssd ground line
85 also shown in FIG. 6. The transistor 149 is included to provide
symmetry between the transistors 144 and 149 and the transistors
146 and 148.
[0046] It should be appreciated that the circuitry shown in FIG. 9
decodes and latches a single cell in the matrix relationship shown
in FIG. 4. Similar decoding and latching circuitry is provided for
each of the other cells in the matrix relationship. When binary
indications of "1" are respectively applied to the gates of each of
the transistors 136, 138 and 140 to represent binary indications of
1 for the row and column in the cell and for the next column in the
matrix relationship, the transistors become conductive. This causes
a low voltage to be applied to the drain of the transistor 134.
Because of this, the transistor 134 becomes conductive when the
clock signal is applied to the gate of the transistor. A low
voltage is accordingly produced on the line 130. This low voltage
is latched by the latching circuit including the transistors 110,
112, 114 and 116 and is inverted as at 131 to provide a {overscore
(lan)} signal on the line 133.
[0047] When the binary indications of the row and column for a cell
in the matrix relationship are low and the binary indication of the
next column is also low to represent binary indications of 0 for
the row and column in the cell and for the next column in the
matrix relationship, the transistors 146, 148 and 144 respectively
become low. As a result, a low voltage is produced on the drain of
the transistor 144. The transistor 144 accordingly becomes
conductive when the clock signal is introduced on the line 135 to
the gate of the transistor. This causes a low voltage to be
produced on the lap line 132. This low voltage is latched by the
latching circuit including the transistors 110, 112, 114 and 116
and is inverted as at 135a to provide a high voltage on the line
137.
[0048] The combination of the decoder and the latch as shown in
FIG. 9 and as described above offers certain advantages over the
prior art, particularly when combined with the clock signal on the
line 135. This combination significantly reduces the ringing
indicated at 94 in FIG. 7. It results in part from the fact that
the clock signal is introduced to the gates of the transistors 134
and 142 at a time when the binary indications on the gates of the
transistors 136, 138, 139 and 140 and the gates of the transistors
144, 146, 148 and 149 have settled to a steady state value such as
at the middle of the time periods shown in FIG. 7.
[0049] FIG. 10 shows a current source and switches included in one
embodiment of the invention for reducing cross talk between digital
circuits and analog circuits in FIG. 10. The current source and the
switches are generally indicated at 160 in FIG. 10. The circuitry
160 operates to inhibit ringing at the transitions 92 of the binary
indications shown in FIG. 7. The inhibition of the ringing at the
transitions 92 of the binary indications shown in FIG. 7 results in
part from the fact that all of the transistors in FIG. 10 are CMOS
transistors of the p-type.
[0050] CMOS transistors of the n type are disposed on the surface
of the substrate of an integrated circuit chip. Because they are at
the surface of the substrate, signals are able to pass through the
substrate between different circuits on the substrate. This
particularly occurs at the time of transitions from one signal to
another. On the other hand, CMOS transistors of the p type are
disposed in wells in the substrate. The disposition of the CMOS
transistors of the p type in wells inhibits signals such as at the
time of signal transitions from passing through the substrate
between different circuits on the substrate. As a result, the
inclusion of only CMOS transistors of the p type in the circuitry
significantly reduces the ringing indicated at 92 in FIG. 7. As
will be seen, all of the transistors shown in FIG. 10 are CMOS
transistors of the p type.
[0051] The circuitry 160 includes the V.sub.dda voltage line 71
also shown in FIG. 6. The source of a transistor 162 is connected
to the V.sub.dda line 71. A bias voltage is applied on a line 163
to the gate of the transistor 162. The drain of the transistor 162
is common with the source of a transistor 164. The gate of the
transistor 164 receives a bias voltage V.sub.bc on a line 165. A
connection is made from the drain of the transistor 164 to the
source of a transistor 166 having a gate and drain common with the
source of a transistor 168. The gate and drain of the transistor
168 are connected to the V.sub.ssa ground line 81 also shown in
FIG. 6.
[0052] The V.sub.dda voltage line 7 (also shown in FIG. 6) is also
connected to the source of a transistor 170 having its gate
connected to the voltage bias line 164. The drain of the transistor
170 and the source of a transistor 172 are common. The gate of the
transistor 172 receives the bias voltage V.sub.bc on the line 165.
A connection is made from the drain of the transistor 172 to the
sources of a pair of transistors 174 and 176. The drains of the
transistors 174 and 176 are respectively connected to first
terminals of a pair of resistors 178 and 180. The other terminals
of the resistors 178 and 180 are connected to the V.sub.ssa ground
line 81 also shown in FIG. 6.
[0053] The voltage on the drain of the transistor 164 is applied to
the source of a transistor 182. The gate of the transistor 182
receives the {overscore (lan)} voltage on the line 133 in FIG. 9. A
connection is made from the drain of the transistor 182 to the gate
of the transistor 174 and to the source of a transistor 184. The
{overscore (lap)} voltage on the line 137 in FIG. 9 is applied to
the gate of the transistor 184. The drain of the transistor 184 is
connected to the drain of the transistor 166.
[0054] Circuitry including transistors 188 and 190 is associated
with the transistor 176 in a manner somewhat similar to the
association between the circuitry including the transistors 182 and
184 with the transistor 174. The source of the transistor 188 is
connected to the drain of the transistor 164. The gate of the
transistor 188 receives the lap voltage on the line 132. The
voltage on the drain of the transistor 188 is applied to the gate
of the transistor 176 and to the source of the transistor 190. The
drain of the transistor 190 is common with the drain and the gate
of the transistor 166.
[0055] The transistors 162, 164, 166 and 168 are connected in
series in a branch to provide reference voltages. For example, a
reference voltage such as approximately 2.7 volts is produced at
the drain of the transistor 164 and a reference voltage such as
approximately 1.2 volts is produced at the gate and the drain of
the transistor 166. Since the branch produces reference voltages,
the current through the transistors in the branch is preferably a
fraction--for example, one eighth (1/8) of the currents produced in
the branch formed by the transistors 170, 172, 174 and 176 and the
resistors 178 and 180 in FIG. 10.
[0056] Assume that the {overscore (lan)} voltage on the line 133 is
positive and that the {overscore (lap)} voltage on the line 137 is
negative. This will cause the transistor 190 to be non-conductive
and the transistor 188 to be conductive. The resultant current
through the transistor 188 will cause a voltage drop to be produced
across the transistor. This will cause the voltage (e.g. 2.1 volts)
on the gate of the transistor 176 to be lower than the voltage
(e.g. 2.7 volts) on the source of the transistor. The resultant
state of conductivity in the transistor 176 causes current to flow
through a circuit including the V.sub.dda line 160, the transistors
170, 172 and 176, the resistance 180 and the V.sub.ssa line 81.
[0057] The current flow through the resistance 180 is substantially
constant as a result of the substantially constant bias applied on
the line 163 to the gate of the transistor 170. The bias applied on
the line 165 to the gate of the transistor 172 causes a high
impedance to be produced in the transistor. This high impedance
compensates for differences in the cumulative current through the
transistor at different times. These differences result from the
fact that (1) the resistance 180 receives the current flowing
through a number of current sources corresponding to the current
source 160 and (2) the number of current sources applying current
to the resistance 180 varies at each instant depending upon the
relative {overscore (lan)} and {overscore (lap)} voltages applied
to such current sources from an individual one of the cells in the
matrix relationship. The current in the resistance 180 at each
instant is an accumulation of the constant currents in the
different cells in the matrix where the value of the {overscore
(lap)} voltage on the line 137 is negative and the value of the
{overscore (lan)} voltage on the line 133 is positive.
[0058] In like manner, when the {overscore (lap)} voltage on the
line 137 is positive and the {overscore (lan)} voltage on the line
133 is negative, the transistor 184 does not conduct and the
transistor 182 is conductive. The resultant flow of current through
the transistor 182 produces a voltage drop in the transistor. This
causes the voltage (e.g. 2.1 volts) on the gate of the transistor
174 to be lower than the voltage (e.g. 2.7 volts) on the source of
the transistor. A substantially constant current flows through a
circuit including the resistance 178 and the transistors 170, 172
and 174. The current in the resistance 178 at each instant is an
accumulation of the constant currents in the different cells in the
matrix where the value of the {overscore (lap)} voltage on the line
137 is positive and the value of the {overscore (lan)} voltage on
the line 133 is negative.
[0059] The circuitry shown in FIGS. 9 and 10 provides an accurate
conversion of binary indications of the cells in a matrix
relationship to an accurate analog value. The circuitry shown in
FIG. 9 significantly reduces the ringing 94 during the binary
indications 90 in FIG. 7. The circuitry shown in FIG. 10
significantly reduces the ringing 92 at the time of the transitions
between the binary indications 90 in FIG. 7.
[0060] Although this invention has been disclosed and illustrated
with reference to particular embodiments, the principles involved
are susceptible for use in numerous other embodiments which will be
apparent to persons of ordinary skill in the art. The invention is,
therefore, to be limited only as indicated by the scope of the
appended claims.
* * * * *