U.S. patent application number 09/899036 was filed with the patent office on 2001-11-15 for i/o interface circuit, semiconductor chip and semiconductor system.
Invention is credited to Urakawa, Yukihiro.
Application Number | 20010040471 09/899036 |
Document ID | / |
Family ID | 17014036 |
Filed Date | 2001-11-15 |
United States Patent
Application |
20010040471 |
Kind Code |
A1 |
Urakawa, Yukihiro |
November 15, 2001 |
I/O interface circuit, semiconductor chip and semiconductor
system
Abstract
A push-pull output buffer contained in an I/O interface circuit
of the present invention comprises a P channel MOSFET and a N
channel MOSFET. The P channel MOSFET is connected between an I/O
node connected to an external circuit through a transmission path
and a first potential node to which a first potential is applied.
The N channel MOSFET is connected between a second potential node
to which a second potential is applied and the I/O node. On/off
status of the P channel MOSFET and N channel MOSFET are controlled
depending on an input mode for inputting a signal from an external
circuit and an output mode for outputting a signal to the external
circuit through a transmission path. In this I/O interface circuit,
the first and second potentials are terminating potentials, and
when input mode is selected, out of the P channel MOSFET and N
channel MOSFET, the MOSFET connected to a potential node to which a
terminating potential is applied is controlled to be always on.
Inventors: |
Urakawa, Yukihiro;
(Kanagawa-ken, JP) |
Correspondence
Address: |
Johnny A. Kumar
FOLEY & LARDNER
Washington Harbour
3000 K Street, N.W., Suite 500
Washington
DC
20007-5109
US
|
Family ID: |
17014036 |
Appl. No.: |
09/899036 |
Filed: |
July 6, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09899036 |
Jul 6, 2001 |
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09146034 |
Sep 2, 1998 |
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6278300 |
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Current U.S.
Class: |
327/112 |
Current CPC
Class: |
H03K 19/018592
20130101 |
Class at
Publication: |
327/112 |
International
Class: |
H03B 001/00 |
Foreign Application Data
Date |
Code |
Application Number |
Sep 2, 1997 |
JP |
P09-237346 |
Claims
What is claimed is:
1. An I/O interface circuit comprising a push-pull output buffer
having: a first driving element connected between an I/O node
connected to an external circuit through a transmission path and a
first potential node to which a first potential is applied; and a
second driving element connected between a second potential node to
which a second potential is applied and said I/O node, wherein
on/off status of said first and second driving elements are
controlled corresponding to an input mode for inputting a signal
from said external circuit and an output mode for outputting a
signal to said external circuit through said transmission path,
said I/O interface circuit being further so constructed that said
first or second potential is terminal potential and when said input
mode is selected, a driving element connected to a potential node
to which the terminal potential is applied, of said first and
second driving elements, is controlled so as to be turned on.
2. An I/O interface circuit comprising: a push-pull output buffer
supplied with first and second potentials and having an output node
connected to an external circuit through a transmission path; and a
switch element connected between the output node of said push-pull
output buffer and a third potential which is a terminal potential,
wherein when input mode for inputting a signal from said external
circuit through said transmission path is selected, said switch
element is controlled so as to be turned on.
3. An I/O interface circuit comprising: first and second push-pull
buffers each supplied with first and second potentials and each
having output node connected to an external circuit through first
and second transmission paths; a switch element connected between
output nodes of said first and second push-pull output buffers,
wherein when input mode for inputting a signal from said external
circuit through said first and second transmission paths is
selected, said switch element is controlled so as to be turned
on.
4. A semiconductor chip comprising: said I/O interface circuit
according to claim 1; a replica of said push-pull output buffer
according to claim 1; an impedance element on a board, connected
between an external pin connected to an output end of said replica
and said second potential; a first element impedance determining
means for comparing a potential appearing in said external pin to
which said impedance element is connected, with an output logic
potential of said reference potential generating circuit and for
determining an impedance value of the first driving element in said
push-pull output buffer according to a result of the comparison;
and a second element impedance determining means for comparing an
output logic potential of said transmission path with the output
logic potential of said reference potential generating circuit and
for determining an impedance value of the second driving element in
said push-pull output buffer according to a result of the
comparison.
5. A semiconductor chip according to claim 4 wherein an impedance
of said impedance element is equal to an impedance of said
transmission path.
6. A semiconductor system comprising: a plurality of semiconductor
chips according to claim 4, connected through said transmission
path; and a control means for controlling an output impedance of
said plurality of the semiconductor chips according to claim 4 so
as to match with an impedance of said transmission path.
7. A semiconductor system according to claim 6 wherein said control
means is a sequencer for executing impedance matching at the time
of boot and at a predetermined time.
8. A semiconductor chip comprising: said I/O interface circuit
according to claim 2; a replica of said push-pull output buffer
according to claim 2; a reference potential generating circuit for
generating an output logic potential; an impedance element on a
board, connected between an external pin connected to an output end
of said replica and said second potential; a first element
impedance determining means for comparing a potential appearing in
said external pin to which said impedance element is connected,
with an output logic potential of said reference potential
generating circuit and for determining an impedance value of a
driving element connected to a potential node supplied with said
first potential in said push-pull output buffer according to a
result of the comparison; and a second element impedance
determining means for comparing an output logic potential of said
transmission path with an output logic potential of said reference
potential generating circuit and for determining an impedance value
of a driving element connected to a potential node supplied with
said second potential in said push-pull output buffer according to
a result of the comparison.
9. A semiconductor chip according to claim 8 wherein an impedance
of said impedance element is equal to an impedance of said
transmission path.
10. A semiconductor system comprising: a plurality of semiconductor
chips according to claim 8, connected through said transmission
path; and a control means for controlling an output impedance of
said plurality of the semiconductor chips according to claim 8 so
as to match with an impedance of said transmission path.
11. A semiconductor system according to claim 10 wherein said
control means is a sequencer for executing impedance matching at
the time of boot and at a predetermined time.
12. A semiconductor chip comprising: said I/O interface circuit
according to claim 3; a replica of said first and second push-pull
output buffer according to claim 3; a reference potential
generating circuit for generating an output logic potential; an
impedance element on a board, inserted between an external pin
connected to an output end of said replica and said second
potential; and an element impedance determining means for comparing
a potential appearing in said external pin to which said impedance
element is connected, with an output logic potential of said
reference potential generating circuit and for determining an
impedance value of a driving element connected to a potential node
supplied with said first potential in said first and second
push-pull output buffers according to a result of the
comparison.
13. A semiconductor chip according to claim 12 wherein an impedance
of said impedance element is equal to an impedance of said
transmission path.
14. A semiconductor system comprising: a plurality of semiconductor
chips according to claim 12, connected through said transmission
path; and a control means for controlling an output impedance of
said plurality of the semiconductor chips according to claim 12 so
as to match with an impedance of said transmission path.
15. A semiconductor system according to claim 14 wherein said
control means is a sequencer for executing impedance matching at
the time of boot and at a predetermined time.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] This invention relates to an I/O interface circuit capable
of carrying out rapid data transmission, a semiconductor chip
having this I/O interface circuit and a semiconductor system
provided with a plurality of the semiconductor chips.
[0003] 2. Description of the Prior Art
[0004] In recent years, the performance of high-performance LSI
such as a micro processor has been rising rapidly. This rise of the
performance is supported by application of high frequency internal
clock by process scaling or introduction of pipeline method.
[0005] On the other hand, currently, signal transmission between
chips cannot meet this application of high frequency internal clock
inside the chip sufficiently. In a conventional TTL/LV-TTL I/O
interface, signal transmission with high frequency wave of more
than 100 MHz is difficult to realize due to crosstalk, simultaneous
signal switching noise (SSN), reflection of signal in transmission
path and the like. Therefore, the TTL/LV-TTL interface and the like
is a bottleneck of the performance of a high performance LSI.
[0006] If the signal transmission speed between the chips is not
increased, a trend of multiple pins is indispensable for securing a
band width, so that this largely influence production, mounting
work, and board cost. Therefore, in the high-performance LSI field,
an I/O interface capable of high speed signal transmission has been
introduced gradually.
[0007] FIGS. 1A-1C show a TTL/LV-TTL I/O interface which has been
generally used in a conventional art. FIG. 1A is a structure
diagram thereof, FIG. 1B is a potential waveform diagram upon "H"
level transmission, and FIG. 1C is a current waveform diagram upon
"H" level transmission.
[0008] When for example, "H" level is transmitted from a chip 110
of TTL to a chip 120 of LV-TTL through a transmission path 101, P
channel MOSFET 112 and N channel MOSFET 113 constituting an I/O
buffer 111 of the chip 110 are both turned on. As a result, current
flowing through the transmission path 101 changes as shown in FIG.
1C and with an convergence of current amount, the potential is
stabilized on VDDQ level as shown in FIG. 1B. Then, on the side of
the chip 120, the "H" level signal of the transmission path 101 is
received by a differential amplifier 121.
[0009] Because the side of the chip 120 in input mode becomes an
open end in this I/O interface, signal reflection occurs in the
transmission path 101 so that transmission waveform is distorted.
Further, because the logical amplitude is large, noise due to dI/dt
occurs in high speed operation. Thus, in the high speed I/O
interface, generally, the transmission path is terminated.
[0010] FIGS. 2A-2E show high speed interface circuits of
conventional various terminating types. FIG. 2A shows a GTL/RSL
interface, FIG. 2B shows a push-pull type HSTL interface, FIG. 2C
shows a SSTL interface, FIG. 2D shows a CTT interface and FIG. 2E
shows a LVDS interface.
[0011] Because terminating resistors 201, 301, 401, 501, 601 are
mounted on a board in the vicinity of the chip 2, if signal is
transmitted from the chip 1 to the chip 2, signal reflection at a
buffer portion of the chip 2 in input mode is suppressed. Further,
because dI/dt can be set small as well as the logical amplitude is
small, there does not occur much noise.
[0012] FIG. 3 is a structure diagram showing a conventional
high-speed interface circuit disclosed in Japanese Patent
Application Laid-Open No.8-204539.
[0013] In the same Figure, reference numeral 710 denotes a
transmission path, numerals 711-714 denote a terminating resistor,
numerals 720, 730, 740, 750 denote a chip, numeral 731 denotes a
resisting element control means, and numerals 732, 733 denote an on
chip terminating means comprising N-MOSFET.
[0014] Because in an open drain I/O interface circuit, a large
reflection occurs in the transmission path when that circuit is
driven from "L" level to "H" level, in this example, the signal
sending side is driven by a push-pull buffer (on chip terminating
resistor means 732, 733) complementarily so as to keep the sending
side chip end of the transmission path 710 from being open.
[0015] However, the above first conventional I/O interface circuit
has such a problem that a terminating resistor is required to be
provided on the board to prevent reflection by an open end thereby
producing a high cost.
[0016] Although in the respective examples shown in FIGS. 2A-2E,
the description is made on an assumption of transmission of a
signal in a single direction between two chips, in case of both-way
transmission of a signal between two chips, the terminating
resistor is required to be inserted in the vicinity of each chip
(parallel termination). This reason is that if signal transmission
is carried out from the chip 2 to the chip 1, the side of the chip
1 becomes an open end so that a distortion of waveform due to
reflection occurs. In such a parallel termination, in the
conventional example, two terminating resistors are needed on the
board.
[0017] Further, in an ordinary system, as well as a point-to-point
connection shown in the conventional example, branch/stub
connections each having a branch in transmission path have been
widely used. In this case, if the parallel termination is carried
out to prevent reflection by the open end, in the conventional
example, a same number of terminating resistors as that of chips
are required to be mounted on the board.
[0018] In the aforementioned patent case, the terminating resistors
711-714 on the transmission path cannot be removed.
[0019] As described above, if it is intended to realize a high
speed I/O interface circuit with terminating system according to
the conventional art, it is necessary to provide the terminating
resistors on the board. Thus, there is a problem in system cost and
the like.
SUMMARY OF THE INVENTION
[0020] Accordingly, the present invention has been made to solve
the above problem, and therefore an object of the invention is to
provide a low cost I/O interface circuit not necessitating the
provision of terminating resistor on a board. Another object of the
present invention is to provide a semiconductor chip capable of
automatically performing impedance matching between the push-pull
buffer and transmission path, and a semiconductor system loaded
with a plurality of the semiconductor chips.
[0021] To achieve the above object, there is provided an I/O
interface circuit comprising a push-pull output buffer having: a
first driving element connected between an I/O node connected to an
external circuit through a transmission path and a first potential
node to which a first potential is applied; and a second driving
element connected between a second potential node to which a second
potential is applied and the I/O node, wherein on/off status of the
first and second driving elements are controlled corresponding to
an input mode for inputting a signal from the external circuit and
an output mode for outputting a signal to the external circuit
through the transmission path, the I/O interface circuit being
further so constructed that the first or second potential is
terminal potential and when the input mode is selected, a driving
element connected to a potential node to which the terminal
potential is applied, of the first and second driving elements, is
controlled so as to be turned on.
[0022] According to the first aspect of the invention, because the
driving element connected to the potential node to which the
terminating potential of the push-pull output buffer in input mode
is applied is controlled so as to be always on, the driving element
acts as a terminating element on the transmission path thereby
absorbing a reflection of a signal on the transmission path.
[0023] Further, to achieve the above object, there is provided an
I/O interface circuit comprising: a push-pull output buffer
supplied with first and second potentials and having an output node
connected to an external circuit through a transmission path; and a
switch element connected between the output node of the push-pull
output buffer and a third potential which is a terminal potential,
wherein when input mode for inputting a signal from the external
circuit through the transmission path is selected, the switch
element is controlled so as to be turned on.
[0024] According to the second aspect of the invention, because the
switch connected to the terminal potential is controlled so as to
be on when input mode is selected, the transmission path is
terminated thereby a reflection of a signal on the transmission
path being absorbed.
[0025] Further, to achieve the above object, there is provided an
I/O interface circuit comprising: first and second push-pull
buffers each supplied with first and second potentials and each
having output node connected to an external circuit through first
and second transmission paths; a switch element connected between
output nodes of the first and second push-pull output buffers,
wherein when input mode for inputting a signal from the external
circuit through the first and second transmission paths is
selected, the switch element is controlled so as to be turned
on.
[0026] According to the third aspect of the invention, because the
switch element connected between the output nodes of the two
push-pull output buffers is controlled so as to be on when input
mode is selected, the transmission path is terminated thereby a
reflection of signal on the transmission path being absorbed.
[0027] Further, to achieve the above object, there is provided a
semiconductor chip comprising: the I/O interface circuit according
to the first aspect; a replica of the push-pull output buffer
according to the first aspect; an impedance element on a board,
connected between an external pin connected to an output end of the
replica and the second potential; a first element impedance
determining means for comparing a potential appearing in the
external pin to which the impedance element is connected, with an
output logic potential of the reference potential generating
circuit and for determining an impedance value of the first driving
element in the push-pull output buffer according to a result of the
comparison; and a second element impedance determining means for
comparing an output logic potential of the transmission path with
the output logic potential of the reference potential generating
circuit and for determining an impedance value of the second
driving element in the push-pull output buffer according to a
result of the comparison.
[0028] According to the fourth aspect, an impedance value of a
first driving element in the push-pull output buffer is determined
using an impedance element on the board, connected between the
external pin and second potential. Further, an output logical
potential of the transmission path is monitored and an impedance
value of a second driving element in the push-pull output buffer is
determined. As a result, an impedance value of a driving element of
the push-pull output buffer can be controlled so as to generate an
appropriate output potential.
[0029] According to a preferred embodiment of the present
invention, an impedance of the impedance element is equal to an
impedance of the transmission path.
[0030] Further, to achieve the above object, there is provided a
semiconductor system comprising: a plurality of semiconductor chips
according to the fourth aspect, connected through the transmission
path; and a control means for controlling an output impedance of
the plurality of the semiconductor chips according to the fourth
aspect so as to match with an impedance of the transmission
path.
[0031] According to a preferred embodiment of the present
invention, the control means is a sequencer for executing impedance
matching at the time of boot and at a predetermined time.
[0032] Further, to achieve the above object, there is provided a
semiconductor chip comprising: the I/O interface circuit according
to the second aspect; a replica of the push-pull output buffer
according to the second aspect; a reference potential generating
circuit for generating an output logic potential; an impedance
element on a board, connected between an external pin connected to
an output end of the replica and the second potential; a first
element impedance determining means for comparing a potential
appearing in the external pin to which the impedance element is
connected, with an output logic potential of the reference
potential generating circuit and for determining an impedance value
of a driving element connected to a potential node supplied with
the first potential in the push-pull output buffer according to a
result of the comparison; and a second element impedance
determining means for comparing an output logic potential of the
transmission path with an output logic potential of the reference
potential generating circuit and for determining an impedance value
of a driving element connected to a potential node supplied with
the second potential in the push-pull output buffer according to a
result of the comparison.
[0033] According to the sixth aspect of the invention, in the
interface state of the second aspect, the same impedance automatic
adjustment function as the fourth aspect is exerted.
[0034] According to a preferred embodiment of the invention, the
impedance of the impedance element is equal to an impedance of the
transmission path.
[0035] Further, to achieve the above object, there is provided a
semiconductor system comprising: a plurality of semiconductor chips
according to the sixth aspect, connected through the transmission
path; and a control means for controlling an output impedance of
the plurality of the semiconductor chips according to the sixth
aspect so as to match with an impedance of said transmission
path.
[0036] According to a preferred embodiment of the invention, the
control means is a sequencer for executing impedance matching at
the time of boot and at a predetermined time.
[0037] Further, to achieve the above object, there is provided a
semiconductor chip comprising: the I/O interface circuit according
to the third aspect; a replica of the first and second push-pull
output buffer according to the third aspect; a reference potential
generating circuit for generating an output logic potential; an
impedance element on a board, inserted between an external pin
connected to an output end of the replica and said second
potential; and an element impedance determining means for comparing
a potential appearing in the external pin to which the impedance
element is connected, with an output logic potential of the
reference potential generating circuit and for determining an
impedance value of a driving element connected to a potential node
supplied with the first potential in the first and second push-pull
output buffers according to a result of the comparison.
[0038] According to the eight aspect of the invention, in the
interface state of the third aspect, the same impedance automatic
adjustment function as the fourth aspect is exerted.
[0039] According to a preferred embodiment of the present
invention, an impedance of the impedance element is equal to an
impedance of the transmission path.
[0040] Further, to achieve the above object, there is provided a
semiconductor system comprising: a plurality of semiconductor chips
according to the eighth aspect, connected through the transmission
path; and a control means for controlling an output impedance of
the plurality of the semiconductor chips according to the eighth
aspect so as to match with an impedance of the transmission
path.
[0041] According to a preferred embodiment of the invention, the
control means is a sequencer for executing impedance matching at
the time of boot and at a predetermined time.
[0042] The nature, principle and utility of the invention will
become more apparent from the following detailed description when
read in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0043] In the accompanying drawings:
[0044] FIGS. 1A-1C are structure diagrams showing a conventional
I/O interface circuit, etc.;
[0045] FIGS. 2A-2E are structure diagrams showing high speed
interface circuits of conventional various terminating systems;
[0046] FIG. 3 is a structure diagram showing a high speed interface
circuit disclosed in Japanese Patent Application Laid-Open
No.8-204539;
[0047] FIG. 4 is a circuit diagram showing a push-pull type HSTL
interface according to a first embodiment of the present
invention;
[0048] FIG. 5 is a diagram showing an example of a SSTL
interface;
[0049] FIG. 6 is a circuit diagram showing an I/O interface circuit
according to a second embodiment of the present invention;
[0050] FIG. 7 is a circuit diagram showing an I/O interface circuit
according to a third embodiment of the present invention;
[0051] FIG. 8 is a circuit diagram showing an I/O interface circuit
according to a fourth embodiment of the present invention;
[0052] FIG. 9 is a major part circuit diagram showing a
semiconductor system according to a fifth embodiment of the present
invention; and
[0053] FIG. 10 is a sequence diagram of a case in which the fifth
embodiment is applied to branch/stub connection of three chips.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0054] Hereinafter, the embodiment of the present invention will be
described with reference to the drawings. FIG. 4 is a structure
diagram showing an I/O interface circuit (push-pull type HST
interface) according to a first embodiment of the present
invention.
[0055] In this embodiment, for simplification of description, it is
assumed that both-way, point-to-point data transmission is carried
out between two chips.
[0056] As shown in FIG. 4, a chip 1 and a chip 2 are connected to
each other through a transmission path 1 having impedance Z0.
According to the push-pull type HST interface of the embodiment,
the chip 1 contains a push-pull output buffer 10 for signal output
and a differential amplifier 20 for signal input. Likewise, the
chip 2 contains a push-pull output buffer 30 for signal output and
a differential amplifier 40 for signal input.
[0057] The push-pull output buffer 10 of the chip 1 comprises a
P-channel MOSFET 11 connected between an I/O node N1 to which an
end of the transmission path 1 is connected and VDDQ potential
(first potential) and a N-channel MOSFET 12 connected between
ground GND potential (second potential) and the aforementioned I/O
node N1.
[0058] Likewise, the push-pull output buffer 30 of the chip 2
comprises a P-channel MOSFET 31 connected between an I/O node N to
which the other end of the transmission path 1 is connected and
VDDQ potential and a N-channel MOSFET 32 connected between the
ground GND potential and the aforementioned I/O node N2.
[0059] A positive terminal (+) of the differential amplifier 20 is
connected to the I/O node N1 of the chip 1 and reference potential
Vref is applied to a negative terminal (-) thereof. Further, output
terminals of the differential amplifiers 20, 40 are connected to
internal circuits 1, 2 (not shown), respectively.
[0060] The FETs 11, 12 of the output buffer 10 of the chip 1 are
turned on/off by each control signal A, B and the FETs 31, 32 of
the output buffer 30 of the chip 2 are turned on/off by each
control signal C, D. According to the present invention, by
devising the control method of this output buffer, a
high-performance push-pull type HSTL interface is realized without
mounting a terminating element on a board.
[0061] Hereinafter, operations [A], [B] for data transmission
according to this embodiment will be described mainly about the
control method of the output buffers 10, 30.
[0062] [A] Data Transmission from the Chip 1 to the Chip 2
[0063] In case of data transmission from the chip 1 to the chip 2,
the output buffers 10, 30 of the chips 1, 2 are set to output mode
(active) and input mode (disabled) respectively.
[0064] In case of data transmission of logic "H", the control
signal A becomes "L" level and the control signal B becomes "H"
level. At the same time, the control signals C, D become "L" level.
As a result, the FETs 11, 12 of the output buffer 10 is turned on
while the FET 31 of the output buffer 30 is turned on and the FET
32 is turned off.
[0065] In case of data transmission of logic "L", the control
signal A becomes "H" level and the control signal B becomes "L"
level while the control signals C, D become "L" level. As a result,
the FETs 11, 12 of the output buffer 10 are turned off, while the
FET 31 of the output buffer 30 is turned on and the FET 32 is
turned off.
[0066] [B] Data Transmission from the Chip 2 to the Chip 1
[0067] In case of data transmission from the chip 2 to the chip 1,
the output buffers 10, 30 of the chips 1, 2 are set to input mode
and output mode, respectively.
[0068] In case of data transmission of logic "H", the control
signals A, B become "L" level. At the same time, the control signal
C becomes "L" level and the control signal D becomes "H" level. As
a result, the FET 11 of the output buffer 10 is turned on and the
FET 12 is turned off. The FETs 31, 32 of the output buffer 30 are
turned on.
[0069] In case of data transmission of logic "L", the control
signals A, B become "L" level while the control signal C becomes
"H" level and the control signal D becomes "L" level. As a result,
the FET 11 of the output buffer 10 is turned on and the FET 12 is
turned off. The FETs 31, 32 of the output buffer are both turned
off.
[0070] As state above, the pull-up element (FETs 11, 31) on the
side of a chip to be in input mode is always controlled to be on.
Consequently, by on-resistance of this pull-up element, the pull-up
element makes a role of a terminating element to the VDDQ of the
transmission path 1. That is, the chip side in input mode is
controlled not so as to be open.
[0071] Therefore, although a terminating resistor is required to be
attached to the board as a signal reflection preventing measure in
a conventional push-pull type HSTl interface described above,
according to this embodiment, the high-performance push-pull type
HSTL interface can be achieved without attaching this terminating
resistor.
[0072] Here, considering a reflection of signal in the transmission
path 1, it is desirable that the FETs 11, 12, 31, 32 of the output
buffers 10, 30 are matched with the transmission path 1 in terms of
impedance. In an ideal case, the output logical level and output
current are as follows.
[0073] That is, in case when the logic "H" is output, the output
potential (typical) is VDDQ and output current is 0. In case when
the logic "L" is output, the output potential (typical) is VDDQ/2
and output current is VDDQ/(2.times.Z0). Where Z0 is an impedance
of the transmission path 1.
[0074] In a word, in case of transmitting a signal in both ways
between two chips, it has been ideal to insert (parallel
termination) a terminating resistor in the vicinity of each chip
according to the conventional art. The reason is that in a case of
the aforementioned HSTL interface of FIG. 2B, when signal is
transmitted from the chip 2 to the chip 1, the chip 1 becomes an
open end so that a distortion of waveform is generated due to the
reflection. In the case of parallel termination, two terminating
resistors are needed on the board in the conventional art.
[0075] On the other hand, because according to this embodiment, the
data receiving side is always controlled so as to be terminated, no
terminating resistor is required on the transmission path. Further,
the output current can be reduced thereby making it possible to
suppress an increase of power.
[0076] If speaking of an effect of this output current reduction in
a concrete way, although the output current becomes 0 in this
embodiment as well as in the conventional example when the logic
"H" is output, when the logic "L" is output, it becomes
VDDQ/(2>Z0) in this embodiment while it becomes VDDQ/Z0 in the
conventional example.
[0077] Although the above description is on the premise that the
terminating potential is VDDQ, the terminating potential can be
GND. An operation of that case is as follows.
[0078] In case of transmitting data of the logic "H" from the chip
1 to the chip 2, the control signal A becomes "L" level and the
control signal B becomes "H" level. At the same time, the control
signals C, D become "H" level. As a result, the FETs 11, 12 of the
output buffer 10 are turned on, and the FET 31 of the output buffer
30 is turned off and the FET 32 is turned on.
[0079] In case of transmitting data of logic "L", the control
signal A becomes "H" level and the control signal B becomes "L"
level and at the same time, the control signals C, D become "H"
level. As a result, the FETs 11, 12 of the output buffer 10 are
both turned off, and the FET 31 of the output buffer 30 is turned
off and the FET 32 is turned on.
[0080] In case of transmitting data of logic "H" from the chip 2 to
the chip 1, the control signals A, B become "H" level. At the same
time, the control signal C becomes "L" level and the control signal
D becomes "H" level. As a result, the FET 11 of the output buffer
10 is turned off and the FET 12 is turned on. The FETs 31, 32 of
the output buffer 30 are both turned on.
[0081] In case of transmitting data of logic "L", the control
signals A, B become "H" level and at the same time, the control
signal C becomes "L" level and the control signal D becomes "H"
level. As a result, the FET 11 of the output buffer 10 is turned
off and the FET 12 is turned on. The FETs 31, 32 of the output
buffer 30 are turned off.
[0082] As described above, the pull-down elements (FETs 12, 32) of
the output buffer in input mode are controlled, so as to be always
on. Therefore, this pull-down element takes a role as a terminating
element to terminate the transmission line 1 to GND.
[0083] In this case, a relation between the output logical level
and output current is desired to be as follows. That is, in case
when the logic "H" is output, the output potential (typical) is
VDDQ/2 and output current is VDDQ/(2.times.Z0). In case when the
logic "L" is output, the output potential (typical) is GND and
output current is 0.
[0084] With SSTL interface in which a resistor Ro is inserted
between each transmission end and I/O nodes N1, N2 of each chip 1,
2 as shown in FIG. 5 as well, a high speed I/O interface can be
achieved by carrying out the same control without mounting any
terminating resistor on the board.
[0085] Next, a second embodiment of the present invention will be
described.
[0086] Although the first embodiment is an example of
point-to-point connection, in this embodiment, examples of branch
connection and stub connection will be described.
[0087] FIG. 6 is a structure diagram showing an I/O interface
circuit according to a second embodiment of the present
invention.
[0088] As shown in the same Figure, the chips 1, 2 and 3 are
connected to each of three ends of a transmission line 1A branched
to two ways at a mid-point through I/O nodes N1, N2, N3. An output
buffer 50 of the chip 3 connected to the I/O node N3 has the same
structure as the chips 1, 2 shown in FIG. 1. That is, this is
constituted in push-pull system of P channel MOSFET 51 and N
channel MOSFET 52. The FETs 51, 52 are turned on/off by the control
signals E and F respectively. Reference numeral 60 denotes a
differential amplifier of the chip 3.
[0089] Hereinafter, data transmission operations A, B, C of this
embodiment will be described mainly about control method of the
output buffers 10, 30, 50.
[0090] [A] Data Transmission from the Chip 1 to the Chips 2, 3
[0091] In case of data transmission from the chip 1 to the chips 2,
3, the output buffer 10 of the chip 1 is set to output mode and the
output buffers 30, 50 of the chips 2, 3 are set to input mode.
[0092] In case of data transmission of logic "H", the control
signal A becomes "L" level, the control signal B becomes "H" level
and the control signals C, D and control signals E, F become "L"
level. As a result, the FETs 11, 12 of the output buffer 10 are
turned on while the FET 31 of the output buffer 30 is turned on and
the FET 32 is turned off. Likewise, the FETs 51, 52 of the output
buffer 50 are turned on and off respectively.
[0093] In case of data transmission of logic "L", the control
signal A becomes "H" level and the control signal B becomes "L"
level. The others are the same as transmission of "H" level. As a
result, the FETs 11, 12 of the output buffer 10 are turned off. The
others are the same as transmission of "H" level.
[0094] [B] Data Transmission from the Chip 2 to the Chips 1, 3
[0095] In case of data transmission from the chip 2 to the chips 1,
3, the output buffer of the chip 2 is set to output mode and the
output buffers 10, 50 of the chips 1, 3 are set to input mode.
[0096] In case of data transmission of logic "H", the control
signals C, D become "L" level and "H" level. The other control
signals A, B and control signals E, F become "L" level. As a
result, the FETs 31, 32 of the output buffer 30 are turned on and
the FET 11 of the output buffer 10 is turned on and the FET 12 is
turned off. Likewise, the FETs 51, 52 of the output buffer 50 are
turned on and off respectively.
[0097] In case of data transmission of logic "L", the control
signal A becomes "L" level and control signal B becomes "H" level.
The others are the same as transmission of "H" level. As a result,
the FETs 31, 32 of the output buffer 30 are turned off and the
others are the same as transmission of "H" level.
[0098] [C] Data Transmission from the Chip 3 to the Chip 1, 2
[0099] In case of data transmission from the chip 3 to the chips 1,
2, the output buffer 50 of the chip 3 is set to output mode and the
output buffers 10, 30 of the chips 1, 2 are set to input mode.
[0100] In case of data transmission of logic "H", the control
signals E, F become "L" level and "H" level respectively, and the
other control signals A, B and C, D become "L" level. As a result,
the FETs 51, 52 of the output buffer 50 are turned on, and the FET
11 of the output buffer 10 is turned on and the FET 12 is turned
off. Likewise, the FETs 31, 32 of the output buffer 30 are turned
on and off respectively.
[0101] In case of data transmission of logic "L", the control
signals E, F become "H" level and "L" level respectively and the
others are the same as transmission of "H" level. As a result, the
FETs 51, 52 of the output buffer 50 are turned off and the others
are the same as transmission of "H" level.
[0102] By controlling the output buffer of the input mode chip so
that an element for outputting a potential at the terminating end
is turned on, parallel termination is possible in branch connection
of three or more chips.
[0103] To carry out parallel termination to prevent a reflection at
the open end, in the conventional example, the terminating
resistors are required to be mounted on the board in the same
quantity as that of the chips. However, according to this
embodiment, no terminating resistors are required to be mounted on
the board as described above.
[0104] To adjust the output level by impedance matching at the
transmission line end and hold an output logical level, the
impedance Z of the output "L" level drive FET needs to be such a
value obtained by a following formula.
Z=Z0/(n-1)
[0105] where:
[0106] n: number of chips
[0107] Z0: impedance of transmission line 1A
[0108] Further, output current I at that time can be obtained by a
following formula.
I=VDDQ.times.(n-1)/(2.times.Z0)
[0109] Although a case in which the terminated voltage is VDDQ has
been stated in the above description, it is permissible that the
GND is a terminal potential. A control at that time is evident from
the first embodiment, and therefore a description thereof is
omitted.
[0110] Next, a third embodiment of the present invention will be
described.
[0111] This embodiment applies a concept of the present invention
with the LVDS interface as its base.
[0112] FIG. 7 is a structure diagram showing an I/O interface
circuit according to the third embodiment of the present
invention.
[0113] As shown in the same Figure, the chips 1, 2 are connected to
each other through the transmission paths 1, 2 of the impedance Z.
As for the I/O interface circuit of this embodiment, the chip 1
comprises two push-pull output buffers 10, 10a and a differential
amplifier 20 for signal input. I/O nodes N1, N11 of the output
buffers 10, 10a are connected to a positive terminal and negative
terminal of the differential amplifier 20, respectively. An N
channel MOSFET 21 which is a switch element is connected between
the positive terminal and negative terminal.
[0114] The chip 2 has the same structure, containing two push-pull
output buffers 30, 30a, differential amplifier 40 for signal input,
and an N channel MOSFET 41 which is a switch element corresponding
to the aforementioned FET 21.
[0115] The FETs 11, 12 constituting the output buffer 10 of the
chip 1 are on/off controlled by control signals A1, B1 respectively
and the FETs 11a, 12a constituting an output buffer 10a are on/off
controlled by control signals A2, B2 respectively. The FETs 31, 32
constituting an output buffer 30 of the chip 2 are on/off
controlled by control signals C1, D1 respectively and the FETs 31a,
32a constituting an output buffer 30a are on/off controlled by
control signals C2, D2 respectively. The FETs 21, 41 are
switching-controlled by control signals J, K respectively.
[0116] Hereinafter, data transmission operations A, B of this
embodiment will be described mainly about control method of the
output buffers 10, 10a, 30, 30a.
[0117] [A] Data Transmission from the Chip 1 to the Chip 2
[0118] In case of data transmission from the chip 1 to the chip 2,
the output buffers 10, 10a of the chip 1 are set to output mode and
the output buffers 30, 30a of the chip 2 are set to input mode.
[0119] In case of data transmission of logic "H", the control
signals A1, B1 become "L" level and the control signals A2, B2
become "H" level and the control signal J becomes "L" level. At the
same time, the control signals C1, D1 become "H" level and "L"
level. The control signals C2, D2 become "H" level and "L" level
respectively, and the control signal K becomes "H" level.
[0120] As a result, the FETs 11, 12 of the output buffer 10 are
turned on and off respectively, and the FETs 11a, 12a of the output
buffer 10a are turned off and on respectively. On the other hand,
the FETs 31, 32, 31a, 32a of the output buffers 30, 30a are all
turned off.
[0121] The FET 21 of the chip 1 is turned off and the FET 41 of the
chip 2 is turned on.
[0122] On the other hand, in case of data transmission of logic
"L", the control signals A1, B1 and control signals A2, B2 are
reversed relative to transmission of "H" level and all other
control signals C1, D1, C2, D2, J, K are the same as transmission
of "H" level.
[0123] As a result, the FETs 11, 12 of the output buffer 10 are
turned off and on respectively, and the FETs 11a, 12a of the output
buffer 10a are turned on and off respectively. On the other hand,
the FETs 31, 32, 31a, 32a of the output buffers 30, 30a are all
turned off. The FET 21 of the chip 1 is turned off and the FET 41
of the chip 2 is turned on.
[0124] [B] Data Transmission from the Chip 1 to the Chip 2
[0125] In case of data transmission from the chip 2 to the chip 1,
the output buffers 10, 10a of the chip 1 are set to input mode and
the output buffers 30, 30a of the chip 2 are set to output
mode.
[0126] In case of data transmission of logic "H", the control
signals A1, B1 and control signals A2, B2 become "H" level and "L"
level respectively and the control signal J becomes "H" level. At
the same time, the control signals C1, D1 become "L" level and the
control signals C2, D2 become "H" level and the control signal K
becomes "L" level.
[0127] As a result, the FETs 11, 12, 11a, 12a of the output buffers
10, 10a are all turned off. On the other hand, the FETs 31, 32 of
the output buffer 30 become "H" level and "L" level respectively.
The FETs 31a, 32a of the output buffer 30a become "L" level and "H"
level respectively.
[0128] On the other hand, in case of data transmission of logic
"L", the control signals C1, D1 and control signals C2, D2 are
reversed relative to transmission of "H" level and all other
control signals A1, B1, A2, B2, J, K are the same as transmission
of "H" level.
[0129] As a result, the FETs 11, 12, 11a, 12a of the output buffers
10, 10a are all turned off. The FETs 31, 32 of the output buffer 30
are turned off and on respectively, and the FETs 31a, 32a of the
output buffer 30a are turned on and off respectively. Then, the FET
21 of the chip 1 is turned on and the FET 41 of the chip 2 is
turned off.
[0130] Because according to this embodiment, the FET 21 or 41 in
input mode is controlled so as to be turned on, the transmission
paths 1, 2 are terminated by this FET on-resistance. Therefore, it
is not necessary to mount a terminating resistor on the board.
[0131] According to this embodiment, even at the time of branch
connection or stub connection, a high speed LVDS-type I/O interface
can be achieved without mounting the terminating resistor on the
board by the same control as described above.
[0132] Next, a fourth embodiment of the present invention will be
described.
[0133] This embodiment applies a concept of the present invention
with the CTT interface as its base.
[0134] FIG. 8 is a structure diagram showing an I/O interface
circuit according to the fourth embodiment of the present
invention.
[0135] According to this embodiment, in a circuit shown in FIG. 4
of the first embodiment, a switch 71 is inserted between the I/O
node N1 and terminal potential VTT and likewise, a switch 72 is
inserted between the I/O node N2 of the chip 2 and terminal
potential VTT.
[0136] According to this embodiment, in case of data transmission
from the chip 1 to the chip 2 or from the chip 2 to the chip 1,
when the output buffers 10, 30 are in input mode, the switch
elements 71, 72 are turned on. As a result, the transmission path 1
is terminated, so that the terminating resistor is not required to,
be mounted on the board.
[0137] Next, a fifth embodiment of the present invention will be
described.
[0138] As described above, considering a reflection of signal in
the transmission path, it is desirable that the push-pull
transistor of each output buffer is matched with the transmission
path in impedance. This embodiment shows an example of an I/O
interface circuit of the first embodiment containing an automatic
impedance adjusting function for automatically matching in the
impedance.
[0139] FIG. 9 shows a major part structure diagram showing a
semiconductor system according to the fifth embodiment.
[0140] This semiconductor system has the chips 1, 2. The chips 1, 2
are connected to each other by a plurality of transmission paths
93-0, 93-1, . . . through external pins 91-0, 91-1, . . . , 92-0,
92-1, . . . .
[0141] The I/O interface circuit of the chip 1 respectively
contains output buffer portions 80-0, 80-1, . . . respectively
connected to the external pins 91-0, 91-1, . . . . The output
buffer portions 80-0, 80-1, . . . comprise output buffers in which
plural P channel MOSFETs (MP0, MP1, MPi-1, MPi) and plural N
channel MOSFETs (MN0, MN1, NNj-1, MNj) are push-pull connected, and
driving circuits 81, 82 for driving the P-MOSFETs(MP0-MPi) and
N-MOSFETs (NMO-MNj).
[0142] As for the size of the MOSFET, if the sizes of MPk, MNk of k
MOSFET are WP(k) and WN(k), the size of the MOSFET can be expressed
according to a following formula with reference to the size WP(0),
WN(0) of the MP0, MN0 which are minimum size MOSFETs.
WP(k)=2.sup.k.times.WP(0) (k=0, 1, . . . I)
WN(k)=2.sup.k.times.WN(0) (k=0, 1, . . . j )
[0143] On the other hand, the chip 1 has a replica 83 of the
aforementioned output buffer and a reference potential generating
circuit 88. The reference potential generating circuit 88 outputs a
logical "L" output (=VDDQ/2) VOL produced by dividing a resistance
in the chip. An external pin 94 is connected to the replica 83.
[0144] The terminal power supply is named VDDQ in the following
description. To ensure impedance matching, a resistor 95 equivalent
to the impedance of the transmission path is inserted between the
external pin 94 and ground GND on the board.
[0145] Then, by comparing a voltage produced in the external pin 94
with an output potential VOL of the reference voltage generating
circuit 88, the counter 85 is counted up or down depending on which
is larger or smaller. Binary output SP of the counter 85 controls
active/inactive of the driving circuit 81 of the replica 83 and the
output buffers 80-0, 80-1, . . . . An effective size of the entire
P-MOSFET can be in a range of WP0.about.(2.sup.(i+1).times.WP0
(increments each WP0) because the size WP(k) of the k P-MOSFET is
expressed as shown above.
[0146] As a result, the P-MOSFET size of the output buffers 80-0,
80-1, . . . in which impedance matching of the transmission paths
93-0, 93-1, . . . is ensured, can be determined. Binary data SP
generated therein is stored in register A and transmitted to all
the output buffer portions 80-0, 80-1, . . . . The size of the
P-MOSFET is controlled/determined to be the same as the
replica.
[0147] Here, control signals DP0, DN0, DP1, DN1, . . . are supplied
from a control circuit (not shown) to the driving circuits 81, 82
of the output buffers 80-1, 80-1, and each output MOSFET is on/off
controlled depending on the input mode/output mode. When the input
mode is selected, the P-MOSFETs are turned on as described in the
first embodiment.
[0148] By carrying out the aforementioned operation for the chips
1, 2, the P-MOSFET serving as a pull-up driver of the output buffer
portions 80-0, 80-1, . . . further acts as a terminating resistor
to match with the transmission path in impedance.
[0149] Next, the size of the N-MOSFET will be adjusted. One of the
transmission path for connecting the chip 1 to the chip 2 is
defined as for reference. First, the chip 1 is adjusted. The chip 2
is set in input mode, and the reference of the chip 1 is set to
output "L" level.
[0150] Here, the output "L" level is compared with output potential
VOL of the reference potential generating circuit 88 by a
comparator 86 and a counter 87 is counted up or down depending on
which is larger or smaller. Binary output SN of the counter 87
controls active/inactive of the driving circuit 82 of each output
buffer portion 80-0, 80-1, . . . . An effective size of the entire
N-MOSFET can be in a range of WN0.about.(2.sup.(i+1)-1).times.WN0
(increments each WN0) because the size WN(k) of the k N-MOSFET is
expressed as shown in the above formula.
[0151] The binary data SN produced in this manner is stored in the
register B and transmitted to all the output buffer, and the size
of the N-MOSFET is controlled/determined to be the same as the
replica. As a result, the N-MOSFET size of the output buffer in
which impedance matching with the transmission path is ensured can
be determined.
[0152] By carrying out the above operation in the chip 2 as well,
impedance matching with the transmission path can be obtained in
all the chips.
[0153] Although this embodiment has been described only in a case
of two chips, a case of branch/stub connection can be achieved by
the same operation except that when the N-MOSFET size is
determined, all the chips than an object chip are set to input
mode. FIG. 10 shows an example of branch/stub connection of three
chips.
[0154] In the same Figure, an impedance element corresponding to a
resistor 95 of FIG. 9 is provided at each chip and impedance
matching of the P-MOSFET is carried out at each chip (step S1).
Next, the chip 1 is set to output mode and the chip 2, 3 are set to
input mode (step S2). Then, impedance matching of the N-MOSFET of
the chip 1 is carried out (step S3).
[0155] After that, the chip 2 is set to output mode and the chips
1, 3 are set to input mode (step S4). Then, impedance matching of
the N-MOSFET of the chip 2 is carried out (step S5).
[0156] Further, the chip 3 is set to output mode and the chips 1, 2
are set to input mode (step S6). Then, impedance matching of the
N-MOSFET of the chip 3 is carried out (step S7).
[0157] If the above sequence ends, the setting of the output
impedance is completed. Before an actual operation mode, the
reference potential is changed from logic L level (VDDQ/2) to
VDDQ.times.3/4.
[0158] Although the example of VDDQ termination has been taken in
this embodiment, it is permissible to terminate the GND end. At
this time, the size is determined in an order from the N-MOSFET to
the P-MOSFET.
[0159] By preparing a sequencer containing the above respective
operations in a chip, impedance matching can be ensured easily.
This can be executed at the time of system boot or during ordinal
operation, so that a high speed interface having an excellent
quality capable of coinciding with an operating environment can be
achieved.
[0160] Although this embodiment has been described taking a
push-pull HSTL-type interface as an example, it is needless to say
that impedance matching can be ensured easily so that a high
quality interface can be achieved if the same operation is carried
out in other terminating type interface.
[0161] As described above, according to the present invention, a
terminating type high speed I/O interface can be achieved without
mounting a terminating resistor on the board. As a result, system
cost can be reduced largely and output current can be reduced.
Therefore, power increase can be suppressed. At the time of
branch/stub connection, parallel termination can be achieved
easily.
[0162] Further, according to the present invention, an impedance of
a driving element of the push-pull output buffer can be controlled
so as to generate an appropriate output potential, so that a
high-quality, high-speed interface can be achieved. Further,
impedance matching corresponding to a system operating environment
can be executed.
[0163] It should be understood that many modifications and
adaptations of the invention will become apparent to those skilled
in the art and it is intended to encompass such obvious
modifications and changes in the scope of the claims appended
hereto.
* * * * *