U.S. patent application number 09/853661 was filed with the patent office on 2001-11-15 for electrode contact section of semiconductor device.
Invention is credited to Tanaka, Masahiro.
Application Number | 20010040255 09/853661 |
Document ID | / |
Family ID | 18648965 |
Filed Date | 2001-11-15 |
United States Patent
Application |
20010040255 |
Kind Code |
A1 |
Tanaka, Masahiro |
November 15, 2001 |
Electrode contact section of semiconductor device
Abstract
A p-type impurity layer is formed in an n-type semiconductor
substrate. Since the p-type impurity layer has a low impurity
concentration and a sufficiently shallow depth of 1.0 .mu.m or
less, the carrier injection coefficient can be reduced. In the
p-type impurity layer, a p-type contact layer of a high impurity
concentration is formed for reducing a contact resistance. Since
the p-type contact layer has a sufficiently shallow depth of 0.2
.mu.m or less, it does not influence the carrier injection
coefficient. Further, a silicide layer is formed between the p-type
contact layer and an electrode such that the contact-layer-side end
of the silicide layer corresponds to that portion of the p-type
contact layer, at which the concentration profile of the contact
layer assumes a peak value. The silicide layer further reduces the
contact resistance.
Inventors: |
Tanaka, Masahiro;
(Yokohama-shi, JP) |
Correspondence
Address: |
OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT PC
FOURTH FLOOR
1755 JEFFERSON DAVIS HIGHWAY
ARLINGTON
VA
22202
US
|
Family ID: |
18648965 |
Appl. No.: |
09/853661 |
Filed: |
May 14, 2001 |
Current U.S.
Class: |
257/342 ;
257/E29.036; 257/E29.086; 257/E29.109; 257/E29.146 |
Current CPC
Class: |
H01L 29/456 20130101;
H01L 29/36 20130101; H01L 29/167 20130101; H01L 29/083
20130101 |
Class at
Publication: |
257/342 |
International
Class: |
H01L 029/76 |
Foreign Application Data
Date |
Code |
Application Number |
May 15, 2000 |
JP |
2000-141914 |
Claims
What is claimed is:
1. An electrode contact section incorporated in a semiconductor
device, comprising: a first-conductivity-type semiconductor
substrate; a second-conductivity-type impurity layer formed in one
surface of the semiconductor substrate and having a thickness of
not more than 1.0 .mu.m from a surface of the semiconductor
substrate; a second-conductivity-type contact layer formed in the
impurity layer and having a thickness of not more than 0.2 .mu.m
from the surface of the semiconductor substrate, the contact layer
being thinner than the impurity layer and having a higher impurity
concentration than the impurity layer; and a first electrode formed
on the contact layer.
2. The electrode contact section according to claim 1, wherein the
impurity layer is provided for carrier injection from the impurity
layer to the semiconductor substrate, and the contact layer is
provided for reducing a contact resistance between the first
electrode and the impurity layer and not for carrier injection.
3. The electrode contact section according to claim 1, further
comprising a second electrode formed at another surface side of the
semiconductor substrate for allowing a current to flow between the
first and second electrodes.
4. The electrode contact section according to claim 3, wherein the
semiconductor device is an IGBT.
5. The electrode contact section according to claim 1, wherein the
impurity layer is formed in the entire one surface of the
semiconductor substrate.
6. The electrode contact section according to claim 1, wherein the
impurity layer is formed in a portion of the one surface of the
semiconductor substrate.
7. An electrode contact section incorporated in a semiconductor
device, comprising: a first-conductivity-type semiconductor
substrate; a second-conductivity-type impurity layer formed in one
surface of the semiconductor substrate; a second-conductivity-type
contact layer formed in the impurity layer, being thinner than the
impurity layer and having a higher impurity concentration than the
impurity layer; a first electrode formed on the contact layer; and
a silicide layer formed between the first electrode and the contact
layer, the silicide layer having a contact-layer-side end thereof
made to substantially correspond to that portion of the contact
layer, at which a concentration profile of the contact layer
assumes a peak value.
8. The electrode contact section according to claim 7, wherein the
impurity layer is provided for carrier injection from the impurity
layer to the semiconductor substrate, and the contact layer is
provided for reducing a contact resistance between the first
electrode and the impurity layer and not for carrier injection.
9. The electrode contact section according to claim 7, further
comprising a second electrode formed at another surface side of the
semiconductor substrate for allowing a current to flow between the
first and second electrodes.
10. The electrode contact section according to claim 9, wherein the
semiconductor device is an IGBT.
11. The electrode contact section according to claim 7, wherein the
impurity layer has a thickness of not more than 1.0 .mu.m from a
surface of the semiconductor substrate.
12. The electrode contact section according to claim 7, wherein the
contact layer has a thickness of not more than 0.2 .mu.m from a
surface of the semiconductor substrate.
13. The electrode contact section according to claim 7, wherein the
silicide layer has a thickness of not more than 0.2 .mu.m from a
surface of the semiconductor substrate, and is thinner than the
contact layer.
14. The electrode contact section according to claim 7, wherein the
impurity layer is formed in the entire one surface of the
semiconductor substrate.
15. The electrode contact section according to claim 7, wherein the
impurity layer is formed in a portion of the one surface of the
semiconductor substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2000-141914, filed May 15, 2000, the entire contents of which are
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to an electrode contact
section incorporated in a semiconductor device.
[0003] In the prior art, en electrode section incorporated in a
semiconductor device is formed of an impurity layer provided in a
semiconductor layer, and an electrode (made of, for example, a
metal such as aluminum) that is in contact with the impurity layer.
The impurity layer is often formed by ion implantation for the
purpose of low cost.
[0004] In the electrode contact section, it is important to reduce
the contact resistance of the electrode and the impurity layer. To
reduce the contact resistance, the concentration of an impurity in
the impurity layer is generally increased.
[0005] However, when forming an impurity layer by ion implantation,
the concentration profile of the impurity layer shows a curved line
with a peak. The impurity concentration of a surface portion of the
semiconductor layer is lower than a peak concentration assumed at
an inner portion thereof. In particular, in a longitudinal power
device such as an IGBT, there is a case where a MOS structure is
provided at one surface of a semiconductor layer, and an impurity
layer is provided at the other surface thereof. In this case, the
impurity layer at the other surface of the semiconductor layer
cannot be annealed at a high temperature for a long time, with the
result that the difference between the peak concentration and the
surface concentration of the impurity layer is increased, and hence
the contact resistance cannot sufficiently be reduced.
[0006] Further, in an IGBT (Insulated Gate Bipolar Transistor) as
shown in FIG. 1, for example, it is necessary to reduce the contact
resistance of an electrode contact section (a contact section
between the impurity layer 2 and an anode layer 3), and also to
quickly prevent carrier injection from an impurity layer
(p.sup.+-type emitter layer) 2 to an n.sup.+-type base layer 1 when
turning off the semiconductor device, in order to turn off the
device at high speed.
[0007] However, to reduce the contact resistance at the electrode
contact section, it is necessary to increase the impurity
concentration of the impurity layer 2. On the other hand, to
quickly turn off the semiconductor device, it is necessary to
reduce the impurity concentration of the impurity layer 2, and also
to make the impurity layer 2 shallow so as to reduce the
coefficient of carrier injection from the impurity layer 2 to the
n.sup.+-type base layer 1.
[0008] In other words, concerning the impurity concentration of the
impurity layer 2 at the electrode contact section, a reduction of
the contact resistance and an increase of the speed of the turn-off
of the semiconductor device (i.e. a reduction of the carrier
injection coefficient) is a tradeoff relationship. Accordingly,
these two purposes cannot be satisfied simultaneously.
BRIEF SUMMARY OF THE INVENTION
[0009] The present invention has been may provided an electrode
contact section of a sufficiently low contact resistance even when
forming an impurity layer by ion implantation. The invention has
been may provided an electrode contact section in which the contact
resistance and the carrier injection coefficient can simultaneously
be reduced.
[0010] According to an aspect of the invention, there is provided
an electrode contact section incorporated in a semiconductor
device, comprising: a first-conductivity-type semiconductor
substrate; a second-conductivity-type impurity layer formed in one
surface of the semiconductor substrate and having a thickness of
not more than 1.0 .mu.m from a surface of the semiconductor
substrate; a second-conductivity-type contact layer formed in the
impurity layer and having a thickness of not more than 0.2 .mu.m
from the surface of the semiconductor substrate, the contact layer
being thinner than the impurity layer and having a higher impurity
concentration than the impurity layer; and a first electrode formed
on the contact layer.
[0011] According to another aspect of the invention, there is
provided an electrode contact section incorporated in a
semiconductor device, comprising: a first-conductivity-type
semiconductor substrate; a second-conductivity-type impurity layer
formed in one surface of the semiconductor substrate; a
second-conductivity-type contact layer formed in the impurity
layer, being thinner than the impurity layer and having a higher
impurity concentration than the impurity layer; a first electrode
formed on the contact layer; and a silicide layer formed between
the first electrode and the contact layer, the silicide layer
having a contact-layer-side end thereof made to substantially
correspond to that portion of the contact layer, at which a
concentration profile of the contact layer assumes a peak
value.
[0012] Additional objects and advantages of the invention will be
set forth in the description which follows, and in part will be
obvious from the description, or may be learned by practice of the
invention. The objects and advantages of the invention may be
realized and obtained by means of the instrumentalities and
combinations particularly pointed out hereinafter.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0013] The accompanying drawings, which are incorporated in and
constitute a part of the specification, illustrate presently
preferred embodiments of the invention, and together with the
general description given above and the detailed description of the
preferred embodiments given below, serve to explain the principles
of the invention.
[0014] FIG. 1 is a sectional view illustrating an IGBT to which the
present invention is applied;
[0015] FIG. 2 is a view illustrating an electrode contact section
incorporated as an example in a semiconductor device according to
the invention;
[0016] FIG. 3 is a view illustrating an electrode contact section
incorporated as a second example in a semiconductor device
according to the invention;
[0017] FIG. 4 is a sectional view illustrating an IGBT to which the
present invention is applied;
[0018] FIG. 5 is a sectional view illustrating an IGBT structure as
a first example according to the invention;
[0019] FIG. 6 is a sectional view illustrating an IGBT structure as
a second example according to the invention;
[0020] FIG. 7 is a sectional view illustrating an IGBT to which the
present invention is applied;
[0021] FIG. 8 is a sectional view illustrating an IGBT structure as
a third example according to the invention;
[0022] FIG. 9 is a sectional view illustrating an IGBT structure as
a fourth example according to the invention;
[0023] FIG. 10 is a sectional view illustrating an IGBT to which
the present invention is applied;
[0024] FIG. 11 is a sectional view illustrating an IGBT structure
as a fifth example according to the invention;
[0025] FIG. 12 is a sectional view illustrating an IGBT structure
as a sixth example according to the invention; and
[0026] FIG. 13 is a graph illustrating the characteristics of an
IGBT according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0027] Electrode contact sections each incorporated in a
semiconductor device according to the present invention will be
described in detail with reference to the accompanying
drawings.
[0028] [A] First Electrode Contact Section
[0029] FIG. 2 shows an electrode contact section incorporated as an
example in a semiconductor device according to the invention.
[0030] As shown, a p-type impurity layer 2 is formed in an n-type
semiconductor substrate 1. The n-type semiconductor layer 1
contains an n-type impurity such as phosphor (P) with a
substantially constant concentration of approx. 10.sup.14
ions/cm.sup.3. The p-type impurity layer 2 is formed in a surface
area of the semiconductor substrate 1 and contains a p-type
impurity such as boron (B). The depth of the p-type impurity layer
2 from the surface of the semiconductor substrate 1 is set at 1.0
.mu.m or less, for example, approx. 0.8 .mu.m. Further, the peak
value of the concentration profile of the p-type impurity layer 2
is set at a value falling within the range of 10.sup.17-10.sup.18
ions/cm.sup.3.
[0031] A p.sup.+-type contact layer 4 is formed in the p-type
impurity layer 2, and an electrode 3 is formed on the p.sup.+-type
contact layer 4. The p.sup.+-type contact layer 4 is thus
interposed between the p-type impurity layer 2 and the electrode 3
and has a higher impurity concentration than the p-type impurity
layer 2. For example, the p.sup.+-type contact layer 4 contains a
p-type impurity such as boron (B) or boron fluoride (BF.sub.2),
etc., and has an impurity concentration peak value of 10.sup.19
ions/cm.sup.3 or more and a surface impurity concentration of
10.sup.18 ions/cm.sup.3 or more. The depth of the p.sup.+-type
contact layer 4 from the surface of the semiconductor substrate 1
is set at 0.2 .mu.m or less, for example, approx. 0.16 .mu.m. The
electrode 3 is formed of, for example, aluminum.
[0032] In the above-described electrode contact structure, the
p-type impurity layer 2 has a low impurity concentration, and a
sufficiently shallow depth of 1.0 .mu.m or less from the surface of
the semiconductor substrate 1. Accordingly, when this electrode
contact structure is applied to the collector (anode) electrode of
an IGBT, the coefficient of carrier (positive hole) injection at
the time of turning off the semiconductor device can be reduced,
thereby increasing the speed of the turn-off operation.
[0033] Further, as described above, the p.sup.+-type contact layer
4 having a higher impurity concentration than the p-type impurity
layer 2 is provided between the p-type impurity layer 2 and the
electrode 3. Since the depth of the p.sup.+-type contact layer 4
from the surface of the semiconductor substrate 1 is set at 0.2
.mu.m or less, the p.sup.+-type contact layer 4 does not influence
the carrier injection coefficient at the time of turning off the
semiconductor device. In other words, the p.sup.+-type contact
layer 4 does not increase the carrier injection coefficient.
[0034] Moreover, since the p.sup.+-type contact layer 4 has a
sufficiently high impurity concentration, the contact resistance at
the electrode contact section can be reduced.
[0035] As described above, the electrode contact section of the
invention can have a sufficiently low contact resistance, and
simultaneously realize a low carrier injection coefficient when
turning off the semiconductor device.
[0036] Although in the above example, the semiconductor substrate 1
is of the n-type and the impurity layer 2 and the p.sup.+-type
contact layer 4 are of the p-type, a similar advantage can be
obtained if the semiconductor substrate 1 is made to be of the
p-type and the impurity layer 2 and the p.sup.+-type contact layer
4 are made to be of the n-type.
[0037] A description will now be given of a method for
manufacturing the electrode contact section shown in FIG. 2.
[0038] First, an n-type semiconductor substrate (e.g. a silicon
substrate) 1 having, for example, an impurity concentration of
approx. 1.5.times.10.sup.14 ions/cm.sup.2 is prepared. A p-type
impurity such as boron (B) is implanted into the semiconductor
substrate by ion implantation. At this time, the acceleration
voltage and the dose, as implantation conditions, are set at, for
example, approx. 60 keV and approx. 1.times.10.sup.13
ions/cm.sup.2, respectively. Thereafter, the resultant structure is
subjected to a thermal diffusion process executed in the atmosphere
of nitrogen of approx. 1050.degree. C. for approx. 20 min. As a
result, a p-type impurity layer (e.g. a p-type emitter layer) 2
having a depth of approx. 0.8 .mu.m from the surface of the
semiconductor substrate 1 is formed.
[0039] Subsequently, a p-type impurity such as boron (B) is
implanted into the p-type impurity layer 2 in the semiconductor
substrate 1 by ion implantation. At this time, the acceleration
voltage and the dose, as implantation conditions, are set at, for
example, approx. 10 keV and approx. 1.times.10.sup.14
ions/cm.sup.2, respectively. After that, the resultant structure is
subjected to a thermal diffusion process executed in the atmosphere
of nitrogen of approx. 800.degree. C. for approx. 30 min. As a
result, a p.sup.+-type contact layer 4 having a depth of approx.
0.16 .mu.m from the surface of the semiconductor substrate 1 is
formed.
[0040] The p.sup.+-type contact layer 4 must be formed very
shallow, and must have a very high impurity concentration. To this
end, the acceleration voltage is set low, the dose is set high, and
the period for executing the thermal diffusion process is set
short, as is described above.
[0041] Boron fluoride (BF.sub.2), for example, may be used as the
p-type impurity, instead of boron (B) (i.e. the element is changed
from a light one to a heavy one), and implanted into the p-type
impurity layer 2 in the semiconductor substrate 1, thereby forming
a p.sup.+-type contact layer 4.
[0042] Subsequently, a thermal oxide film formed on a surface
portion of the semiconductor substrate 1, i.e. on a surface portion
of the p.sup.+-type contact layer 4, is removed using antimony
fluoride. After that, the electrode 3 made of a metal such as
aluminum is provided on the p.sup.+-type contact layer 4 by
sputtering or CVD.
[0043] Thereafter, the resultant structure is subjected to a heat
treatment executed for approx. 30 min. in the atmosphere of
nitrogen of approx. 450.degree. C., thereby diffusing the atoms
(e.g. aluminum atoms) of the electrode 3 into the semiconductor
substrate 1, i.e. into the p.sup.+-type contact layer 4 so as to
reduce the contact resistance of the electrode 3 and the
p.sup.+-type contact layer 4.
[0044] As a result, the electrode contact section according to the
invention is completed.
[0045] In the electrode contact structure of the invention, the
depth and impurity concentration of the p-type impurity layer 2
substantially determine the carrier injection coefficient. In the
present example, the peak value of the impurity concentration
profile of the p-type impurity layer 2 falls within the range of
10.sup.17-10.sup.18 ions/cm.sup.3, and the depth of the layer 2 is
set at a sufficiently low value of 1.0 .mu.m or less. Accordingly,
if this structure is applied to the collector electrode of an IGBT,
the carrier injection coefficient when turning off the IGBT can be
reduced, thereby increasing the speed of the turn-off
operation.
[0046] In addition, since the p.sup.+-type contact layer 4, which
has a higher impurity concentration than the p-type impurity layer
2 and is provided between the p-type impurity layer 2 and the
electrode 3, is set to have a depth of 0.2 .mu.m or less from the
surface of the semiconductor substrate 1, it does not influence the
carrier injection coefficient at the time of turning off the
semiconductor device. In other words, the p.sup.+-type contact
layer 4 does not increase the carrier injection coefficient.
Further, since the peak value of the impurity concentration profile
of the p.sup.+-type contact layer 4 is set at approx. 10.sup.19
ions/cm.sup.3, the contact resistance of the electrode contact
section is also reduced.
[0047] [B] Second Electrode Contact Section
[0048] In the above-described electrode contact section having a
first impurity profile, the p-type impurity layer 2 is made to be
sufficiently shallow (1.0 .mu.m or less) and have a low
concentration (10.sup.17-10.sup.18 ions/cm.sup.3), and the
p.sup.+-type contact layer 4 interposed between the p-type impurity
layer 2 and the electrode 3 has a sufficiently high impurity
concentration (approx. 10.sup.19 ions/cm.sup.3). This structure
simultaneously realizes a low contact resistance and a low carrier
injection coefficient.
[0049] However, when forming the p.sup.+-type contact layer 4 by
ion implantation, its surface impurity concentration is lower than
the peak value of its impurity profile. In this state, the contact
resistance of the electrode contact section cannot sufficiently be
reduced.
[0050] In light of this, in the second example of the invention, a
silicide layer 5 is formed between the electrode 3 and the
p.sup.+-type contact layer 4.
[0051] This example is not characterized by the provision of the
silicide layer 5, but by the depth of the silicide layer 5 from the
surface of the semiconductor substrate 1, more specifically, by the
relationship between the depth of the silicide layer 5 from the
surface of the semiconductor substrate 1, and the peak value of the
impurity profile of the p.sup.+-type contact layer 4.
[0052] An electrode contact section incorporated as a second
example in the invention will be described.
[0053] FIG. 3 shows the second example.
[0054] In this example, a p-type impurity layer 2 is formed in an
n-type semiconductor substrate 1. The n-type semiconductor layer 1
contains an n-type impurity such as phosphor (P) with a
substantially constant concentration of approx. 10.sup.14
ions/cm.sup.3. The p-type impurity layer 2 is formed in a surface
area of the semiconductor substrate 1 and contains a p-type
impurity such as boron (B). The depth of the p-type impurity layer
2 from the surface of the semiconductor substrate 1 is set at 1.0
.mu.m or less, for example, approx. 0.8 .mu.m. Further, the peak
value of the concentration profile of the p-type impurity layer 2
is set at a value falling within the range of 10.sup.17-10.sup.18
ions/cm.sup.3.
[0055] A p.sup.+-type contact layer 4 is formed in the p-type
impurity layer 2, and an electrode 3 is formed on the p.sup.+-type
contact layer 4. The p.sup.+-type contact layer 4 is thus
interposed between the p-type impurity layer 2 and the electrode 3
and has a higher impurity concentration than the p-type impurity
layer 2. For example, the p.sup.+-type contact layer 4 contains a
p-type impurity such as boron (B) or boron fluoride (BF.sub.2),
etc., and has an impurity concentration peak value of 10.sup.19
ions/cm.sup.3 or more and a surface impurity concentration of
10.sup.18 ions/cm.sup.3 or more. The depth of the p.sup.+-type
contact layer 4 from the surface of the semiconductor substrate 1
is set at 0.2 .mu.m or less, for example, approx. 0.16 .mu.m. The
electrode 3 is formed of, for example, aluminum.
[0056] Further, in this example, a silicide layer 5 is provided
between the electrode 3 and the p.sup.+-type contact layer 4. The
silicide layer 5 is formed by, for example, a thermal treatment in
which atoms (e.g. aluminum atoms) constituting the electrode 3
react with atoms (silicon atoms) constituting the semiconductor
substrate 1.
[0057] The depth of the silicide layer 5 from the surface of the
semiconductor substrate 1 is set equal to or shallower than the
depth of the p.sup.+-type contact layer 4 from the surface of the
semiconductor substrate 1. In this example, since the depth of the
p.sup.+-type contact layer 4 from the surface of the semiconductor
substrate 1 is set at 0.2 .mu.m or less, the depth of the silicide
layer 5 from the surface of the semiconductor substrate 1 is also
set at 0.2 .mu.m or less.
[0058] To minimize the contact resistance, it is necessary to make
the position of the bottom of the silicide layer 5 correspond to
that portion of the p.sup.+-type contact layer 4, at which the
concentration profile of the layer 4 assumes a peak value. In other
words, the electrode 3 is electrically connected to the lowest
resistance portion of the p.sup.+-type contact layer 4
(corresponding to a portion thereof at which the concentration
profile assumes the peak value) via the silicide layer 5, thereby
reducing the contact resistance.
[0059] In the electrode contact structure described above, the
p-type impurity layer 2 has a low impurity concentration, and a
sufficiently shallow depth of 1.0 .mu.m or less from the surface of
the semiconductor substrate 1. Accordingly, if this electrode
contact structure is applied to the collector electrode (anode
electrode) of an IGBT, the carrier (positive hole) injection
coefficient when turning off the IGBT can be reduced, thereby
increasing the speed of the turn-off operation.
[0060] In addition, since the p.sup.+-type contact layer 4, which
has a higher impurity concentration than the p-type impurity layer
2 and is provided between the p-type impurity layer 2 and the
electrode 3, is set to have a depth of 0.2 .mu.m or less from the
surface of the semiconductor substrate 1, it does not influence the
carrier injection coefficient at the time of turning off the
semiconductor device. In other words, the p.sup.+-type contact
layer 4 does not increase the carrier injection coefficient.
[0061] Further, the p.sup.+-type contact layer 4 has a sufficiently
high impurity concentration, and the silicide layer 5 is provided
between the electrode 3 and the p.sup.+-type contact layer 4. The
position of the bottom of the silicide layer 5 is made to
correspond to that portion of the p.sup.+-type contact layer 4, at
which the concentration profile of the layer 4 assumes a peak
value. Accordingly, the contact resistance of the electrode contact
section is further reduced.
[0062] FIG. 13 shows the relationship between a saturation voltage
Vce (sat) between the collector and the emitter and the thickness
of the silicide layer 5 (the depth from the surface of the
semiconductor substrate 1), obtained when the concentration profile
of the p.sup.+-type contact layer 4 assumes a peak value at a depth
of 0.04 .mu.m from the surface of the semiconductor substrate
1.
[0063] As is understood from FIG. 13, the saturation voltage Vce
(sat) between the collector and the emitter is minimum when the
position of the bottom of the silicide layer 5 (i.e. the thickness
of the layer 5) corresponds to that portion of the p.sup.+-type
contact layer 4, at which the concentration profile of the layer 4
assumes the peak value, i.e., when the thickness of the layer 5 is
0.04 .mu.m. This means that the contact resistance is minimum when
the position of the bottom of the silicide layer 5 (i.e. the
thickness of the layer 5) corresponds to that portion of the
p.sup.+-type contact layer 4, at which the concentration profile of
the layer 4 assumes the peak value.
[0064] As described above, the electrode contact section of the
invention simultaneously realizes a low contact resistance and a
low carrier injection coefficient.
[0065] Although in the above-described example, the semiconductor
substrate 1 is of the n-type and the impurity layer 2 and the
contact layer 4 are of the p-type, the same advantage can be
obtained by making the semiconductor substrate 1 be of the p-type
and the impurity layer 2 and the contact layer 4 be of the
n-type.
[0066] A description will be given of a method for manufacturing
the electrode contact section shown in FIG. 3.
[0067] First, an n-type semiconductor substrate (e.g. a silicon
substrate) 1 having, for example, an impurity concentration of
approx. 1.5.times.10.sup.14 ions/cm.sup.2 is prepared. A p-type
impurity such as boron (B) is implanted into the semiconductor
substrate by ion implantation. At this time, the acceleration
voltage and the dose, as implantation conditions, are set at, for
example, approx. 60 keV and approx. 1.times.10.sup.13
ions/cm.sup.2, respectively. Thereafter, the resultant structure is
subjected to a thermal diffusion process executed in the atmosphere
of nitrogen of approx. 1050.degree. C. for approx. 20 min. As a
result, a p-type impurity layer (e.g. a p-type emitter layer) 2
having a depth of approx. 0.8 .mu.m from the surface of the
semiconductor substrate 1 is formed.
[0068] Subsequently, a p-type impurity such as boron (B) is
implanted into the p-type impurity layer 2 in the semiconductor
substrate 1 by ion implantation. At this time, the acceleration
voltage and the dose, as implantation conditions, are set at, for
example, approx. 10 keV and approx. 1.times.10.sup.14
ions/cm.sup.2, respectively. After that, the resultant structure is
subjected to a thermal diffusion process executed in the atmosphere
of nitrogen of approx. 800.degree. C. for approx. 30 min. As a
result, a p.sup.+-type contact layer 4 having a depth of approx.
0.16 .mu.m from the surface of the semiconductor substrate 1 is
formed.
[0069] The p.sup.+-type contact layer 4 must be formed very
shallow, and must have a very high impurity concentration. To this
end, the acceleration voltage is set low, the dose is set high, and
the period for executing the thermal diffusion process is set
short, as is described above.
[0070] Boron fluoride (BF.sub.2), for example, may be used as the
p-type impurity, instead of boron (B) (i.e. the element is changed
from a light one to a heavy one), and implanted into the p-type
impurity layer 2 in the semiconductor substrate 1, thereby forming
a p.sup.+-type contact layer 4.
[0071] Subsequently, a thermal oxide film formed on a surface
portion of the semiconductor substrate 1, i.e. on a surface portion
of the p.sup.+-type contact layer 4, is removed using antimony
fluoride. After that, an electrode 3 made of a metal such as
aluminum and having a thickness of approx. 0.05 .mu.m is provided
on the p.sup.+-type contact layer 4 by sputtering or CVD.
[0072] Thereafter, the resultant structure is subjected to a heat
treatment executed for approx. 30 min. in the atmosphere of
nitrogen of approx. 450.degree. C., thereby diffusing the atoms
(e.g. aluminum atoms) of the electrode 3 into the semiconductor
substrate 1, i.e. into the p.sup.+-type contact layer 4. As a
result, a silicide layer 5 is formed. The thickness of the silicide
layer 5 (the depth from the surface of the semiconductor substrate
1) is made substantially equal to that thickness of the
p.sup.+-type contact layer 4 from the surface of the semiconductor
substrate 1, at which the concentration profile of the layer 4
assumes a peak value.
[0073] For example, when the concentration profile of the layer 4
assumes the peak value at a depth of approx. 0.04 .mu.m from the
surface of the semiconductor substrate 1, the silicide layer 5 is
made to have a thickness of approx. 0.04 .mu.m.
[0074] As a result, the contact resistance between the electrode 3
and the p-type impurity layer 2 in the electrode contact section is
minimized.
[0075] Thus, the electrode contact section of the invention is
completed.
[0076] In the electrode contact structure of the invention, the
carrier injection coefficient is basically determined from the
depth and impurity concentration of the p-type impurity layer 2. In
this example, the peak value of the concentration profile of the
p-type impurity layer 2 is set at a value falling within the range
of 10.sup.17-10.sup.18 ions/cm.sup.3. Further, the depth of the
p-type impurity layer 2 from the surface of the semiconductor
substrate 1 is set at a sufficient low value of 1.0 .mu.m or less.
Accordingly, when this electrode contact structure is applied to
the collector electrode of an IGBT, the coefficient of carrier
injection at the time of turning off the semiconductor device can
be reduced, thereby increasing the speed of the turn-off
operation.
[0077] Further, as described above, the p.sup.+-type contact layer
4 having a higher impurity concentration than the p-type impurity
layer 2 is provided between the p-type impurity layer 2 and the
electrode 3. Since the depth of the p.sup.+-type contact layer 4
from the surface of the semiconductor substrate 1 is set at 0.2
.mu.m or less, the p.sup.+-type contact layer 4 does not influence
the carrier injection coefficient at the time of turning off the
semiconductor device. In other words, the p.sup.+-type contact
layer 4 does not increase the carrier injection coefficient.
Moreover, since the peak value of the impurity concentration
profile of the p.sup.+-type contact layer 4 is set at approx.
10.sup.19 ions/cm.sup.3, the contact resistance of the electrode
contact section is also reduced.
[0078] In addition, the p.sup.+-type contact layer 4 has a
sufficiently high impurity concentration, and the silicide layer 5
is provided between the electrode 3 and the p.sup.+-type contact
layer 4. Further, the position of the bottom of the silicide layer
5 is made to correspond to that portion of the p.sup.+-type contact
layer 4, at which the concentration profile of the layer 4 assumes
a peak value. Accordingly, the contact resistance of the electrode
contact section is further reduced.
[0079] [C] Embodiment
[0080] A description will now be given of the case of applying the
above-described electrode contact section (according to the first
or second example) to an IGBT.
[0081] First, the IGBT will be described.
[0082] FIG. 4 shows a general structure for the IGBT.
[0083] An n-type semiconductor substrate (silicon substrate) 1
serves as an n-type base layer. A p-type base layer 7 is formed on
one surface of the semiconductor substrate 1, and an n.sup.+-type
emitter layer 8 is formed in the p-type base layer 7.
[0084] In a surface area of the one surface of the semiconductor
substrate 1, a gate electrode 10 is formed on the p-type base layer
(channel section) 7 between the n-type base layer 1 and the
n.sup.+-type emitter layer 8, with an insulating layer 9 interposed
therebetween. Further, an emitter electrode 11 is formed on the
p-type base layer 7 and the n.sup.+-type emitter layer 8.
[0085] A p.sup.+-type emitter layer 2 is formed on the other
surface of the semiconductor substrate 1. The p.sup.+-type emitter
layer 2 serves as a p-type impurity layer that constitutes an
electrode contact section according to the invention. A collector
electrode 3 is formed on the p.sup.+-type emitter layer 2.
[0086] As described above, in the IGBT, it is important to reduce
the contact resistance of the p.sup.+-type emitter layer 2 and the
collector electrode 3, and also to reduce the coefficient of
carrier (positive hole) injection from the p.sup.+-type emitter
layer 2 to the n-type base layer 1 so as to increase the speed of
the turn-off operation.
[0087] The application of the electrode contact structure of the
invention to the IGBT enables the simultaneous realization of a
reduction of the contact resistance and the carrier injection
coefficient.
[0088] FIG. 5 shows an IGBT as a first example of the
invention.
[0089] This example relates to an IGBT to which the above-described
first electrode contact section is applied.
[0090] A p-type base layer 7 is formed on one surface of an n-type
semiconductor substrate (n-type base layer) 1, and an n.sup.+-type
emitter layer 8 is formed in the p-type base layer 7. In a surface
area of the one surface of the semiconductor substrate 1, a gate
electrode 10 is formed on the p-type base layer (channel section) 7
between the n-type base layer 1 and the n.sup.+-type emitter layer
8, with an insulating layer 9 interposed therebetween. Further, an
emitter electrode 11 is formed on the p-type base layer 7 and the
n.sup.+-type emitter layer 8.
[0091] A p.sup.+-type emitter layer 2 is formed on the other
surface of the semiconductor substrate 1. The p.sup.+-type emitter
layer 2 contains a p-type impurity such as boron (B). The depth of
the p.sup.+-type emitter layer 2 from the other surface of the
semiconductor substrate 1 is set at 1.0 .mu.m or less, for example,
approx. 0.8 .mu.m. Further, the peak value of the concentration
profile of the p.sup.+-type emitter layer 2 is set at a value
falling within the range of 10.sup.17-10.sup.18 ions/cm.sup.3.
[0092] A p.sup.++-type contact layer 4 is formed in the
p.sup.+-type emitter layer 2, and a collector electrode 3 is formed
on the p.sup.++-type contact layer 4. The p.sup.++-type contact
layer 4 is thus interposed between the p.sup.+-type emitter layer 2
and the collector electrode 3 and has a higher impurity
concentration than the p.sup.+-type emitter layer 2.
[0093] For example, the p.sup.++-type contact layer 4 contains a
p-type impurity such as boron (B) or boron fluoride (BF.sub.2),
etc., and has an impurity concentration peak value of 10.sup.19
ions/cm.sup.3 or more and a surface impurity concentration of
10.sup.18 ions/cm.sup.3 or more. The depth of the p.sup.++-type
contact layer 4 from the surface of the semiconductor substrate 1
is set at 0.2 .mu.m or less, for example, approx. 0.16 .mu.m. The
collector electrode 3 is formed of, for example, aluminum.
[0094] In the above-described electrode contact structure, the
p.sup.+-type emitter layer 2 has a low impurity concentration, and
a sufficiently shallow depth of 1.0 .mu.m or less from the surface
of the semiconductor substrate 1. Accordingly, the coefficient of
carrier (positive hole) injection at the time of turning off the
IGBT can be reduced, thereby increasing the speed of the turn-off
operation.
[0095] Further, as described above, the p.sup.++-type contact layer
4 having a higher impurity concentration than the p.sup.+-type
emitter layer 2 is provided between the p.sup.+-type emitter layer
2 and the collector electrode 3. Since the depth of the
p.sup.++-type contact layer 4 from the surface of the semiconductor
substrate 1 is set at 0.2 .mu.m or less, the p.sup.+-type contact
layer 4 does not influence the carrier injection coefficient at the
time of turning off the IGBT. In other words, the p.sup.++-type
contact layer 4 does not increase the carrier injection
coefficient.
[0096] Moreover, since the p.sup.+-type contact layer 4 has a
sufficiently high impurity concentration, the contact resistance of
the electrode contact section is reduced.
[0097] As described above, the electrode contact section of the
IGBT enables the simultaneous realization of a sufficient reduction
of the contact resistance and reduction of the carrier injection
coefficient.
[0098] Although in the above-described example, the semiconductor
substrate 1 is of the n-type and the emitter layer 2 and the
contact layer 4 are of the p-type, the same advantage can be
obtained by making the semiconductor substrate 1 be of the p-type
and the emitter layer 2 and the contact layer 4 be of the
n-type.
[0099] A method for manufacturing the IGBT shown in FIG. 5 will be
described.
[0100] First, an n-type semiconductor substrate (e.g. a silicon
substrate) 1 having, for example, an impurity concentration of
approx. 1.5.times.10.sup.14 ions/cm.sup.2 is prepared. A p-type
base layer 7, an n.sup.+-type emitter layer 8, an insulating film
9, a gate electrode 10 and an emitter electrode 11 are formed on
one surface of the semiconductor substrate 1.
[0101] Subsequently, a p-type impurity such as boron (B) is
implanted into the other surface of the semiconductor substrate 1
by ion implantation. At this time, the acceleration voltage and the
dose, as implantation conditions, are set at, for example, approx.
60 keV and approx. 1.times.10.sup.13 ions/cm.sup.2, respectively.
Thereafter, the resultant structure is subjected to a thermal
diffusion process executed in the atmosphere of nitrogen of approx.
1050.degree. C. for approx. 20 min. As a result, a p.sup.+-type
emitter layer 2 having a depth of approx. 0.8 .mu.m from the other
surface of the semiconductor substrate 1 is formed.
[0102] Subsequently, a p-type impurity such as boron (B) is
implanted into the p.sup.+-type emitter layer 2 in the other
surface of the semiconductor substrate 1 by ion implantation. At
this time, the acceleration voltage and the dose, as implantation
conditions, are set at, for example, approx. 10 keV and approx.
1.times.10.sup.14 ions/cm.sup.2, respectively. After that, the
resultant structure is subjected to a thermal diffusion process
executed in the atmosphere of nitrogen of approx. 800.degree. C.
for approx. 30 min. As a result, a p.sup.++-type contact layer 4
having a depth of approx. 0.16 .mu.m from the other surface of the
semiconductor substrate 1 is formed.
[0103] The p.sup.++-type contact layer 4 must be formed very
shallow, and must have a very high impurity concentration. To this
end, the acceleration voltage is set low, the dose is set high, and
the period for executing the thermal diffusion process is set
short, as is described above.
[0104] Boron fluoride (BF.sub.2), for example, may be used as the
p-type impurity, instead of boron (B) (i.e. the element is changed
from a light one to a heavy one), and implanted into the
p.sup.+-type emitter layer 2 in the semiconductor substrate 1,
thereby forming a p.sup.++-type contact layer 4.
[0105] Subsequently, a thermal oxide film formed on a surface
portion of the other surface of the semiconductor substrate 1, i.e.
on a surface portion of the p.sup.++-type contact layer 4, is
removed using antimony fluoride. After that, a collector electrode
3 made of a metal such as aluminum is provided on the p.sup.++-type
contact layer 4 by sputtering or CVD.
[0106] Thereafter, the resultant structure is subjected to a heat
treatment executed for approx. 30 min. in the atmosphere of
nitrogen of approx. 450.degree. C., thereby diffusing the atoms
(e.g. aluminum atoms) of the collector electrode 3 into the
semiconductor substrate 1, i.e. into the p.sup.++-type contact
layer 4 so as to reduce the contact resistance of the collector
electrode 3 and the p.sup.++-type contact layer 4.
[0107] As a result, the IGBT according to the invention is
completed.
[0108] FIG. 6 shows an IGBT as a second example of the
invention.
[0109] This example relates to an IGBT to which the above-described
second electrode contact section is applied.
[0110] A p-type base layer 7 is formed on one surface of an n-type
semiconductor substrate (n-type base layer) 1, and an n.sup.+-type
emitter layer 8 is formed in the p-type base layer 7. In a surface
area of the one surface of the semiconductor substrate 1, a gate
electrode 10 is formed on the p-type base layer (channel section) 7
between the n-type base layer 1 and the n.sup.+-type emitter layer
8, with an insulating layer 9 interposed therebetween. Further, an
emitter electrode 11 is formed on the p-type base layer 7 and the
n.sup.+-type emitter layer 8.
[0111] A p.sup.+-type emitter layer 2 is formed on the other
surface of the semiconductor substrate 1. The p.sup.+-type emitter
layer 2 contains a p-type impurity such as boron (B). The depth of
the p.sup.+-type emitter layer 2 from the other surface of the
semiconductor substrate 1 is set at 1.0 .mu.m or less, for example,
approx. 0.8 .mu.m. Further, the peak value of the concentration
profile of the p.sup.+-type emitter layer 2 is set at a value
falling within the range of 10.sup.17-10.sup.18 ions/cm.sup.3.
[0112] A p.sup.++-type contact layer 4 is formed in the
p.sup.+-type emitter layer 2, and a collector electrode 3 is formed
on the p.sup.++-type contact layer 4. The p.sup.++-type contact
layer 4 is thus interposed between the p.sup.+-type emitter layer 2
and the collector electrode 3 and has a higher impurity
concentration than the p.sup.+-type emitter layer 2.
[0113] For example, the p.sup.++-type contact layer 4 contains a
p-type impurity such as boron (B) or boron fluoride (BF.sub.2),
etc., and has an impurity concentration peak value of 10.sup.19
ions/cm.sup.3 or more and a surface impurity concentration of
10.sup.18 ions/cm.sup.3 or more. The depth of the p.sup.++-type
contact layer 4 from the surface of the semiconductor substrate 1
is set at 0.2 .mu.m or less, for example, approx. 0.16 .mu.m. The
collector electrode 3 is formed of, for example, aluminum.
[0114] Further, in this example, a silicide layer 5 is provided
between the collector electrode 3 and the p.sup.++-type contact
layer 4. The silicide layer 5 is formed by, for example, a thermal
treatment in which atoms (e.g. aluminum atoms) constituting the
collector electrode 3 react with atoms (silicon atoms) constituting
the semiconductor substrate 1.
[0115] The depth of the silicide layer 5 from the other surface of
the semiconductor substrate 1 is set equal to or shallower than the
depth of the p.sup.++-type contact layer 4 from the other surface
of the semiconductor substrate 1. In this example, since the depth
of the p.sup.++-type contact layer 4 from the other surface of the
semiconductor substrate 1 is set at 0.2 .mu.m or less, the depth of
the silicide layer 5 from the other surface of the semiconductor
substrate 1 is also set at 0.2 .mu.m or less.
[0116] To minimize the contact resistance, it is necessary to make
the position of the bottom of the silicide layer 5 correspond to
that portion of the p.sup.++-type contact layer 4, at which the
concentration profile of the layer 4 assumes a peak value. In other
words, the collector electrode 3 is electrically connected to the
lowest resistance portion of the p.sup.++-type contact layer 4
(corresponding to a portion thereof at which the concentration
profile assumes the peak value) via the silicide layer 5, thereby
reducing the contact resistance.
[0117] In the electrode contact structure described above, the
p.sup.+-type emitter layer 2 has a low impurity concentration, and
a sufficiently shallow depth of 1.0 .mu.m or less from the other
surface of the semiconductor substrate 1. Accordingly, the carrier
(positive hole) injection coefficient when turning off the IGBT can
be reduced, thereby increasing the speed of the turn-off
operation.
[0118] In addition, since the p.sup.++-type contact layer 4, which
has a higher impurity concentration than the p.sup.+-type emitter
layer 2 and is provided between the p.sup.+-type emitter layer 2
and the collector electrode 3, is set to have a depth of 0.2 .mu.m
or less from the surface of the semiconductor substrate 1, it does
not influence the carrier injection coefficient at the time of
turning off the IGBT. In other words, the p.sup.++-type contact
layer 4 does not increase the carrier injection coefficient.
[0119] Further, the p.sup.++-type contact layer 4 has a
sufficiently high impurity concentration, and the silicide layer 5
is provided between the collector electrode 3 and the p.sup.++-type
contact layer 4. The position of the bottom of the silicide layer 5
is made to correspond to that portion of the p.sup.++-type contact
layer 4, at which the concentration profile of the layer 4 assumes
a peak value. Accordingly, the contact resistance of the electrode
contact section is further reduced.
[0120] Thus, the electrode contact section of the IGBT according to
the invention enables the simultaneous realization of a sufficient
reduction of the contact resistance and reduction of the carrier
injection coefficient.
[0121] Although in the above-described example, the semiconductor
substrate 1 is of the n-type and the emitter layer 2 and the
contact layer 4 are of the p-type, the same advantage can be
obtained by making the semiconductor substrate 1 be of the p-type
and the emitter layer 2 and the contact layer 4 be of the
n-type.
[0122] A method for manufacturing the IGBT shown in FIG. 6 will be
described.
[0123] First, an n-type semiconductor substrate (e.g. a silicon
substrate) 1 having, for example, an impurity concentration of
approx. 1.5.times.10.sup.14 ions/cm.sup.2 is prepared. A p-type
base layer 7, an n+-type emitter layer 8, an insulating film 9, a
gate electrode 10 and an emitter electrode 11 are formed on one
surface of the semiconductor substrate 1.
[0124] Subsequently, a p-type impurity such as boron (B) is
implanted into the other surface of the semiconductor substrate 1
by ion implantation. At this time, the acceleration voltage and the
dose, as implantation conditions, are set at, for example, approx.
60 keV and approx. 1.times.10.sup.13 ions/cm.sup.2, respectively.
Thereafter, the resultant structure is subjected to a thermal
diffusion process executed in the atmosphere of nitrogen of approx.
1050.degree. C. for approx. 20 min. As a result, a p.sup.+-type
emitter layer 2 having a depth of approx. 0.8 .mu.m from the other
surface of the semiconductor substrate 1 is formed.
[0125] Subsequently, a p-type impurity such as boron (B) is
implanted into the p.sup.+-type emitter layer 2 in the other
surface of the semiconductor substrate 1 by ion implantation. At
this time, the acceleration voltage and the dose, as implantation
conditions, are set at, for example, approx. 10 keV and approx.
1.times.10.sup.14 ions/cm.sup.2, respectively. After that, the
resultant structure is subjected to a thermal diffusion process
executed in the atmosphere of nitrogen of approx. 800.degree. C.
for approx. 30 min. As a result, a p.sup.++-type contact layer 4
having a depth of approx. 0.16 .mu.m from the other surface of the
semiconductor substrate 1 is formed.
[0126] The p.sup.++-type contact layer 4 must be formed very
shallow, and must have a very high impurity concentration. To this
end, the acceleration voltage is set low, the dose is set high, and
the period for executing the thermal diffusion process is set
short, as is described above.
[0127] Boron fluoride (BF.sub.2), for example, may be used as the
p-type impurity, instead of boron (B) (i.e. the element is changed
from a light one to a heavy one), and implanted into the
p.sup.+-type emitter layer 2 in the semiconductor substrate 1,
thereby forming a p.sup.++-type contact layer 4.
[0128] Subsequently, a thermal oxide film formed on a surface
portion of the other surface of the semiconductor substrate 1, i.e.
on a surface portion of the p.sup.++-type contact layer 4, is
removed using antimony fluoride. After that, a collector electrode
3 made of a metal such as aluminum and having a thickness of
approx. 0.05 .mu.m is provided on the p.sup.++-type contact layer 4
by sputtering or CVD.
[0129] Thereafter, the resultant structure is subjected to a heat
treatment executed for approx. 30 min. in the atmosphere of
nitrogen of approx. 450.degree. C., thereby diffusing the atoms
(e.g. aluminum atoms) of the collector electrode 3 into the
semiconductor substrate 1, i.e. into the p.sup.++-type contact
layer 4 so as to form a silicide layer 5. The thickness of the
silicide layer 5 (the depth from the other surface of the
semiconductor substrate 1) is made substantially equal to that
thickness of the p.sup.++-type contact layer 4 from the other
surface of the semiconductor substrate 1, at which the
concentration profile of the layer 4 assumes a peak value.
[0130] For example, when the concentration profile of the layer 4
assumes the peak value at a depth of approx. 0.04 .mu.m from the
other surface of the semiconductor substrate 1, the silicide layer
5 is made to have a thickness of approx. 0.04 .mu.m.
[0131] As a result, the contact resistance between the collector
electrode 3 and the p.sup.+-type emitter layer 2 in the electrode
contact section is reduced.
[0132] The collector electrode 3 may be formed after forming the
silicide layer 5.
[0133] Thus, the IGBT according to the invention is completed.
[0134] FIG. 8 shows an IGBT as a third example of the
invention.
[0135] This example relates to an IGBT (a reference example) as
shown in FIG. 7, in which a plurality of p.sup.+-type emitter
layers 2A isolated from each other are formed, and to which the
above-described first electrode contact section is applied.
[0136] A p-type base layer 7 is formed on one surface of an n-type
semiconductor substrate (n-type base layer) 1, and an n.sup.+-type
emitter layer 8 is formed in the p-type base layer 7. In a surface
area of the one surface of the semiconductor substrate 1, a gate
electrode 10 is formed on the p-type base layer (channel section) 7
between the n-type base layer 1 and the n.sup.+-type emitter layer
8, with an insulating layer 9 interposed therebetween. Further, an
emitter electrode 11 is formed on the p-type base layer 7 and the
n.sup.+-type emitter layer 8.
[0137] A plurality of p.sup.+-type emitter layers 2A isolated from
each other are formed on the other surface of the semiconductor
substrate 1. Each p.sup.+-type emitter layer 2A contains a p-type
impurity such as boron (B). The depth of each p.sup.+-type emitter
layer 2A from the other surface of the semiconductor substrate 1 is
set at 1.0 .mu.m or less, for example, approx. 0.8 .mu.m. Further,
the peak value of the concentration profile of each p.sup.+-type
emitter layer 2A is set at a value falling within the range of
10.sup.17-10.sup.18 ions/cm.sup.3.
[0138] A p.sup.++-type contact layer 4A is formed in each
p.sup.+-type emitter layer 2A, and a collector electrode 3 is
formed on the resultant p.sup.++-type contact layers 4A. Further,
insulating films 6 are formed on respective exposed portions of the
other surface of the n-type base layer (semiconductor substrate) 1.
Accordingly, the collector electrode 3 is electrically connected to
the plurality of p.sup.+-type emitter layers 2A, and electrically
isolated from the n-type base layer 1.
[0139] The p.sup.++-type contact layers 4A are interposed between
the respective p.sup.+-type emitter layers 2A and the collector
electrode 3, and have a higher impurity concentration than the
p.sup.+-type emitter layers 2A.
[0140] For example, each p.sup.++-type contact layer 4A contains a
p-type impurity such as boron (B) or boron fluoride (BF.sub.2),
etc., and has an impurity concentration peak value of 10.sup.19
ions/cm.sup.3 or more and a surface impurity concentration of
10.sup.18 ions/cm.sup.3 or more. The depth of each p.sup.++-type
contact layer 4A from the other surface of the semiconductor
substrate 1 is set at 0.2 .mu.m or less, for example, approx. 0.16
.mu.m. The collector electrode 3 is formed of, for example,
aluminum.
[0141] In the electrode contact structure described above, the
p.sup.+-type emitter layers 2A have a low impurity concentration,
and a sufficiently shallow depth of 1.0 .mu.m or less from the
other surface of the semiconductor substrate 1. Accordingly, the
carrier (positive hole) injection coefficient when turning off the
IGBT can be reduced, thereby increasing the speed of the turn-off
operation.
[0142] The carrier injection coefficient can be controlled by
changing the depth of the p.sup.+-type emitter layers 2A or contact
ratio W1/W2.
[0143] In addition, since the p.sup.++-type contact layers 4, which
have a higher impurity concentration than the p.sup.+-type emitter
layers 2A and are provided between the respective p.sup.+-type
emitter layers 2A and the collector electrode 3, are set to have a
depth of 0.2 .mu.m or less from the other surface of the
semiconductor substrate 1, they do not influence the carrier
injection coefficient at the time of turning off the IGBT. In other
words, the p.sup.++-type contact layers 4A do not increase the
carrier injection coefficient.
[0144] Further, since the p.sup.++-type contact layers 4 have a
sufficiently high impurity concentration, the contact resistance of
the electrode contact section is reduced.
[0145] Thus, the electrode contact section of the IGBT according to
the invention enables the simultaneous realization of a sufficient
reduction of the contact resistance and reduction of the carrier
injection coefficient.
[0146] Although in the above-described example, the semiconductor
substrate 1 is of the n-type and the emitter layers 2A and the
contact layers 4A are of the p-type, the same advantage can be
obtained by making the semiconductor substrate 1 be of the p-type
and the emitter layers 2A and the contact layers 4A be of the
n-type.
[0147] A method for manufacturing the IGBT shown in FIG. 8 will be
described.
[0148] First, an n-type semiconductor substrate (e.g. a silicon
substrate) 1 having, for example, an impurity concentration of
approx. 1.5.times.10.sup.14 ions/cm.sup.2 is prepared. A p-type
base layer 7, an n.sup.+-type emitter layer 8, an insulating film
9, a gate electrode 10 and an emitter electrode 11 are formed on
one surface of the semiconductor substrate 1.
[0149] Subsequently, a p-type impurity such as boron (B) is
implanted into the other surface of the semiconductor substrate 1
by ion implantation. At this time, the acceleration voltage and the
dose, as implantation conditions, are set at, for example, approx.
60 keV and approx. 1.times.10.sup.13 ions/cm.sup.2, respectively.
Thereafter, the resultant structure is subjected to a thermal
diffusion process executed in the atmosphere of nitrogen of approx.
1050.degree. C. for approx. 20 min. As a result, p.sup.+-type
emitter layers 2A having a depth of approx. 0.8 .mu.m from the
other surface of the semiconductor substrate 1 are formed.
[0150] Subsequently, a p-type impurity such as boron (B) is
implanted into the p.sup.+-type emitter layers 2A in the other
surface of the semiconductor substrate 1 by ion implantation. At
this time, the acceleration voltage and the dose, as implantation
conditions, are set at, for example, approx. 10 keV and approx.
1.times.10.sup.14 ions/cm.sup.2, respectively. After that, the
resultant structure is subjected to a thermal diffusion process
executed in the atmosphere of nitrogen of approx. 800.degree. C.
for approx. 30 min. As a result, p.sup.++-type contact layers 4A
having a depth of approx. 0.16 .mu.m from the other surface of the
semiconductor substrate 1 are formed.
[0151] The p.sup.++-type contact layers 4A must be formed very
shallow, and must have a very high impurity concentration. To this
end, the acceleration voltage is set low, the dose is set high, and
the period for executing the thermal diffusion process is set
short, as is described above.
[0152] Boron fluoride (BF.sub.2), for example, may be used as the
p-type impurity, instead of boron (B) (i.e. the element is changed
from a light one to a heavy one), and implanted into the
p.sup.+-type emitter layers 2A in the semiconductor substrate 1,
thereby forming p.sup.++-type contact layers 4A.
[0153] Subsequently, a thermal oxide film formed on a surface
portion of the other surface of the semiconductor substrate 1, i.e.
on a surface portion of the p.sup.++-type contact layers 4A, is
removed using antimony fluoride. After that, an insulating film 6
is formed on the other surface side of the semiconductor substrate
1 by, for example, CVD. The insulating film 6 is patterned by PEP
or RIE, thereby forming contact holes that extend to the respective
p.sup.++-type contact layers 4A. Then, a collector electrode 3
extending to the p.sup.++-type contact layers 4A is formed by
sputtering or CVD.
[0154] Thereafter, the resultant structure is subjected to a heat
treatment executed for approx. 30 min. in the atmosphere of
nitrogen of approx. 450.degree. C., thereby diffusing the atoms
(e.g. aluminum atoms) of the collector electrode 3 into the
semiconductor substrate 1, i.e. into the p.sup.++-type contact
layers 4A. As a result, the contact resistance between the
collector electrode 3 and the p.sup.++-type contact layers 4 is
reduced.
[0155] Thus, the IGBT according to the invention is completed.
[0156] FIG. 9 shows an IGBT as a fourth example of the
invention.
[0157] This example relates to an IGBT (a reference example) as
shown in FIG. 7, in which a plurality of p.sup.+-type emitter
layers 2A isolated from each other are formed, and to which the
above-described second electrode contact section is applied.
[0158] A p-type base layer 7 is formed on one surface of an n-type
semiconductor substrate (n-type base layer) 1, and an n.sup.+-type
emitter layer 8 is formed in the p-type base layer 7. In a surface
area of the one surface of the semiconductor substrate 1, a gate
electrode 10 is formed on the p-type base layer (channel section) 7
between the n-type base layer 1 and the n.sup.+-type emitter layer
8, with an insulating layer 9 interposed therebetween. Further, an
emitter electrode 11 is formed on the p-type base layer 7 and the
n.sup.+-type emitter layer 8.
[0159] A plurality of p.sup.+-type emitter layers 2A isolated from
each other are formed on the other surface of the semiconductor
substrate 1. Each p.sup.+-type emitter layer 2A contains a p-type
impurity such as boron (B). The depth of each p.sup.+-type emitter
layer 2A from the other surface of the semiconductor substrate 1 is
set at 1.0 .mu.m or less, for example, approx. 0.8 .mu.m. Further,
the peak value of the concentration profile of each p.sup.+-type
emitter layer 2A is set at a value falling within the range of
10.sup.17-10.sup.18 ions/cm.sup.3.
[0160] A p.sup.++-type contact layer 4A is formed in each
p.sup.+-type emitter layer 2A, and a collector electrode 3 is
formed on the resultant p.sup.++-type contact layers 4A. Further,
insulating films 6 are formed on respective exposed portions of the
other surface of the n-type base layer (semiconductor substrate) 1.
Accordingly, the collector electrode 3 is electrically connected to
the plurality of p.sup.+-type emitter layers 2A, and electrically
isolated from the n-type base layer 1.
[0161] The p.sup.++-type contact layers 4A are interposed between
the respective p.sup.+-type emitter layers 2A and the collector
electrode 3, and have a higher impurity concentration than the
p.sup.+-type emitter layers 2A.
[0162] For example, each p.sup.++-type contact layer 4A contains a
p-type impurity such as boron (B) or boron fluoride (BF.sub.2),
etc., and has an impurity concentration peak value of 10.sup.19
ions/cm.sup.3 or more and a surface impurity concentration of
10.sup.18 ions/cm.sup.3 or more. The depth of each p.sup.++-type
contact layer 4A from the other surface of the semiconductor
substrate 1 is set at 0.2 .mu.m or less, for example, approx. 0.16
.mu.m. The collector electrode 3 is formed of, for example,
aluminum.
[0163] Further, in this example, a silicide layer 5 is provided
between the collector electrode 3 and each p.sup.+-type contact
layer 4A. The silicide layer 5 is formed by, for example, a thermal
treatment in which atoms (e.g. aluminum atoms) constituting the
electrode 3 react with atoms (silicon atoms) constituting the
semiconductor substrate 1.
[0164] The depth of the silicide layer 5 from the other surface of
the semiconductor substrate 1 is set equal to or shallower than the
depth of each p.sup.+-type contact layer 4A from the other surface
of the semiconductor substrate 1. In this example, since the depth
of each p.sup.+-type contact layer 4A from the other surface of the
semiconductor substrate 1 is set at 0.2 .mu.m or less, the depth of
the silicide layer 5 from the surface of the semiconductor
substrate 1 is also set at 0.2 .mu.m or less.
[0165] To minimize the contact resistance, it is necessary to make
the position of the bottom of the silicide layer 5 correspond to
that portion of each p.sup.+-type contact layer 4A, at which the
concentration profile of the layer 4A assumes a peak value. In
other words, the collector electrode 3 is electrically connected to
the lowest resistance portion of each p.sup.+-type contact layer 4A
(corresponding to a portion thereof at which the concentration
profile assumes the peak value) via the silicide layer 5, thereby
reducing the contact resistance.
[0166] In the electrode contact structure described above, the
p.sup.+-type emitter layers 2A have a low impurity concentration,
and a sufficiently shallow depth of 1.0 .mu.m or less from the
other surface of the semiconductor substrate 1. Accordingly, the
carrier (positive hole) injection coefficient when turning off the
IGBT can be reduced, thereby increasing the speed of the turn-off
operation.
[0167] The carrier injection coefficient can be controlled by
changing the depth of the p.sup.+-type emitter layers 2A or contact
ratio W1/W2.
[0168] In addition, since the p.sup.++-type contact layers 4, which
have a higher impurity concentration than the p.sup.+-type emitter
layers 2A and are provided between the respective p.sup.+-type
emitter layers 2A and the collector electrode 3, are set to have a
depth of 0.2 .mu.m or less from the other surface of the
semiconductor substrate 1, they do not influence the carrier
injection coefficient at the time of turning off the IGBT. In other
words, the p.sup.++-type contact layers 4A do not increase the
carrier injection coefficient.
[0169] Further, the p.sup.++-type contact layers 4 have a
sufficiently high impurity concentration, and the silicide layer 5
is provided between the collector electrode 3 and each
p.sup.++-type contact layer 4A. The position of the bottom of the
silicide layer 5 is made to correspond to that portion of each
p.sup.++-type contact layer 4A, at which the concentration profile
of the layer 4A assumes a peak value. Accordingly, the contact
resistance of the electrode contact section is further reduced.
[0170] Thus, the electrode contact section of the IGBT according to
the invention enables the simultaneous realization of a sufficient
reduction of the contact resistance and reduction of the carrier
injection coefficient.
[0171] Although in the above-described example, the semiconductor
substrate 1 is of the n-type and the emitter layers 2A and the
contact layers 4A are of the p-type, the same advantage can be
obtained by making the semiconductor substrate 1 be of the p-type
and the emitter layers 2A and the contact layers 4A be of the
n-type.
[0172] A method for manufacturing the IGBT shown in FIG. 9 will be
described.
[0173] First, an n-type semiconductor substrate (e.g. a silicon
substrate) 1 having, for example, an impurity concentration of
approx. 1.5.times.10.sup.14 ions/cm.sup.2 is prepared. A p-type
base layer 7, an n.sup.+-type emitter layer 8, an insulating film
9, a gate electrode 10 and an emitter electrode 11 are formed on
one surface of the semiconductor substrate 1.
[0174] Subsequently, a p-type impurity such as boron (B) is
implanted into the other surface of the semiconductor substrate 1
by ion implantation. At this time, the acceleration voltage and the
dose, as implantation conditions, are set at, for example, approx.
60 keV and approx. 1.times.10.sup.13 ions/cm.sup.2, respectively.
Thereafter, the resultant structure is subjected to a thermal
diffusion process executed in the atmosphere of nitrogen of approx.
1050.degree. C. for approx. 20 min. As a result, p.sup.+-type
emitter layers 2A having a depth of approx. 0.8 .mu.m from the
other surface of the semiconductor substrate 1 are formed.
[0175] Thereafter, a p-type impurity such as boron (B) is implanted
into the p.sup.+-type emitter layers 2A in the other surface of the
semiconductor substrate 1 by ion implantation. At this time, the
acceleration voltage and the dose, as implantation conditions, are
set at, for example, approx. 10 keV and approx. 1.times.10.sup.14
ions/cm.sup.2, respectively. Then, the resultant structure is
subjected to a thermal diffusion process executed in the atmosphere
of nitrogen of approx. 800.degree. C. for approx. 30 min. As a
result, p.sup.++-type contact layers 4A having a depth of approx.
0.16 .mu.m from the other surface of the semiconductor substrate 1
are formed.
[0176] The p.sup.++-type contact layers 4A must be formed very
shallow, and must have a very high impurity concentration. To this
end, the acceleration voltage is set low, the dose is set high, and
the period for executing the thermal diffusion process is set
short, as is described above.
[0177] Boron fluoride (BF.sub.2), for example, may be used as the
p-type impurity, instead of boron (B) (i.e. the element is changed
from a light one to a heavy one), and implanted into the
p.sup.+-type emitter layers 2A in the semiconductor substrate 1,
thereby forming p.sup.++-type contact layers 4A.
[0178] Subsequently, a thermal oxide film formed on a surface
portion of the other surface of the semiconductor substrate 1, i.e.
on a surface portion of the p.sup.++-type contact layers 4A, is
removed using antimony fluoride. After that, an insulating film 6
is formed on the other surface side of the semiconductor substrate
1 by, for example, CVD. The insulating film 6 is patterned by PEP
or RIE, thereby forming contact holes that extend to the respective
p.sup.++-type contact layers 4A. Then, a collector electrode 3
extending to the p.sup.++-type contact layers 4A is formed by
sputtering or CVD.
[0179] Thereafter, the resultant structure is subjected to a heat
treatment executed for approx. 30 min. in the atmosphere of
nitrogen of approx. 450.degree. C., thereby diffusing the atoms
(e.g. aluminum atoms) of the collector electrode 3 into the
semiconductor substrate 1, i.e. into the p.sup.++-type contact
layers 4A, so as to form a silicide layer 5. The thickness of the
silicide layer 5 (the depth from the surface of the semiconductor
substrate 1) is made substantially equal to that thickness of each
p.sup.+-type contact layer 4A from the other surface of the
semiconductor substrate 1, at which the concentration profile of
each layer 4A assumes a peak value.
[0180] For example, when the concentration profile of each layer 4A
assumes the peak value at a depth of approx. 0.04 .mu.m from the
surface of the semiconductor substrate 1, the silicide layer 5 is
made to have a thickness of approx. 0.04 .mu.m.
[0181] As a result, the contact resistance between the collector
electrode 3 and the p.sup.++-type contact layers 4 is reduced.
[0182] The collector electrode 3 may be formed after forming the
silicide layer 5.
[0183] Thus, the IGBT according to the invention is completed.
[0184] FIG. 11 shows an IGBT as a fifth example of the
invention.
[0185] This example relates to a so-called
collector-short-circuited (or anode-short-circuited) IGBT (a
reference example) as shown in FIG. 10, to which the
above-described first electrode contact section is applied.
[0186] A p-type base layer 7 is formed on one surface of an n-type
semiconductor substrate (n-type base layer) 1, and an n.sup.+-type
emitter layer 8 is formed in the p-type base layer 7. In a surface
area of the one surface of the semiconductor substrate 1, a gate
electrode 10 is formed on the p-type base layer (channel section) 7
between the n-type base layer 1 and the n.sup.+-type emitter layer
8, with an insulating layer 9 interposed therebetween. Further, an
emitter electrode 11 is formed on the p-type base layer 7 and the
n.sup.+-type emitter layer 8.
[0187] A plurality of p.sup.+-type emitter layers 2B and a
plurality of n.sup.+-type base layers 12 are formed on the other
surface of the semiconductor substrate 1. Each p.sup.+-type emitter
layer 2B contains a p-type impurity such as boron (B). The depth of
each p.sup.+-type emitter layer 2B from the other surface of the
semiconductor substrate 1 is set at 1.0 .mu.m or less, for example,
approx. 0.8 .mu.m. Further, the peak value of the concentration
profile of each p.sup.+-type emitter layer 2B is set at a value
falling within the range of 10.sup.17-10.sup.18 ions/cm.sup.3.
[0188] A p.sup.++-type contact layer 4B is formed in each
p.sup.+-type emitter layer 2B, and a collector electrode 3 is
formed on the resultant p.sup.++-type contact layers 4B. Further,
the p.sup.++-type contact layers 4B are interposed between the
respective p.sup.+-type emitter layers 2B and the collector
electrode 3, and have a higher impurity concentration than the
p.sup.+-type emitter layers 2B.
[0189] For example, each p.sup.++-type contact layer 4B contains a
p-type impurity such as boron (B) or boron fluoride (BF.sub.2),
etc., and has an impurity concentration peak value of 10.sup.19
ions/cm.sup.3 or more and a surface impurity concentration of
10.sup.18 ions/cm.sup.3 or more. The depth of each p.sup.++-type
contact layer 4B from the other surface of the semiconductor
substrate 1 is set at 0.2 .mu.m or less, for example, approx. 0.16
.mu.m. The collector electrode 3 is formed of, for example,
aluminum.
[0190] In the electrode contact structure described above, the
p.sup.+-type emitter layers 2B have a low impurity concentration,
and a sufficiently shallow depth of 1.0 .mu.m or less from the
other surface of the semiconductor substrate 1. Accordingly, the
carrier (positive hole) injection coefficient when turning off the
IGBT can be reduced, thereby increasing the speed of the turn-off
operation.
[0191] In addition, since the p.sup.++-type contact layers 4B,
which have a higher impurity concentration than the p.sup.+-type
emitter layers 2B and are provided between the respective
p.sup.+-type emitter layers 2B and the collector electrode 3, are
set to have a depth of 0.2 .mu.m or less from the other surface of
the semiconductor substrate 1, they do not influence the carrier
injection coefficient at the time of turning off the IGBT. In other
words, the p.sup.++-type contact layers 4B do not increase the
carrier injection coefficient.
[0192] Further, since the p.sup.++-type contact layers 4B have a
sufficiently high impurity concentration, the contact resistance of
the electrode contact section is reduced.
[0193] Thus, the electrode contact section of the IGBT according to
the invention enables the simultaneous realization of a sufficient
reduction of the contact resistance and reduction of the carrier
injection coefficient.
[0194] Although in the above-described example, the semiconductor
substrate 1 is of the n-type and the emitter layers 2B and the
contact layers 4B are of the p-type, the same advantage can be
obtained by making the semiconductor substrate 1 be of the p-type
and the emitter layers 2B and the contact layers 4B be of the
n-type.
[0195] A method for manufacturing the IGBT shown in FIG. 11 will be
described.
[0196] First, an n-type semiconductor substrate (e.g. a silicon
substrate) 1 having, for example, an impurity concentration of
approx. 1.5.times.10.sup.14 ions/cm.sup.2 is prepared. A p-type
base layer 7, an n+-type emitter layer 8, an insulating film 9, a
gate electrode 10 and an emitter electrode 11 are formed on one
surface of the semiconductor substrate 1.
[0197] Subsequently, an n-type impurity such as phosphor (P) is
implanted into the other surface of the semiconductor substrate 1
by ion implantation, and subjected to a thermal diffusion
treatment, thereby forming an n.sup.+-type base layer 12 in a
surface portion of the other surface of the semiconductor substrate
1.
[0198] Then, a p-type impurity such as boron (B) is implanted into
the other surface of the semiconductor substrate 1 by ion
implantation. At this time, the acceleration voltage and the dose,
as implantation conditions, are set at, for example, approx. 60 keV
and approx. 1.times.10.sup.13 ions/cm.sup.2, respectively.
Thereafter, the resultant structure is subjected to a thermal
diffusion process executed in the atmosphere of nitrogen of approx.
1050.degree. C. for approx. 20 min. As a result, p.sup.+-type
emitter layers 2B having a depth of approx. 0.8 .mu.m from the
other surface of the semiconductor substrate 1 are formed.
[0199] Thereafter, a p-type impurity such as boron (B) is implanted
into the p.sup.+-type emitter layers 2B in the other surface of the
semiconductor substrate 1 by ion implantation. At this time, the
acceleration voltage and the dose, as implantation conditions, are
set at, for example, approx. 10 keV and approx. 1.times.10.sup.14
ions/cm.sup.2, respectively. Then, the resultant structure is
subjected to a thermal diffusion process executed in the atmosphere
of nitrogen of approx. 800.degree. C. for approx. 30 min. As a
result, p.sup.++-type contact layers 4B having a depth of approx.
0.16 .mu.m from the other surface of the semiconductor substrate 1
are formed.
[0200] The p.sup.++-type contact layers 4B must be formed very
shallow, and must have a very high impurity concentration. To this
end, the acceleration voltage is set low, the dose is set high, and
the period for executing the thermal diffusion process is set
short, as is described above.
[0201] Boron fluoride (BF.sub.2), for example, may be used as the
p-type impurity, instead of boron (B) (i.e. the element is changed
from a light one to a heavy one), and implanted into the
p.sup.+-type emitter layers 2B in the semiconductor substrate 1,
thereby forming p.sup.++-type contact layers 4B.
[0202] Subsequently, a thermal oxide film formed on a surface
portion of the other surface of the semiconductor substrate 1, i.e.
on a surface portion of the p.sup.++-type contact layers 4B, is
removed using antimony fluoride. Then, a collector electrode 3
extending to the p.sup.++-type contact layers 4B and the
n.sup.+-type base layers 12 is formed by sputtering or CVD.
[0203] Thereafter, the resultant structure is subjected to a heat
treatment executed for approx. 30 min. in the atmosphere of
nitrogen of approx. 450.degree. C., thereby diffusing the atoms
(e.g. aluminum atoms) of the collector electrode 3 into the
semiconductor substrate 1, i.e. into the p.sup.++-type contact
layers 4B and the n.sup.+-type base layers 12, so as to reduce the
contact resistance between the collector electrode 3 and the
p.sup.++-type contact layers 4B, and that between the collector
electrode 3 and the n.sup.+-type base layers 12.
[0204] Thus, the IGBT according to the invention is completed.
[0205] FIG. 12 shows an IGBT as a sixth example of the
invention.
[0206] This example relates to a so-called
collector-short-circuited (or anode-short-circuited) IGBT (a
reference example) as shown in FIG. 10, to which the
above-described second electrode contact section is applied.
[0207] A p-type base layer 7 is formed on one surface of an n-type
semiconductor substrate (n-type base layer) 1, and an n.sup.+-type
emitter layer 8 is formed in the p-type base layer 7. In a surface
area of the one surface of the semiconductor substrate 1, a gate
electrode 10 is formed on the p-type base layer (channel section) 7
between the n-type base layer 1 and the n.sup.+-type emitter layer
8, with an insulating layer 9 interposed therebetween. Further, an
emitter electrode 11 is formed on the p-type base layer 7 and the
n.sup.+-type emitter layer 8.
[0208] A plurality of p.sup.+-type emitter layers 2B and a
plurality of n.sup.+-type base layers 12 are formed on the other
surface of the semiconductor substrate 1. Each p.sup.+-type emitter
layer 2B contains a p-type impurity such as boron (B). The depth of
each p.sup.+-type emitter layer 2B from the other surface of the
semiconductor substrate 1 is set at 1.0 .mu.m or less, for example,
approx. 0.8 .mu.m. Further, the peak value of the concentration
profile of each p.sup.+-type emitter layer 2B is set at a value
falling within the range of 10.sup.17-10.sup.18 ions/cm.sup.3.
[0209] A p.sup.++-type contact layer 4B is formed in each
p.sup.+-type emitter layer 2B, and a collector electrode 3 is
formed on the resultant p.sup.++-type contact layers 4B. Further,
the p.sup.++-type contact layers 4B are interposed between the
respective p.sup.+-type emitter layers 2B and the collector
electrode 3, and have a higher impurity concentration than the
p.sup.+-type emitter layers 2B.
[0210] For example, each p.sup.++-type contact layer 4B contains a
p-type impurity such as boron (B) or boron fluoride (BF.sub.2),
etc., and has an impurity concentration peak value of 10.sup.19
ions/cm.sup.3 or more and a surface impurity concentration of
10.sup.18 ions/cm.sup.3 or more. The depth of each p.sup.++-type
contact layer 4B from the other surface of the semiconductor
substrate 1 is set at 0.2 .mu.m or less, for example, approx. 0.16
.mu.m. The collector electrode 3 is formed of, for example,
aluminum.
[0211] Further, in this example, a silicide layer 5 is provided
between the collector electrode 3 and each p.sup.+-type contact
layer 4B and the collector electrode and each n.sup.+-type base
layer 12. The silicide layer 5 is formed by, for example, a thermal
treatment in which atoms (e.g. aluminum atoms) constituting the
electrode 3 react with atoms (silicon atoms) constituting the
semiconductor substrate 1.
[0212] The depth of the silicide layer 5 from the other surface of
the semiconductor substrate 1 is set equal to or shallower than the
depth of each p.sup.+-type contact layer 4B from the other surface
of the semiconductor substrate 1. In this example, since the depth
of each p.sup.+-type contact layer 4B from the other surface of the
semiconductor substrate 1 is set at 0.2 .mu.m or less, the depth of
the silicide layer 5 from the surface of the semiconductor
substrate 1 is also set at 0.2 .mu.m or less.
[0213] To minimize the contact resistance, it is necessary to make
the position of the bottom of the silicide layer 5 correspond to
that portion of each p.sup.+type contact layer 4B, at which the
concentration profile of each layer 4B assumes a peak value. In
other words, the collector electrode 3 is electrically connected to
the lowest resistance portion of each p.sup.+-type contact layer 4B
(corresponding to a portion thereof at which the concentration
profile assumes the peak value) via the silicide layer 5, thereby
reducing the contact resistance.
[0214] In the electrode contact structure described above, the
p.sup.+-type emitter layers 2B have a low impurity concentration,
and a sufficiently shallow depth of 1.0 .mu.m or less from the
other surface of the semiconductor substrate 1. Accordingly, the
carrier (positive hole) injection coefficient when turning off the
IGBT can be reduced, thereby increasing the speed of the turn-off
operation.
[0215] In addition, since the p.sup.++-type contact layers 4B,
which have a higher impurity concentration than the p.sup.+-type
emitter layers 2B and are provided between the respective
p.sup.+-type emitter layers 2B and the collector electrode 3, are
set to have a depth of 0.2 .mu.m or less from the other surface of
the semiconductor substrate 1, they do not influence the carrier
injection coefficient at the time of turning off the IGBT. In other
words, the p.sup.++-type contact layers 4B do not increase the
carrier injection coefficient.
[0216] Further, the p.sup.++-type contact layers 4B have a
sufficiently high impurity concentration, and the silicide layer 5
is provided between the collector electrode 3 and each p.sup.+-type
contact layer 4B and between the collector electrode 3 and each
n.sup.+-type base layer 12. The position of the bottom of the
silicide layer 5 is made to correspond to that portion of each
p.sup.+-type contact layer 4B, at which the concentration profile
of each layer 4B assumes a peak value. Accordingly, the contact
resistance of the electrode contact section is further reduced.
[0217] Thus, the electrode contact section of the IGBT according to
the invention enables the simultaneous realization of a sufficient
reduction of the contact resistance and reduction of the carrier
injection coefficient.
[0218] Although in the above-described example, the semiconductor
substrate 1 is of the n-type and the emitter layers 2B and the
contact layers 4B are of the p-type, the same advantage can be
obtained by making the semiconductor substrate 1 be of the p-type
and the emitter layers 2B and the contact layers 4B be of the
n-type.
[0219] A method for manufacturing the IGBT shown in FIG. 12 will be
described.
[0220] First, an n-type semiconductor substrate (e.g. a silicon
substrate) 1 having, for example, an impurity concentration of
approx. 1.5.times.10.sup.14 ions/cm.sup.2 is prepared. A p-type
base layer 7, an n+-type emitter layer 8, an insulating film 9, a
gate electrode 10 and an emitter electrode 11 are formed on one
surface of the semiconductor substrate 1.
[0221] Subsequently, an n-type impurity such as phosphor (P) is
implanted into the other surface of the semiconductor substrate 1
by ion implantation, and subjected to a thermal diffusion
treatment, thereby forming an n.sup.+-type base layer 12 in a
surface portion of the other surface of the semiconductor substrate
1.
[0222] Then, a p-type impurity such as boron (B) is implanted into
the other surface of the semiconductor substrate 1 by ion
implantation. At this time, the acceleration voltage and the dose,
as implantation conditions, are set at, for example, approx. 60 keV
and approx. 1.times.10.sup.13 ions/cm.sup.2, respectively.
Thereafter, the resultant structure is subjected to a thermal
diffusion process executed in the atmosphere of nitrogen of approx.
1050.degree. C. for approx. 20 min. As a result, p.sup.+-type
emitter layers 2B having a depth of approx. 0.8 .mu.m from the
other surface of the semiconductor substrate 1 are formed.
[0223] Thereafter, a p-type impurity such as boron (B) is implanted
into the p.sup.+-type emitter layers 2B in the other surface of the
semiconductor substrate 1 by ion implantation. At this time, the
acceleration voltage and the dose, as implantation conditions, are
set at, for example, approx. 10 keV and approx. 1.times.10.sup.14
ions/cm.sup.2, respectively. Then, the resultant structure is
subjected to a thermal diffusion process executed in the atmosphere
of nitrogen of approx. 800.degree. C. for approx. 30 min. As a
result, p.sup.++-type contact layers 4B having a depth of approx.
0.16 .mu.m from the other surface of the semiconductor substrate 1
are formed.
[0224] The p.sup.++-type contact layers 4B must be formed very
shallow, and must have a very high impurity concentration. To this
end, the acceleration voltage is set low, the dose is set high, and
the period for executing the thermal diffusion process is set
short, as is described above.
[0225] Boron fluoride (BF.sub.2), for example, may be used as the
p-type impurity, instead of boron (B) (i.e. the element is changed
from a light one to a heavy one), and implanted into the
p.sup.+-type emitter layers 2B in the semiconductor substrate 1,
thereby forming p.sup.++-type contact layers 4B.
[0226] Subsequently, a thermal oxide film formed on a surface
portion of the other surface of the semiconductor substrate 1, i.e.
on a surface portion of the p.sup.++-type contact layers 4B, is
removed using antimony fluoride. Then, a collector electrode 3
having a thickness of approx. 0.05 .mu.m is formed on the
p.sup.++-type contact layers 4B and the n.sup.+-type base layers 12
by sputtering or CVD.
[0227] Thereafter, the resultant structure is subjected to a heat
treatment executed for approx. 30 min. in the atmosphere of
nitrogen of approx. 450.degree. C., thereby diffusing the atoms
(e.g. aluminum atoms) of the collector electrode 3 into the
semiconductor substrate 1, i.e. into the p.sup.++-type contact
layers 4B and the n.sup.+-type base layers 12, so as to form a
silicide layer 5. The thickness of the silicide layer 5 (the depth
from the other surface of the semiconductor substrate 1) is made
substantially equal to that thickness of each p.sup.++-type contact
layer 4B from the other surface of the semiconductor substrate 1,
at which the concentration profile of each layer 4B assumes a peak
value.
[0228] For example, when the concentration profile of each layer 4B
assumes the peak value at a depth of approx. 0.04 .mu.m from the
other surface of the semiconductor substrate 1, the silicide layer
5 is made to have a thickness of approx. 0.04 .mu.m.
[0229] As a result, the contact resistance between the collector
electrode 3 and each p.sup.+-type emitter layer 2B in the electrode
contact section and between the collector electrode 3 and each
n.sup.+-type base layer 12 is reduced.
[0230] The collector electrode 3 may be formed after forming the
silicide layer 5.
[0231] Thus, the IGBT according to the invention is completed.
[0232] [D] Advantage
[0233] As described above, in the present invention, the peak value
of the concentration profile of the p-type impurity layer (the
p.sup.+-type emitter layer) is set at a value falling within the
range of 10.sup.17-10.sup.18 ions/cm.sup.3. Further, the depth of
the p-type impurity layer from the surface of the semiconductor
substrate is set at a sufficient low value of 1.0 .mu.m or less.
Accordingly, the carrier injection coefficient when turning off the
IGBT can be reduced, thereby increasing the speed of the turn-off
operation.
[0234] Moreover, a p.sup.+-type contact layer having a higher
impurity concentration than the p-type impurity layer (the
p.sup.+-type emitter layer) is provided between the p-type impurity
layer and the electrode 3. Since the depth of the p.sup.+-type
contact layer from the surface of the semiconductor substrate is
set at 0.2 .mu.m or less, the p.sup.+-type contact layer does not
influence the carrier injection coefficient at the time of turning
off the semiconductor device. Further, since the peak value of the
concentration profile of the p.sup.+-type contact layer is set at
approx. 10.sup.19 ions/cm.sup.3, the contact resistance of the
electrode contact section is reduced.
[0235] In addition, the p.sup.+-type contact layer has a
sufficiently high impurity concentration, and a silicide layer is
provided between the electrode and the p.sup.+-type contact layer.
The position of the bottom of the silicide layer is made to
correspond to that portion of the p.sup.+-type contact layer, at
which the concentration profile of the contact layer assumes a peak
value. Accordingly, the contact resistance of the electrode contact
section is further reduced.
[0236] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *