Semiconductor integrated circuit, operating state detector, and electronic equipment

Abstract

The present invention relates to a semiconductor integrated circuit having function blocks with differing operating frequencies and to a semiconductor integrated circuit wherein the threshold voltages of MOS transistors that configure these function blocks are different for each function block. In first to Nth function blocks (30-1 to 30-N), which are supplied with constant voltages (V.sub.C1 to V.sub.CN) generated by a constant voltage generation section (20) as power voltages, any variation in operating speed or in the capability of the transistors is detected by an operating state detector (40) as a voltage (V.sub.fre). Further, an operating state encoding section (50) encodes the voltage (V.sub.fre), a voltage output control section (60) modifies basic voltages (V.sub.B1 to V.sub.BN) of the constant voltage generation section (20), and constant voltages (V.sub.C1 to V.sub.CN) for the function blocks (30-1 to 30-N) is modified.

Description

TECHNICAL FIELD

[0001] The present invention relates to an improvement in a semiconductor integrated circuit and electronic equipment using the same, comprising a constant voltage generation section that increases or decreases a power voltage supplied from an external power source to generate a constant voltage, and a function block that uses the constant voltage generated from the constant voltage generation section as a power source.

BACKGROUND OF ART

[0002] An example of this type of semiconductor integrated circuit is shown in FIG. 11. In FIG. 11, a reference power voltage 2 obtained from an external power source 1 is supplied to a constant voltage generation device 3. The constant voltage generation device 3 generates a fixed constant voltage 4, based on the reference power voltage 2, and supplies it as a power voltage to first and second function blocks 6A and 6B. The first and second function blocks 6A and AB convert any input signals 5A and AB based on corresponding specific functions, to generated output signals 7A and AB having specific functions. When the first and second function blocks 6A and AB are in a standby state, the operation of the corresponding first and second function blocks 6A and 6B is halted and the current supplied from the output constant voltage 4 is reduced by suppressing the signals 5A and AB by function stop signals 8A and AB.

[0003] With a conventional semiconductor integrated circuit, the constant voltage 4 is necessary for enabling response at the highest operating speed for all operating states for converting any input signals 5A and AB to specific functions.

[0004] However, when the constant voltage 4 is supplied at the highest operating speed in all of the operating states of the first and second function blocks 6A and AB, even if it is necessary for one function block 5A to operate at the highest speed, it could happen that such an operating speed is not required for the other function block 5B. As a case in which the difference between the highest operating speed and the lowest operating speed in operation is extremely large, it is possible to consider that a data access circuit and a frequency converter are used in common within the semiconductor integrated circuit.

[0005] If prior-art techniques are used, a high power voltage corresponding to the highest response speed will be necessary for one function block 6A in such a case, and it is not possible to control the power consumption.

[0006] With prior-art techniques, although it is possible to reduce the operating current on standby, a large amount of operating current is consumed during operation when the semiconductor integrated circuit contains at least two circuits having different operating speed respectively and there is an extremely large difference between the highest operating speed and the lowest operating speed while in the operating state, because the power voltage while in the operating state is supplied as a voltage level at a signal response that is enabled by the highest operating speed of the function blocks. It is therefore difficult to guarantee the circuit response speed at both the highest operating speed and the lowest operating speed necessary for the function blocks, while simultaneously implementing a reduction in power current.

[0007] The MOS transistors that configure the plurality of function blocks often have different threshold voltages, due to unevenness in the semiconductor wafer surface during the manufacturing process. This raises a technical problem in that the frequency response speeds will be different for each function block, even if the same power voltage is supplied to all of the function blocks operating at the same speed.

[0008] An objective of the present invention is to provide a semiconductor integrated circuit and electronic equipment using the same which solve the previously described technical problems and make it possible to reduce the operating current flowing during operation and thus reduce the power consumption, even if there are at least two circuits, which have different operating speed respectively, coexisting within the semiconductor integrated circuit, and the difference between the highest operating speed and the lowest operating speed is extremely large.

[0009] Another objective of the present invention is to provide a semiconductor integrated circuit and electronic equipment using the same which make it possible to reduce variations in the frequency response speeds of a plurality of function blocks, even when the manufacturing process has created differences in the threshold voltages of MOS transistors configuring those function blocks and the same power voltage is supplied to the function blocks operating at the same operating speed.

DISCLOSURE OF INVENTION

[0010] A semiconductor integrated circuit in accordance with the present invention comprises:

[0011] at least one constant voltage generation section for increasing or decreasing a power voltage supplied from at least one external power source, based on a basic voltage, to generate at least one constant voltage;

[0012] at least one function block to which is supplied the at least one constant voltage generated by the at least one constant voltage generation section;

[0013] at least one operating state detection section for generating a second signal indicating an operating state of the at least one function block, based on a first signal including operating speed information of the at least one function block;

[0014] at least one operating state encoding section for encoding an operating state of the function block to generate operating state data, based on the second signal; and

[0015] at least one voltage output control section for modifying the basic voltage of the at least one constant voltage generation section, based on the operating state data.

[0016] The semiconductor integrated circuit of this aspect of the invention makes it possible to obtain the optimal power voltage necessary for the operation of the function blocks, based on the generation of a second signal indicating the operating state of these function blocks, which in turn is based on a first signal comprising operating speed information (the actual operating frequency) of each function block. The semiconductor integrated circuit of the present invention also makes it possible to implement the supply of the optimal power voltage corresponding to the operating speed of each function block, even when the threshold voltages of the MOS transistors thereof vary from the design values during the manufacturing process.

[0017] This aspect of the invention makes it possible to achieve the effect of reducing the power consumption by setting power voltages that are optimized for the operation of each of the function blocks from a signal period in which rapid operation is necessary to a signal period in which the response during low-speed operation is sufficient.

[0018] With this aspect of the present invention, an operating-setting signal is preferably input to each function block, and that function block supplies the first signal to the at least one operating state detection section when the operating-setting signal is active.

[0019] In such a case, the operating-setting signal could be set in such a manner that it becomes active at timings on the time axis that differ for each of the plurality of function blocks.

[0020] This means that one each of the at least one operating state detection section, at least one operating state encoding section, at least one voltage output control section, and at least one constant voltage generation section can be used in common for the plurality of function blocks.

[0021] With this aspect of the present invention, the voltage output control section may comprise a digital-analog converter for performing a digital-to-analog conversion on the operating state data; and a sample-and-hold circuit for sampling an output of the digital-analog converter based on the operating-setting signal, and generating the basic voltage. This configuration makes it possible to continue to hold a proper basic voltage for each function block, to ensure the optimal constant voltage for each function block.

[0022] With the present invention, the operating state detection section may further comprise an integrator for integrating the first signal; and a peak detector for detecting a peak value of an output of the integrator, and holding the peak value as the second signal.

[0023] Alternatively, in stead of the above described peak detector, the operating state detection section of the present invention may further comprise a peak-to-peak detector for detecting a voltage amplitude of an output of the integrator, and holding the voltage amplitude as the second signal.

[0024] This configuration makes it possible to apply negative feedback accurately, even when the manufacturing process has changed the threshold voltages of the P- and N-channel transistors from their design values, and there are differences in the amplitude between the rise and fall of the integrator output.

[0025] With the present invention, the operating state encoding section may comprise a plurality of comparators for comparing the voltage level of the second signal with each of a plurality of reference voltage levels; and a decoder for encoding outputs of the plurality of comparators. This makes it easy to use the second signal for encoding, for providing negative feedback.

[0026] The operating state encoding section of the present invention may further comprise a plurality of voltage-dividing resistors for dividing the constant voltage from the constant voltage generation section, to create the plurality of reference voltage levels.

[0027] This configuration makes it easy to create a preliminary signal when encoding is implemented based on the second signal.

[0028] In a semiconductor integrated circuit in accordance with another aspect of the present invention, the at least one operating state detection section is modified into at least one frequency-voltage converter, and the at least one frequency-voltage converter converts the actual operating frequency of the at least one function block into a voltage level.

[0029] As described previously, a second signal that indicates the operating state of each function block is generated based on a first signal containing the actual operating frequency of that function block, then the optimal power voltage necessary for the operation of the function block is obtained therefrom.

[0030] This frequency-voltage converter preferably converts a frequency of an input signal that is input to the function block into a voltage level. This is because the input signal usually contains the maximum frequency among the signals within the function block, so it reflects the actual operating frequency of the function block.

[0031] Since power consumption can be reduced in electronic equipment in accordance with the present invention, which comprises the above semiconductor integrated circuit, it can be applied as appropriate to many different applications, particularly to timepieces, mobile computers, and portable phones.

BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a block diagram of a first embodiment of the present invention;

[0033] FIG. 2 is a block diagram showing details of a configuration in which a first function block of FIG. 1 is operating as a frequency converter and negative feedback is used to modify the constant voltage supplied to that frequency converter;

[0034] FIG. 3 is a timing chart showing signal waveforms during the process of applying negative feedback in the configuration of FIG. 2;

[0035] FIG. 4 is a schematic view illustrating the operation of the operating state encoding section of FIG. 2;

[0036] FIG. 5 is a timing chart showing signal waveforms during the process of using negative feedback to modify the constant voltage supplied to the second function block;

[0037] FIG. 6 is a timing chart showing signal waveforms during the process of using negative feedback to modify the constant voltage supplied to the Nth function block;

[0038] FIG. 7 is a timing chart of a second embodiment of the present invention, showing the signal waveforms during the process of using negative feedback to modify the constant voltages supplied to function blocks to which the same input signal is input, when the threshold voltages Vth of the MOS transistors configuring the function blocks of FIG. 1 are different;

[0039] FIG. 8 is a block diagram of a device in accordance with a third embodiment of the present invention;

[0040] FIG. 9 is a timing chart showing signal waveforms during the process of using negative feedback to modify the constant voltage supplied to the plurality of function blocks used in the circuit of FIG. 8;

[0041] FIG. 10 is a block diagram of electronic equipment in accordance with a fourth embodiment of the present invention; and

[0042] FIG. 11 is a block diagram of a prior-art semiconductor integrated circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[0043] First Embodiment

[0044] A first embodiment of the present invention is described below with reference to FIGS. 1 to 6.

[0045] FIG. 1 is a block diagram of the overall structure of the device in accordance with an embodiment of the present invention. In FIG. 1, the device of this embodiment comprises an external power source 1 and a semiconductor integrated circuit 10. The semiconductor integrated circuit 10 comprises a constant voltage generation section 20, first to Nth function blocks 30-1 to 30-N, an operating state detector 40, an operating state encoding section 50, and a voltage output control section 60.

[0046] The device of this embodiment is characterized in that constant voltages V.sub.C (V.sub.C1 to V.sub.CN) that are supplied to the first to Nth function blocks 30-1 to 30-N, respectively, can be controlled by negative feedback based on the operating states of the corresponding first to Nth function blocks 30-1 to 30-N, in other words, their actual operating frequencies.

[0047] A power voltage VS that is output from the external power source 1 is supplied to the constant voltage generation section 20, where the constant voltages V.sub.C1 to V.sub.CN are generated with reference to basic voltages V.sub.B1 to V.sub.BN. The constant voltages V.sub.C1 to V.sub.CN generated by the constant voltage generation section 20 are supplied as power voltages to the corresponding first to Nth function blocks 30-1 to 30-N. The first to Nth function blocks 30-1 to 30-N use their specific functions to modify corresponding input signals V.sub.IN1 to V.sub.INN and generate corresponding output signals V.sub.OUT1 to V.sub.OUTN. When the operation stopping signals S.sub.STOP1 to S.sub.STOPN are non-active (i.e., are at the 1-state) and the operation determination setting signals S.sub.SET1 to S.sub.SETN are active (i.e., are at the 1-state), the input signals V.sub.IN1 to V.sub.INN that are input to the corresponding first to Nth function blocks 30-1 to 30-N are output as the operation signal S1 without change to the operating state detector 40.

[0048] When the operation determination setting signals S.sub.SET1 to S.sub.SETN are at the 0-state, the operation signal S1 is not generated from the first to Nth function blocks 30-1 to 30-N. Note that each of the operation determination setting signals S.sub.SET1 to S.sub.SETN becomes active at a different timing on the time axis. Therefore, the operating states of the first to Nth function blocks 30-1 to 30-N are detected by the operating state detector 40 at correspondingly different timings.

[0049] The operating state detector 40 outputs to the operating state encoding section 50 an operating state signal S2 having a voltage V.sub.fre corresponding to the operating states of the first to Nth function blocks 30-1 to 30-N, in other words, their actual operating frequencies, based on the operation signal S1. This means that the operating state detector 40 functions as a frequency-voltage converter.

[0050] The operating state encoding section 50 detects the voltage V.sub.fre of the operating state signal S2 and generates n-bit digitized operating state data D in accordance with voltage level encoding information that has been set previously.

[0051] This operating state data D is input to the voltage output control section 60. The voltage output control section 60 converts the operating state data D into voltages in accordance with voltage generation information that was set previously. These converted voltages are supplied to the constant voltage generation section 20 as the basic voltages V.sub.B1 to V.sub.BN.

[0052] The constant voltage generation section 20 modifies the levels of the constant voltages V.sub.C1 to V.sub.CN forming the power voltages for the first to Nth function blocks 30-1 to 30-N, based on the thus-supplied basic voltages V.sub.B1 to V.sub.BN.

[0053] The description now turns to the operation and a specific configuration for modifying and controlling the constant voltage V.sub.C1 of the first function block 30-1 of FIG. 1 by negative feedback, with reference to FIGS. 2 to 4.

[0054] FIG. 2 is a block diagram of a specific configuration for modifying and controlling the constant voltage V.sub.C1 of the first function block 30-1 by negative feedback.

[0055] The power voltage VS that is output from the external power source 1 is supplied to the constant voltage generation section 20, which generates the constant voltage V.sub.C1 with reference to the basic voltage V.sub.B1. This constant voltage generation section 20 comprises an operational amplifier 22, a transistor Q1, and two resistors R1 and R2. The basic voltage V.sub.B1 from the voltage output control section 60 is connected to an inverted-input pin of the operational amplifier 22 and the connection point between the resistors R1 and R2 is connected to a direct-input pin of the operational amplifier 22. This configuration ensures that the operational amplifier 22 and the other components form a negative feedback amplification circuit, such that if the voltage at the direct-input pin varies with respect to the basic voltage V.sub.B1 the output of the operational amplifier 22 is also changed, ensuring that the output of the operational amplifier 22 is stable. The voltage V.sub.C1 that is output from the constant voltage generation section 20 during this stage is given by:

V.sub.C1=V.sub.B1.times.R1/(R1+R2)

[0056] It is clear that, if the basic voltage V.sub.B1 varies, the constant voltage V.sub.C1 can also be varied in this manner.

[0057] Note that the constant voltage generation section 20 shown in FIG. 2 does not include the circuitry for generating the constant voltages VC.sub.2 to V.sub.CN to be supplied to the second to Nth function blocks 30-2 to 30-N, based on the basic voltages VB.sub.2 to V.sub.BN, but in actual practice there will be N negative feedback amplification circuits, comprising the operational amplifier 22, the transistor Q1, and the resistors R1 and R2 within the constant voltage generation section 20. In the state before negative feedback is applied, the basic voltages V.sub.B1 to V.sub.BN are set to initial voltages.

[0058] The constant voltage V.sub.C1 that is generated by the constant voltage generation section 20 is applied as the power voltage to the first function block 30-1. The first function block 30-1 modifies any input signal S.sub.IN1 into any frequency to generate the output signal V.sub.OUT1, by using flip-flops D.sub.F0 to D.sub.Fm and frequency-switching signals F.sub.D0 to F.sub.Dm, in accordance with setting signals F.sub.S0 to F.sub.Sm and resetting signals F.sub.R0 to F.sub.Rm that are generated by a frequency setting decoder 34.

[0059] The signal S.sub.IN1 that has been input to the first function block 30-1 is input to a logical product gate AND together with the function stop signal S.sub.STOP1 and the input signal S.sub.IN1 is output without change in the function stop signal S.sub.STOP1 is non-active, in other words, when it is at the 1-state. When the function stop signal S.sub.STOP1 is active, in other words, at the 0-state, the logical product gate AND does not transmit the input signal S.sub.IN1; it controls the input signal S.sub.IN1 to be at the 0-state and stops the functioning of the first function block 30-1.

[0060] The input signal S.sub.IN1 that is output when the function stop signal S.sub.STOP1 is at the 1-state is output to the operating state detector 40 (see FIG. 3) as the operation signal S1 through the operating state transmitter 32, when the operation determination setting signal S.sub.SET1 is at the 1-state (period T.sub.1 in FIG. 3). Note that when the operation determination setting signal S.sub.SET1 is in the 0-state, the input signal S.sub.IN1 is not transferred to the operating state transmitter 32 and the operation signal S1 remains at the 0-state.

[0061] The operating state detector 40 comprises an integrator 42 and a peak detector 42. The input operation signal S1 is integrated by the integrator 42 to become an integration signal S.sub.INTE. The peak value of this integration signal S.sub.INTE is held by the peak detector 44 and the operating state signal S2 is generated therefrom (see FIG. 3).

[0062] As described previously, the operating state detector 40 functions as a frequency-voltage converter for detecting a voltage corresponding to the actual operating frequency of the first function block 30-1, in order to detect the operating state of the first function block 30-1. To ensure that the input signal S.sub.IN1 contains the maximum frequency of all the signals that are used by the first function block 30-1, the configuration is generally such that the operating state detector 40 of this embodiment integrates the input signal S.sub.IN1 and holds the peak value thereof. Therefore, the voltage V.sub.fre of the operating state signal S2, which is the output of the operating state detector 40, is at a level corresponding to the actual operating frequency of the first function block 30-1.

[0063] This operating state signal S2 is input to the operating state encoding section 50. This operating state encoding section 50 comprises resistors r.sub.0 to r.sub.n, voltage comparators 52-1 to 52-n, and a decoder 54. The resistors r.sub.0 to r.sub.n are connected in series and the constant voltage V.sub.C1 is applied to the resistor r.sub.0. This constant voltage V.sub.C1 is divided by the resistors r.sub.0 to r.sub.n to generate reference voltages V.sub.ref to V.sub.refn at the connection points of respective resistors.

[0064] The voltage V.sub.fre of the operating state signal S2 is input in common to the direct-input pins of n voltage comparators 52-1 to 52-n, and the reference voltages V.sub.ref1 to V.sub.refn are input individually to the corresponding inverted-input pins thereof.

[0065] Thus the n voltage comparators 52-1 to 52-n compare the corresponding reference voltages V.sub.ref1 to V.sub.refn with the voltage of the operating state signal S2. This will be described below with reference to FIG. 4. Voltage is plotted along the vertical axis of FIG. 4 and if the resistances for the previously described reference voltages V.sub.ref1 to V.sub.refn are all the same, the relationships between the reference voltages V.sub.ref1 to V.sub.refn are as shown in FIG. 4. If the level of the voltage V.sub.fre of the operating state signal S2 is V.sub.P1, as shown in FIG. 4, the outputs of the nvoltage comparators 52-1 to 52-n is expressed as (00001111) if represented in sequence by 1 or 0 for n=8.

[0066] The outputs of these n voltage comparators 52-1 to 52-n are input to the decoder 54 where they are encoded. The decoder 54 inverts the string of data (00001111) of the signals input from the n voltage comparators 52-1 to 52-n, from the most significant bit to the least significant bit, for the encoding. This means that the output of the decoder 54 is (11110000) in the above-described example. Otherwise, if the voltage V.sub.fre of the operating state signal S2 is determined to be the maximum value V.sub.ref1 of the comparison voltage, for example, the decoder 54 encodes the minimum digital data (00000000); if it is determined to be the minimum value V.sub.refn, for example, it encodes the maximum digital data (11111111); to generate the n-bit operating state data D.

[0067] This operating state data D is input to the voltage output control section 60 which is configured of a digital-analog converter 62 and a sample-and-hold circuit 64. Thus input operating state data D, which is n-bit digital data, is converted by the digital-analog converter 62 to an analog voltage. Further, the analog voltage is sampled by the operating-setting signal S.sub.SET1 at the sample-and-hold circuit 64, and the level of the analog voltage is held when the operating-setting period ends (when the operating-setting signal S.sub.SET1 switches from 1 to 0), to modify the basic voltage of the constant voltage generation section 20 from the initial voltage to V.sub.B1. The constant voltage generation section modifies the level of the constant voltage V.sub.C1 based on the modified basic voltage V.sub.B1, as described previously. As a result, the first function block 30-1 is supplied with the constant voltage V.sub.C1 fitting to the operating state thereof, as the power voltage.

[0068] Signal waveforms used in the process of modifying the constant voltages V.sub.C2 and V.sub.CN by negative feedback for the second function block 30-2 and the Nth function block 30-N in the circuit of FIG. 1 are shown in FIGS. 5 and 6, respectively, in a similar manner to that of FIG. 3.

[0069] In this case, the periods T.sub.1, T.sub.2, and T.sub.N during which the corresponding operation determination setting signals S.sub.SET1, S.sub.SET2and S.sub.SETN are active in FIGS. 3, 5, and 6 are set to different timings on the time axis. This ensures that a negative feedback amplification circuit comprising the operating state detector 40, the operating state encoding section 50, the voltage output control section 60, and the constant voltage generation section 20 can be used in common by a plurality of function blocks which are the first to Nth function blocks 30-1 to 30-N.

[0070] It is clear from a comparison of FIGS. 3, 5, and 6 in this case that, if the frequencies of the input signals S.sub.IN1, S.sub.IN2, and S.sub.INN that are input to the first, second, and Nth function blocks 30-1, 30-2, and 30-N are S.sub.fre1, S.sub.fre2, and S.sub.freN, respectively, their relationship is such that: S.sub.fre2<S.sub.fre1&l- t;S.sub.freN. In addition, the effective value (area under the rectangular waveform) of the input signal increases as the operating frequency decreases, so that the power consumed by the function block increases.

[0071] With this embodiment, if the power consumption of a function block is increasing, the constant voltage that is supplied thereto decreases, so that the power consumed thereby decreases.

[0072] The relationships between the peak voltage V.sub.P1 of the operating state signal S2 of FIG. 3 and the peak voltages V.sub.P2 and V.sub.PN of the operating state signal S2 of FIGS. 4 and 6 are such that: V.sub.PN<V.sub.P1<V.sub.P2. Thus the relationships between the basic voltages V.sub.B1, V.sub.B2, and V.sub.BN generates by the sample-and-hold circuit 64 are V.sub.B2<V.sub.B1<V.sub.BN. This makes it possible to reduce the constant voltage supplied to a function block in which the operating frequency has dropped, enabling a reduction in power consumption.

[0073] Second Embodiment

[0074] The timing chart of FIG. 7 shows the signal waveforms obtained when the threshold voltages of MOS transistors that configure the semiconductor integrated circuit 10 of FIG. 1 are different for each function block, and the circuitry of FIGS. 1 and 2 is used to apply negative feedback, in a similar manner to that of FIG. 3.

[0075] In this case, if the threshold voltage of the MOS transistor of the first function block 30-1 is assumed to be V.sub.th1, the threshold voltage of the MOS transistor of the second function block 30-2 is assumed to be V.sub.th2, and the threshold voltage of the MOS transistor of the Nth function block 30-N is assumed to be V.sub.thN the relationships between these threshold voltages are: V.sub.th2<V.sub.th1<V.sub.thN.

[0076] When the constant voltage V.sub.C1 of the first function block 30-1 is modified by negative feedback, the threshold voltage of the MOS transistor is V.sub.th1, and thus the peak value of an integration signal S.sub.INTE1 from the integrator 42 is V.sub.P1. Similarly, when the constant voltages VC.sub.2 and V.sub.CN of the second and Nth function blocks 30-2 and 30-N are modified, the threshold voltages of the MOS transistors in each block are V.sub.th2 and V.sub.thN, and thus integration signals S.sub.INTE2 and S.sub.INTEN from the integrator 42 are at V.sub.P2 and V.sub.PN, respectively.

[0077] With the previously described embodiment, the peak value of the input signal S.sub.IN is different if the frequency thereof is different, but with this embodiment, differences in the threshold voltages of the MOS transistors configuring the function blocks ensures that the peak values are still different, even if an input signal S.sub.IN of the same frequency shown in FIG. 7 is input to each of the function blocks 30-1, 30-2, and 30-N. It should be noted that although only the operating-setting signal S.sub.SET1 is shown to be active during the period T.sub.1 in FIG. 7, the peak values V.sub.P2 and V.sub.PN described above are detected in periods T.sub.2 and T.sub.N during which the operating-setting signals S.sub.SET2 and S.sub.SETN are active, respectively. The relationships between these peak values is, as shown in FIG. 7, such that: V.sub.PN<V.sub.P1<V.sub.P2.

[0078] Since the threshold voltage of a MOS transistor changes depending on factors present during the manufacturing process, therefore, the relationship of the threshold voltage V.sub.th and the voltage V.sub.IN of the input signal S.sub.IN with respect to the on-resistance Ron of the MOS transistor when it is operating is: Ron=1/(K.times.V.sub.IN-V.sub.th)- . This constant K is determined by the manufacturing process of the semiconductor integrated circuit and the physical form of the MOS transistor. Thus, if the voltage VIN of the input signal S.sub.IN is the same and the constant K is fixed, the on-resistance Ron of the MOS transistor changes with variations in the threshold voltage V.sub.th thereof. This means that the on-resistance Ron increases when the threshold voltage V.sub.th increases, and the on-resistance Ron decreases when the threshold voltage V.sub.th decreases. Thus the voltage amplitude of the integration signal S.sub.INTE changes as the output impedance of the signal that is input to the integrator 42 changes.

[0079] The relationship between the on-resistance Ron and V.sub.th of the MOS transistor ensures that the relationships between the peak voltage V.sub.P1, the peak voltage V.sub.P2, and the peak voltage V.sub.PN are, as mentioned previously: V.sub.PN<V.sub.P1<V.sub.P2.

[0080] In this embodiment too, the constant voltages V.sub.C1, V.sub.C2, and V.sub.CN supplied to the corresponding function blocks 30-1, 30-2, and 30-N are modified by negative feedback based on the basic voltages V.sub.B1, V.sub.B2, and V.sub.BN that are modified in accordance with the peak voltages thereof, so that there is no variation in frequency response speed between the first to Nth function blocks 30-1 to 30-N, even when an input signal S.sub.IN of the same frequency is input to the function blocks 30-1 to 30-N.

[0081] Third Embodiment

[0082] A block diagram of a circuit in accordance with a third embodiment of the present invention is shown in FIG. 8. The circuit of FIG. 8 differs from the circuit shown in FIG. 2 in that a peak-to-peak detector 70 is used instead of the peak detector 44 of FIG. 2.

[0083] This peak-to-peak detector 70 differs from the peak detector 44 in that it holds the voltage amplitude of the integration signal S.sub.INTE1 in contrast to the peak detector 44 which detects and hold the peak value of the integration signal S.sub.INTE1.

[0084] The timing chart of FIG. 9 shows the signal waveforms obtained when the threshold voltages of MOS transistors that configure the semiconductor integrated circuit 10 of FIG. 1 are different for each function block, and the circuitry of FIGS. 1 and 8 is used to apply negative feedback.

[0085] The relationships between the threshold voltages of P-channel MOS transistors configuring the first, second, and Nth function blocks 30-1, 30-2, and 30-N are such that: V.sub.thp2<V.sub.tbp1<V.sub.thpN.

[0086] In this case, the threshold voltage of the P-channel MOS transistor of the first function block 30-1 is V.sub.thp1, the threshold voltage of an N-channel MOS transistor is V.sub.thn1, and the voltage amplitude of the integration signal S.sub.INTE1 generated by the integrator 44 is V.sub.pp1 (see FIG. 9).

[0087] The threshold voltage of the P-channel MOS transistor of the second function block 30-2 is V.sub.thp2, the threshold voltage of an N-channel MOS transistor is V.sub.thn2, and the voltage amplitude of the integration signal S.sub.INTE2 generated by the integrator 44 is V.sub.pp2 (see FIG. 9).

[0088] The threshold voltage of the P-channel MOS transistor of the Nth function block 30-N is V.sub.thpN the threshold voltage of an N-channel MOS transistor is V.sub.thnN and the voltage amplitude of the integration signal S.sub.INTEN generated by the integrator 44 is V.sub.ppN (see FIG. 9).

[0089] When the relationships between these voltage amplitudes is, as shown in FIG. 9, such that: V.sub.ppN<V.sub.pp2<V.sub.pp1; the relationships between the basic voltages V.sub.B1, V.sub.B2, and V.sub.BN that are each generated by the sample-and-hold circuit 64 is: V.sub.B2 <V.sub.B1<V.sub.BN; and the threshold voltages of each of the P-channel MOS transistors and N-channel MOS transistors are different for each function block; there is no variation in frequency response speed between the function blocks, even when an input signal S.sub.IN of the same frequency is input to the function blocks, in a similar manner to that exhibited by the second embodiment.

[0090] This embodiment is particularly superior to the use of the peak detector 44 of FIG. 2 in that, even if there are differences in amplitude between rise and fall of the initial integrated waveform, the voltage amplitude of the integrated waveforms that are used in common can be detected accurately, as shown in FIG. 9 for the integration signal S.sub.INTE2.

[0091] Fourth Embodiment

[0092] A block diagram of electronic equipment that uses a semiconductor integrated circuit having the previously described voltage control section is shown in FIG. 10.

[0093] This electronic equipment 310 is configured of a system control section 312, a specific function generation section 313, and a semiconductor integrated circuit 300 that are all driven by a power source 311. The system control section 312 has the function of controlling the entire system of the electronic equipment 310, such as a microprocessor, bus control system, or memory control system. The specific function generation section 313 functions to provide specific control over a device such as a data transfer device, an internal or external storage device, or a input-output device. The system control section 312 and the specific function generation section 313 are connected by input-output signals 315, for inputting and outputting signals and data. The power source 311 supplies a power voltage 314 to all of structural elements of the electronic equipment 310.

[0094] The semiconductor integrated circuit 300 provided within the electronic equipment 310 uses an internal power voltage control section 302 to raise or lower the voltage of an internal constant-voltage source 303 and thus modify the power voltage supplied to a group of function blocks 304, when there is a change in the operating speed of an input signal 301 imparted thereto by the system control section 312 and the specific function generation section 313. When the voltage that is output by the internal constant-voltage source 303 of the semiconductor integrated circuit 300 is modified, the semiconductor integrated circuit 300 generates a detection signal 305 and supplies it to the system control section 312 and the specific function generation section 313. This detection signal 305 is used to convey to the system control section 312 and the specific function generation section 313 the instruction that the power consumption of the semiconductor integrated circuit 300 is being controlled.

[0095] Note that the present invention is not limited to the above-described embodiments and various other modifications thereof are possible within the scope of the present invention. For example, the embodiment shown in FIG. 1 uses the low voltage generation section 20, the operating state detector 40, the operating state encoding section 50, and the voltage output control section 60 in common for the plurality of function blocks 30-1 to 30-N, but these components could be provided individually for each of these function blocks. Similarly, the embodiment of FIG. 1 has a configuration such that power is supplied from one external power source 1 to the semiconductor integrated circuit 10, but the present invention can also be applied to a semiconductor integrated circuit in which different power voltages of, for example, 3 V, 5 V, and so on are supplied from a plurality of external power sources. In such a case, it would be necessary to provide the same number of constant voltage generation sections as external power sources.

Claims

What is claimed is:

1. A semiconductor integrated circuit comprising: at least one constant voltage generation section for increasing or decreasing a power voltage supplied from at least one external power source, based on a basic voltage, to generate at least one constant voltage; at least one function block to which is supplied said at least one constant voltage generated by said at least one constant voltage generation section; at least one operating state detection section for generating a second signal indicating an operating state of said at least one function block, based on a first signal including operating speed information of said at least one function block; at least one operating state encoding section for encoding an operating state of said function block to generate operating state date, based on said second signal; and at least one voltage output control section for modifying said basic voltage of said at least one constant voltage generation section, based on said operating state data.

2. The semiconductor integrated circuit as defined in claim 1, wherein: an operating-setting signal is input to said at least one function block, and said at least one function block supplies said first signal to said at least one operating state detection section when said operating-setting signal is active.

3. The semiconductor integrated circuit as defined in claim 2; wherein: one each of said at least one operating state detection section, said at least one operating state encoding section, said at least one voltage output control section, and said at least one constant voltage generation section is provided in common for said plurality of function blocks; and said operating-setting signal becomes active at different timings along the time axis for each of said plurality of function blocks.

4. The semiconductor integrated circuit as defined in claim 1, wherein: said at least one voltage output control section comprises: a digital-analog converter for performing a digital-to-analog conversion on said operating state data; and a sample-and-hold circuit for sampling an output of said digital-analog converter based on said operating-setting signal, and generating said basic voltage.

5. The semiconductor integrated circuit as defined in claim 1, wherein: said at least one operating state detection section comprises: an integrator for integrating said first signal; and a peak detector for detecting a peak value of an output of said integrator, and holding said peak value as said second signal.

6. The semiconductor integrated circuit as defined in claim 1, wherein: said at least one operating state detection section comprises: an integrator for integrating said first signal; and a voltage amplitude detector for detecting a voltage amplitude of an output of said integrator, and holding said voltage amplitude as said second signal.

7. The semiconductor integrated circuit as defined in claim 1, wherein: said at least one operating state encoding section comprises: a plurality of comparators for comparing the voltage level of said second signal with each of a plurality of reference voltage levels; and an encoder for encoding outputs of said plurality of comparators.

8. The semiconductor integrated circuit as defined in claim 7, further comprising: a plurality of voltage-dividing resistors for dividing said constant voltage from said at least one constant voltage generation section, to create said plurality of reference voltage levels.

9. A semiconductor integrated circuit comprising: at least one constant voltage generation section for increasing or decreasing a power voltage supplied from at least one external power source, based on a basic voltage, to generate at least one constant voltage; at least one function block to which is supplied said at least one constant voltage generated by said at least one constant voltage generation section; at least one frequency-voltage converter for converting an actual operating frequency of said at least one function block into a voltage level; at least one operating state encoding section for encoding an operating state of said function block to generate operating state data, based on the output voltage of said frequency-voltage converter; and at least one voltage output control section for modifying said basic voltage of said at least one constant voltage generation section, based on said operating state data.

10. The semiconductor integrated circuit as defined in claim 9, wherein: said frequency-voltage converter converts a frequency of an input signal that is input to said at least one function block into a voltage level.

11. The semiconductor integrated circuit as defined in claim 10, wherein: an operating-setting signal is input to said at least one function block, and said at least one function block supplies said input signal to said frequency-voltage converter when said operating-setting signal is active.

12. The semiconductor integrated circuit as defined in claim 11, wherein: one each of said at least one frequency-voltage converter, said at least one operating state encoding section, said at least one voltage output control section, and said at least one constant voltage generation section is provided in common for said plurality of function blocks; and said operating-setting signal becomes active at different timings along the time axis for each of said plurality of function blocks.

13. Electronic equipment comprising the semiconductor integrated circuit as defined in claim 1.