U.S. patent application number 09/800552 was filed with the patent office on 2001-11-01 for output driver circuit with well-controlled output impedance.
This patent application is currently assigned to Rambus Inc.. Invention is credited to Donnelly, Kevin S., Garlepp, Bruno Werner, Zerbe, Jared LeVan.
Application Number | 20010035768 09/800552 |
Document ID | / |
Family ID | 22655381 |
Filed Date | 2001-11-01 |
United States Patent
Application |
20010035768 |
Kind Code |
A1 |
Garlepp, Bruno Werner ; et
al. |
November 1, 2001 |
Output driver circuit with well-controlled output impedance
Abstract
An output driver circuit for driving a signal onto a signal
line. The output driver circuit comprises at least one driver
circuit and a passive network. The passive network is configured to
limit the variation in the output impedance of the output driver
circuit. The output driver circuit thus provides an output
impedance that closely matches the loaded impedance of the signal
line at all times so as to minimize secondary reflections on the
signal line.
Inventors: |
Garlepp, Bruno Werner;
(Mountain View, CA) ; Donnelly, Kevin S.; (San
Francisco, CA) ; Zerbe, Jared LeVan; (Palo Alto,
CA) |
Correspondence
Address: |
PENNIE & EDMONDS LLP
3300 Hillview Avenue
Palo Alto
CA
94304
US
|
Assignee: |
Rambus Inc.
|
Family ID: |
22655381 |
Appl. No.: |
09/800552 |
Filed: |
March 6, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09800552 |
Mar 6, 2001 |
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09179139 |
Oct 26, 1998 |
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6198307 |
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Current U.S.
Class: |
326/30 |
Current CPC
Class: |
H03K 19/0005 20130101;
H04L 25/0278 20130101; H04L 25/028 20130101; H04L 25/0272
20130101 |
Class at
Publication: |
326/30 |
International
Class: |
H03K 019/003 |
Claims
What is claimed is:
1. An output driver circuit including an output for coupling to a
conductor of a signal line, the output having an output impedance,
the output driver circuit comprising: a driver circuit having an
output; and a passive network coupled to the output of the driver
circuit and to the output of the output driver circuit, the passive
network configured to limit variation in the output impedance to a
predefined range while the output driver circuit operates within a
predefined range of expected operating conditions.
2. The output driver circuit of claim 1, wherein the passive
network comprises: a series resistor including a first end coupled
to the output of the driver circuit and a second end; a parallel
resistor including a first end coupled to the second end of the
series resistor and a second end coupled to a voltage supply; and
an output coupled to the second end of the series resistor and to
the first end of the parallel resistor for coupling to the
conductor.
3. The output driver circuit of claim 2, wherein the passive
network further comprises: a capacitor coupled between the second
end of the parallel resistor and the voltage supply.
4. An electronic system for generating and transmitting a digital
signal, comprising: (1) an output driver circuit, comprising: (a) a
driver circuit having an output; (b) a passive network coupled to
the output of the driver circuit, comprising: (i) a series resistor
including a first end coupled to the output of the driver circuit
and a second end; (ii) a parallel resistor including a first end
coupled to the second end of the series resistor and a second end;
(iii) a capacitor coupled between the second end of the parallel
resistor and a first voltage supply; and (iv) an output coupled to
the second end of the series resistor and to the first end of the
parallel resistor for coupling to the conductor; and (c) an output
coupled to the output of the passive network, the output having an
output impedance; and (2) a signal line, comprising: (a) a
conductor including a first end coupled to the output of the output
driver circuit and a second end; (b) a resistor including a first
end coupled to the second end of the conductor and a second end;
and (c) a capacitor coupled between the second end of the resistor
and a second voltage supply.
5. An output driver circuit including first and second outputs for
coupling to first and second conductors, respectively, of a
differential signal line, the first and second outputs having first
and second output impedances, respectively, the output driver
circuit comprising: a first driver circuit having an output; a
second driver circuit having an output; and a passive network
coupled to the outputs of the first and second driver circuits and
to the first and second outputs of the output driver circuit, the
passive network configured to limit variation in the first and
second output impedances to a predefined range while the output
driver circuit operates within a predefined range of expected
operating conditions.
6. The output driver circuit of claim 5, wherein: the first and
second conductors have first and second loaded impedances,
respectively; and the first and second output impedances do not
fall below about 75 percent and do not exceed about 150 percent of
the first and second loaded impedances, respectively, while the
output driver circuit operates within the predefined range of
expected operating conditions.
7. An output driver circuit for coupling to a differential signal
line having a first conductor and a second conductor, comprising: a
first driver circuit having an input and an output; a second driver
circuit having an input and an output; and a passive network
coupled to the outputs of the first and second driver circuits and
including a first output for coupling to the first conductor and a
second output for coupling to the second conductor, comprising: a
first parallel resistor including a first end coupled to the first
output of the passive network and a second end coupled to a
differential ground node; and a second parallel resistor including
a first end coupled to the second output of the passive network and
a second end coupled to the differential ground node.
8. The output driver circuit of claim 7, wherein the passive
network further comprises: a capacitor including a first end
coupled to the differential ground node and a second end coupled to
a voltage supply.
9. The output driver circuit of claim 7, wherein: the first and
second driver circuits each comprise a p-channel transistor and an
n-channel transistor connected in a CMOS inverter configuration;
and the passive network further comprises: a first series resistor
including a first end connected to the output of the first driver
circuit and a second end connected to the first end of the first
parallel resistor; and a second series resistor including a first
end connected to the output of the second driver circuit and a
second end connected to the first end of the second parallel
resistor.
10. The output driver circuit of claim 9, further comprising: a
first predriver including an input connected to the input of the
first driver circuit and an output connected to the gate of the
p-channel transistor of the first driver circuit, the first
predriver having a first and second delay from its input to its
output for a low-to-high and high-to-low output transition,
respectively; a second predriver including an input connected to
the input of the first driver circuit and an output connected to
the gate of the n-channel transistor of the first driver circuit,
the second predriver having a third and fourth delay from its input
to its output for a low-to-high and high-to-low output transition,
respectively, wherein the third delay is larger than the first
delay and the second delay is larger than the fourth delay; a third
predriver including an input connected to the input of the second
driver circuit and an output connected to the gate of the p-channel
transistor of the second driver circuit, the third predriver having
a fifth and sixth delay from its input to its output for a
low-to-high and high-to-low output transition, respectively; and a
fourth predriver including an input connected to the input of the
second driver circuit and an output connected to the gate of the
n-channel transistor of the second driver circuit, the fourth
predriver having a seventh and eighth delay from its input to its
output for a low-to-high and high-to-low output transition,
respectively, wherein the seventh delay is larger than the fifth
delay and the sixth delay is larger than the eighth delay.
11. The output driver circuit of claim 7, wherein: (1) the first
driver circuit comprises: a first p-channel transistor including a
source coupled to a power supply, a drain and a gate coupled to the
input of the first driver circuit; a first series resistor
including a first end coupled to the drain of the first p-channel
transistor and a second end coupled to the output of the first
driver circuit; a second series resistor including a first end
coupled to the output of the first driver circuit and a second end;
and a first n-channel transistor including a drain coupled to the
second end of the second series resistor, a source coupled to a
ground supply and a gate coupled to the input of the first driver
circuit; and (2) the second driver circuit comprises: a second
p-channel transistor including a source coupled to the power
supply, a drain and a gate coupled to the input of the second
driver circuit; a third series resistor including a first end
coupled to the drain of the second p-channel transistor and a
second end coupled to the output of the second driver circuit; a
fourth series resistor including a first end coupled to the output
of the second driver circuit and a second end; and a second
n-channel transistor including a drain coupled to the second end of
the fourth series resistor, a source coupled to the ground supply
and a gate coupled to the input of the second driver circuit.
12. The output driver circuit of claim 11, further comprising: a
first predriver including an input connected to the input of the
first driver circuit and an output connected to the gate of the
first p-channel transistor, the first predriver having a first and
second delay from its input to its output for a low-to-high and
high-to-low output transition, respectively; a second predriver
including an input connected to the input of the first driver
circuit and an output connected to the gate of the first n-channel
transistor, the second predriver having a third and fourth delay
from its input to its output for a low-to-high and high-to-low
output transition, respectively, wherein the third delay is larger
than the first delay and the second delay is larger than the fourth
delay; a third predriver including an input connected to the input
of the second driver circuit and an output connected to the gate of
the second p-channel transistor, the third predriver having a fifth
and sixth delay from its input to its output for a low-to-high and
high-to-low output transition, respectively; and a fourth predriver
including an input connected to the input of the second driver
circuit and an output connected to the gate of the second n-channel
transistor, the fourth predriver having a seventh and eighth delay
from its input to its output for a low-to-high and high-to-low
output transition, respectively, wherein the seventh delay is
larger than the fifth delay and the sixth delay is larger than the
eighth delay.
13. An electronic system for generating and transmitting a digital
signal, comprising: (1) an output driver circuit, comprising: (a) a
first driver circuit having an input and an output; (b) a second
driver circuit having an input and an output; (c) a passive network
coupled to the outputs of the first and second driver circuits,
comprising: (i) a first parallel resistor including a first end
coupled to a first output of the passive network and a second end
coupled to a first differential ground node; and (ii) a second
parallel resistor including a first end coupled to a second output
of the passive network and a second end coupled to the first
differential ground node; and (d) first and second outputs coupled
to the first and second outputs of the passive network,
respectively; and (2) a signal line, comprising: (a) a first
conductor including a first end coupled to the first output of the
output driver circuit and a second end; (b) a first resistor
including a first end coupled to the second end of the first
conductor and a second end coupled to a second differential ground
node; (c) a second conductor including a first end coupled to the
second output of the output driver circuit and a second end; and
(d) a second resistor including a first end coupled to the second
end of the second conductor and a second end coupled to the second
differential ground node.
14. The electronic system of claim 13, further comprising a
capacitor having a first end coupled to the second differential
ground node and a second end coupled to a power supply.
15. An output driver circuit for coupling to a differential signal
line having a first conductor and a second conductor, comprising: a
first output for coupling to a first end of the first conductor; a
first p-channel transistor including a source coupled to a power
supply, a drain coupled to the first output and a gate for
receiving a first drive signal having a voltage such that the first
p-channel transistor operates in a saturation or cutoff region of
operation only; a first n-channel transistor including a drain
coupled to the first output, a source coupled to a ground supply
and a gate for receiving a second drive signal having a voltage
such that the first n-channel transistor operates in a saturation
or cutoff region of operation only; a first resistor including a
first end coupled to the first output and a second end coupled to a
differential ground node; a second output for coupling to a first
end of the second conductor; a second p-channel transistor
including a source coupled to the power supply, a drain coupled to
the second output and a gate for receiving a third drive signal
having a voltage such that the second p-channel transistor operates
in a saturation or cutoff region of operation only; a second
n-channel transistor including a drain coupled to the second
output, a source coupled to the ground supply and a gate for
receiving a fourth drive signal having a voltage such that the
second n-channel transistor operates in a saturation or cutoff
region of operation only; and a second resistor including a first
end coupled to the second output and a second end coupled to the
differential ground node.
16. The output driver circuit of claim 15, further comprising: a
first predriver for receiving a first input signal and generating
the first drive signal; a second predriver for receiving the first
input signal and generating the second drive signal; a third
predriver for receiving a second input signal and generating the
third drive signal; and a fourth predriver for receiving the second
input signal and generating the fourth drive signal.
17. The output driver circuit of claim 15, further comprising: a
capacitor including a first end coupled to the differential ground
node and a second end coupled to a voltage supply.
Description
[0001] The present invention relates generally to the field of
digital circuits, and more particularly to an output driver circuit
with a well-controlled output impedance for driving signal lines in
a high-speed digital system.
BACKGROUND OF THE INVENTION
[0002] A signal line is a conductor used to transmit electrical
signals between the various devices in an electronic system. Output
driver circuits contained on each device are used to buffer signals
originating from the device so that they may be driven onto the
signal line.
[0003] For example, FIG. 1 illustrates a prior art digital system 1
including a plurality of devices 2, a signal transmitting device 3
and a signal line 4. The transmitting device 3 contains an output
driver circuit 5 that generates a single-ended signal for output
onto the signal line 4. The devices 2 are connected to the signal
line 4 at various points to receive the signal. The signal line 4
includes a conductor 12, a termination resistor R.sub.T and a
termination voltage V.sub.Term. The termination resistor R.sub.T is
connected to the end of the conductor 12 opposite the end connected
to the output driver circuit 5. The termination resistor R.sub.T
absorbs the incident signal, thereby preventing reflections of the
signal from occurring at the end of the conductor 12. The
termination resistor R.sub.T is also connected to the termination
voltage V.sub.Term. The termination voltage V.sub.Term is used to
raise the voltage of the conductor 12 to the high voltage level
V.sub.oh.
[0004] An embodiment of the prior art digital system 1, a memory
system 6, is shown in FIG. 2. Memory system 6 includes a plurality
of dynamic random-access memories (DRAMs) 11, a clock chip 7, a
clock line 8 and a memory controller 24. The clock chip 7 contains
a clock driver circuit 9 that generates a single-ended clock signal
for output onto the clock line 8. The clock line 8 includes a
conductor 10 that passes through the memory controller 24 such that
the conductor is divided into two portions: a CTM (clock to master)
portion and a CFM (clock from master) portion. The CTM portion
propagates the clock signal from the clock driver circuit 9 towards
the memory controller 24 (the memory controller is the master
device in the system). The CFM portion propagates the clock signal
from the memory controller 24 towards the DRAMs 11. The DRAMs 11
are connected to both the CTM and CFM portions of the conductor 10.
The conductor 10 is divided in this manner so that the clock signal
can maintain a specific phase relationship with data signals (not
shown) that are transmitted between the DRAMs 11 and the memory
controller 24 as the signals propagate, regardless of whether the
data signals are transmitted from the DRAMs to the memory
controller or vice versa.
[0005] FIG. 3 shows a simplified electrical model of the clock
driver circuit 9 and the clock line 8 in the memory system 6. In
this model, the clock line 8 is represented by a transmission line
of loaded impedance Z.sub.0. The loaded impedance Z.sub.0 includes
the unloaded characteristic impedance Z.sub.0' of the conductor 10
as well as the impedance of the DRAMs 11 and any other devices
connected to the conductor. In order to minimize clock signal
reflections at the end of the conductor 10, the resistance of the
termination resistor R.sub.T is typically set to equal the loaded
impedance Z.sub.0 of the conductor.
[0006] FIG. 4 is a waveform diagram illustrating the clock signal
produced by the clock driver circuit 9 as a function of time. The
clock signal has a high voltage level V.sub.oh and a low voltage
level V.sub.ol, where V.sub.oh=V.sub.Term,
V.sub.ol=V.sub.Term-2*(V.sub.Term-V.sub.Ref), and V.sub.Ref is a
reference voltage. As a result, the clock signal has a voltage
swing V.sub.sw of V.sub.sw=2*(V.sub.Term-V.sub.Ref). The clock
driver circuit 9 generates this waveform by operating as a
switching current source, alternately turning on and off, sinking
current every other half-cycle of the clock period. The clock
signal is converted into an internal clock signal for use within
the DRAMs 11 by circuitry (not shown) within the DRAMs. The
circuitry generates the internal clock signal by comparing the
voltage of the clock signal with the reference voltage
V.sub.ref.
[0007] Unfortunately, the single-ended clock driver circuit 9
produces clock signals with relatively poor timing accuracy, i.e.,
"clock jitter," especially at higher clock frequencies. There are
several causes for the clock jitter. First, the voltage of the
clock signal is dependent on the voltage V.sub.Term, which
typically suffers from significant "noise" (i.e., rapid voltage
fluctuations). The noise in the voltage V.sub.Term may be caused,
for example, by the switching on and off of numerous transistors in
the system that are coupled to the voltage source. Second, the
internal clock signal that is derived from the clock signal is
dependent on the voltage V.sub.Ref, which is also noise-prone for
similar reasons.
[0008] A third cause for the clock jitter are the primary and
secondary reflections of the clock signal produced on the clock
line 8. Primary reflections are reflections of the clock signal
produced along the conductor 10 by taps along the conductor at
which the DRAMs 11 are connected and by the termination resistor
R.sub.T. The reflections travel back towards the clock driver
circuit 9. These reflections occur because of an impedance mismatch
or discontinuity in the clock line 8 caused by the taps and/or the
termination resistor. The primary reflections in turn cause
secondary reflections to occur at the output of the clock driver
circuit 9. The secondary reflections occur because the output
impedance of the clock driver circuit 9, which acts as a high
output impedance current source, is significantly greater than the
loaded impedance Z.sub.0 of the clock line 8. The secondary
reflections travel back down the conductor 10, thereby disturbing
the clock signal waveform and causing jitter in the clock signal
received by the DRAMs 11.
[0009] In view of the shortcomings of the prior art, it is an
object of the present invention to provide a clock driver circuit
that generates clock signals with minimal clock jitter despite the
presence of noisy voltage supply signals.
[0010] It is another object of the present invention to provide a
clock driver circuit that presents an output impedance that closely
matches the loaded impedance of the clock line so as to minimize
secondary reflections on the clock line.
[0011] More generally, it is an object of the present invention to
provide an output driver circuit that generates a signal on a
signal line with these characteristics.
SUMMARY OF THE INVENTION
[0012] In summary, the present invention is an output driver
circuit for driving a signal onto a signal line. The output driver
circuit provides an output impedance that closely matches the
loaded impedance of the signal line at all times so as to minimize
secondary reflections on the signal line. The output driver circuit
may be used as a clock driver circuit to drive a clock signal onto
a clock line. In this application, the output driver circuit
provides a clock signal with minimal clock jitter despite the
presence of noisy voltage supplies.
[0013] The output driver circuit of the present invention includes
at least one driver circuit and a passive network. The passive
network is coupled to the output of the driver circuit and includes
an output corresponding to each driver circuit for coupling to a
signal line conductor. The passive network, which may be composed
of a network of resistors, is configured to limit the variation in
the output impedance of the output driver circuit.
[0014] The output driver circuit of the present invention includes
embodiments that generate a single-ended signal and other
embodiments that generate a differential signal. For the
single-ended signal embodiments, the output driver circuit includes
a single driver circuit coupled to a passive network. The passive
network includes a series resistor and a parallel resistor. The
series resistor is connected between the output of the driver
circuit and the output of the passive network. The parallel
resistor is connected between the output of the passive network and
a voltage supply, such as V.sub.DD or Gnd. The passive network may
optionally include a capacitor connected between the parallel
resistor and the voltage supply to provide an AC ground.
[0015] For the differential signal embodiments, the output driver
circuit includes first and second driver circuits and a passive
network that includes first and second outputs. In a first
embodiment, the passive network includes a first series resistor
connected between the output of the first driver circuit and the
first output of the passive network, a first parallel resistor
coupled between the first output of the passive network and a
differential ground node, a second series resistor connected
between the output of the second driver circuit and the second
output of the passive network and a second parallel resistor
coupled between the second output of the passive network and the
differential ground node.
[0016] In a second differential signal embodiment of the output
driver circuit, the first and second driver circuits each comprise
a p-channel transistor and an n-channel transistor in an
inverter-like configuration, a first series resistor connected
between the drain of the p-channel transistor and the output of the
inverter and a second series resistor connected between the drain
of the n-channel transistor and the output of the inverter. In this
embodiment, the passive network includes a first parallel resistor
coupled between the output of the first driver circuit and a
differential ground node and a second parallel resistor coupled
between the output of the second driver circuit and the
differential ground node.
[0017] In a third differential signal embodiment of the output
driver circuit, the first and second driver circuits each comprise
a p-channel transistor and an n-channel transistor in an inverter
configuration and the passive network includes a first parallel
resistor coupled between the output of the first driver circuit and
a differential ground node and a second parallel resistor coupled
between the output of the second driver circuit and the
differential ground node. In this embodiment, the gates of the
p-channel and n-channel transistors of the first and second driver
circuits are driven with signals having voltages such that the
transistors operate in a saturation or cutoff region of operation
only. The output driver circuit may further include predrivers to
generate these signals.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Additional objects and features of the present invention
will be more readily apparent from the following detailed
description and appended claims when taken in conjunction with the
drawings, in which:
[0019] FIG. 1 is a block diagram of a prior art digital system,
including a plurality of devices, a signal transmitting device and
a signal line.
[0020] FIG. 2 is a block diagram of a prior art memory system,
including a plurality of DRAMs, a memory controller, a clock chip
and a clock line.
[0021] FIG. 3 is a simplified electrical model of the single-ended
clock driver of FIG. 2.
[0022] FIG. 4 is a waveform diagram illustrating the output voltage
waveform generated by the clock driver of FIG. 3 as a function of
time.
[0023] FIG. 5 is a circuit diagram of a single-ended clock driver
in accordance with the present invention.
[0024] FIG. 6 is a waveform diagram illustrating the output voltage
waveform generated by the clock driver of FIG. 5 as a function of
time.
[0025] FIG. 7 is a circuit diagram of a single-ended clock driver
in accordance with a second alternate embodiment of the present
invention.
[0026] FIG. 8 is a circuit diagram of a single-ended clock driver
in accordance with an alternate embodiment of the present
invention.
[0027] FIG. 9 is a simplified electrical model of a differential
clock driver in accordance with the present invention.
[0028] FIG. 10 is a waveform diagram illustrating the output
voltage waveforms generated by the clock driver of FIG. 9 as a
function of time.
[0029] FIG. 11 is a block diagram of a memory system in accordance
with the present invention, including a plurality of DRAMs, a
memory controller, a clock chip and differential clock lines.
[0030] FIG. 12 is a block diagram of an internal clock generating
circuit for use in the DRAMs of FIG. 11.
[0031] FIG. 13 is a circuit diagram of a first alternative design
for a differential clock driver.
[0032] FIG. 14 is a diagram illustrating the output voltage
waveforms and output impedance of the clock driver of FIG. 13 as a
function of time.
[0033] FIG. 15 is a circuit diagram of a second alternative design
for a differential clock driver.
[0034] FIG. 16 is a circuit diagram of a quasi-differential clock
driver in accordance with the present invention.
[0035] FIG. 17 is a diagram illustrating the output voltage
waveforms and output impedance of the clock driver of FIG. 16 as a
function of time.
[0036] FIG. 18 is a circuit diagram of a DC equivalent circuit for
the clock driver and differential clock lines of FIG. 16 when
V.sub.ln=0 V and V.sub.ln.sub..sub.--=V.sub.DD.
[0037] FIG. 19 is a circuit diagram of a quasi-differential clock
driver in accordance with an alternate embodiment of the present
invention.
[0038] FIG. 20 is a circuit diagram of a quasi-differential clock
driver in accordance with a second alternate embodiment of the
present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0039] To reduce the clock jitter experienced by prior art clock
drivers, the present invention employs a clock driver that presents
an output impedance that closely matches the loaded impedance of
the clock line. This reduces clock jitter by minimizing the
occurrence of secondary reflections on the clock line.
[0040] FIG. 5 shows a single-ended clock driver circuit 71 in
accordance with the present invention. The clock driver circuit 71
has an input In for receiving an input clock signal. The clock
driver circuit 71 also has an output Out for generating a
single-ended clock signal CTM. The output Out is connected to the
clock line 8, which as described in the background section above,
has a loaded impedance of Z.sub.0.
[0041] The clock driver circuit 71 further includes a p-channel
transistor M.sub.p and an n-channel transistor M.sub.n configured
as a CMOS inverter. The p-channel transistor M.sub.p includes a
source connected to a power supply V.sub.DD, a drain, and a gate
connected to the input In. The n-channel transistor M.sub.n
includes a drain connected to the drain of the p-channel transistor
M.sub.p, a source connected to a ground supply V.sub.SS and a gate
connected to the input In.
[0042] The clock driver circuit 71 additionally includes a passive
network composed of a series resistor R.sub.s and a parallel
resistor R.sub.p. A first end of the series resistor R.sub.s is
connected to the output of the CMOS inverter, i.e., the drains of
the transistors M.sub.p and M.sub.n. A second end of the series
resistor R.sub.s is connected to the output Out of the clock driver
circuit 71. A first end of the parallel resistor R.sub.p is
connected to the output Out of the clock driver circuit 71. A
second end of the parallel resistor R.sub.p is connected to a
voltage source V.sub.p. The voltage source V.sub.p may comprise any
voltage supply, such as V.sub.DD. The resistors R.sub.s and R.sub.p
may be formed from either discrete components or devices integrated
on the same substrate as the transistors M.sub.p and M.sub.n. In
the preferred embodiment, V.sub.Term.gtoreq.V.sub.DD and
V.sub.p=V.sub.Term.
[0043] Optionally, the clock driver circuit 71 may include two
predriver circuits (not shown), one predriver circuit connected
between the input In and the gate of the transistor M.sub.p and the
other predriver circuit connected between the input In and the gate
of the transistor M.sub.n. The predriver circuits minimize the
wasted "shoot-through" current passing through the transistors
M.sub.p and M.sub.n during transitions of the clock signal CTM by
skewing the timing of the signals fed to the transistors M.sub.p
and M.sub.n. The operation of predriver circuits are described in
further detail below with respect to the clock driver circuit
15.
[0044] The clock driver circuit 71 may be used to construct a
quasi-differential clock driver circuit by placing two clock driver
circuits 71 in parallel. Complementary input signals are fed to the
inputs of the two clock driver circuits to produce a differential
clock signal at the circuit outputs.
[0045] The output impedance Z.sub.out of the clock driver circuit
71 is given by the equation:
Z.sub.out=R.sub.p.parallel.[R.sub.s+(1/(G.sub.ds,p.parallel.1/G.sub.ds,n)]-
,
[0046] where G.sub.ds,p and G.sub.ds,n are the drain-to-source
conductances of the transistors M.sub.p and M.sub.n, respectively,
and the symbol ".parallel." means "in parallel with" such that
R.sub.1.parallel.R.sub.2=(R.sub.1* R.sub.2)/(R.sub.1+R.sub.2). The
drain-to-source resistances 1/G.sub.ds,p and 1/G.sub.ds,n may vary
significantly during circuit operation, reaching into the thousands
of ohms when the transistors are operating in the saturation
region, as discussed below with respect to the clock driver circuit
25. As seen from the equation, however, the parallel resistor
R.sub.p limits the maximum output impedance Z.sub.out to R.sub.p.
As a result, the variation in the output impedance Z.sub.out is
relatively well-controlled. By selecting the appropriate values for
R.sub.p, R.sub.s, G.sub.ds,p and G.sub.ds,n, the output impedance
Z.sub.out can thus be closely matched to the loaded impedance
Z.sub.0 of the clock line 8. These values may be determined using a
design procedure similar to that given below with respect to the
clock driver circuit 15.
[0047] FIG. 6 illustrates the waveform of the signal CTM generated
by the clock driver circuit 71 as a function of time. The signal
CTM has a high voltage level V.sub.oh equal to the termination
voltage V.sub.Term and a low voltage level V.sub.ol that is greater
than V.sub.SS. The voltage of the signal CTM is thus always fairly
high (i.e., near V.sub.DD). Consequently, the p-channel transistor
M.sub.p operates in either the linear or cut-off regions of
operation, but not in saturation. The p-channel transistor M.sub.p
thus provides very little pull-up current; it is merely used to
provide good R.sub.out impedance matching when the n-channel
transistor M.sub.n is off during every other half clock cycle.
Because the p-channel transistor M.sub.p does not operate in the
saturation region, the variation in the output impedance Z.sub.out
during circuit operation is further reduced.
[0048] The clock driver circuit 71 is particularly advantageous for
use with the combination of relatively low power supply voltages
(e.g., V.sub.DD.ltoreq.1.8 V) and higher V.sub.Term voltages (e.g.,
V.sub.Term.gtoreq.1.8 V). At these low power supply voltages, the
p-channel transistor M.sub.p provides very little pull-up current.
Nevertheless, the performance of the clock driver circuit 71 is not
significantly degraded because the circuit primarily uses the
parallel resistor R.sub.p, not the p-channel transistor M.sub.p, to
pull up the clock line 8. The variation in the output impedance
Z.sub.out is even further reduced at these low voltages because the
operation of the p-channel transistor M.sub.p is always linear.
[0049] FIG. 7 shows an alternative embodiment of a single-ended
clock driver circuit in accordance with the present invention.
Clock driver circuit 72 is identical to the clock driver circuit 71
shown in FIG. 5 except that the second end of the parallel resistor
R.sub.p is connected to a voltage supply V.sub.p' through a
capacitor C.sub.p. The voltage source V.sub.p' may comprise any
voltage supply, such as V.sub.DD or Gnd. The capacitor C.sub.p
provides an AC ground connection to the voltage source V.sub.p' for
the parallel resistor R.sub.p. By coupling the parallel resistor
R.sub.p to an AC ground, the common-mode voltage of the clock
signal CTM is not affected by the voltage source V.sub.p'.
[0050] FIG. 8 shows a second alternative embodiment of a
single-ended clock driver circuit in accordance with the present
invention. Clock driver circuit 73 is identical to the clock driver
circuit 72 shown in FIG. 7 except that the termination resistor
R.sub.T is connected to the voltage supply V.sub.p' through a
capacitor C.sub.T. The function of the capacitor C.sub.T is similar
to that of the capacitor C.sub.p, i.e., the capacitor C.sub.T
provides an AC ground connection to the voltage source V.sub.p' for
the termination resistor R.sub.T.
[0051] The capacitors C.sub.p and C.sub.T of clock driver should be
set to a sufficiently large capacitance such that:
X.sub.Cp=1/(2*.pi.*f*C.sub.p)<<R.sub.p, and
X.sub.CT=1/(2*.pi.*f*C.sub.T)<<R.sub.T,
[0052] where f is the frequency of the output signal CTM.
[0053] The single-ended clock driver circuits described above
provide a well-controlled output impedance, thereby minimizing the
secondary reflections at the output that contribute to clock
jitter. However, these clock driver circuits still rely on the
voltage signals V.sub.Term and V.sub.Ref to generate clock signals
and thus are still susceptible to clock jitter.
[0054] To further reduce the susceptibility to clock jitter, an
alternate embodiment of the present invention employs a clock
driver that generates a differential, rather than a single-ended,
clock signal. A differential clock signal includes two signals that
vary over time in a symmetrical but complementary manner about a
common-mode voltage. A single-ended clock signal may be derived
from the differential clock signal by measuring the difference in
voltage between the two signals.
[0055] A clock driver that generates a differential clock signal
provides several advantages over a driver that generates a
single-ended clock signal. First, the internal clock signal that is
derived from the differential clock signal is cleaner and has less
clock jitter because the noise-prone voltage sources V.sub.Term and
V.sub.Ref are not used to generate either the differential clock
signal or the internal single-ended clock signal that is derived
from it. Second, the differential clock driver needs to generate an
output voltage swing that is only half as large as the single-ended
clock driver to produce a clock signal of equivalent amplitude.
[0056] FIG. 9 is a simplified electrical model of a differential
clock driver 15 and a pair of differential clock lines 17 in
accordance with the present invention. The differential clock
driver 15 includes two inputs, In and In_, for receiving a periodic
binary signal and the complement of the periodic binary signal,
respectively, generated by an oscillator circuit (not shown). The
differential clock driver 15 also includes two outputs, Out and
Out_, for generating the differential signals CTM and CTMN,
respectively. The signal CTM is generated from the periodic binary
signal received by the input In, while the signal CTMN is generated
from the periodic binary signal received by the input In_. The
signals CTM and CTMN together comprise the differential clock
signal generated by the differential clock driver 15.
[0057] The pair of differential clock lines 17 includes two
conductors 18 and 19 for transmitting the differential signals CTM
and CTMN, respectively. Each of the differential clock lines is
represented by a transmission line of loaded impedance Z.sub.0. The
loaded impedance Z.sub.0 includes the unloaded characteristic
impedance Z.sub.0' of the respective conductor 18 or 19 as well as
the impedance of any devices, such as DRAMs 11, connected to the
conductor. An internal clock generating circuit (see FIG. 12)
contained in each such device converts the differential signals CTM
and CTMN into a single-ended internal clock signal for use within
the device.
[0058] The differential clock lines 17 also include two termination
resistors R.sub.T1 and R.sub.T2. A first end of each termination
resistor R.sub.T1 and R.sub.T2 is connected to the end of the
respective conductor 18 or 19 opposite the end connected to the
clock driver 15. A second end of the termination resistor R.sub.T1
is connected to a second end of the termination resistor R.sub.T2
at a node Ch_mid to form an electrical connection between
conductors 18 and 19. Assuming the signals CTM and CTMN are truly
differential, i.e., the signals are 180 degrees out-of-phase with
each other, the node Ch_mid will appear as a differential ground
with the conductors 18 and 19 being terminated with the termination
resistors R.sub.T1 and R.sub.T2, respectively. The termination
resistors R.sub.T1 and R.sub.T2 prevent reflections of the
differential signals CTM and CTMN from occurring at the end of the
conductors 18 and 19, respectively. In order to minimize the signal
reflections, the resistance of the termination resistors R.sub.T1
and R.sub.T2 is set to equal the loaded impedance Z.sub.0 of the
differential clock lines 17. Optionally, a capacitor C.sub.End is
connected between the node Ch_mid and a power supply (as shown by
the dotted lines in FIG. 9) to reinforce the differential
ground.
[0059] FIG. 10 illustrates the waveforms of the differential
signals CTM and CTMN generated by the clock driver circuit 15 as a
function of time. The signals CTM and CTMN are preferably
complementary, i.e., 180 degrees out of phase with each other, as
shown in the figure. However, the signals CTM and CTMN will be
complementary only if the periodic binary signals supplied to the
inputs In and In.sub.-- of the clock driver circuit 15 are also
complementary. The signals CTM and CTMN each have a high voltage
level V.sub.oh, a low voltage level V.sub.ol and a common mode
voltage V.sub.cm. The common mode voltage V.sub.cm is the average
voltage of the signal, which ideally is identical for the signals
CTM and CTMN as shown in the figure.
[0060] FIG. 11 is a block diagram of a memory system 22 employing
the differential clock driver circuit 15 of the present invention.
The memory system 22 includes differential clock lines 17, a
plurality of DRAMs 11 and a memory controller 24. The figure does
not show data busses or other aspects of the memory system 22 not
relevant to the present invention. The conductors 18 and 19 of the
differential clock lines 17 pass through the memory controller 24
such that the conductors are divided into two portions: a CTM/CTMN
(clock to master) portion and a CFM/CFMN (clock from master)
portion. The CTM/CTMN portion propagates the clock signal from the
clock driver circuit 15 towards the memory controller 24. The
CFM/CFMN portion propagates the clock signal from the memory
controller 24 towards the DRAMs 11. The DRAMs 11 are connected to
both the CTM/CTMN and CFM/CFMN portions of the conductors 18 and
19. An internal clock generating circuit 20 is contained in each
DRAM 11 that converts the differential clock signal into a
single-ended internal clock signal for use within the DRAM. As
mentioned in the background section, the conductors 18 and 19 are
divided in this manner so that the clock signal can maintain a
certain phase relationship with the data signals transmitted
between the DRAMs 11 and the memory controller 24 as the signals
propagate, regardless of whether the data signals are transmitted
from the DRAMs to the memory controller or vice versa.
[0061] FIG. 12 is a block diagram of an embodiment of the internal
clock generating circuit 20 contained within each of the DRAMs 11.
The internal clock generating circuit 20 includes one or more
differential amplifiers 21 in series to amplify the differential
clock signal CTM/CTMN. The internal clock generating circuit 20
also includes a differential to single-ended converter 28 connected
to the output of the differential amplifiers to convert the
amplified differential clock signal into a single-ended clock
signal CLK.
[0062] The differential clock driver circuit 15 of the present
invention will be described in further detail below. To provide a
greater appreciation for the advantages of the present invention,
however, design considerations for a differential clock driver
circuit along with several alternative designs will now be
described. A differential clock driver circuit should provide the
following features for optimum operation: (1) an appropriate
voltage swing V.sub.sw and common mode voltage V.sub.cm for the
differential clock signal and (2) an output impedance that closely
matches the loaded impedance of the differential clock lines to
prevent secondary reflections from occurring at the output of the
driver.
[0063] FIG. 13 is a circuit diagram of a first alternative design
for a differential clock driver. The clock driver circuit 25 is
actually a "quasi-differential" clock driver circuit because its
operation approximates that of a true differential circuit. A true
differential clock driver supplies two output signals which always
swing in a complementary fashion about a common-mode voltage
V.sub.cm in response to an input signal. By contrast, the output
signals of the quasi-differential clock driver circuit 25 will
swing in a complementary fashion about a common-mode voltage
V.sub.cm, only if its two inputs, In and In_, are driven by
complementary signals (i.e., signals which differ in phase by 180
degrees). If the quasi-differential clock driver circuit 25 is
driven with input signals that are not complementary, the circuit
will generate output signals that are likewise not complementary
and thus will not operate in the same manner as a true differential
circuit.
[0064] Continuing to refer to FIG. 13, quasi-differential clock
driver circuit 25 includes two complementary metal-oxide
semiconductor (CMOS) inverter circuits 26 and 27. The inverter
circuits 26 and 27 include inputs In and In_, respectively, which
receive complementary binary signals. The clock driver circuit 25
further includes two series resistors R.sub.s1 and R.sub.s2 that
are connected between the outputs of inverter circuits 26 and 27,
respectively, and the conductors 18 and 19 of the differential
clock lines 17, respectively. The resistances of series resistors
R.sub.s1 and R.sub.s2 are set to Z.sub.0-1/G.sub.ds, where Z.sub.0
is the loaded impedance of the differential clock lines 17 and
G.sub.ds is the small-swing drain-to-source conductance of the
p-channel or n-channel (field effect) transistors in the CMOS
inverter circuits 26 and 27 when they are fully turned on. In this
manner, the output impedance Z.sub.out of the clock driver circuit
25 equals the impedance Z.sub.0 of the differential clock lines 17
whenever the output signals CTM and CTMN are not transitioning
(i.e., when they are at V.sub.oh or V.sub.ol). Because of the
matching impedance, secondary reflections at the clock driver
circuit 25 are suppressed during steady-state conditions.
[0065] Whenever the output signals CTM and CTMN are transitioning
between V.sub.ol and V.sub.oh, however, the clock driver circuit 25
does not provide a good impedance match to the differential clock
lines 17. During these transitions, the transistors of the inverter
circuits 26 and 27 move into the saturation region of operation,
thereby causing the small-swing resistance 1/G.sub.ds of the
transistors to increase dramatically to 1/G.sub.ds,sat, which is
often well into the thousands of ohms. Since the output impedance
Z.sub.out of the clock driver circuit 25 is composed of the
drain-to-source resistance 1/G.sub.ds of the p-channel or n-channel
transistor in series with the series resistor R.sub.s1 or R.sub.s2,
the output impedance Z.sub.out will also be very high. The
variation in the output impedance Z.sub.out of the clock driver
circuit 25 in relation to the output signals CTM and CTMN is
illustrated in FIG. 14. Because the output impedance Z.sub.out no
longer matches the loaded impedance Z.sub.0 of the differential
clock lines 17, secondary reflections may occur during transitions
of the signals CTM and CTMN.
[0066] Another disadvantage of the clock driver circuit 25 is that
it outputs the signals CTM and CTMN with a reduced voltage swing
V.sub.sw. This is because the series resistors R.sub.s1 and
R.sub.s2 form a voltage divider with the loaded impedance Z.sub.0
of the differential clock lines 17, thereby reducing the maximum
voltage that can be output by the clock driver circuit 25.
[0067] Yet another disadvantage of the clock driver circuit 25 is
that the common mode voltage V.sub.cm of the output signals CTM and
CTMN cannot be adjusted easily. The common mode voltage V.sub.cm is
fixed at V.sub.cm=0.5*(V.sub.DD+V.sub.SS) by the output of the
inverters 26 and 27. Therefore, the common mode voltage V.sub.cm
cannot be varied without changing the supply voltages V.sub.DD or
V.sub.SS, which is usually impractical.
[0068] The clock driver circuit 25 thus suffers from two
shortcomings: (1) a poor impedance match to the differential clock
lines 17 during output signal transitions and (2) an inability to
set an arbitrary voltage swing V.sub.sw or common mode voltage
V.sub.cm.
[0069] FIG. 15 is a circuit diagram of a second alternative design
for a differential clock driver. Differential clock driver circuit
30 includes a differential pair predriver 32 followed by a
differential common-drain stage 34. The differential pair predriver
32 includes inputs In and In.sub.-- which receive complementary
binary signals. The differential common-drain stage 34 includes two
n-channel MOS transistors M.sub.n1 and M.sub.n2 that are each
connected between the power supply V.sub.DD and a respective
differential output of the common-drain stage. The differential
common-drain stage 34 also includes two current sources I.sub.1 and
I.sub.2 that are connected between the respective differential
output of the common-drain stage and a ground supply V.sub.SS. The
current sources I.sub.1 and I.sub.2 bias the transistors M.sub.n1
and M.sub.n2 so that the source conductance G.sub.m of the
transistors does not vary substantially over the entire output
voltage range of the common-drain stage 34.
[0070] The differential clock driver circuit 30 also includes two
series resistors R.sub.s1 and R.sub.s2 that are connected between
the two outputs of the differential common-drain stage 34 and the
conductors 18 and 19 of the differential clock lines 17,
respectively. The resistances of the series resistors R.sub.s1 and
R.sub.s2 are set to Z.sub.0-1/G.sub.m, where Z.sub.0 is the loaded
impedance of the differential clock lines 17. In this manner, the
output impedance Z.sub.out of the clock driver circuit 30 equals
the impedance Z.sub.0 of the differential clock lines 17. Unlike
the clock driver circuit 25 described earlier, however, the output
impedance Z.sub.out of the clock driver circuit 30 has little
variation during circuit operation because of the well-controlled
conductance G.sub.m of the transistors M.sub.n1 and M.sub.n2. As a
result, the clock driver circuit 30 maintains a good impedance
match with the differential clock lines 17 at all times, thereby
suppressing secondary reflections more effectively than the clock
driver 25.
[0071] Unfortunately, the clock driver circuit 30 also suffers from
several disadvantages. One disadvantage is that the clock driver
circuit 30 consumes a large amount of power. The power consumption
of the clock driver circuit 30 is high because the current sources
I.sub.1 and I.sub.2 must sink a relatively large current in order
to ensure that the conductance G.sub.m of the transistors M.sub.n1
and M.sub.n2 does not vary significantly over the entire output
voltage range of the common-drain stage 34.
[0072] Another disadvantage of the clock driver circuit 30 is that
the maximum common mode voltage V.sub.cm and high voltage level
V.sub.oh it is capable of generating is relatively low. This is
because the n-channel transistors M.sub.n1 and M.sub.n2 limit the
maximum voltage that can be generated at the outputs of the
common-drain stage 34 to V.sub.DD-V.sub.gs,on, where V.sub.gs,on is
the gate-to-source voltage of the transistors M.sub.n1 and M.sub.n2
when turned on. Moreover, the voltage V.sub.gs,on can be fairly
large because of the body effect experienced by the transistors
M.sub.n1 and M.sub.n2 and the high current sunk by the current
sources I.sub.1 and I.sub.2.
[0073] Yet another disadvantage of the clock driver circuit 30 is
that it generates output signals having highly asymmetrical rising
and falling edges. The signal edges are asymmetrical because the
common-drain stage 34 provides an active pull-up (through the
transistors M.sub.n1 and M.sub.n2) and a passive pull-down (through
the current sources I.sub.1 and I.sub.2).
[0074] Therefore, although the clock driver circuit 30 is an
improvement over the previously described clock driver circuit 25,
it suffers from three other shortcomings: (1) a relatively high
power consumption, (2) an output signal having a relatively low
maximum common mode voltage V.sub.cm and high voltage level
V.sub.oh and (3) an output signal with asymmetrical edge rates.
[0075] Having illustrated two alternative designs for a
differential clock driver circuit, a differential clock driver
circuit in accordance with the present invention will now be
described. FIG. 16 is a circuit diagram of the quasi-differential
clock driver circuit 15 and the differential clock lines 17 shown
earlier in FIG. 9. As mentioned earlier, the quasi-differential
clock driver circuit 15 has two inputs, In and In.sub.-- for
receiving complementary binary signals. As also discussed, the
clock driver circuit 15 has two outputs Out and Out.sub.-- for
generating the differential signals CTM and CTMN, respectively,
which together comprise the differential clock signal.
[0076] The clock driver circuit 15 includes two CMOS inverters 41
and 45. The CMOS inverter 41 includes a p-channel transistor
M.sub.p1 and an n-channel transistor M.sub.n1. The p-channel
transistor M.sub.p1 includes a source connected to the power supply
V.sub.DD, a drain, and a gate connected to the input In. The
n-channel transistor M.sub.n1 includes a drain connected to the
drain of the p-channel transistor M.sub.p1, a source connected to
the ground supply V.sub.SS and a gate connected to the input In.
Similarly, the CMOS inverter 45 includes a p-channel transistor
M.sub.p2 and an n-channel transistor M.sub.n2. The p-channel
transistor M.sub.p2 includes a source connected to the power supply
V.sub.DD, a drain, and a gate connected to the input In_. The
n-channel transistor M.sub.n2 includes a drain connected to the
drain of the p-channel transistor M.sub.p2, a source connected to
the ground supply V.sub.SS and a gate connected to the input In_.
In the preferred embodiment, the transistors M.sub.p1 and M.sub.n1
of the inverter 41 are of equal size (i.e., channel width and
length) to the respective transistors M.sub.p2 and M.sub.n2 of the
inverter 45 so that the clock driver circuit 15 is symmetrical. In
this embodiment, the drain-to-source conductances G.sub.ds,p) of
the p-channel transistors M.sub.p1 and M.sub.p2 are equal and the
drain-to-source conductances G.sub.ds,n of the n-channel
transistors M.sub.n1 and M.sub.n2 are also equal.
[0077] The clock driver circuit 15 also includes two series
resistors R.sub.s1 and R.sub.s2. A first end of the series resistor
R.sub.s1 is connected to the output of the inverter 41, i.e., the
drains of the transistors M.sub.p1 and M.sub.n1. A second end of
the series resistor R.sub.s1 is connected to the output Out of the
clock driver circuit 15. Similarly, a first end of the series
resistor R.sub.s2 is connected to the output of the inverter 45,
i.e., the drains of the transistors M.sub.p2 and M.sub.n2. A second
end of the series resistor R.sub.s2 is connected to the output
Out.sub.-- of the clock driver circuit 15. Preferably, the series
resistors R.sub.s1 and R.sub.s2 are of equal resistance
R.sub.s=R.sub.s1=R.sub.s2 so that the clock driver circuit 15 is
symmetrical.
[0078] The clock driver circuit 15 further includes two parallel
resistors R.sub.p1 and R.sub.p2. A first end of the parallel
resistor R.sub.p1 is connected to the output Out of the clock
driver circuit 15. A second end of the parallel resistor R.sub.p1
is connected to a node labeled "mid." Similarly, a first end of the
parallel resistor R.sub.p2 is connected to the output Out.sub.-- of
the clock driver circuit 15. A second end of the parallel resistor
R.sub.p2 is connected to the mid node. Preferably, the parallel
resistors R.sub.p1 and R.sub.p2 are of equal resistance
R.sub.p=R.sub.p1=R.sub.p2 so that the clock driver circuit 15 is
symmetrical. If the clock driver circuit 15 is symmetrical, the mid
node acts as a differential ground provided that a truly
complementary signal is supplied to the inputs In and In_.
[0079] The clock driver circuit 15 may optionally include a
capacitor C.sub.mid. A first end of the capacitor C.sub.mid is
connected to the mid node. A second end of the capacitor C.sub.mid
is connected to a stable voltage supply such as the ground supply
V.sub.SS. The capacitor C.sub.mid reinforces the differential
ground at the mid node, preventing the node from temporarily
drifting from the common mode potential, by providing a low
impedance AC path from the node to the ground supply. The mid node
may drift from the common mode potential for two reasons: (1) small
imbalances may exist between the two sides of the clock driver
circuit 15; for example, slight differences in the value of
R.sub.p1 and R.sub.p2, and (2) the input signals In and In.sub.--
may not be perfectly complementary due to small timing skews
between the signals.
[0080] The series resistors R.sub.s1 and R.sub.s2, the parallel
resistors R.sub.p1 and R.sub.p2 and the capacitor C.sub.mid of the
clock driver circuit 15 may be formed from either discrete
components or devices integrated on the same substrate as the
transistors M.sub.p1, M.sub.p2, M.sub.n1 and M.sub.n2.
[0081] The clock driver circuit 15 provides a well-controlled
output impedance Z.sub.out that can be closely matched to the
loaded impedance Z.sub.0 of the differential clock lines 17.
Assuming that the mid node is a differential ground node, the
output impedance Z.sub.out of the clock driver circuit 15 is
expressed as:
Z.sub.out=R.sub.p.parallel.[R.sub.s+(1/G.sub.ds,p.parallel.1/G.sub.ds,n)],
[0082] where R.sub.p=R.sub.p1=R.sub.p2, R.sub.s=R.sub.s132 R.sub.s2
and the symbol ".parallel." means "in parallel with" such that
R.sub.1.parallel.R.sub.2=(R.sub.1*R.sub.2)/(R.sub.1+R.sub.2). When
the output Out is at the voltage V.sub.oh, the expression
simplifies to:
Z.sub.out=R.sub.p.parallel.(R.sub.s+1/G.sub.ds,p)=R.sub.p*(R.sub.s+1/G.sub-
.ds,p)/(R.sub.p+R.sub.s+1/G.sub.ds,p).
[0083] Similarly, when the output Out is at the voltage V.sub.ol,
the expression reduces to:
Z.sub.out=R.sub.p.parallel.(R.sub.s+1/G.sub.ds,n)=R.sub.p*(R.sub.s+1/G.sub-
.ds,n)/(R.sub.p+R.sub.s+1/G.sub.ds,n).
[0084] Therefore, the output impedance Z.sub.out of the clock
driver circuit 15 when the output is not transitioning resembles
that of the previously described clock driver circuit 25 shown in
FIG. 13.
[0085] Unlike the clock driver 25, however, the output impedance
Z.sub.out of the clock driver circuit 15 does not increase
significantly when its outputs are transitioning. As indicated
earlier with respect to the clock driver 25, the 1/G.sub.ds,p and
1/G.sub.ds,n values of the transistors M.sub.p1, M.sub.p2, M.sub.n1
and M.sub.n2 increase dramatically when the outputs Out and
Out.sub.-- are transitioning between V.sub.oh and V.sub.ol.
However, since the mid node is a differential ground, the
differential clock lines 17 still see a relatively low resistance
path to ground through the parallel resistors R.sub.p1 and
R.sub.p2. Therefore, the maximum output impedance Z.sub.out of each
output of the clock driver circuit 15 is limited to R.sub.p, the
resistance of the parallel resistors R.sub.p1 and R.sub.p2. The
variation in the output impedance Z.sub.out of the clock driver
circuit 15 in relation to the output signals CTM and CTMN is
illustrated in FIG. 17.
[0086] In general, while the output driver circuit of the present
invention operates within the predefined range of expected
operating conditions, the output impedance Z.sub.out of the output
driver circuit will not fall below about 75 percent and will not
exceed about 150 percent of the clock line impedance Z.sub.0.
Preferably (i.e., in the preferred embodiments), the output
driver's passive network limits variation in the output driver's
output impedance to an even smaller range, such as between 90 and
140 percent of Z.sub.0.
[0087] Besides having a well-controlled output impedance, the clock
driver circuit 15 provides a readily adjustable voltage swing
V.sub.sw and common-mode voltage V.sub.cm. The voltage swing
V.sub.sw of the signals CTM and CTMN generated between the outputs
Out and Out.sub.-- is:
V.sub.sw=(V.sub.DD-V.sub.ds,p-V.sub.ds,n-V.sub.SS)*[(R.sub.p1+R.sub.p2).pa-
rallel.(2*Z.sub.0)]/{R.sub.s1+R.sub.s2+[(R.sub.p1+R.sub.p2).parallel.(2*Z.-
sub.0)]},
[0088] where V.sub.ds,p is the drain-to-source voltage of the
p-channel transistors M.sub.p1 and M.sub.p2 when the gate is at
V.sub.SS and V.sub.ds,n is the drain-to-source voltage of the
n-channel transistors M.sub.n1 and M.sub.n2 when the gate is at
V.sub.DD. This equation for the output voltage swing V.sub.sw is
derived by applying simple voltage divider analysis to the circuit
shown in FIG. 16. Using similar voltage divider analysis, the
common-mode voltage V.sub.cm of the signals CTM and CTMN is:
V.sub.cm=V.sub.SS+V.sub.ds,n+0.5*V.sub.sw+(V.sub.DD-V.sub.ds,p-V.sub.ds,n--
V.sub.SS)*R.sub.s1/{R.sub.s1+R.sub.s2+[(R.sub.p1+R.sub.p2).parallel.(2*Z.s-
ub.0)]}.
[0089] Examining these equations, it can be seen that the voltage
swing V.sub.sw and the common-mode voltage V.sub.cm may be set to
the desired level by adjusting the resistances of the series
resistors R.sub.s1 and R.sub.s2, the resistances of the parallel
resistors R.sub.p1 and R.sub.p2 or the sizes (i.e., channel length
and width) of the transistors M.sub.p1, M.sub.p2, M.sub.n1 and
M.sub.n2 accordingly.
[0090] In the preferred embodiment of the clock driver circuit 15,
the circuit is symmetrical such that the series resistors R.sub.s1
and R.sub.s2 are equal and the parallel resistors R.sub.p1 and
R.sub.p2 are equal. If the clock driver circuit 15 is symmetrical,
the equations for the voltage swing V.sub.sw and the common-mode
voltage V.sub.cm reduce to the following:
V.sub.sw=(V.sub.DD-V.sub.ds,p-V.sub.ds,n-V.sub.SS)*(R.sub.p.parallel.Z.sub-
.0)/[R.sub.s+(R.sub.p.parallel.Z.sub.0)]
[0091] and
V.sub.cm=V.sub.SS+V.sub.ds,n+0.5*V.sub.sw+(V.sub.DD-V.sub.ds,p-V.sub.ds,n--
V.sub.SS)*R.sub.s/[R.sub.s+(R.sub.p.parallel.Z.sub.0)],
[0092] where R.sub.s=R.sub.s1=R.sub.s2 and
R.sub.p=R.sub.p1=R.sub.p2.
[0093] In the preferred embodiment of the clock driver circuit 15,
the transistors M.sub.p1, M.sub.p2, M.sub.n1 and M.sub.n2 are sized
large enough to operate well into the linear region. As a result,
the voltage V.sub.ds,p+V.sub.ds,n will be much less than the
voltage V.sub.DD-V.sub.SS and the equations for the output voltage
swing V.sub.sw and the common-mode voltage V.sub.cm then reduce to
the following approximations:
V.sub.sw.congruent.(V.sub.DD-V.sub.SS)*(R.sub.p.parallel.Z.sub.0)/[R.sub.s-
+(R.sub.p.parallel.Z.sub.0)]
[0094] and
V.sub.cm.congruent.V.sub.SS+0.5*V.sub.sw+(V.sub.DD-V.sub.SS)*R.sub.s/[R.su-
b.s+(R.sub.p.parallel.Z.sub.0)].congruent.0.5*(V.sub.DD-V.sub.SS).
[0095] A procedure for designing the clock driver circuit 15 to
provide a specified output impedance Z.sub.out, voltage swing
V.sub.sw and common-mode voltage V.sub.cm will now be described.
FIG. 18 shows a DC equivalent circuit diagram of the clock driver
circuit 15 that is useful for illustrating the design procedure.
The design procedure assumes that the clock driver circuit 15 is
symmetrical such that R.sub.s=R.sub.s1=R.sub.s2,
R.sub.p=R.sub.p1=R.sub.p2, M.sub.p=M.sub.p1=M.sub.p2 and
M.sub.n=M.sub.n1=M.sub.n2. In the figure, the input In is driven to
V.sub.SS and the input In.sub.-- is driven to V.sub.DD to turn on
transistors M.sub.p1 and M.sub.n2 and turn off transistors M.sub.n1
and M.sub.p2. To simplify the diagram, the two transistors which
are turned off have been omitted.
[0096] Referring to FIG. 18, the design procedure is as follows.
The procedure assumes the following parameters are given: V.sub.DD,
V.sub.SS, V.sub.sw, V.sub.cm, Z.sub.0 and f, where f is the
frequency of the output signals CTM and CTMN.
[0097] Step 1: Choose R.sub.p such that R.sub.p>Z.sub.0. This
sets the maximum output impedance Z.sub.out of the output driver
circuit 15.
[0098] Step 2: Compute I.sub.o=V.sub.sw/(2*Z.sub.0). I.sub.o is the
current flowing through the differential clock lines 17.
[0099] Step 3: Compute I.sub.p=V.sub.sw/(2*R.sub.p).
[0100] Step 4: Compute I.sub.T=I.sub.o+I.sub.p.
[0101] Step 5: Compute R.sub.T=(Z.sub.0*R.sub.p)/(R.sub.p-Z.sub.0).
R.sub.T=R.sub.s+1/G.sub.ds and 1/G.sub.ds is the desired
drain-to-source resistance of the transistors M.sub.p or M.sub.n
when turned on.
[0102] Step 6: Choose R.sub.s such that R.sub.s<R.sub.T.
Calculate 1/G.sub.ds=R.sub.T-R.sub.s.
[0103] Step 7: Compute
.vertline.V.sub.ds,p.vertline.=V.sub.DD-[(I.sub.T*R-
.sub.s)+(0.5*V.sub.sw)+V.sub.cm]. V.sub.ds,p is the drain-to-source
voltage of the transistors M.sub.p1 or M.sub.p2.
[0104] Step 8: Compute
V.sub.ds,n=V.sub.cm-[(0.5*V.sub.sw)+(I.sub.T*R.sub.- s)].
V.sub.ds,n is the drain-to-source voltage of the transistors
M.sub.n1 and M.sub.n2.
[0105] Step 9: Adjust the channel width (W.sub.p or W.sub.n) and
length (L.sub.p or L.sub.n) of the transistors M.sub.p1, M.sub.p2,
M.sub.n1 and M.sub.n2 such that: 1 I ds , p = I ds , n - I T ,
where: I ds , p = K p * W p / L p * { [ V gs , p - V T , p * V ds ,
p ] - V ds , p 2 / 2 } , I ds , n = K n * W n / L n * { [ ( V gs ,
n - V T , n ) * V ds , n ] - V ds , n 2 / 2 } , and ( a ) 1 / G ds
, p = 1 / G ds , n = 1 / G ds , where : G ds , p = d ( I ds , p ) /
d ( V ds , p ) , G ds , n = d ( I ds , n ) / d ( V ds , n ) . ( b
)
[0106] I.sub.ds,p and I.sub.d,sn are the drain-to-source currents,
G.sub.ds,p and G.sub.ds,n are the drain-to-source conductances,
K.sub.p and K.sub.n are the process gain factors, and V.sub.T,p and
V.sub.T,n are the threshold voltages of the transistors
M.sub.p1/M.sub.p2 and M.sub.n1/M.sub.n2, respectively. Typically,
.vertline.V.sub.gs,p.vertline- .=V.sub.gs,n=V.sub.DD-V.sub.SS.
[0107] Step 10: If it is impossible to satisfy both equations 9(a)
and 9(b), return to step 6 and choose a different value for
R.sub.s. Repeat steps 6 to 9 until the equation in step 9(a) is met
nearly exactly and the equation in step 9(b) is met
approximately.
[0108] Step 11 (optional): If the clock driver circuit 15 includes
the capacitor C.sub.mid, adjust the value of the capacitance of the
capacitor C.sub.mid such that its reactance X.sub.Cmid is less than
about 10 percent of R.sub.p, i.e.:
C.sub.mid>5/(.pi.*f*R.sub.p).
[0109] The following example illustrates the design procedure for
an actual implementation of the clock driver circuit 15. In this
example, the clock driver circuit 15 is implemented in a standard
0.5 micron (.mu.m), 3.3 volt (V) CMOS process. The following
parameters are given for the design: V.sub.DD=3.465 V, V.sub.SS=0.0
V, V.sub.sw=600 mV, V.sub.cm=1.70 V, Z.sub.0=28 ohms and f=400 MHz.
The steps in the design procedure are as follows:
[0110] Step 1: Let R.sub.p=39 ohms (this is a common 5% tolerance
resistor value).
[0111] Step 2: I.sub.o=10.71 mA.
[0112] Step 3: I.sub.p=7.69 mA.
[0113] Step 4: I.sub.T=18.41 mA.
[0114] Step 5: R.sub.T=99 ohms.
[0115] Step 6: Let R.sub.s=68 ohms (this is a common 5% tolerance
resistor value). Thus, 1/G.sub.ds=31 ohms.
[0116] Step 7: V.sub.ds,p=213 mV.
[0117] Step 8: V.sub.ds,n=148 mV.
[0118] Step 9: For I.sub.ds,p=I.sub.ds,n to equal I.sub.T=18.41 mA,
computer simulations indicate that the required dimensions for the
transistors M.sub.p and M.sub.n are: W.sub.p=275 .mu.m, L.sub.p=0.5
.mu.m, W.sub.n=235 .mu.m and L.sub.p=1.0 .mu.m. With these
dimensions, the resistance of the transistors M.sub.p and M.sub.n
is 1/G.sub.ds,p=15 ohms and 1/G.sub.ds,n=12 ohms, which is
sufficiently close to the desired value of 1/G.sub.ds=31 ohms.
[0119] Step 10: Equations 9(a) and 9(b) are both satisfied.
[0120] Step 11: C.sub.mid>102 pF. Let C.sub.mid=100 pF (this is
a standard capacitance value).
[0121] In this design example, the output impedance Z.sub.out of
the clock driver circuit 15 when the outputs Out and Out.sub.-- are
at either V.sub.oh or V.sub.ol is
Z.sub.out=R.sub.p*(R.sub.s+1/G.sub.ds)/(R.sub.p+R-
.sub.s+1/G.sub.ds)=26.2 ohms (i.e., about 93.5% of Z.sub.0). This
value is very close to the desired impedance of Z.sub.0=28 ohms.
The maximum output impedance Z.sub.out, which occurs when the
outputs are transitioning, is Z.sub.out=R.sub.p=39 ohms, a value
that is about 139 percent of the value of the loaded impedance
Z.sub.0. Therefore, it can be seen that the variation in the output
impedance Z.sub.out of the clock driver circuit 15 is relatively
well-controlled, thereby minimizing the occurrence of secondary
reflections at the outputs Out and Out_.
[0122] FIG. 19 is a circuit diagram of a quasi-differential clock
driver 55 in accordance with an alternate embodiment of the present
invention. Quasi-differential clock driver 55 is identical to the
clock driver circuit 15 just described except for two modifications
that further enhance its performance. The modifications can be made
either simultaneously as illustrated in the figure or
individually.
[0123] The first modification is that the clock driver circuit 55
includes predriver circuits 57, 58, 59 and 60. The predriver
circuits 57 and 58 are connected between the input In and the gates
of the transistors M.sub.p1 and M.sub.n1, respectively. Similarly,
the predriver circuits 59 and 60 are connected between the input
In.sub.-- and the gates of the transistors M.sub.p2 and M.sub.n2,
respectively.
[0124] The predriver circuits 57, 58, 59 and 60 minimize the wasted
"shoot-through" current passing through the transistors
M.sub.p1/M.sub.n1 and M.sub.p2/M.sub.n2 from V.sub.DD to V.sub.SS
during transitions of the output signals CTM and CTMN,
respectively. The predriver circuits prevent the shoot-through from
occurring by skewing the timing of the signals fed to the p-channel
transistors M.sub.p1 and M.sub.p2 as compared with the signals fed
to the n-channel transistors M.sub.n1 and M.sub.n2 so that the
transistor in each driver circuit that had been supplying current
is shut off before the other transistor is turned on. For example,
if transistor M.sub.p1 is on and transistor M.sub.n1 is off (i.e.,
V.sub.g,p1=V.sub.g,n1=V.sub.SS), the predriver circuits 57 and 58
skew the timing of the input signals to transistors M.sub.p1 and
M.sub.n1 so that the input to M.sub.p1 rises before the input to
M.sub.n1 rises, thereby turning off transistor M.sub.p1 before
turning on transistor M.sub.n1.
[0125] The predriver circuits 57, 58, 59 and 60 each have a delay
from its input to its output for a low-to-high and high-to-low
output transition. To provide the desired timing, the predriver
circuits have the following input to output delays: (1) the
low-to-high delay of the predriver circuit 58 is larger than the
low-to-high delay of the predriver circuit 57, (2) the high-to-low
delay of the predriver circuit 57 is larger than the high-to-low
delay of the predriver circuit 58, (3) the low-to-high delay of the
predriver circuit 60 is larger than the low-to-high delay of the
predriver circuit 59 and (4) the high-to-low delay of the predriver
circuit 59 is larger than the high-to-low delay of the predriver
circuit 60. The technique of using predrivers to reduce the
shoot-through current in output drivers is well-known in the art
and thus the details of the predrivers 57, 58, 59 and 60 will not
be further discussed.
[0126] The second modification to the clock driver circuit 55 is
that the series resistors R.sub.s1 and R.sub.s2 of the clock driver
circuit 15 are each replaced by two resistors. R.sub.s1 is replaced
by series resistors R.sub.s,p1 and R.sub.s,n1, where R.sub.s,p1 is
connected between the drain of the transistor M.sub.p1 and the
output Out and R.sub.s,n1 is connected between the output Out and
the drain of the transistor M.sub.n1. R.sub.s2 is replaced by
series resistors R.sub.s,p2 and R.sub.s,n2, where R.sub.s,p2 is
connected between the drain of the transistor M.sub.p2 and the
output Out.sub.-- and R.sub.s,n2 is connected between the output
Out.sub.-- and the drain of the transistor M.sub.n2. This
arrangement of the series resistors allows a different R.sub.s
value to be selected for the p-channel transistors M.sub.p1 and
M.sub.p2 and for the n-channel transistors M.sub.n1 and M.sub.n2
(see step 6 of the design procedure above). This is particularly
useful to accommodate large differences between the conductances
G.sub.ds,p and G.sub.ds,n of the p-channel and n-channel
transistors, respectively, so that the output impedance of each
CMOS inverter is approximately the same regardless of whether its
p- or n-channel transistor is on. The resistor arrangement also
reduces the shoot-through current in the clock driver circuit
because of the increased resistance between the p- and n-channel
transistors of the clock driver's CMOS inverters.
[0127] FIG. 20 is a circuit diagram of a quasi-differential clock
driver circuit 65 in accordance with a second alternate embodiment
of the present invention. Quasi-differential clock driver circuit
65 is similar in construction to the clock driver circuit 15
described above except that the circuit includes predrivers 67, 68,
69 and 70 to further improve its performance. The clock driver
circuit 65 also omits the series resistors R.sub.s1 and R.sub.s2.
The predrivers 67 and 68 are connected between the input In and the
gates of the transistors M.sub.p1 and M.sub.n1, respectively.
Similarly, the predrivers 69 and 70 are connected between the input
In.sub.-- and the gates of the transistors M.sub.p2 and M.sub.n2,
respectively.
[0128] The predrivers 67, 68, 69 and 70 are used to drive the
transistors M.sub.p1, M.sub.n1, M.sub.p2 and M.sub.n2,
respectively, such that the transistors operate in either the
saturation or cutoff regions of operation only. Unlike the
transistors of the clock driver circuit 15, the transistors
M.sub.p1, M.sub.n1, M.sub.p2 and M.sub.n2 never operate in the
linear region. Consequently, the resistance 1/G.sub.ds of the
transistors M.sub.p1, M.sub.n1, M.sub.p2 and M.sub.n2 is always
very large. Because of this, the output impedance Z.sub.out is not
significantly affected by variations in the transistor conductance
G.sub.ds and is essentially equal to the resistance of the parallel
resistors R.sub.p1 and R.sub.p2, that is:
Z.sub.out=R.sub.p.parallel.1/G.sub.ds=(R.sub.p*1/G.sub.ds)/(R.sub.p+1/G.su-
b.ds).congruent.R.sub.p,
[0129] where R.sub.p=R.sub.p1=R.sub.p2. Therefore, the output
impedance Z.sub.out of the clock driver circuit 65 is essentially
constant, providing a very close match to the loaded impedance
Z.sub.0 of the differential clock lines 17 under all operating
conditions.
[0130] A procedure for designing the clock driver circuit 65 to
provide a specified output impedance Z.sub.out, voltage swing
V.sub.sw and common-mode voltage V.sub.cm will now be described.
The design procedure assumes that the clock driver circuit 65 is
symmetrical such that R.sub.p=R.sub.p1=R.sub.p2,
M.sub.p=M.sub.p1=M.sub.p2 and M.sub.n=M.sub.n1=M.sub.n2. The
procedure assumes the following parameters are given: V.sub.DD,
V.sub.SS, V.sub.sw, V.sub.cm, Z.sub.0 and f.
[0131] Step 1: Choose R.sub.p such that R.sub.p=Z.sub.0. This sets
the output impedance Z.sub.out of the output driver circuit 65 to
equal Z.sub.0.
[0132] Step 2: Compute I.sub.o=V.sub.sw/(2*Z.sub.0). I.sub.o is the
current flowing through the differential clock lines 17.
[0133] Step 3: Compute I.sub.p=V.sub.sw/(2*R.sub.p).
[0134] Step 4: Compute I.sub.T=I.sub.o+I.sub.p.
[0135] Step 5: Compute
.vertline.V.sub.ds,p.vertline.=V.sub.DD-V.sub.cm+(0- .5*V.sub.sw).
V.sub.ds,p is the drain-to-source voltage of the transistors
M.sub.p1 and M.sub.p2.
[0136] Step 6: Compute V.sub.ds,n=V.sub.cm-V.sub.SS-(0.5*V.sub.sw).
V.sub.ds,n is the drain-to-source voltage of the transistors
M.sub.n1 and M.sub.n2.
[0137] Step 7: Adjust the channel width W.sub.p and length L.sub.p
and the gate voltage V.sub.gs,p of the transistors M.sub.p1 and
M.sub.p2 such that: 2 I ds , p = I T , where: I ds , p = 0.5 * K p
* W p / L p * ( V gs , p - V T , p ) 2 , and ( a ) V gs , p - V ds
, p < V T , p . ( b )
[0138] I.sub.ds,p is the drain-to-source current, K.sub.p is the
process gain factor, and V.sub.T,p is the threshold voltage of the
transistors M.sub.p1 and M.sub.p2.
[0139] Step 8: Adjust the channel width W.sub.n and length L.sub.n
and the gate voltage V.sub.gs,n of the transistors M.sub.n1 and
M.sub.n2 such that: 3 I ds , n = I T , where: I ds , n = 0.5 * K n
* W n / L n * ( V gs , n - V T , n ) 2 , and ( a ) V gs , n - V ds
, n < V T , n . ( b )
[0140] I.sub.ds,n is the drain-to-source current, K.sub.n is the
process gain factor, and V.sub.T,n is the threshold voltage of the
transistors M.sub.n1 and M.sub.n2.
[0141] Step 9: Design the predrivers 67 and 69 to drive the gates
of the p-channel transistors M.sub.p1 and M.sub.p2 with the voltage
V.sub.gs,p determined in step 7. Design the predrivers 68 and 70 to
drive the gates of the n-channel transistors M.sub.n1 and M.sub.n2
with the voltage V.sub.gs,n determined in step 8. Driving the
transistors with these voltages ensures that the transistors
operate in the saturation or cutoff regions only. The design of the
predrivers 67, 68, 69 and 70 is beyond the scope of the present
invention and thus will not be discussed further.
[0142] Step 10 (optional): If the clock driver circuit 65 includes
the capacitor C.sub.mid, adjust the value of the capacitance of the
capacitor C.sub.mid such that its reactance X.sub.Cmid is less than
about 10 percent of R.sub.p, i.e.:
C.sub.mid>5/(.pi.*f*R.sub.p).
[0143] Step 11 (optional): Set R.sub.p slightly higher than Z.sub.0
such that: R.sub.p.parallel.G.sub.ds,p=Z.sub.0 or
R.sub.p.parallel.G.sub.ds,n=- Z.sub.0.
[0144] In summary, the preferred embodiment of the present
invention includes a differential clock driver circuit providing
several advantages over prior art clock driver designs. First, the
clock driver circuit does not rely on the noise-prone voltages
V.sub.Term or V.sub.Ref to generate the clock signal. Second, the
clock driver circuit has a well-controlled output impedance
Z.sub.out that closely matches the loaded impedance Z.sub.0 of the
differential clock lines at all times, thereby minimizing the
occurrence of secondary reflections at its output. These two
features reduce the jitter of the clock signal produced by the
clock driver circuit. Third, the voltage swing V.sub.sw and
common-mode voltage V.sub.cm of the clock driver circuit can be
readily adjusted by varying the values of the resistors and/or the
sizes of the transistors in the circuit.
[0145] While the present invention has been described with
reference to a few specific embodiments, the description is
illustrative of the invention and is not to be construed as
limiting the invention. Various modifications may occur to those
skilled in the art without departing from the true spirit and scope
of the invention as defined by the appended claims. For example,
the output driver circuit of the present invention may be used to
drive signals other than a clock signal onto a bus, such as data or
address signals.
* * * * *