U.S. patent application number 09/811073 was filed with the patent office on 2001-10-25 for cmos sense structure having silicon dioxide outer ring around sense region.
Invention is credited to Chen, Ming-I, Pan, Jui-Hsiang.
Application Number | 20010034092 09/811073 |
Document ID | / |
Family ID | 21659446 |
Filed Date | 2001-10-25 |
United States Patent
Application |
20010034092 |
Kind Code |
A1 |
Chen, Ming-I ; et
al. |
October 25, 2001 |
CMOS sense structure having silicon dioxide outer ring around sense
region
Abstract
A CMOS structure having a silicon dioxide outer ring around the
sense region. The CMOS sense structure has a substrate, a n.sup.-
region, a n.sup.+ region, an isolation region, a field implant
region and a silicon dioxide outer ring region. The n.sup.- region
is formed in the substrate, and the n.sup.+ region is formed within
the n.sup.- region. The isolation region is formed in the substrate
next to the edge of the n.sup.- region. The field implant region is
formed under the isolation region. The silicon dioxide outer ring
region is formed over the n.sup.- region, a portion of the
isolation region and a portion of the n.sup.+ region. The silicon
dioxide outer ring can prevent surface leakage that is caused by
etching and lengthening the distance from the n.sup.- region to the
field implant region so that edge junction leakage is reduced.
Inventors: |
Chen, Ming-I; (Tainan Hsien,
Tawain, CN) ; Pan, Jui-Hsiang; (Hsinchu, Taiwan,
CN) |
Correspondence
Address: |
THOMAS, KAYDEN, HORSTEMEYER & RISLEY, LLP
100 GALLERIA PARKWAY, NW
STE 1750
ATLANTA
GA
30339-5948
US
|
Family ID: |
21659446 |
Appl. No.: |
09/811073 |
Filed: |
March 16, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09811073 |
Mar 16, 2001 |
|
|
|
09560013 |
Apr 27, 2000 |
|
|
|
Current U.S.
Class: |
438/199 ;
257/E27.016; 257/E27.132 |
Current CPC
Class: |
H01L 27/14689 20130101;
H01L 27/1462 20130101; H01L 27/0629 20130101; H01L 27/1463
20130101; H01L 27/14609 20130101 |
Class at
Publication: |
438/199 |
International
Class: |
H01L 021/8238 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 19, 2000 |
TW |
89107355 |
Claims
What is claimed is:
1. A CMOS sense structure having a silicon dioxide outer ring
around the sense region, comprising: a substrate; a n.sup.- region
in the substrate; a n.sup.+ region within the n.sup.- region of the
substrate; an isolation region in the substrate in contact with the
edge of the n.sup.- region; a field implant region under the
isolation region; and a silicon dioxide outer ring over the n.sup.-
region, a portion of the isolation region and a portion of the
n.sup.+ region.
2. The structure of claim 1, wherein material forming the isolation
region includes silicon dioxide.
3. The structure of claim 1, wherein the field implant region
includes a P-type ion implant region.
4. A method of forming a CMOS sense structure having a silicon
dioxide outer ring thereon, comprising the steps of: providing a
substrate having a device region, a plurality of isolation regions
and a CMOS sense region, wherein one side of the isolation region
is in contact with the device region and the other side of the
isolation region is in contact with the CMOS sense region, a field
implant region is under each isolation region, and the silicon
dioxide outer ring is over the isolation region and the edge
junction of the CMOS sense region; and conducting a n.sup.+ and a
n.sup.- implant sequentially to implant ions into the CMOS sense
region.
5. The method of claim 4, wherein material for forming the
isolation region includes silicon dioxide.
6. The method of claim 4, wherein the step of forming the field
implant regions under the isolation region include implanting
P-type ions into the substrate.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Taiwan
application Ser. No. 89107355, filed Apr. 19, 2000.
BACKGROUND OF THE INVENTION
[0002] 1. Field of Invention
[0003] The present invention relates to a CMOS sense structure.
More particularly, the present invention relates to a CMOS sense
structure having a silicon dioxide outer ring around the sense
region for lowering surface leakage and edge junction leakage.
[0004] 2. Description of Related Art
[0005] FIG. 1 is a schematic cross-sectional side view of a
conventional CMOS sense Is structure. As shown in FIG. 1, the CMOS
sense structure includes a substrate 10, a n.sup.+ region 12, a
n.sup.- region 14, isolation regions 16 and field implant regions
18. The substrate 10 can be a P-type substrate (or a P-well), for
example. The n.sup.+ region 12 and the n.sup.- region 14 are formed
by implanting identical ions, but with different concentrations,
into the substrate 10. The concentration of ions inside the n.sup.+
region is higher than the concentration of ions inside the n.sup.-
region. The n.sup.+ region 12 and the n.sup.- region 14 together
form the diode in the sense region. The isolation region 16 and the
field implant region 18 on each side of the sense region are used
for isolating device regions (not shown in the figure).
[0006] Because etching is conducted in the process of forming
spacers or polysilicon gates in the device regions, the depletion
region 22 near the edge of the sense region may be etched, leading
to surface damages. Consequently, a large dark current may form on
the surface of the sense region. The dark current is referred to as
surface leakage. An excessive surface leak may result in poor image
quality.
SUMMARY OF THE INVENTION
[0007] Accordingly, one object of the present invention is to
provide a CMOS sense structure having an outer silicon dioxide ring
around the sense region. The outer silicon dioxide ring serves as a
protective layer to prevent any damages on the depletion region
near the edge of the sense region when spacer etching or
polysilicon etching is conducted to reduce the leakage current.
[0008] To achieve these and other advantages and in accordance with
the purpose of the invention, as embodied and broadly described
herein, the invention provides a CMOS structure having a silicon
dioxide outer ring around the sense region. The CMOS sense
structure includes a substrate, a n.sup.- region, a n.sup.+ region,
an isolation region, a field implant region and a silicon dioxide
outer ring region. The n.sup.- region is formed in the substrate,
and the n.sup.+ region is formed within the n.sup.- region. The
isolation region is formed in the substrate next to the edge of the
n.sup.- region. The field implant region is formed under the
isolation region. The silicon dioxide outer ring region is formed
over the n.sup.- region, a portion of the isolation region and a
portion of the n.sup.+ region.
[0009] The substrate can be a P-type substrate. The n.sup.+ region
and the n.sup.- region form a diode structure. The isolation region
is formed using a silicon dioxide. The field implant region is
formed by implanting p-type ions. In addition, the silicon dioxide
outer ring is formed over the n.sup.- region, a portion of the
isolation region and a portion of the n.sup.+ region. Hence, the
outer ring can protect the depletion region of the sense region
against any damages that are caused by etching and reducing the
current leak.
[0010] The invention also provides a method of forming a CMOS sense
structure having a silicon dioxide outer ring around the sense
region. First, a substrate having a device region, a plurality of
isolation regions and a CMOS sense region is provided. One side of
the isolation region is in contact with the device region while the
other side of the isolation region is in contact with the CMOS
sense region. There is a field implant region under each isolation
region. A silicon dioxide outer ring is formed over the isolation
region and the edge junction of the CMOS sense region. Finally, an
n.sup.+ and an n.sup.- implant are conducted sequentially,
implanting ions into the CMOS sense region.
[0011] The substrate can be a P-type substrate. The n.sup.+ region
and the n.sup.- region form a diode structure. The isolation region
is formed using a silicon dioxide. The field implant region is
formed by implanting p-type ions. In this invention, since the
silicon dioxide outer ring is formed before the n.sup.+ and n.sup.-
implants, distance of separation between the n.sup.+/n.sup.- field
implant regions is increased. Hence, edge junction leakage is
lowered.
[0012] It is to be understood that both the foregoing general
description and the following detailed description are exemplary,
and are intended to provide further explanation of the invention as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention. In the
drawings,
[0014] FIG. 1 is a schematic cross-sectional side view of a
conventional CMOS sense structure;
[0015] FIG. 2A is a schematic cross-sectional view showing a CMOS
sense structure having a silicon dioxide outer ring thereon
according to a preferred embodiment of this invention;
[0016] FIG. 2B is a schematic top view of the CMOS sense structure
shown in FIG. 2A; and
[0017] FIGS. 3A through 3F are schematic cross-sectional views
showing the progression of steps for producing the CMOS sense
structure of this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0018] Reference will now be made in detail to the present
preferred embodiments of the invention, examples of which are
illustrated in the accompanying drawings. Wherever possible, the
same reference numbers are used in the drawings and the description
to refer to the same or like parts.
[0019] FIG. 2A is a schematic cross-sectional view showing a CMOS
sense structure having a silicon dioxide outer ring thereon
according to a preferred embodiment of this invention. FIG. 2B is a
schematic top view of the CMOS sense structure shown in FIG.
2A.
[0020] As shown in FIG. 2A, a CMOS sense structure includes a
substrate 30, a n.sup.+ region 32, a n region 34, isolation regions
36, field implant regions 38 and a silicon dioxide outer ring 42.
The substrate 30 can be a P-type substrate or a P-well above a
substrate, for example. The n.sup.+ region 32 and the n.sup.-
region 34 are formed within the substrate 30, and the n.sup.+
region 32 is formed entirely within the n.sup.- region 34. Although
identical types of ions are implanted into the n.sup.+ region 32
and the n.sup.- region 34, the concentrations of the ions in the
implanted regions 32 and 34 are different. In general, the
concentrations of the ions in the n.sup.+ region is greater than
the concentration of ions in the n.sup.- region. Due to a
difference in the concentrations of the ions, the n.sup.+ region 32
and n.sup.- region 34 together form the diode of the sense
structure.
[0021] The isolation regions 36 and the field implant regions 38
are structures for isolating different device regions. The
isolation region 36 is a silicon dioxide layer formed over the
substrate 30. The isolation region 36 is in contact with the edge
of the n.sup.- region 34. The field implant region 38 is under the
isolation region 36 and is formed by a P-type ion implant. The
silicon dioxide outer ring 42 is formed over the entire n.sup.-
region 34, a portion of the isolation region 36 and a portion of
the n.sup.+ region 32. As shown in FIG. 2B, the central portion 44
is the sense region of the n.sup.- region 34 and the n.sup.+ region
32, and the outer ring 46 is the region covered by the silicon
dioxide outer ring 42.
[0022] FIGS. 3A through 3F are schematic cross-sectional views
showing the progression of steps for producing the CMOS sense
structure of this invention.
[0023] As shown in FIG. 3A, a substrate of a P-well 50 having a
device region 52, a plurality of isolation regions 54 and a CMOS
sense region 56 is provided. One side of the isolation region 54 is
in contact with the device region 52, while the other side of the
isolation region 54 is in contact with the CMOS sense region 56.
There is a field implant region 58 under the isolation region 54.
To prepare for the formation of spacers, a silicon dioxide layer 60
is formed by APCVD or PECVD after source/drain implant in the
device region 52.
[0024] As shown in FIG. 3B, a patterned photoresist layer 62 is
formed around the edge (covering a portion of the isolation region
as well) of the sense region 56, which is the desirable location
for the silicon dioxide outer ring. As shown in FIG. 3C, a spacer
etching is carried out. Hence, spacers 64 are formed in the device
region 52, and a silicon dioxide ring 66 is formed over the
junction region between the isolation region 54 and the CMOS sense
region 56. As shown in FIG. 3D, a source/drain implant is carried
out to form surrounding device structures 68 in the device region
52. To prepare for ion implantation, an opening is formed in the
sense region by forming a photoresist layer 70 over other regions
(for example, the device region 52 and the isolation region 54), as
shown in FIG. 3E. An implantation is carried out by implanting ions
into the sense region with a tilt angle, as shown in FIG. 3F. For
example, a n.sup.+ implant and a n.sup.- implant are sequentially
conducted to form an n.sup.+ region 72 and the an n.sup.- region
74. The regions 72 and 74 together form the sensor diode of a CMOS
sensor.
[0025] In this invention, the silicon dioxide outer ring is formed
over the junction region between the sense region and the isolation
region before carrying out spacer etching. Hence, any damaging
effect on the sensor diode due to etching is minimized, and surface
leakage is greatly reduced.
[0026] In addition, since the silicon dioxide outer ring is formed
before carrying out tilt-angle implant of ions into the sense
region to form the n+ and the n- regions, the junction surface of
the sensor diode is closer to the surface. Therefore, the distance
between junction surfaces for the n+/n-/field implant regions is
increased, leading to a further reduction of current leak from the
junctions.
[0027] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
present invention cover modifications and variations of this
invention provided they fall within the scope of the following
claims and their equivalents.
* * * * *