U.S. patent application number 09/816924 was filed with the patent office on 2001-10-25 for method for carrying out a burn-in process for electrically stressing a semiconductor memory.
Invention is credited to Ayadi, Kamel, Lindolf, Jurgen, Oezoguz-Geissler, Nedim.
Application Number | 20010033518 09/816924 |
Document ID | / |
Family ID | 7636020 |
Filed Date | 2001-10-25 |
United States Patent
Application |
20010033518 |
Kind Code |
A1 |
Ayadi, Kamel ; et
al. |
October 25, 2001 |
Method for carrying out a burn-in process for electrically
stressing a semiconductor memory
Abstract
A circuit configuration is described that has a first voltage
terminal, a second voltage terminal and a control input. A
reference-ground potential is applied to the first voltage terminal
and an operating voltage is applied to the second voltage terminal.
The control input is supplied with a control voltage, the control
voltage assumes voltage values which alternate between the
reference-ground potential and the operating voltage. The
alternation of the control voltage has the effect that components
such as transistors and inverter that are present in the circuit
configuration are active and thereby experience an accelerated
aging process.
Inventors: |
Ayadi, Kamel; (Puchheim,
DE) ; Lindolf, Jurgen; (Friedberg, DE) ;
Oezoguz-Geissler, Nedim; (Taufkirchen, DE) |
Correspondence
Address: |
LERNER AND GREENBERG, P.A.
Post Office Box 2480
Hollywood
FL
33022-2480
US
|
Family ID: |
7636020 |
Appl. No.: |
09/816924 |
Filed: |
March 23, 2001 |
Current U.S.
Class: |
365/201 |
Current CPC
Class: |
G11C 29/50 20130101 |
Class at
Publication: |
365/201 |
International
Class: |
G11C 029/00 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 23, 2000 |
DE |
100 14 388.1 |
Claims
We claim:
1. A method for carrying out a burn-in process for electrically
stressing semiconductor memories, which comprises the steps of:
providing a memory having a circuit configuration with a first
voltage terminal, a second voltage terminal, a control input, and a
MOS transistor; applying a reference-ground potential to the first
voltage terminal; applying a second voltage to the second voltage
terminal; and applying a control voltage to the control input, and
varying the control voltage.
2. The method according to claim 1, which comprises providing the
control voltage with voltage values which alternate between the
reference-ground potential and an operating voltage.
3. The method according to claim 1, wherein the MOS transistor is
part of an inverter, the control input is an inverter input, the
first voltage terminal is a first inverter voltage supply, and the
second voltage terminal is a second inverter voltage supply.
4. The method according to claim 1, which comprises setting the
second voltage to a value of an operating voltage.
5. The method according to claim 1, which comprises setting the
second voltage present at the second voltage terminal to alternate
between the reference-ground potential and an operating
voltage.
6. The method according to claim 1, which comprises setting the
second voltage to alternate at a first frequency and the control
voltage to alternate at a second frequency between the
reference-ground potential and an operating voltage.
7. The method according to claim 6, which comprises setting the
first frequency to be equal to the second frequency, and the first
voltage and the second voltage have a phase difference of between
150 and 210 degrees.
8. The method according to claim 7, which comprises varying the
phase difference.
Description
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] The invention relates to a method for carrying out a burn-in
process for electrically stressing a semiconductor memory.
[0002] Semiconductor memories are used to store information and can
be realized as a semiconductor component. One semiconductor memory
is e.g. a dynamic random access memory (DRAM). It contains a cell
array with memory cells and an addressing periphery. The memory
cells of the memory cell array contain a selection transistor and a
storage capacitor. The addressing periphery is usually formed from
transistors fabricated using CMOS technology. CMOS denotes
Complimentary Metal Oxide Semiconductor and contains both N-MOS and
P-MOS transistors.
[0003] In order to ensure that the transistors used have high
reliability over the entire lifetime of a memory product, a burn-in
process is carried out. The dictates of production result in that
transistors are not able to maintain an identical behavior
throughout their lifetime, which is reflected in an input and
output characteristic curve that is changed over time. The change
in the transistors is caused e.g. by "hot carrier injection"
(injection of high-energy charge carriers), which affects
transistors having a short channel length to an increasing extent.
The threshold voltage of a freshly produced transistor is not
stable since high-energy charge carriers are accumulated in the
gate oxide. The introduction of a burn-in process makes it possible
to stabilize the transistor properties at a constant value. The
stabilization is carried out during the burn-in phase, while the
memory is in a test environment, so that the module has stable
properties during operation. The burn-in processes are usually
carried out in a furnace in which the memories are exposed to an
elevated temperature. Documents that describe the performance of a
burn-in include U.S. Pat. Nos. 5,976,899; 5,917,765; 5,898,186;
5,748,543; 5,636,171; and 6,018,485. Two documents that describe
circuits for carrying out a burn-in process are U.S. Pat. Nos.
5,986,917 and 5,424,990. Further insights on the stressing of MOS
transistors can be found in the reference by Zhi Chen et. al.,
titled "On the Mechanism for Interface Trap Generation in MOS
Transistors Due to Channel Hot Carrier Stressing", IEEE Electron
Device Letters, Vol. 21, No. 1, January 2000, p. 24.
SUMMARY OF THE INVENTION
[0004] It is accordingly an object of the invention to provide a
method for carrying out a burn-in process for electrically
stressing a semiconductor memory that overcomes the above-mentioned
disadvantages of the prior art methods of this general type, which
carries out a burn-in process for a memory and stabilizes the
electrical characteristics of the memory.
[0005] With the foregoing and other objects in view there is
provided, in accordance with the invention, a method for carrying
out a burn-in process for electrically stressing semiconductor
memories. The method includes providing a memory having a circuit
configuration with a first voltage terminal, a second voltage
terminal, a control input, and a MOS transistor. A reference-ground
potential is applied to the first voltage terminal. A second
voltage is applied to the second voltage terminal and a control
voltage is applied to the control input, and the control voltage is
then varied.
[0006] The mechanism on which the burn-in process according to the
invention is based is dynamic stressing of a MOS transistor. In
order to stress a MOS transistor, e.g. its source terminal is
applied to a reference-ground potential, its drain terminal is
applied to an operating voltage and its gate terminal is applied to
an alternating voltage, which assumes values between the
reference-ground potential and the operating voltage. The voltage
at the drain terminal is chosen e.g. to be greater than the voltage
at the gate terminal. Under these stress conditions, the properties
of a transistor change as much in a few hours as in two years
during normal operation. As a result, its input voltage is
stabilized and remains constant during normal operation in the
memory during its expected 10-year operating life for the customer.
It is advantageous that a transistor in the memory circuit
periphery which is changed by stress can be identified as early as
during the test phase, so that the defective memory is not supplied
as a product. Under the action of stress, for example the threshold
voltage of the transistor is changed and stabilized. Combinational
blocks containing transistors are disposed in the circuit
periphery.
[0007] In a development of the method according to the invention,
the control voltage assumes voltage values which alternate between
the reference-ground potential and an operating voltage.
Accelerated aging of the circuit configuration is achieved by this
procedure.
[0008] A further mode of the method according to the invention
provides for the circuit configuration to contain an inverter. The
control voltage is applied to an inverter input, the
reference-ground potential is applied to a first inverter voltage
supply and the second voltage is applied to a second inverter
voltage supply. The effect achieved by this configuration is that a
transistor to be stressed is disposed in the circuit configuration.
Furthermore, it is provided that the circuit configuration contains
an inverter. An inverter is the basic element of every CMOS circuit
and is also contained in the circuit periphery of a memory.
Moreover, logic functions such as AND, NAND, OR, NOR, XOR etc., are
contained in the circuit blocks.
[0009] In a development of the method according to the invention,
the second voltage assumes the value of the operating voltage. By
virtue of this configuration, the voltage difference between the
reference-ground potential and the operating voltage is dropped
across the circuit configuration.
[0010] An advantageous instance of the method according to the
invention provides for the second voltage present at the second
voltage terminal to alternate between the reference-ground
potential and the operating voltage. The alternation of the second
voltage increases the stress for the circuit configuration, so that
the stressing time can be reduced and the same stress effect is
achieved in a shorter time.
[0011] A development of the method according to the invention
provides for the second voltage to alternate at a first frequency
and the control voltage to alternate at a second frequency between
the reference-ground potential and the operating voltage. The
periodic alternation of the second voltage and control voltage at a
fixed frequency in each case enables a simple circuitry realization
of a configuration for carrying out a burn-in process.
[0012] An advantageous mode of the method according to the
invention provides for the first frequency to be equal to the
second frequency, and the two voltages to have a phase difference
of between 150 and 210 degrees. A phase difference of 180 degrees
results in that the two signals are exactly in antiphase. The
tolerance range of between 150 and 210 degrees phase shift enables
variation of the phase shift in the specified range, which results
in a wide variety of stress configurations for the circuit
configuration. A further advantageous configuration of the method
according to the invention provides for the phase difference to be
varied. A great variety of configurations of the operating voltage
and the control voltage can be generated through the variation of
the phase difference. As a result, the stress of the circuit
configuration is increased further, which reduces the time for the
burn-in process.
[0013] Other features which are considered as characteristic for
the invention are set forth in the appended claims.
[0014] Although the invention is illustrated and described herein
as embodied in a method for carrying out a burn-in process for
electrically stressing a semiconductor memory, it is nevertheless
not intended to be limited to the details shown, since various
modifications and structural changes may be made therein without
departing from the spirit of the invention and within the scope and
range of equivalents of the claims.
[0015] The construction and method of operation of the invention,
however, together with additional objects and advantages thereof
will be best understood from the following description of specific
embodiments when read in connection with the accompanying
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a diagram of a voltage profile according to the
invention;
[0017] FIG. 2 is a diagram of another voltage profile;
[0018] FIG. 3 is a diagram of a further voltage profile;
[0019] FIG. 4 is a block diagram of a circuit configuration having
voltage supply terminals;
[0020] FIG. 5 is a graph of a family of input characteristic curves
of a P-channel transistor before it is stressed;
[0021] FIG. 6 is a graph of the family of input characteristic
curves of the P-channel transistor after it ha been stressed;
and
[0022] FIG. 7 is a graph showing a change in the threshold voltage
under the action of stress over time.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0023] In all the figures of the drawing, sub-features and integral
parts that correspond to one another bear the same reference symbol
in each case. Referring now to the figures of the drawing in detail
and first, particularly, to FIG. 4 thereof, there is shown a
circuit configuration 1 having a first voltage terminal 2, a second
voltage terminal 3 and a control input 4. The circuit configuration
1 is part of a memory circuit. In the circuit configuration 1 there
is a logic block 25, containing e.g. a MOS transistor or a CMOS
inverter. Voltage profiles are described below which are suitable
for stressing the circuit configuration 1 and thus allowing it to
be prematurely aged in order that the circuit configuration 1
adopts a constant behavior.
[0024] In FIG. 1, time is represented on the abscissa and voltage
is represented on the ordinate. Also shown are the profile of a
reference-ground potential 5, the profile of an operating voltage
8, the profile of a second voltage 6, which is identical to the
profile of the operating voltage 8, and the profile of a control
voltage 7. In this exemplary embodiment, the control voltage 7
alternates between the reference-ground potential 5 and the
operating voltage 8. In order to stress the circuit configuration 1
with the voltage profile from FIG. 1, for example the first voltage
terminal 2 is connected to the reference-ground potential 5, the
second voltage terminal 3 is connected to the second voltage 6, and
the control input 4 is connected to the control voltage 7. Usually,
the magnitude of the voltages is chosen such that the components
encompassed by the circuit configuration 1 experience an aging
process but are not directly destroyed by over-voltages.
[0025] FIG. 2 illustrates a further exemplary embodiment of a
voltage profile according to the invention. The difference from
FIG. 1 is that, in FIG. 2, the second voltage 6 is not kept
constant at the value of the operating voltage 8, but rather
alternates between the reference-ground potential 5 and the
operating voltage 8. In this case, the second voltage 6 oscillates
at a first frequency 9 and the control voltage 7 oscillates at a
second frequency 10. In this exemplary embodiment, the two
frequencies are identical but the corresponding voltages have a
phase shift of about 180 degrees. As a result, the second voltage 6
reaches a high voltage value when the control voltage 7 assumes a
low voltage value, and vice versa. The aging process of the circuit
configuration 1 is accelerated by this procedure.
[0026] FIG. 3 illustrates a further exemplary embodiment of a
voltage profile according to the invention. In contrast to FIG. 2,
in FIG. 3 the phase angle of the second voltage 6 and of the
control voltage 7 is not constant at 180 degrees, but rather can be
varied in a range of .+-.30 degrees. The stress on the circuit
configuration 1 is increased further through the variation of the
phase angle, so that the time required for accelerated aging
(burn-in) of the circuit configuration 1 can advantageously be
reduced.
[0027] FIG. 5 shows a family of input characteristic curves of a
P-channel transistor that was recorded directly after the
production of the P-channel transistor. The five characteristic
curves illustrated are associated with different source-drain
voltages, where the bottom most characteristic curve can be
assigned to the lowest source-drain voltage and the top most
characteristic curve can be assigned to the highest source-drain
voltage. It can be seen that the transistor exhibits a good
turn-off behavior with 10.sup.-11 ampere even at high source-drain
voltages.
[0028] FIG. 6 illustrates the family of input characteristic curves
of the transistor disclosed in FIG. 5 after the burn-in process
according to the invention. It can clearly be seen that the
turn-off behavior is no longer very good at high source-drain
voltages since the source-drain currents of 10.sup.-7 ampere flow,
which is a factor of 10,000 greater than before the burn-in
process.
[0029] With regard to FIG. 7, the variation of the threshold
voltage is represented against time. It can clearly be seen that
the threshold voltage decreases over the course of time and is
stabilized.
[0030] The functional principle consists in the fact that a
frequency present in the memory switches the transistors of the
circuit on and off. In this case, gate and drain terminals of the
transistors are connected via contacts to the voltage that is
generated on the memory chip and is pulsed at the frequency.
[0031] Furthermore, it is advantageous to apply a temperature
gradient during the electrical stress phase to the memory, in order
to shorten the stress phase.
* * * * *