U.S. patent application number 09/814176 was filed with the patent office on 2001-10-25 for analog/digital pwm control circuit of a winding.
This patent application is currently assigned to STMicroelectronics S.r.I.. Invention is credited to Galbiati, Ezio, Nessi, Maurizio, Palestra, Marco.
Application Number | 20010033504 09/814176 |
Document ID | / |
Family ID | 8175257 |
Filed Date | 2001-10-25 |
United States Patent
Application |
20010033504 |
Kind Code |
A1 |
Galbiati, Ezio ; et
al. |
October 25, 2001 |
Analog/digital PWM control circuit of a winding
Abstract
A feedback control circuit is for the current in a load formed
by a winding in series with a current sensing resistor, coupled to
a full-bridge output stage, an amplifier coupled to the terminals
of the sensing resistor, and a controller fed with the output of
the amplifier and with a voltage reference and producing a
correction signal. The circuit has a PWM converter for generating a
pair of control signals. The PWM converter includes an up/down
counter producing a count value and logic circuitry that produces
the twos-complement of the correction signal. A pair of registers
are coupled to the outputs of the controller and of the logic
circuitry. A first comparator coupled to the outputs of the counter
and of the first register produces the first control signal, if the
count signal exceeds the value stored in the first register. A
second comparator coupled to the counter and to the second register
produces the second control signal, if the count signal overcomes
the value stored in the second register.
Inventors: |
Galbiati, Ezio; (Agnadello,
IT) ; Nessi, Maurizio; (Como, IT) ; Palestra,
Marco; (Bergamo, IT) |
Correspondence
Address: |
CHRISTOPHER F. REGAN
Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
P.O. Box 3791
Orlando
FL
32802-3791
US
|
Assignee: |
STMicroelectronics S.r.I.
Agrate Brianza
IT
|
Family ID: |
8175257 |
Appl. No.: |
09/814176 |
Filed: |
March 21, 2001 |
Current U.S.
Class: |
363/98 |
Current CPC
Class: |
H02M 7/53873
20130101 |
Class at
Publication: |
363/98 |
International
Class: |
H02M 003/24 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 23, 2000 |
EP |
00830225.9 |
Claims
That which is claimed is:
1. A feedback control circuit of the current flowing in a load
constituted by a winding in series to a current sensing resistor,
comprising a full-bridge stage, driven by a pair of control signals
first (In+) and second (In-), coupled to the current terminals of
said load, an amplifier (Sense_Ampl) having a noninverting input
and an inverting input respectively coupled to the terminals of
said sensing resistor, producing an amplified replica voltage
(Vsense) of the voltage drop on said sensing resistor, a controller
(Controllore) coupled to the output of said amplifier and to a
voltage reference from outside (Vin) representing a desired value
of the current in the load, producing a correction signal, a PWM
converter coupled to the output of said controller and to a clock
signal (sys_clk), generating said pair of control signals (In+,
In-), characterized in that said PWM converter comprises an up/down
counter coupled to said clock signal (sys_clk), producing a count
value; a logic circuitry coupled to the output of said controller,
producing a signal that is the complement to two of said correction
signal; a pair of registers first (D_In+) and second (D_In-)
respectively coupled to the outputs of said controller and of said
circuitry; a first comparator (comp.sub.--1) coupled to the outputs
of said counter and of said first register (D_In+), producing said
first control signal (In+) if said count value exceeds the value
stored in the first register (D_In+); a second comparator
(comp.sub.--2) coupled to the outputs of said counter and of said
second register (D_In-), producing said second control signal (In-)
if said count value exceeds the value stored in the second register
(D_In-).
2. The circuit of claim 1 wherein said controller is constituted by
an adder coupled to said voltage reference (Vin) and to the output
of said amplifier (Sense_Ampl), producing an error signal (err), a
correction filter coupled to the output of said adder, producing
said correction signal.
3. The circuit of claim 2, wherein said counter produces an enable
flag (ADstart) each time it attains the top value or the bottom
value of the count and includes an integrator coupled to the output
of said adder producing an intermediate signal (Err_Out), an
analog/digital converter enabled by said enable flag (ADstart) and
coupled to the output of said integrator, producing said correction
signal.
4. The circuit according to claim 2, wherein said counter produces
an enable flag (ADstart) each time it attains the top value or the
bottom value of the count, said controller comprises an
analog/digital converter enabled by said enable flag (ADstart),
coupled to the output of said amplifier (Sense_Ampl) and providing
to said adder a datum (A/Dout) representing said amplified replica
voltage (Vsense), said correction filter is an infinite impulse
response digital filter (IIR).
Description
FIELD OF THE INVENTION
[0001] The present invention relates to the field of pulse width
modulation (PWM), and, more particularly, to a circuit for
controlling the current flowing in a winding driven in PWM mode
through a full-bridge stage.
BACKGROUND OF THE INVENTION
[0002] In a PWM switching regulator, a square wave drives the
control terminal of a switch of a full-bridge stage determining its
ON or off state. Alternating conduction states to nonconduction
states, the load driven by the full-bridge stage will be either
crossed by a current or not whose mean value during a turn-on and a
turn-off phase can be controlled by varying the duty cycle of the
driving square wave.
[0003] A particularly effective method of controlling a full-bridge
is the one disclosed in U.S. Pat. No. 5,917,720 issued to the same
assignee. A block diagram of a circuit implementing the method,
including by a control loop of the PWM driver at a constant
frequency, is depicted in FIG. 1. The point of interest of this
method is that the current flowing in the load is controlled by
varying the respective duty cycle of the two outputs OUT+ and OUT-
of the power stage Power_Ampl. By increasing the duty cycle of the
output OUT+ and by decreasing the duty cycle of the output OUT- or
vice versa, a current having direction and intensity that depend on
the difference between the duty cycles of the outputs is forced in
the load.
[0004] The current is controlled by detecting the voltage drop on a
current sensing resistance connected in series to the winding to be
controlled, amplifying this voltage drop with an operational
amplifier Sense_Ampl that produces a feedback voltage, and closing
the feedback loop with the amplifier Error_Ampl, that compares the
feedback voltage with a reference value representing the desired
current value. The output Err_Out of the amplifier Error_Ampl is
compared with two reference triangular wave signals Tria1 and Tria2
of opposite phases thus generating the two driving signals In+ and
In- of the power stage.
[0005] An important aspect of such a system is that the two signals
Tria1 and Tria2 of opposite phase must be precisely generated with
the same amplitude and with a mean value equal to the reference
voltage Vref to which the Sense_Ampl and the Error_Ampl are
referred. This is not easy to achieve because of the offset of the
operational amplifiers that make the generation of the two
triangular wave oscillating signals critical and very often the two
signals are not perfectly symmetrical and do not have the same mean
value Vref.
[0006] This results in a degradation of the performance of the
current control when operating at low currents and particularly
when controlling at null current. In fact in that situation, by
setting the input voltage Vctl equal to the reference voltage Vref,
the output Err_Out of the Error_Ampl tends to equal Vref. However,
because of asymmetries and unbalances of the two triangular wave
references, the two driving signals of the power stage In+ and In-
do not result perfectly in phase and do not have the same duty
cycle and so the differential voltage applied to the load is not
null, but assumes a value proportional to the difference between
the two triangular wave voltage references.
[0007] It is evident that there is a need for a PWM current control
circuit that prevents such a degradation of the control at a
relatively low level of current in the load.
SUMMARY OF THE INVENTION
[0008] It is an object of the present invention to provide a partly
analog and partly digital circuit controlling, through a feedback
loop, the current flowing in a winding of an induction machine,
such as a DC motor or a Voice Coil Motor, that overcomes the
drawback of known circuits. The current flowing in the load is
delivered by a full-bridge stage driven by a PWM digital
converter.
[0009] More precisely, the invention includes a feedback control
circuit of the current flowing in a load formed by a winding in
series to a current sensing resistor. The circuit comprises an
output full-bridge stage, driven by a pair of first and second
control signals. The circuit may also include an amplifier having a
noninverting and an inverting input respectively coupled to the
terminals of the current sensing resistor for producing an
amplified replica of the voltage drop on the sensing resistor. The
circuit may also include a controller coupled to the output of the
amplifier and to a reference voltage representing a desired value
of the current in the load for producing a correction signal. In
addition, the circuit may include a PWM converter coupled to the
output of the controller and to a clock signal for generating the
pair of control signals.
[0010] The point of interest of the control circuit of the
invention includes the structure of the PWM converter that
comprises an up/down counter fed with the clock signal, producing a
certain count, combinatory logic circuitry coupled to the output of
the controller producing a signal that is the twos-complement of
the correction signal, and a pair of first and second registers
coupled to the outputs of the controller and of the combinatory
logic circuitry, respectively. Also, a first comparator is coupled
to the outputs of the counter and of the first register for
producing the first control signal if the count exceeds the value
stored in the first register. A second comparator is coupled to the
counter and to the second register for producing the second control
signal if the count overcomes the value stored in the second
register. According to a preferred embodiment of the invention the
controller can be realized by an adder coupled to the reference
voltage and to the output of the amplifier producing an error
signal, and a correction filter coupled to the output of the adder,
producing the correction signal.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The different aspects and advantages of the invention will
become clearer through the following detailed description and by
referring to the attached drawings wherein:
[0012] FIG. 1 is a schematic block diagram of a current control
loop according to the prior art;
[0013] FIG. 2 is a schematic block diagram of the current control
loop in accordance with the invention;
[0014] FIG. 3 is a schematic block diagram of the PWM Converter of
FIG. 2;
[0015] FIG. 4 is a waveform diagram showing the waveforms of
operation of the PWM Converter;
[0016] FIG. 5 is another waveform diagram showing the waveforms of
operation of the PWM Converter; and
[0017] FIG. 6 is a schematic block diagram of an alternative
embodiment of the current control loop in accordance with the
invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0018] The present invention is directed to a PWM current control
circuit that overcomes the mentioned problem of lack of precision
when controlling driving, at minimum or null value, of the current
flowing in the load caused by asymmetry and unbalances between the
two triangular wave references.
[0019] A block diagram of an embodiment of the mixed analog/digital
circuit of the invention is depicted in FIG. 2. The use of analog
circuits together with digital circuits becomes very convenient
because it makes possible the realization of a system that is
perfectly compatible with the systems used at present wherein the
driving voltage interface is an analog circuit, and to obtain an
improved precision and ruggedness in generating the driving signals
for the power stage. In fact the generation of these signals is
done by a digital circuit that is practically exempt from the above
mentioned asymmetry and unbalance problems.
[0020] The purely analog part of the circuit includes the sensing
amplifier Sense_Ampl and the error amplifier Error_Ampl. The
Sense_Ampl detects the current flowing in the load and the sensing
resistor Rs producing an amplified voltage that is fedback and
compared with the input voltage Vin, representing the desired value
of the current to be forced in the winding.
[0021] The error signal resulting from the comparison is amplified
by the Error_Ampl that also guarantees stability and a reduction of
the high frequency components via the compensation network Rc and
Cc. In this way, a quality detection of the current in the load and
an outstanding precision in controlling the current is obtained
while using the same analog interface with the driving voltage Vin
as in known circuits.
[0022] The analog to digital converter A/D, which in FIG. 2 is
depicted as an N bit converter, couples the analog part with the
digital part of the current control loop. In the example
considered, N is equal to 8 and so the output of the A/D converter
is an integer number between 0 and 255. Of course, N may also be
different from 8. The input dynamic of the A/D converter is
established by the two references maximum Vxx+ and minimum Vxx- and
is centered on the value of Vref. In this way, if the output of the
Error_Ampl is equal to Vref, the output of the A/D converter is
equal to 128. If the output of the Error_Ampl is equal to or lower
than Vxx-, the output of the A/D converter is equal to 0. While if
the output of the Error_Ampl is equal to or greater than Vxx+, the
output of the A/D converter is equal to 255.
[0023] The digital conversion of the output voltage of the
Error_Ampl is carried out in a synchronous manner in respect to the
switching of the output stage and is commanded by the enable signal
ADstart produced by the PWM_Converter.
[0024] A block diagram of the PWM_Converter of the circuit of the
invention is depicted in FIG. 3. It comprises two registers D_In+
and D_In-, whereby the value ADout produced by the A/D converter is
written in the first register and the twos-complement of the
bit-string representing the value is written in the second
register, an up/down counter Up/Dn_Counter and two digital
comparators Comp1 and Comp2. The counter and the comparators are of
8 bits in this example.
[0025] The counter Up/Dn_Counter is increased and/or decreased at
the rate of a system clock signal SysClk, determining with a
complete up and down count cycle the switching frequency of the
current in the load. The data ADout is complemented to two by
producing a complement signal which, summed to ADout, provides a
value equal to the number of states of the counter. In such a way,
the digital comparators Comp1 and Comp2 will produce two signals
having complementary duty cycles, i.e. duty cycles whose sum is
equal to 1. It is important that such a condition be verified to
make the difference between the duty cycles of In+ and In-, that
determines the intensity of the current forced in the load, vary in
the broadest possible range, i.e. between -1 and +1.
[0026] The contents of the two registers D_In+ and D_In- are
compared with the output of the Up/Dn_Counter by the digital
comparator Comp1 and by the digital comparator Comp2, respectively.
The control signals In+ and In- of the comparators are respectively
active when the value stored in D_In+ or in D_In- are equal to or
greater than the output of the counter. The enabling signal of the
analog/digital conversion is generated by the PWM_Converter, for
example, each time the Up/Dn_Counter attains the values 0 and 255,
or when it assumes the value of 128 or even in both cases.
[0027] Such a choice depends on the desired sampling frequency and
on the conversion speed of the A/D that is used. The case in which
the enable signal ADstart is generated when the output of the
Up/Dn_Counter is equal to 0 or 255, will be considered by way of
example. If the Error_Ampl produces a voltage Err_Out whose value
is converted in the digital number ADout=128, then the
PWM_Converter generates two signals In+ and In- having the same
phase and duty cycle equal to 50%, because the registers D_In+ and
D_In- will contain the same value. In fact if ADout=128, the two
registers D_In+ and D_In- will contain the same value so that the
comparators Comp1 and Comp2 generate the same result In+ and In-
identical having the same phase and duty cycle equal to 50%.
[0028] It is clear that in such a condition the current in the load
is null because the two branches of the full-bridge output stage
are driven by two signals with the same phase and the same duty
cycle, so even if the current terminal OUT+ and OUT- of the load
are continuously switched from GND to the supply voltage Vp, across
the load the potential difference is null. Should a current be
forced in the load, from OUT+ to OUT-, the input data Vin must be
greater than Vref and as a consequence, when the control loop
reaches a stable condition, the output of the Error_Ampl assumes a
value greater than Vref.
[0029] The digital conversion of the output of the Error_Ampl
produces a number between 128 and 255, for example 150. The
PWM_Converter stores this data in the register D_In+, while the
value 106 (i.e. the complement to two of the 8 bits string
representing the number 150) is stored in the register D_In-. The
comparators Comp1 and Comp2 compare the content of the registers
D_In+ and D_In- with the output of the counter Up/Dn_Counter
generating a signal In+ with duty cycle greater than 50% and a
signal In- with duty cycle lower than 50% respectively, as depicted
in FIG. 4. On the contrary, should a current be forced in the load,
from OUT- to OUT+, the input data Vin must be lower than Vref and
as a consequence, when the control loop reaches a stable condition,
the output of the Error_Ampl assumes a value lower than Vref.
[0030] The digital conversion of the output of the Error_Ampl
produces a number between 0 or 128, for example 30. The
PWM_Converter stores this data in the register D_In+, while the
value 226 (i.e. the twos-complement of the 8 bit string
representing the number 30) is stored in the register D_In-. The
comparators Comp1 and Comp2 compare the content of the registers
D_In+ and D_In- with the output of the Up/Dn_Counter generating a
signal In+ with duty cycle lower than 50% and a signal In- with
duty cycle greater than 50%, respectively, as depicted in FIG.
5.
[0031] In both cases it is possible to note that the enable signal
of the A/D converter is synchronous with the peaks of the
triangular wave produced by the Up/Dn_Counter. Therefore, the
digital conversion of the output of the Error_Ampl is carried out
in the middle of the free-wheeling phase of the current in the
load, when both the outputs OUT+ and OUT- are coupled to GND or to
Vp.
[0032] The block diagram of another embodiment of the PWM current
control circuit of the invention, is different from the one of FIG.
2 because it is almost completely digital. According to this
alternative embodiment, the analog/digital conversion is carried
out at the output of the Sense_Ampl, producing a feedback signal of
the control loop in digital form that allows a digital embodiment
of the controller.
[0033] The input datum Digital_Vin, representing the value of the
desired current in the load, is in digital form and is fed together
with the feedback signal to the Controller. The controller may be
realized by hard wired logic and provides for summation
amplification and filtering of the error signal Err with a certain
transfer function F(z) satisfying the bandwidth constraint and
ensuring stability to the current control loop.
[0034] At each sampling of the voltage produced by the Sense_Ampl,
determined by the signal ADstart, the controller calculates the
error signal Err as the difference between the input datum
Digital_Vin indicating the current to be forced in the load and the
feedback datum Adout, thereby producing by the filter F(z) the
desired correction signal. A generic digital filter F(z) can be
described by the following polynomial:
y.sub.n=a.sub.0x.sub.n+a.sub.1x.sub.n-1+ . . .
+b.sub.1y.sub.n-1+b.sub.2y.- sub.n-2+ . . .
[0035] wherein x.sub.i is the i-th input, y.sub.i is the i-th
output and the dots indicate that there are other terms that depend
on the order of the filter.
[0036] The calculation of a filter generally needs M+N+1 products,
where M is the order of the numerator and N the order of the
denominator of the transfer function, and M+N sums. This must be
considered when designing the filter because, when the adder has
produced the error value Err, the filter F(z) must be able to
complete its computations before the next ADstart signal.
[0037] Once the coefficients, and the signals and have been
quantized, the filter is calculated with an infinite precision.
Therefore, in designing the filter it is necessary to avoid
internal saturations and thus provide a sufficiently high number of
bits for each internal signal. In particular it is more convenient
to assign to the coefficients of the filter, a sufficiently high
number of bits to prevent the calculation of the filter from
introducing an excessive quantization noise.
[0038] According to a preferred embodiment of the invention, the
filter F(z) is an IIR filter of the first order, whose transfer
function is: 1 H ( z ) = a 0 z + a 1 b 0 z + b 1
[0039] Depending on the desired performances in terms of bandwidth
and phase margin of the current control loop, the order of the
filter can be changed.
* * * * *