U.S. patent application number 09/844952 was filed with the patent office on 2001-10-04 for integrated circuit having an on-board reference generator.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Manning, Troy.
Application Number | 20010026477 09/844952 |
Document ID | / |
Family ID | 22878641 |
Filed Date | 2001-10-04 |
United States Patent
Application |
20010026477 |
Kind Code |
A1 |
Manning, Troy |
October 4, 2001 |
Integrated circuit having an on-board reference generator
Abstract
An integrated circuit includes a differential amplifier having a
first terminal that is operable to receive an input signal and
having a second terminal. The integrated circuit also includes a
reference circuit that generates a reference signal on the second
terminal of the amplifier. During testing of the integrated
circuit, the reference circuit can be activated to generate the
reference signal such that a tester need not supply it as a test
signal. During normal operation, however, either the reference
circuit can generate the reference signal or the reference signal
can be supplied by an external source.
Inventors: |
Manning, Troy; (Meridian,
ID) |
Correspondence
Address: |
Bryan A. Santarelli
GRAYBEAL JACKSON HALEY LLP
155 - 108th Avenue NE, Suite 350
Bellevue
WA
98004-5901
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
22878641 |
Appl. No.: |
09/844952 |
Filed: |
April 27, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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09844952 |
Apr 27, 2001 |
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09233774 |
Jan 19, 1999 |
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Current U.S.
Class: |
365/189.09 ;
365/201 |
Current CPC
Class: |
G11C 29/12 20130101 |
Class at
Publication: |
365/189.09 ;
365/201; 365/233 |
International
Class: |
G11C 007/14; G11C
029/00 |
Claims
What is claimed:
1. An integrated circuit, comprising: a differential amplifier
having a first terminal operable to receive an input signal and
having a second terminal; and a reference circuit coupled to the
amplifier and operable to generate a first reference signal on the
second terminal.
2. The integrated circuit of claim 1, further comprising an
integrated-circuit terminal coupled to the second terminal of the
amplifier and operable to receive a second reference signal.
3. The integrated circuit of claim 1 wherein the reference circuit
is operable to generate the first reference signal during a test
mode of operation.
4. The integrated circuit of claim 1 wherein the first reference
signal comprises a reference voltage.
5. The integrated circuit of claim 1, further comprising: an
integrated-circuit terminal operable to receive a second reference
signal; and a buffer circuit coupled to the integrated-circuit
terminal, the amplifier, and the reference circuit, the buffer
circuit operable to couple the integrated-circuit terminal to the
second terminal of the amplifier during a first mode of operation
and to uncouple the integrated-circuit terminal from the second
terminal of the amplifier during a second mode of operation.
6. The integrated circuit of claim 1, further comprising: an
integrated-circuit terminal operable to receive a second reference
signal; and a buffer circuit coupled to the integrated-circuit
terminal, the amplifier, and the reference circuit, the buffer
circuit operable to uncouple the integrated-circuit terminal from
the second terminal of the amplifier during a test mode of
operation and to couple the integrated-circuit terminal to the
second terminal of the amplifier during a nontest mode of
operation.
7. The integrated circuit of claim 1, further comprising: wherein
the first reference signal has a first magnitude; an
integrated-circuit terminal operable to receive a second reference
signal having a second magnitude that approximately equals the
first magnitude; and a buffer circuit coupled to the
integrated-circuit terminal, the amplifier, and the reference
circuit, the buffer circuit operable to couple the
integrated-circuit terminal to the second terminal of the amplifier
during a first mode of operation and to uncouple the
integrated-circuit terminal from the second terminal of the
amplifier during a second mode of operation.
8. The integrated circuit of claim 1, further comprising: first and
second power-supply terminals; and wherein the reference circuit
comprises: a load coupled to the first supply terminal; a switch
serially coupled to the load and operable to enable the reference
circuit when closed and disable the reference circuit when open;
and a diode serially coupled between the switch and the second
supply terminal.
9. An integrated circuit, comprising: a differential amplifier
having first and second input terminals; and a reference-signal
generator having a reference-signal output terminal coupled to the
second input terminal of the amplifier.
10. The integrated circuit of claim 9, further comprising a
reference-signal terminal coupled to the second input terminal of
the amplifier.
11. The integrated circuit of claim 9, further comprising: a
reference-signal terminal; and a buffer having a first input
terminal coupled to the reference-signal terminal and an output
terminal coupled to the second terminal of the amplifier.
12. An integrated circuit, comprising: a conductive reference pad
operable to receive a first reference signal; a circuit having a
first input terminal coupled to the reference pad; and a reference
circuit coupled to the circuit and operable to generate a second
reference signal on the first input terminal.
13. The integrated circuit of claim 12 wherein: the first reference
signal has a first magnitude; and the second reference signal has a
second magnitude that is approximately equal to the first
magnitude.
14. The integrated circuit of claim 12, further comprising: a
conductive input pad operable to receive an input signal; and
wherein the circuit has a second input terminal coupled to the
input pad.
15. The integrated circuit of claim 12 wherein the circuit further
comprises: a second input terminal operable to receive an input
signal; and a differential amplifier having first and second input
terminals respectively coupled to the first and second input
terminals of the circuit.
16. The integrated circuit of claim 12, further comprising: a logic
circuit operable to receive a mode input signal, to generate a mode
output signal having a first value if the mode input signal
identifies a first mode of operation, and to generate the mode
output signal having a second value if the mode input signal
identifies a second mode of operation; and a buffer circuit coupled
to the logic circuit and between the reference pad and the circuit,
the buffer circuit operable to couple the first reference signal to
the first input terminal of the circuit if the mode output signal
has the first value and to uncouple the first reference signal from
the first input terminal of the circuit if the mode output signal
has the second value.
17. The integrated circuit of claim 12, further comprising: a
conductive mode pad operable to receive a mode input signal; a
logic circuit coupled to the mode pad and operable to generate a
mode output signal having a first value if the mode input signal
indicates a first mode of operation and to generate the mode output
signal having a second value if the mode input signal indicates a
second mode of operation; and a buffer circuit coupled to the logic
circuit and between the reference pad and the circuit, the buffer
circuit operable to couple the first reference signal to the first
input terminal of the circuit if the mode output signal has the
first value and to uncoupled the first reference signal from the
first input terminal of the circuit if the mode output signal has
the second value.
18. The integrated circuit of claim 12 wherein the circuit
comprises a clock input terminal operable to receive a clock
signal.
19. An integrated circuit, comprising: a conductive reference pad;
a circuit having a first input terminal coupled to the reference
pad; and a reference-signal generator having an output terminal
coupled to the first input terminal of the circuit.
20. The integrated circuit of claim 19, further comprising: a
conductive input pad; and wherein the circuit has a second input
terminal coupled to the conductive input pad.
21. The integrated circuit of claim 19, further comprising: a
mode-selection circuit having a mode output terminal; and a buffer
coupled between the reference pad and the circuit, the buffer
having a control terminal coupled to the mode output terminal, a
first input terminal coupled to the reference pad, and an output
terminal coupled to the first input terminal of the circuit.
22. The integrated circuit of claim 19, further comprising: a
conductive mode pad; a mode-selection circuit having an input
terminal coupled to the mode pad and having a mode output terminal;
and a buffer coupled between the reference pad and the circuit, the
buffer having a control terminal coupled to the mode output
terminal, an input terminal coupled to the reference pad, and an
output terminal coupled to the first input terminal of the
circuit.
23. The integrated circuit of claim 19 wherein the circuit further
comprises: a second input terminal; and a differential amplifier
having a first and second input terminals respectively coupled to
the first and second input terminals of the circuit.
24. An integrated circuit, comprising: a package; a
reference-signal terminal accessible from outside of the package
and operable to receive a first reference signal; a circuit
disposed inside of the package and having a first input terminal
coupled to the reference-signal terminal; and a reference circuit
disposed inside of the package, coupled to the circuit, and
operable to generate a second reference signal on the first input
terminal of the circuit.
25. The integrated circuit of claim 24 wherein the circuit
comprises: a second input terminal operable to receive an input
signal; and a differential amplifier having first and second input
terminals respectively coupled to the first and second input
terminals of the circuit.
26. The integrated circuit of claim 24, further comprising: an
input-signal terminal accessible from outside of the package and
operable to receive an input signal; and wherein the circuit
comprises a second input terminal coupled to the input-signal
terminal.
27. The integrated circuit of claim 24, further comprising: a
conductive mode terminal accessible from outside the package and
operable to receive a mode input signal; a logic circuit disposed
within the package, coupled to the mode terminal, and operable to
generate a mode output signal having a first value if the mode
input signal indicates a first mode of operation and to generate
the mode output signal having a second value if the mode input
signal indicates a second mode of operation; and a buffer circuit
disposed within the package, coupled to the logic circuit, coupled
between the reference-signal terminal and the circuit, and operable
to couple the reference-signal terminal to the first input terminal
of the circuit if the mode output signal has the first value and to
uncouple the reference-signal terminal from the first input
terminal of the circuit if the mode output signal has the second
value.
28. The integrated circuit of claim 24, further comprising: a
clock-signal terminal accessible from outside of the package and
operable to receive a clock signal; an input-signal terminal
accessible from outside of the package and operable to receive an
input signal; and wherein the circuit comprises: a second input
terminal coupled to the input-signal terminal; a clock input
terminal coupled to the clock-signal terminal; and a differential
amplifier having a first, second, and clock input terminals
respectively coupled to the first, second, and clock input
terminals of the circuit.
29. An integrated circuit, comprising: a package; a
reference-signal terminal accessible from outside of the package; a
circuit disposed inside of the package and having a first input
terminal coupled to the reference-signal terminal; and a
reference-signal generator disposed inside of the package and
having an output terminal coupled to the first input terminal of
the circuit.
30. The integrated circuit of claim 29, further comprising: an
input-signal terminal accessible from outside of the package; and
wherein the circuit comprises a second input terminal coupled to
the input-signal terminal.
31. The integrated circuit of claim 29, further comprising: a
conductive mode terminal accessible from outside the package; a
mode-select circuit disposed within the package and having an
output terminal; and a buffer disposed within the package, coupled
between the reference-signal terminal and the circuit, and having a
control terminal coupled to the output terminal of the mode-select
circuit, an input terminal coupled to the reference-signal
terminal, and an output terminal coupled to the first input
terminal of the circuit.
32. The integrated circuit of claim 29, further comprising: a
clock-signal terminal accessible from outside of the package; an
input-signal terminal accessible from outside of the package; and
wherein the circuit comprises: a second input terminal coupled to
the input-signal terminal; a clock input terminal coupled to the
clock-signal terminal; and a differential amplifier having a first,
second, and clock input terminals respectively coupled to the
first, second, and clock input terminals of the circuit.
33. A memory circuit, comprising: a conductive reference-signal
pad; a conductive address-signal pad; a conductive data-signal pad;
an address decoder that includes a differential amplifier having a
first input terminal coupled to the reference-signal pad and having
a second input terminal coupled to the address-signal pad; a
reference-signal generator having an output terminal coupled to the
first input terminal of the amplifier; a memory array coupled to
the address decoder; and a read/write circuit coupled to the
data-signal pad and to the memory array.
34. A memory circuit, comprising: a conductive reference-signal
pad; a conductive data-signal pad; a conductive address-signal pad;
an address decoder coupled to the address-signal pad; a memory
array coupled to the address decoder; a read/write circuit coupled
to the memory array and including a differential amplifier having a
first input terminal coupled to the reference-signal pad and having
a second terminal coupled to the data-signal pad; and a
reference-signal generator having an output terminal coupled to the
first input terminal of the amplifier.
35. A memory circuit, comprising: a conductive reference-signal
pad; a conductive address-signal pad; a conductive data-signal pad;
a conductive control-signal pad; an address decoder coupled to the
address-signal pad; a memory array coupled to the address decoder;
a read/write circuit coupled to the data-signal pad and to the
memory array; a control circuit coupled to the address decoder, the
control circuit including a differential amplifier having a first
input terminal coupled to the reference-signal pad and having a
second terminal coupled to the control-signal pad; and a
reference-signal generator having an output terminal coupled to the
first terminal of the amplifier.
36. A memory circuit, comprising: a package; a reference-signal
terminal accessible from outside of the package; an address-signal
terminal accessible from outside of the package; a data-signal
terminal accessible from outside of the package; an address decoder
disposed within the package and including a differential amplifier
having a first input terminal coupled to the reference-signal
terminal and having a second input terminal coupled to the
address-signal terminal; a reference-signal generator disposed
within the package and having an output terminal coupled to the
first input terminal of the amplifier; a memory array disposed
within the package and coupled to the address decoder; and a
read/write circuit disposed within the package and coupled to the
data-signal terminal and to the memory array.
37. A memory circuit, comprising: a package; a reference-signal
terminal accessible from outside of the package; an address-signal
terminal accessible from outside of the package; a data-signal
terminal accessible from outside of the package; an address decoder
disposed within the package and coupled to the address-signal
terminal; a memory array disposed within the package and coupled to
the address decoder; a read/write circuit disposed within the
package, coupled to the memory array, and including a differential
amplifier having a first input terminal coupled to the
reference-signal terminal and having a second terminal coupled to
the data-signal terminal; and a reference-signal generator disposed
within the package and having an output terminal coupled to the
first input terminal of the amplifier.
38. A memory circuit, comprising: a package; a reference-signal
terminal accessible from outside of the package; an address-signal
terminal accessible from outside of the package; a data-signal
terminal accessible from outside of the package; a control-signal
terminal accessible from outside of the package; an address decoder
disposed within the package and coupled to the address-signal
terminal; a memory array disposed within the package and coupled to
the address decoder; a read/write circuit disposed within the
package and coupled to the data-signal terminal and to the memory
array; a control circuit disposed within the package and coupled to
the address decoder, the control circuit including a differential
amplifier having a first input terminal coupled to the
reference-signal terminal and having a second terminal coupled to
the control-signal terminal; and a reference-signal generator
disposed within the package and having an output terminal coupled
to the first terminal of the amplifier.
39. An electronic system, comprising: a data input device; a data
output device; and a computer circuit coupled to the data input and
output devices and including a processor and a memory circuit
coupled to the processor, the memory circuit including: a package;
a reference-signal terminal accessible from outside of the package;
an address-signal terminal accessible from outside of the package;
a data-signal terminal accessible from outside of the package; an
address decoder disposed within the package and including a
differential amplifier having a first input terminal coupled to the
reference-signal terminal and having a second input terminal
coupled to the address-signal terminal; a reference-signal
generator disposed within the package and having an output terminal
coupled to the first input terminal of the amplifier; a memory
array disposed within the package and coupled to the address
decoder; and a read/write circuit disposed within the package and
coupled to the data-signal terminal and to the memory array.
40. An electronic system, comprising: a data input device; a data
output device; and a computer circuit coupled to the data input and
output devices and including a processor and a memory circuit
coupled to the processor, the memory circuit including: a package;
a reference-signal terminal accessible from outside of the package;
an address-signal terminal accessible from outside of the package;
a data-signal terminal accessible from outside of the package; an
address decoder disposed within the package and coupled to the
address-signal terminal; a memory array disposed within the package
and coupled to the address decoder; a read/write circuit disposed
within the package, coupled to the memory array, and including a
differential amplifier having a first input terminal coupled to the
reference-signal terminal and having a second terminal coupled to
the data-signal terminal; and a reference-signal generator disposed
within the package and having an output terminal coupled to the
first input terminal of the amplifier.
41. An electronic system, comprising: a data input device; a data
output device; and a computer circuit coupled to the data input and
output devices and including a processor and a memory circuit
coupled to the processor, the memory circuit including: a package;
a reference-signal terminal accessible from outside of the package;
an address-signal terminal accessible from outside of the package;
a data-signal terminal accessible from outside of the package; a
control-signal terminal accessible from outside of the package; an
address decoder disposed within the package and coupled to the
address-signal terminal; a memory array disposed within the package
and coupled to the address decoder; a read/write circuit disposed
within the package and coupled to the data-signal terminal and to
the memory array; a control circuit disposed within the package and
coupled to the address decoder, the control circuit including a
differential amplifier having a first input terminal coupled to the
reference-signal terminal and having a second terminal coupled to
the control-signal terminal; and a reference-signal generator
disposed within the package and having an output terminal coupled
to the first terminal of the amplifier.
42. A method, comprising: internally generating a first reference
signal on a first terminal of a differential amplifier disposed in
an integrated circuit; and coupling an input signal to a second
terminal of the differential amplifier.
43. The method of claim 42 wherein the generating comprises
internally generating the first reference signal during a test mode
of the integrated circuit.
44. The method of claim 42, further comprising: wherein the
generating comprises coupling the first reference signal to the
first terminal of the amplifier during a first operational mode of
the integrated circuit; and coupling a second reference signal to
the first terminal of the amplifier during a second operational
mode of the integrated circuit.
45. A method, comprising: during a first time period, providing an
externally generated reference signal to a terminal of a circuit
disposed in an integrated circuit; and during a second time period,
providing an internally generated reference signal to the terminal
of the circuit.
46. The method of claim 45 wherein the circuit comprises a
differential amplifier having an input terminal coupled to the
terminal of the circuit.
47. The method of claim 45, further comprising generating the
internally generated reference signal with a reference circuit
disposed in the integrated circuit.
48. The method of claim 45, further comprising: operating the
integrated circuit in a first mode during the first time period;
and operating the integrated circuit in a second mode during the
second time period.
49. The method of claim 45, further comprising: operating the
integrated circuit in a nontest mode during the first time period;
and operating the integrated circuit in a test mode during the
second time period.
50. The method of claim 45 wherein the first time period does not
overlap the second time period.
Description
TECHNICAL FIELD
[0001] The invention relates generally to electronic circuits, and
more specifically to an integrated circuit (IC) having an on-board
reference generator. For example, if the generator is on-board a
memory circuit, one can activate the generator to provide an
internal reference signal during a test mode of the memory circuit,
and one can deactivate the generator to allow the memory circuit to
receive an external reference signal during normal operation.
BACKGROUND OF THE INVENTION
[0002] Because it is generally true that the fewer signals needed
to test an IC the higher and more efficient the testing throughput
for a batch of the ICs, IC design engineers strive to minimize the
number of signals needed to test an IC. For example, suppose that
an IC tester has sixty signal probes. If each of the ICs being
tested requires twenty test signals, then the tester can test three
ICs at a time. If, however, each of the ICs requires twenty one
test signals, then the tester can test only two ICs at a time. Thus
in this example, just one extra test signal per IC decreases the
testing throughput by one third. Furthermore, in the latter case,
the IC tester is significantly under utilized, and thus the testing
is relatively inefficient with respect to the tester, because
eighteen signal probes (60-42) are unused during each test
cycle.
[0003] FIG. 1 is a schematic diagram of a portion of a
reduced-signal-level dynamic random access memory (DRAM) circuit 10
such as a Direct Rambus.RTM. DRAM (RDRAM.RTM.) specified by Rambus
Inc. of Mountain View, Calif. The memory circuit 10 includes one or
more terminals 12.sub.0-12.sub.n for receiving digital signals
S.sub.0-S.sub.n, a reference terminal 14 for receiving a reference
voltage Vref, and clock terminals 16a and 16b for receiving
complimentary Clock From Master signals CFM and CFM, respectively.
Typically, Vref is half way between the logic 0 and logic 1 levels
of S.sub.0-S.sub.n to provide symmetrical noise margins. Also, CFM
and {overscore (CFM)} are typically derived from the rising and
falling edges, respectively, of a single Master Clock (MC) signal
(not shown) having a 50% duty cycle and the same frequency as CFM
and {overscore (CFM)}. In one embodiment, the signals
S.sub.0-S.sub.n have logic 0=1.8 volts (V) and logic 1=1.0V,
Vref=1.4V, and CFM and {overscore (CFM)} each have a frequency of
400 megahertz (MHz).
[0004] The memory circuit 10 also includes differential input
buffers 18.sub.0-18.sub.n and 20.sub.0-20.sub.n for converting the
voltage levels of S.sub.0-S.sub.n into voltage levels that are
compatible with the circuitry (not shown) internal to the memory
circuit 10. These buffers are arranged in pairs [18.sub.0,
20.sub.0], . . . ,[18.sub.n, 20.sub.n] for alternately sampling the
signals S.sub.0-S.sub.n, respectively. Specifically, each buffer 18
receives a respective signal S on a non-inverting (+) terminal,
Vref on an inverting (-) terminal, and CFM on a clock terminal 22.
Similarly, each buffer 20 receives a respective signal S on a
non-inverting terminal, Vref on an inverting terminal, and
{overscore (CFM)} on a clock terminal 24. Receiving the
complimentary CFM and {overscore (CFM)} signals instead of the MC
signal provides the memory circuit 10 with two major advantages.
First, although each buffer pair [18, 20] effectively samples a
respective signal S on both the rising and falling edges--and thus
at twice the frequency--of MC, each buffer of the pair operates at
only half this sampling rate. Furthermore, each buffer of the pair
is sensitive to the same clock-edge polarity, i.e., either rising
or falling, and thus all the buffers 18 and 20 can have the same
circuit design. Reducing the sampling rate of and using a single
design for the buffers 18 and 20 often reduces the overall design
and layout complexity of the memory circuit 10.
[0005] The memory circuit 10 also includes an IC package 21. The
terminals 12.sub.0-12.sub.n, 14, and 16a and 16b are disposed on
the outside of the package 21, and the buffers 18.sub.0-18.sub.n
and 20.sub.0-20.sub.n are disposed inside of the package 21.
[0006] In operation, using the input-buffer pair [18.sub.0,
20.sub.0] and the signal values given above as examples, the buffer
18.sub.0 samples S.sub.0 by comparing S.sub.0 to Vref in response
to the rising edge of CFM. If S.sub.0 equals logic 0, i.e., 1.8 V,
then the buffer 18.sub.0 generates a high output-voltage level,
which the circuitry internal to the memory circuit 10 interprets as
a logic 0. Conversely, if So equals logic 1, ie., 1.0 V, then the
buffer 18.sub.0 generates a low output-voltage level, which the
circuitry internal to the memory circuit 10 interprets as a logic
1. The buffer 200 samples S.sub.0 in response to the rising edge of
{overscore (CFM)} in a similar manner. The remaining input-buffer
pairs [18.sub.1, 20.sub.1], . . . ,[18.sub.n, 20.sub.n]
respectively sample S.sub.1-S.sub.n in a similar manner.
[0007] Specific examples of the memory circuit 10 are described in
more detail in the Advance Information sheet for the Direct
RDRAM.RTM. 128/144-Mbit (256 k.times.16/18.times.32 S) and in other
Rambus.RTM. publications, which are available from Rambus
Incorporated of Mountain View, Calif. or from the Rambus website at
www.rambus.com, and which are incorporated by reference herein.
[0008] Unfortunately, one must provide Vref to the terminal 14
during testing of the memory circuit 10 so that the differential
input buffers 18 and 20 will function properly. Thus, as discussed
above, providing Vref as a test signal may significantly lower the
testing throughput and efficiency for a batch of the memory
circuits 10.
SUMMARY OF THE INVENTION
[0009] In one aspect of the invention, an integrated circuit
includes a differential amplifier having a first terminal that is
operable to receive an input signal and having a second terminal.
The integrated circuit also includes a reference circuit that
generates a reference signal on the second terminal of the
amplifier.
[0010] Therefore, during testing of such an IC, the tester can
enable the on-board reference circuit to internally generate the
reference signal such that the tester need not provide the
reference signal. During normal operation, however, the IC can use
the reference circuit to internally generate the reference signal
or can receive the reference signal from an external source.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] A description of the various embodiments of the invention is
made with reference to the following drawings where like reference
numerals are used for like elements.
[0012] FIG. 1 is a schematic diagram of a portion of a conventional
memory circuit.
[0013] FIG. 2 is a schematic diagram of a portion of a memory
circuit according to an embodiment of the invention.
[0014] FIG. 3 is a schematic diagram of an embodiment of the
reference-signal generator of FIG. 2.
[0015] FIG. 4 is a block diagram of the memory circuit of FIG. 2
according to an embodiment of the invention.
[0016] FIG. 5 is a block diagram of an electronic system that
incorporates the memory circuit of FIGS. 2 and 4.
DETAILED DESCRIPTION OF THE INVENTION
[0017] FIG. 2 is a schematic diagram of a portion of a
reduced-signal-level memory circuit 30 according to an embodiment
of the invention. The memory circuit 30 is similar to the memory
circuit 10 of FIG. 1 except that it includes an on-board
reference-signal generator 32, which in one embodiment is used to
internally generate a reference signal Vrefint during testing of
the circuit 30. Furthermore, because system designers often want
the flexibility of using a reference-signal value of their choice
for certain other operational modes of the circuit 30, in one
embodiment the circuit 30 receives an externally generated
reference signal during operation in these other modes. Thus, in
one embodiment, the circuit 30 accepts an externally generated
reference signal during a normal mode of operation, but internally
generates a reference signal during a test mode to reduce the
number of test signals needed from the tester.
[0018] Like the memory circuit 10, the memory circuit 30 includes
the terminals 12.sub.0-12.sub.n for respectively receiving the
signals S.sub.0-S.sub.n, the reference terminal 14 for receiving an
externally generated reference signal Vrefext, the complimentary
clock terminals 16a and 16b for receiving CFM and {overscore
(CFM)}, the buffer pairs [18.sub.0, 20.sub.0], . . . ,[18.sub.n,
20.sub.n] for respectively sampling S.sub.0-S.sub.n, and the
package 21. The memory circuit 30 also includes terminals 36.sub.0
and 36.sub.1 for respectively receiving digital mode signals
M.sub.0 and M.sub.1. A mode logic circuit 34 configures the
internal circuitry of the circuit 30 and controls the generator 32
according to the operational mode indicated by M.sub.0 and M.sub.1.
In one embodiment, the reference terminal 14 and the output
terminal of the generator 32 are both directly connected to the
buffers 18.sub.0-18.sub.n and 20.sub.0-20.sub.n. In another
embodiment, however, an optional isolation buffer 38, which is
controlled by the mode logic 34, uncouples the terminal 14 from the
output terminal of the generator 32 and from the buffers
18.sub.0-18.sub.n and 20.sub.0-20.sub.n if the generator 32 is
enabled. The generator 32, mode logic 34, and buffer 38 are
disposed inside of the package 21, and the terminals 36.sub.0 and
36.sub.1 are disposed outside of the package 21.
[0019] In operation, the buffers 18.sub.0-18.sub.n and
20.sub.0-20.sub.n sample S.sub.0-S.sub.n as described above in
conjunction with FIG. 1. Furthermore, during a first mode of
operation such as a normal mode, the system in which the memory
circuit 30 is installed provides Vrefext and values for M.sub.0 and
M.sub.1 such that the mode logic circuit 34 deactivates the
generator 32. If the buffer 38 is present, the mode circuit 34
enables it to couple Vrefext to the buffers 18.sub.0-18.sub.n and
20.sub.0-20.sub.n. Conversely, during a second mode of operation
such as a test mode, the system, which may include a tester, does
not provide Vrefext and provides values for M.sub.0 and M.sub.1
such that the mode circuit 34 activates the generator 32 to
generate Vrefint. If the buffer 38 is present, the mode circuit 34
disables it such that the terminal 14 is electrically isolated from
the generator 32 and the buffers 18.sub.0-18.sub.n and
20.sub.0-20.sub.n. Thus, the buffer 38 prevents damage to the
generator 32 that otherwise might occur if the system drives a
signal onto the terminal 14.
[0020] In addition to the above-described embodiment, other
embodiments of the memory circuit 30 are also possible. For
example, S.sub.0-S.sub.n and Vref may be coupled to the inverting
and non-inverting terminals of the respective buffers
18.sub.0-18.sub.n and 20.sub.0-20.sub.n. Furthermore, although
described as a DC voltage, the reference signal may be an AC
voltage or an AC or DC current. Moreover, if a lower sampling
frequency is acceptable, then the circuit 30 can receive a single
clock signal and include single input buffers to respectively
sample each signal S.sub.0-S.sub.n. Additionally, the circuit 30
may be designed to receive more or fewer mode signals M.
Furthermore, the terminal 14 can be eliminated and the generator 32
permanently activated such that it generates Vref internally during
all operational modes of the memory circuit 30.
[0021] FIG. 3 is a schematic diagram of an embodiment of the
reference-signal generator 32 of FIG. 2. The generator 32 includes
a relatively long-channel PMOS transistor 40, switching PMOS and
NMOS transistors 42 and 44, and diode-connected NMOS transistors 46
and 48, which are all connected in series between a power-supply
voltage VDD and ground. The gate of the transistor 40 is coupled to
ground such that the transistor 40 acts as a high-impedance load to
limit the current drawn by the generator 32. The gates of the
transistors 42 and 44 respectively receive complementary enable
signals ENABLE and {overscore (ENABLE)} from the mode circuit 34
(FIG. 2), and turn the generator 32 on and off in response to these
signals. The generator provides the reference signal Vrefint on an
output terminal 50, which is at the junction of the drains of the
transistors 42 and 44.
[0022] In an operational mode during which the memory circuit 30
receives an externally generated reference signal, the mode logic
34 generates {overscore (ENABLE)} inactive logic 1 and ENABLE
inactive logic 0 to deactivate the transistors 42 and 44 and thus
to put the terminal 50 in a high-impedance state. This prevents a
signal conflict at the inverting terminals of the buffers
18.sub.0-18.sub.n and 20.sub.0-20.sub.n.
[0023] In an operational mode during which the memory circuit 30
internally generates a reference signal, the mode logic 34
generates {overscore (ENABLE)} active logic 0 and ENABLE active
logic 1 to activate the transistors 42 and 44 and thus to allow a
current to flow through the transistors 46 and 48. The relatively
high resistance of the transistor 40 limits this current to a
desired level. While activated, the transistor 44 effectively acts
as a short circuit such that Vrefint at the node 50 is
approximately equal to the voltage across the transistors 46 and
48. Because the transistors 46 and 48 are diode connected, they
generate drain-to-source voltage drops equal to their respective
threshold voltages. Therefore, Vrefint approximately equals the sum
of the threshold voltages of the transistors 46 and 48, which can
be conventionally constructed to generate a desired value such as
1.4 V for Vrefint.
[0024] Although shown as a series combination of transistors, in
other embodiments the generator 32 can be any other type of
reference circuit that can generate Vrefint having a desired
value.
[0025] FIG. 4 is a block diagram of an embodiment of the memory
circuit 30 of FIG. 2. For example, the memory circuit 30 may be
similar to a Direct RDRAM.RTM.
128/144-MBIT(256K.times.16/18.times.32 S), which is described in
more detail in the Advanced Information sheet available from Rambus
Incorporated of Mountain View, Calif. or from the Rambus website at
www.rambus.com. Because of its relatively high operating frequency,
the memory circuit 30 uses two sets of clock signals, one set for
clocking in signals received the receiving of data from the system
in which the circuit 30 is installed, and another set for clocking
out signals to the system. For example, the set of clock signals
CFM and CFM (FIG. 2) are used to clock in signals received from the
system. For clarity, however, these sets of clock signals have been
omitted from FIG. 4. Furthermore, the signals received from and
sent to the system by the memory circuit 30 have voltage,
logic-level, and frequency characteristics that are similar to
those describe above for S.sub.0-S.sub.n (FIG. 2).
[0026] The memory circuit 30 includes a row-decoding circuit 60 for
receiving packets of row commands and addresses from a row bus 62.
The row-decoding circuit 60 includes a row demultiplexer 64 for
sequentially receiving portions of a row-information packet from
the row bus 62 and presenting the row-information packet to a row
decoder 66, which selects an addressed row of memory cells (not
shown) in a memory array 68.
[0027] A column-decoding circuit 70 receives packets of column
commands and addresses from a column bus 72. The column-decoding
circuit 70 includes a column demultiplexer 74 for sequentially
receiving portions of a column-information packet from the column
bus 72 and presenting the column-information packet to a column
decoder 76, which selects an addressed column of memory cells (not
shown) in the memory array 68. For convenience, the combination of
the row- and column-decoder circuits 60 and 70 can be referred to
as an address decoder.
[0028] A control circuit 78 receives packets of control information
from a control bus 80 and controls the row- and column-decoding
circuits 60 and 70. The control circuit 78 includes control
registers 82 for storing the control information, which includes,
e.g., circuit-configuration information and a chip address assigned
to the memory circuit 30 by the system in which the circuit 30 is
installed.
[0029] The memory array 68 includes one or more memory banks
84.sub.0-84.sub.n, which each include one or more rows of memory
cells, and includes a set of sense-amplifiers 86.sub.0-86.sub.y,
which write data to and read data from the respective banks
84.sub.0-84.sub.n. The sense amplifiers 86 receive write data from
and provide read data to internal data busses DQAint and DQBint. In
one embodiment, each sense amplifier 86 can read or write up to
half a row at one time. Thus, two sense amplifiers 86 are
respectively coupled to each bank 84 so that together these two
sense amplifiers can write or read an entire row at one time. To
reduce the number of sense amplifiers 86, the memory banks 84 share
them. For example, the banks 84.sub.0 and 84.sub.1 share the sense
amplifier 86.sub.1.
[0030] A read/write circuit 88a transfers data between the internal
data bus DQAint and an external data bus DQAext, and another
read/write circuit 88b transfers data between the internal data bus
DQBint and an external data bus DQBext. Both DQAext and DQBext
communicate with the data bus of the system in which the memory
circuit 30 is installed. The read/write circuit 88a includes a
write demultiplexer 90a for serially receiving groups of write-data
bits from DQAext and converting these groups into parallel data. A
write buffer 92a receives the parallel write data from the
demultiplexer 90a and provides it to DQAint. The read/write circuit
88a also includes a read multiplexer 94a, which receives read data
from DQAint, converts the read data into groups of read-data bits,
and sequentially provides these groups of read-data bits to DQAext.
Likewise, the read/write circuit 88b includes a write demultiplexer
90b, a write buffer 92b, and a read multiplexer 94b.
[0031] Typically, some or all of the following above-described
circuits include input buffers like the input buffers 18 and 20 of
FIG. 2: the row-decoding circuit 60, the column-decoding circuit
70, the control circuit 78, and the read/write circuits 88a and
88b. Each of these circuits may include its own reference generator
32 and optional isolation buffer 38, or the memory circuit 30 may
include one generator 32 and one optional isolator 38 for all of
these circuits. For example, the control circuit 78 may include the
generator 32 and optional isolator 38 for use by the entire memory
circuit 30, and may receive CFM and CFM from the control bus
80.
[0032] In operation during an initialization cycle of the memory
circuit 30, the control circuit 78 receives one or more control
packets from the bus 80, stores the corresponding control
information in the control registers 82, and configures the
internal circuitry, operating mode(s), and chip address of the
memory circuit 30.
[0033] During a read or write operation, the row-decoding circuit
60 sequentially receives portions of the row packet from the bus
62, each portion including one or more row-packet bits. For
example, in one embodiment, the row bus 62 is three bits wide, and
a row packet includes twenty four bits. Therefore, the decoding
circuit 60 receives the row packet as eight sequential packet
portions of three bits each. The row demultiplexer 64 sequentially
receives these packet portions and arranges the packet bits in a
parallel format. The row decoder 66 receives the row packet from
the demultiplexer 64 in this parallel format and enables the bank
84 and the row within this bank that are specified by the row
packet. The row decoder 66 also controls the memory array 68 to
implement the row-transfer mode specified by the row packet.
Generally, the row-transfer mode indicates how the selected bank
and row transfer data from or to the respective sense amplifiers
86. Similarly, the column-decoding circuit 70 sequentially receives
portions of the column packet from the bus 72, each portion
including one or more column-packet bits. For example, in one
embodiment, the column bus 72 is five bits wide and the column
packet includes forty bits. Therefore, the decoding circuit 70
receives the column packet as eight sequential packet portions of
five bits each. The column demultiplexer 74 sequentially receives
these packet portions and arranges the packet bits in a parallel
format. The column decoder 76 receives the column packet from the
demultiplexer 74 in this parallel format and enables the column or
columns that are specified by the column packet. The column decoder
76 also controls the memory array 68 to implement the
column-transfer mode specified by the column packet. Generally, the
column-transfer mode specifies how the sense amplifiers 86 transfer
data to or from the busses DQAint and DQBint.
[0034] In operation during a read cycle, the respective sense
amplifiers 86 provide half the data stored in the memory cells of
the specified row and column or columns to the read multiplexer 94a
and half to the read multiplexer 94b via DQAint and DQBint,
respectively. The multiplexers 94a and 94b receive their respective
data portions in parallel format, convert this parallel data into
respective groups of bits, and sequentially provide these groups of
bits to DQAext and DQBext, respectively. For example, in one
embodiment, the busses DQAint and DQBint are both seventy two bits
wide, and the busses DQAext and DQBext are both nine bits wide.
Therefore, the read multiplexer 94a receives the seventy two read
bits in parallel via DQAint and provides the read bits to DQAext as
a sequence of eight groups of nine data bits each. Likewise, the
read multiplexer 94b receives the seventy two read bits in parallel
via DQBint and provides the read bits to DQBext as a sequence of
eight groups of nine data bits each.
[0035] In operation during a write cycle, the write demultiplexers
90a and 90b sequentially receive respective groups of write data
bits from DQAext and DQBext, respectively, and arrange these groups
of data bits in a parallel format. For example, in the embodiment
described above where DGAext and DQBext include nine bits each and
DQAint and DQBint include seventy two bits each, the demultiplexers
90a and 90b each receive eight respective groups of data bits and
convert then into respective seventy-two bit words. The write
buffers 92a and 92b receive these words of write data from the
demultiplexers 90a and 90b and provide them to DQAint and DQBint,
respectively. The respective sense amplifiers 86 then write the
data from DQAint and DQBint into the specified row and column or
columns of memory cells in the array 68.
[0036] FIG. 5 is a block diagram of an electronic system 100, such
as a computer system, that incorporates the memory circuit 30 of
FIGS. 2 and 4. The system 100 includes computer circuitry 102 for
performing computer functions such as executing software to perform
desired calculations and tasks. The circuitry 102 typically
includes a processor 104 and the memory circuit 30, which is
coupled to the processor 104. One or more input devices 106, such
as a keyboard, mouse, or microphone, are coupled to the computer
circuitry 102 and allow an operator (not shown) to input data
thereto. One or more output devices 108 are coupled to the computer
circuitry 102 to provide to the operator data generated by the
computer circuitry 102. Examples of such output devices 108 include
a printer and a video display unit. One or more data-storage
devices 110 are coupled to the computer circuitry 102 to store data
on or to retrieve data from external storage media (not shown).
Examples of such storage devices 110 and the corresponding storage
media include drives that accept hard and floppy disks, tape
cassettes, and compact disk read-only memories (CD ROMS).
Typically, the computer circuitry 102 includes row, column,
control, and data busses that are respectively coupled to the row
bus 62, column bus 72, control bus 80, and data busses DQAext and
DQBext of the memory device 30.
[0037] From the foregoing it will be appreciated that, although
specific embodiments of the invention have been described herein
for purposes of illustration, various modifications may be made
without deviating from the spirit and scope of the invention.
* * * * *
References