U.S. patent application number 09/811598 was filed with the patent office on 2001-09-27 for semiconductor integrated circuit device and a method of manufacturing thereof.
Invention is credited to Akamatsu, Shiro, Kato, Masataka, Owada, Fukuo, Satoh, Akihiko, Takahashi, Masahito.
Application Number | 20010024859 09/811598 |
Document ID | / |
Family ID | 18573949 |
Filed Date | 2001-09-27 |
United States Patent
Application |
20010024859 |
Kind Code |
A1 |
Takahashi, Masahito ; et
al. |
September 27, 2001 |
Semiconductor integrated circuit device and a method of
manufacturing thereof
Abstract
A gate electrode of a field-effect transistor used as a
peripheral circuit is constituted by the same gate electrode
structure as a double-level gate electrode structure of nonvolatile
memory cells, and a contact hole for connecting those conductive
films constituting the gate electrode is provided at a location
which two-dimensionally overlaps an active area within a plane of
the gate electrode. A hole for connecting between the two layers of
the gate electrode of a first field-effect transistor used as
perpheral circuit is provided at a location which two-dimensionally
overlaps the active area within the plane of the gate electrode,
and a hole for connecting between the two layers of the gate
electrode of a second field-effect transistor used as a peripheral
circuit is provided at a location which two-dimensionally overlaps
an isolation area within the plane of the gate electrode. The gate
length of the first field-effect transistor is longer than the gate
length of the second field-effect transistor, and the gate width of
the first field-effect transistor is wider than the gate width of
the second field-effect transistor.
Inventors: |
Takahashi, Masahito;
(Tachikawa, JP) ; Akamatsu, Shiro; (Kodaira,
JP) ; Satoh, Akihiko; (Hachiouji, JP) ; Owada,
Fukuo; (Ome, JP) ; Kato, Masataka; (Koganei,
JP) |
Correspondence
Address: |
ANTONELLI TERRY STOUT AND KRAUS
SUITE 1800
1300 NORTH SEVENTEENTH STREET
ARLINGTON
VA
22209
|
Family ID: |
18573949 |
Appl. No.: |
09/811598 |
Filed: |
March 20, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09811598 |
Mar 20, 2001 |
|
|
|
09791832 |
Feb 26, 2001 |
|
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Current U.S.
Class: |
438/286 ;
257/E21.682; 257/E27.103; 257/E29.129 |
Current CPC
Class: |
H01L 27/115 20130101;
H01L 29/42324 20130101; H01L 27/11521 20130101; G11C 16/0416
20130101; G11C 7/18 20130101 |
Class at
Publication: |
438/286 |
International
Class: |
H01L 021/336 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 28, 2000 |
JP |
2000-052436 |
Claims
What is claimed is:
1. A semiconductor integrated circuit device comprising a plurality
of nonvolatile memory cells and a field-effect transistor for the
use as a peripheral circuit on a semiconductor substrate, each of
said plurality of nonvolatile memory cells comprising; a pair of
memory-cell semiconductor regions provided on said semiconductor
substrate; a first gate electrode provided over said semiconductor
substrate via a first insulating film at a location between said
pair of memory-cell semiconductor regions; and a second gate
electrode provided over said first gate electrode via a second
insulating film; said field-effect transistor for the use as a
peripheral circuit comprising; a pair of peripheral-circuit
semiconductor regions provided on said semiconductor substrate;
said first gate electrode provided over said semiconductor
substrate via a gate insulating film at a location between said
pair of peripheral-circuit semiconductor regions; said second gate
electrode provided over said first gate electrode via said second
insulating film; and a hole provided in said second insulating film
so as to electrically connect said first gate electrode and said
second gate electrode, said hole being provided at a location which
two-dimensionally overlaps an active area within the plane of said
first and second gate electrodes.
2. A semiconductor integrated circuit device comprising a plurality
of nonvolatile memory cells and a field-effect transistor for the
use as a peripheral circuit on a semiconductor substrate, each of
said plurality of nonvolatile memory cells comprising; a pair of
memory-cell semiconductor regions provided on said semiconductor
substrate; a first gate electrode provided over said semiconductor
substrate via a first insulating film at a location between said
pair of memory-cell semiconductor regions; and a second gate
electrode provided over said first gate electrode via a second
insulating film; said field-effect transistor for the use as a
peripheral circuit comprising; a pair of peripheral-circuit
semiconductor regions provided on said semiconductor substrate;
said first gate electrode provided over said semiconductor
substrate via a gate insulating film at a location between said
pair of peripheral-circuit semiconductor regions; said second gate
electrode provided over said first gate electrode via said second
insulating film; and a hole provided in said second insulating film
so as to electrically connect said first gate electrode and said
second gate electrode, said hole being provided both at a location
which two-dimensionally overlaps an active area and at a location
which two-dimensionally overlaps an isolation area within the plane
of said first and second gate electrodes.
3. A semiconductor integrated circuit device comprising a plurality
of nonvolatile memory cells and a field-effect transistor for the
use as a peripheral circuit on a semiconductor substrate, each of
said plurality of nonvolatile memory cells comprising; a pair of
memory-cell semiconductor regions provided on said semiconductor
substrate; a first gate electrode provided over said semiconductor
substrate via a first insulating film at a location between said
pair of memory-cell semiconductor regions; and a second gate
electrode provided over said first gate electrode via a second
insulating film; said field-effect transistor for the use as a
peripheral circuit comprising; a pair of peripheral-circuit
semiconductor regions provided on said semiconductor substrate;
said first gate electrode provided over said semiconductor
substrate via a gate insulating film at a location between said
pair of peripheral-circuit semiconductor regions; said second gate
electrode provided over said first gate electrode via said second
insulating film; and a hole provided in said second insulating film
so as to electrically connect said first gate electrode and said
second gate electrode, said hole being provided not at a location
which two-dimensionally overlaps an active area, but at a location
which two-dimensionally overlaps an isolation area within the plane
of said first and second gate electrodes.
4. A semiconductor integrated circuit device comprising a plurality
of nonvolatile memory cells and first and second field-effect
transistors for the use as a peripheral circuit on a semiconductor
substrate, each of said nonvolatile memory cells comprising; a pair
of memory-cell semiconductor regions provided on said semiconductor
substrate; a first gate electrode provided over said semiconductor
substrate via a first insulating film at a location between said
pair of memory-cell semiconductor regions; and a second gate
electrode provided over said first gate electrode via a second
insulating film; said first and second field-effect transistors for
the use as peripheral circuits comprising; a pair of
peripheral-circuit semiconductor regions provided on said
semiconductor substrate; said first gate electrode provided over
said semiconductor substrate via a gate insulating film at a
location between said pair of peripheral-circuit semiconductor
regions; said second gate electrode provided over said first gate
electrode via said second insulating film; and a hole provided in
said second insulating film so as to electrically connect said
first gate electrode and said second gate electrode, said hole
being provided at a location which two-dimensionally overlaps an
active area within the plane of said first and second gate
electrodes in said first field-effect transistor, and being
provided at a location which two-dimensionally overlaps an
isolation area within the plane of said first and second gate
electrodes in said second field-effect transistor.
5. A semiconductor integrated circuit device according to claim 4
wherein the gate length of said first field-effect transistor is
longer than the gate length of said second field-effect
transistor.
6. A semiconductor integrated circuit device according to claim 4
or 5 wherein the gate width of said first field-effect transistor
is wider than the gate width of said second field-effect
transistor.
7. A semiconductor integrated circuit device according to claim 4,
5 or 6 wherein said gate insulating film of said first field-effect
transistor has a larger thickness than the thickness of said gate
insulating film of said second field-effect transistor.
8. A semiconductor integrated circuit device according to any one
of claims 4 through 7 wherein the driving voltage of said first
field-effect transistor is higher than the driving voltage of said
second field-effect transistor.
9. A semiconductor integrated circuit device according to any one
of claims 4 through 7 wherein said first field-effect transistor is
a field-effect transistor constituting an input circuit, an output
circuit, an input/output bidirectional circuit, a power circuit or
a booster circuit.
10. A semiconductor integrated circuit device comprising a
plurality of nonvolatile memory cells and a protective field-effect
transistor on a semiconductor substrate, each of said plurality of
nonvolatile memory cells comprising; a pair of memory-cell
semiconductor regions provided on said semiconductor substrate; a
first gate electrode provided over said semiconductor substrate via
a first insulating film at a location between said pair of
memory-cell semiconductor regions; and a second gate electrode
provided over said first gate electrode via a second insulating
film; said protective field-effect transistor comprising; said pair
of memory-cell semiconductor regions provided on said semiconductor
substrate; said first gate electrode provided over said
semiconductor substrate via said first insulating film at a
location between said pair of memory-cell semiconductor regions;
said second gate electrode provided over said first gate electrode
via said second insulating film; and a hole provided in said second
insulating film so as to electrically connect said first gate
electrode and said second gate electrode.
11. A semiconductor integrated circuit device according to claim 10
wherein said hole is provided at a location which two-dimensionally
overlaps an active area, or at a location which two-dimensionally
overlaps an isolation area within the plane of said first and
second gate electrodes.
12. A semiconductor integrated circuit device according to claim 10
wherein said hole is provided both at a location which
two-dimensionally overlaps an active region and at a location which
two-dimensionally overlaps an isolation area within the plane of
said first and second gate electrodes.
13. A semiconductor integrated circuit device comprising a
plurality of nonvolatile memory cells and a capacitor element on a
semiconductor substrate, each of said plurality of nonvolatile
memory cells comprising; a pair of memory-cell semiconductor
regions provided on said semiconductor substrate; a first gate
electrode provided over said semiconductor substrate via a first
insulating film at a location between said pair of memory-cell
semiconductor regions; and a second gate electrode provided over
said first gate electrode via a second insulating film; said
capacitor element comprising; an active area for the capacitor
element formed in said semiconductor substrate; said first gate
electrode provided thereon via said first insulating film so as
that it two-dimensionally overlaps said active area; said second
gate electrode provided over said first gate electrode via said
second insulating film; and a hole provided in said second
insulating film so as to electrically connect said first gate
electrode and said second gate electrode.
14. A semiconductor integrated circuit device according to claim 13
wherein said hole is provided at a location which two-dimensionally
overlaps an active area for said capacitor element or at a location
which two-dimensionally overlaps an isolation area, or at the both
locations which two-dimensionally overlap, respectively, the active
area for said capacitor element and the isolation area within the
plane of said first and second gate electrodes.
15. A semiconductor integrated circuit device according to claim 13
or 14 wherein a hole for electrically connecting said second gate
electrode and a wiring thereon is provided at a location which
two-dimensionally overlaps an isolation area of said semiconductor
substrate.
16. A semiconductor integrated circuit device according to claim 13
or 14 wherein said active area for said capacitor element is
divided by an isolation area interposed therebetween, and a hole
for electrically connecting said second gate electrode and a wiring
thereon is provided at a location which two-dimensionally overlaps
said isolation area of said semiconductor substrate.
17. A semiconductor integrated circuit device comprising a
plurality of nonvolatile memory cells and a field-effect transistor
for the use as a peripheral circuit on a semiconductor substrate,
each of said plurality of nonvolatile memory cells comprising; a
pair of memory-cell semiconductor regions provided on said
semiconductor substrate; a first gate electrode provided over said
semiconductor substrate via a first insulating film at a location
between said pair of memory-cell semiconductor regions; and a
second gate electrode provided over said first gate electrode via a
second insulating film; said field-effect transistor for the use as
a peripheral circuit comprising; a pair of peripheral-circuit
semiconductor regions provided on said semiconductor substrate;
said first gate electrode provided over said semiconductor
substrate via a gate insulating film at a location between said
pair of peripheral-circuit semiconductor regions; said second gate
electrode provided over said first gate electrode via said second
insulating film; and a hole provided in said second insulating film
so as to electrically connect said first gate electrode and said
second gate electrode, said second gate electrode including a first
conductive film and a second conductive film formed on said first
conductive film, said second conductive film being directly
connected to said first gate electrode via said hole, said hole
being provided at a location which two-dimensionally overlaps an
active region within the plane of said first and second gate
electrodes.
18. A manufacturing method of a semiconductor integrated circuit
device comprising the steps of; (a) forming an isolation area and
an active area in a semiconductor substrate; (b) forming a first
insulating film over said semiconductor substrate; (c) forming a
conductive film for constituting a first gate electrode over said
first insulating film; (d) forming a second insulating film over
said conductive film for constituting said first gate electrode;
(e) opening a hole reaching to said conductive film for
constituting said first gate electrode within said second
insulating film at a location over a gate electrode formation
region of a field-effect transistor for the use as a peripheral
circuit; (f) forming a conductive film for constituting a second
gate electrode over said second insulating film and said hole; (g)
forming a double-level gate electrode of a nonvolatile memory cell
by patterning said conductive film for constituting said first gate
electrode, said second insulating film and said conductive film for
constituting said second gate electrode; (h) forming a pair of
semiconductor regions for said nonvolatile memory cell within said
semiconductor substrate; (i) forming a gate electrode of said
field-effect transistor for the use as a peripheral circuit by
patterning said conductive film for constituting said first gate
electrode, said second insulating film and said conductive film for
constituting said second gate electrode; and (j) forming a pair of
semiconductor regions for said field-effect transistor for the use
as a peripheral circuit within said semiconductor substrate;
wherein said hole is provided at a location which two-dimensionally
overlaps said active area within the plane of said gate electrode
of said field-effect transistor for the use as a peripheral
circuit.
19. A manufacturing method of a semiconductor integrated circuit
device comprising the steps of; (a) forming an isolation area and
an active area in a semiconductor substrate; (b) forming a first
insulating film over said semiconductor substrate; (c) forming a
conductive film for constituting a first gate electrode over said
first insulating film; (d) forming a second insulating film over
said first conductive film; (e) opening a hole reaching to said
conductive film for constituting said first gate electrode within
said second insulating film at a location over a gate electrode
formation region of a field-effect transistors for the use as
peripheral circuits; (f) forming a conductive film for constituting
a second gate electrode over said second insulating film; (g)
forming a double-level gate electrode of a nonvolatile memory cell
by patterning said conductive film for constituting said first gate
electrode, said second insulating film and said conductive film for
constituting said second gate electrode; (h) forming a pair of
semiconductor regions for said nonvolatile memory cell in said
semiconductor substrate; (i) forming gate electrodes of said first
and second field-effect transistors for the use as peripheral
circuits by patterning said conductive film for constituting said
first gate electrode, said second insulating film and said
conductive film for constituting said second gate electrode; (j)
forming a pair of semiconductor regions for said first field-effect
transistor for the use as a peripheral circuit in said
semiconductor substrate; and (k) forming a pair of semiconductor
regions for said second field-effect transistor for the use as a
peripheral circuit in said semiconductor substrate; wherein said
hole is provided at a location which two-dimensionally overlaps
said active area within the plane of said gate electrode formation
region in the case of said first field-effect transistor, and said
hole is provided at a location which two-dimensionally overlaps
said isolation area within the plane of said gate electrode
formation region in the case of said second field-effect
transistor.
20. A manufacturing method of a semiconductor integrated circuit
device according to claim 19 wherein the gate length of said first
field-effect transistor is longer than the gate length of said
second field-effect transistor.
21. A manufacturing method of a semiconductor integrated circuit
device according to claim 19 or 20 wherein the gate width of said
first field-effect transistor is wider than the gate width of said
second field-effect transistor.
22. A manufacturing method of a semiconductor integrated circuit
device according to claim 19, 20 or 21 wherein said first
insulating film includes a relatively thick insulating film and a
relatively thin insulating film, and said gate insulating film of
said first field-effect transistor is formed with said relatively
thick insulating film and said gate insulating film of said second
field-effect transistor is formed with said relatively thin
insulating film.
23. A manufacturing method of a semiconductor integrated circuit
device according to any one of claims 19 through 22 wherein the
driving voltage of said first field-effect transistor is higher
than the driving voltage of said second field-effect
transistor.
24. A manufacturing method of a semiconductor integrated circuit
device according to any one of claims 19 through 22 wherein said
first field-effect transistor is a field-effect transistor
constituting an input circuit, an output circuit, an input/output
bidirectional circuit, a power circuit or a booster circuit.
25. A manufacturing method of a semiconductor integrated circuit
device comprising the steps of; (a) forming an isolation area and
an active area in a semiconductor substrate; (b) forming a first
insulating film over said semiconductor substrate; (c) forming a
conductive film for constituting a first gate electrode over said
first insulating film; (d) forming a second insulating film over
said first conductive film for constituting the first gate
electrode; (e) opening a hole reaching to said conductive film for
constituting said first gate electrode within said second
insulating film at a location over a gate electrode formation
region of a protective field-effect transistor; (f) forming a
conductive film for constituting a second gate electrode over said
second insulating film and said hole; (g) forming a double-level
gate electrode of a nonvolatile memory cell and a gate electrode of
said protective field-effect transistor by patterning said
conductive film for constituting said first gate electrode, said
second insulating film and said conductive film for constituting
said second gate electrode; and (h) forming pairs of semiconductor
regions for said nonvolatile memory cell and said protective
field-effect transistor in said semiconductor substrate.
26. A manufacturing method of a semiconductor integrated circuit
device according to claim 25 wherein said hole is provided at a
location which two-dimensionally overlaps said active area, or at a
location which two-dimensionally overlaps said isolation area
within the plane of said gate electrode.
27. A manufacturing method of a semiconductor integrated circuit
device according to claim 25 wherein said hole is provided both at
a location which two-dimensionally overlaps said active area and at
a location which two-dimensionally overlaps said isolation area
within the plane of said gate electrode.
28. A manufacturing method of a semiconductor integrated circuit
device comprising the steps of; (a) forming an isolation area and
an active area in a semiconductor substrate; (b) forming a first
insulating film over said semiconductor substrate; (c) forming a
conductive film for constituting a first gate electrode over said
first insulating film; (d) forming a second insulating film over
said conductive film for constituting said first gate electrode;
(e) opening a hole reaching to said conductive film for
constituting said first gate electrode within said second
insulating film at a location over an electrode formation region of
a capacitor element; (f) forming a conductive film for constituting
a second gate electrode over said second insulating film and said
hole; (g) forming a double-level gate electrode of a nonvolatile
memory cell by patterning said conductive film for constituting
said first gate electrode, said second insulating film and said
conductive film for constituting said second gate electrode; (h)
forming a pair of semiconductor regions for said nonvolatile memory
cell in said semiconductor substrate; and (i) forming an electrode
of said capacitor element by patterning said conductive film for
constituting said first gate electrode, said second insulating film
and said conductive film for constituting said second gate
electrode.
29. A manufacturing method of a semiconductor integrated circuit
device according to claim 28 wherein said hole is provided at a
location which two-dimensionally overlaps said active area, or a
location which two-dimensionally overlaps said isolation area, or
both at the location which two-dimensionally overlaps said active
area and at the location which two-dimensionally overlaps said
isolation area, within the plane of said electrode of said
capacitor element.
30. A manufacturing method of a semiconductor integrated circuit
device according to claim 28 or 29 wherein a hole for electrically
connecting said electrode of said capacitor element and a wiring
thereon is formed at a location which two-dimensionally overlaps
said isolation area.
31. A manufacturing method of a semiconductor integrated circuit
device comprising the steps of; (a) forming an isolation area and
an active area in a semiconductor substrate; (b) forming a first
insulating film over said semiconductor substrate; (c) forming a
conductive film for constituting a first gate electrode over said
first insulating film; (d) forming a second insulating film over
said conductive film for constituting said first gate electrode;
(e) selectively eliminating a portion of said second insulating
film, which has been formed within a peripheral circuit region; (f)
forming a conductive film for constituting a second gate electrode
over said second insulating film and said conductive film for
constituting said first gate electrode; (g) forming a double-level
gate electrode of a nonvolatile memory cell by patterning said
conductive film for constituting said first gate electrode, said
second insulating film and said conductive film for constituting
said second gate electrode; (h) forming a pair of semiconductor
regions for said nonvolatile memory cell in said semiconductor
substrate; and (i) forming a gate electrode of a field-effect
transistor within said peripheral circuit region by patterning said
conductive film for constituting said first gate electrode and said
conductive film for constituting said second gate electrode; and
(j) forming a pair of semiconductor regions for said field-effect
transistor within said peripheral circuit region, in said
semiconductor substrate.
Description
[0001] DRAMs (Dynamic Random Access Memory), thus it is expected to
be effective for the use as a substitute of magnetic disks.
[0002] A flash memory (EEPROM) has a function to electrically
erase, in batch, the data stored in a given range of a memory cell
array (all the memory cells in the memory cell array or a given
group of the memory cells). Among such flash memories (EEPROM), a
demand for those having a 1-bit/1-MISFET (metal insulator
semiconductor field-effect transistor) structure is drastically
growing as they allow higher levels of integration. In the
1-bit/1-MISFET structure, a memory cell fundamentally comprises one
double-level gate MISFET. This double-level gate MISFET is formed
by providing a floating gate electrode over a semiconductor
substrate via a tunnel insulating film, and additionally forming a
control gate electrode thereon via an interlayer film. Data storing
operation is performed by injecting electrons into the floating
gate electrode, and by drawing the electrons out from the floating
gate electrode.
[0003] For the flash memories (EEPROM), a structure is disclosed in
Japanese Patent Laid-Open No. 306889/1996, in which floating gates
are provided to transistors other than memory cells of the flash
memories, and the floating gates and control gates of the
transistors other than the memory cells are connected via metal
wirings.
[0004] Also, a structure and the manufacturing method thereof are
disclosed in, for example, Japanese Patent Laid-Open NO.
25069/1990, wherein a first gate oxide film, a first gate
electrode, a second gate oxide film, a second gate electrode and a
high-melting point silicide film are deposited as a common
structure for both nonvolatile memory cells having a double gate
structure and MOS transistors, and in the MOS transistor, the first
gate electrode and the second gate electrode are connected via a
contact hole formed within the second gate oxide film.
[0005] As another example, there is a structure and the
manufacturing method thereof disclosed in, for example, Japanese
Patent Laid-Open No. 34977/1988 which is a publication of a patent
application corresponding to U.S. Pat. No. 4,780,431, in which a
same gate structure is used for EEPROM nonvolatile memory cells and
associated transistors, and for the associated transistors, a first
silicon layer and a second silicon layer formed thereon are
connected by etching a portion of an oxide thin film provided
between them.
[0006] As still another example, there is a nonvolatile
semiconductor memory device and the manufacturing method thereof
disclosed in, for example, Japanese Patent Application Laid-Open
No. 298314/1996 in which, after sequentially forming a first
polysilicon film and a second gate oxide film from the bottom over
a memory cell region and a peripheral circuit region, the second
gate insulating film within the peripheral circuit region is
selectively removed, and a second polysilicon film is then
deposited.
SUMMARY OF THE INVENTION
[0007] The inventor of the present invention discovered, however,
that in the above mentioned techniques for the semiconductor
integrated circuit device including nonvolatile memories have the
following problems.
[0008] That is, where the double-level gate electrode structure is
employed for the field-effect transistors of the peripheral
circuitry, the resistivity of the gate electrodes cannot be reduced
according to the types of the field-effect transistors by simply
providing the contact holes for connecting between the two layers
of the gate electrode, and as the through current of the whole
flash memory (EEPROM) increases, the power consumption also
increases.
[0009] When attempting to change the layout of each of the
components (i.e. contact holes connecting the source and drain to a
first-level wiring layer) of a field-effect transistor used as a
peripheral circuit in order to solve the above problem, a desirable
layout can hardly be obtained. That is, there is a problem in that
it is difficult to represent a device structure without entailing
inconveniences in circuit designing.
[0010] An object of the present invention is to provide a technique
which allows the reduction in the resistivity of the gate
electrodes of the peripheral circuits of a semiconductor integrated
circuit device including nonvolatile memories.
[0011] Another object of the present invention is to provide a
technique which allows the reduction in the power consumption of a
semiconductor integrated circuit device including nonvolatile
memories.
[0012] Still another object of the present invention is to provide
a technique which allows the lay-outing of the devices intended for
peripheral circuits of a semiconductor integrated circuit device
including nonvolatile memories to be performed more easily.
[0013] Yet another object of the present invention is to provide a
technique which allows the transition to be made more easily from
the circuit designing of peripheral circuits to the device
designing of a semiconductor integrated circuit device having
nonvolatile memories.
[0014] The above and other object and novel feature of the present
invention will be apparent when reading the following description
in conjunction with the attached drawings.
[0015] The summary of a representative invention among the
inventions disclosed herein may be briefly explained as
follows.
[0016] In the present invention, the gate electrode of a
field-effect transistor for a peripheral circuit is constituted by
the same gate electrode structure as that of nonvolatile memory
cells having a double-level gate electrode structure, and a hole
for the connection between the two layers of the gate electrode of
the field-effect transistor for the peripheral circuit is formed at
a location which two-dimensionally overlaps an active area within
the plane of the gate electrode.
[0017] Moreover, in the present invention, the gate electrode of a
field-effect transistor for a peripheral circuit is constituted by
the same gate electrode structure as that of nonvolatile memory
cells having a double-level gate electrode structure, and a hole
for the connection between the two layers of the gate electrode of
the field-effect transistor for a peripheral circuit is formed at
each of a location which two-dimensionally overlaps an active area
and a location which two-dimensionally overlaps an isolation area
within the planes of the gate electrode.
[0018] Furthermore, in the present invention, the gate electrode of
a field-effect transistor for a peripheral circuit is constituted
by the same gate electrode structure as that of nonvolatile memory
cells having a double-level gate electrode structure, and a hole
for the connection between the two layers of the gate electrodes of
the field-effect transistor for the peripheral circuit is formed at
a location which two-dimensionally overlaps an isolation area
within the planes of the gate electrode.
[0019] Also in the present invention, the gate electrodes of first
and second field-effect transistors for a peripheral circuit are
constituted by the same gate electrode structure as that of
nonvolatile memory cells having a double-level gate electrode
structure, and a hole for the connection between the two layers of
the gate electrode of the first field-effect transistor is formed
at a location which two-dimensionally overlaps an active area
within the planes of the gate electrode, and a hole for the
connection between the two layers of the gate electrode of the
second field-effect transistor is formed at a location which
two-dimensionally overlaps an isolation area within the planes of
the gate electrodes. The gate length of the first field-effect
transistor is longer than the gate length of the second
field-effect transistor. The gate width of the first field-effect
transistor is wider than the gate width of the second field-effect
transistor.
[0020] Furthermore, in the present invention, the first gate
electrode of the double-level gate electrode is made of
polycrystalline silicon, and the second gate electrode includes a
high-melting point metal silicide film or a high-melting point
metal film.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 is an illustrative diagram showing the block
structure of a flash memory (EEPROM) according to one embodiment of
the present invention.
[0022] FIG. 2 is a partial schematic circuit diagram of an
exemplary memory array included in the flash memory (EEPROM) of
FIG. 1.
[0023] FIG. 3 is a waveform diagram of signals in write mode of the
flash memory (EEPROM) of FIG. 1.
[0024] FIG. 4 is a schematic circuit diagram showing one example of
an input circuit of the flash memory (EEPROM) of FIG. 1.
[0025] FIG. 5 is a schematic circuit diagram showing another
example of the input circuit of the flash memory (EEPROM) of FIG.
1.
[0026] FIG. 6 is a schematic circuit diagram showing one example of
input/output bidirectional circuit of the flash memory (EEPROM) of
FIG. 1.
[0027] FIG. 7 is a schematic plan view of the memory array of FIG.
1.
[0028] FIG. 8 is a schematic plan view of the same two-dimensional
area of FIG. 7 but shows a layout layer located above the layer
shown in FIG. 7.
[0029] FIG. 9 is a cross-sectional view of FIG. 7 taken along the
line A-A.
[0030] FIG. 10 is a cross-sectional view of FIG. 7 taken along the
line B-B.
[0031] FIG. 11 is a cross-sectional view of FIG. 7 taken along the
line C-C.
[0032] FIG. 12 is a cross-sectional view of FIG. 7 taken along the
line D-D.
[0033] FIG. 13 is a cross-sectional view of the flash memory
(EEPROM) of FIG. 1 during a manufacturing process.
[0034] FIG. 14 is a cross-sectional view for illustrating a defect
occurred during the manufacturing process of the flash memory
(EEPROM) that has been discussed by the inventor of the present
invention.
[0035] FIG. 15 (a) is a plan view showing the layout of a device
constituting a peripheral circuit of the flash memory (EEPROM) of
FIG. 1, and FIG. 15 (b) is a cross-sectional view of FIG. 15 (a)
taken along the line A-A.
[0036] FIG. 16 (a) is a plan view showing the layout of another
device constituting the peripheral circuit of the flash memory
(EEPROM) of FIG. 1, and FIG. 16 (b) is a cross-sectional view of
FIG. 16 (a) taken along the line A-A.
[0037] FIG. 17 (a) is a plan view of a modified example of the
layout of the element constituting the peripheral circuit of the
flash memory (EEPROM) shown in FIG. 15, and FIG. 17 (b) is a
cross-sectional view of FIG. 17 (a) taken along the line A-A.
[0038] FIG. 18 (a) is a plan view of a modified example of the
layout of the device constituting the peripheral circuit of the
flash memory (EEPROM) shown in FIG. 15, and FIG. 18 (b) is a
cross-sectional view of FIG. 18 (a) taken along the line A-A.
[0039] FIG. 19 (a) is a plan view of a modified example of the
layout of the device constituting the peripheral circuit of the
flash memory (EEPROM) shown in FIG. 15, and FIG. 19 (b) is a
cross-sectional view of FIG. 19 (a) taken along the line A-A.
[0040] FIG. 20 (a) is a plan view showing the layout of a device
for protecting the flash memory (EEPROM) of FIG. 1, and FIG. 20 (b)
is a cross-sectional view of FIG. 20 (a) taken along the line
A-A.
[0041] FIG. 21 is a plan view of one example of the layout of
capacitor elements forming the flash memory (EEPROM) of FIG. 1.
[0042] FIG. 22 is a cross-sectional view of FIG. 21 taken along the
line A-A.
[0043] FIG. 23 is a schematic plan view of the flash memory
(EEPROM) of FIG. 1 during a manufacturing process.
[0044] FIG. 24 is a schematic cross-sectional view of the flash
memory (EEPROM) during the same manufacturing process as FIG.
23.
[0045] FIG. 25 is a schematic cross-sectional view of the flash
memory (EEPROM) showing a section different from that shown in FIG.
24 during the same manufacturing process as FIG. 23.
[0046] FIG. 26 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during a manufacturing process subsequent to the process shown in
FIGS. 23 to 25.
[0047] FIG. 27 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 26.
[0048] FIG. 28 is a schematic plan view of the flash memory
(EEPROM) showing the same section as that shown in FIG. 23 during a
manufacturing process subsequent to the process shown in FIGS. 26
and 27.
[0049] FIG. 29 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during the same manufacturing process as that shown in FIG. 28.
[0050] FIG. 30 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 28.
[0051] FIG. 31 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during a manufacturing process subsequent to the process shown in
FIGS. 28 to 30.
[0052] FIG. 32 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 31.
[0053] FIG. 33 is a schematic plan view of the flash memory
(EEPROM) showing the same section as that shown in FIG. 23 during a
manufacturing process subsequent to the process shown in FIGS. 31
and 32.
[0054] FIG. 34 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during the same manufacturing process as that shown in FIG. 33.
[0055] FIG. 35 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 33.
[0056] FIG. 36 is a schematic plan view of the flash memory
(EEPROM) showing the same section as that shown in FIG. 23 during a
manufacturing process subsequent to the process shown in FIGS. 33
to 35.
[0057] FIG. 37 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during the same manufacturing process as that shown in FIG. 36.
[0058] FIG. 38 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 36.
[0059] FIG. 39 is a schematic plane view of the flash memory
(EEPROM) showing the same section as that shown in FIG. 26 during a
manufacturing process subsequent to the process shown in FIGS. 36
to 38.
[0060] FIG. 40 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during the same manufacturing process as that shown in FIG. 39.
[0061] FIG. 41 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 39.
[0062] FIG. 42 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during a manufacturing process subsequent to the process shown in
FIGS. 39 to 41.
[0063] FIG. 43 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 42.
[0064] FIG. 44 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during a manufacturing process subsequent to the process shown in
FIGS. 42 and 43.
[0065] FIG. 45 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 44.
[0066] FIG. 46 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during a manufacturing process subsequent to the process shown in
FIGS. 44 and 45.
[0067] FIG. 47 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 46.
[0068] FIG. 48 is a schematic plan view of the flash memory
(EEPROM) showing the same section as that shown in FIG. 23 during a
manufacturing process subsequent to the process shown in FIGS. 46
and 47.
[0069] FIG. 49 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during the same manufacturing process as that shown in FIG. 48.
[0070] FIG. 50 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 48.
[0071] FIG. 51 is a schematic plan view of the flash memory
(EEPROM) showing the same section as that shown in FIG. 23 during a
manufacturing process subsequent to the process shown in FIGS. 48
to 50.
[0072] FIG. 52 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during the same manufacturing as that process shown in FIG. 51.
[0073] FIG. 53 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 51.
[0074] FIG. 54 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 24
during a manufacturing process subsequent to the process shown in
FIGS. 51 to 53.
[0075] FIG. 55 is a schematic cross-sectional view of the flash
memory (EEPROM) showing the same section as that shown in FIG. 25
during the same manufacturing process as that shown in FIG. 54.
[0076] FIG. 56 is a schematic cross-sectional view of a flash
memory (EEPROM) according to another embodiment of the present
invention during a manufacturing process.
[0077] FIG. 57 is a schematic cross-sectional view of the flash
memory (EEPROM) of FIG. 56 along another cutting line during the
manufacturing process.
[0078] FIG. 58 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 56.
[0079] FIG. 59 is a schematic cross-sectional view of the flash
memory (EEPROM) along another cutting line during the manufacturing
process shown in FIG. 58.
[0080] FIG. 60 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 58.
[0081] FIG. 61 is a schematic cross-sectional view of the flash
memory (EEPROM) along another cutting line during the manufacturing
process shown in FIG. 60.
[0082] FIG. 62 is a schematic cross-sectional view of a flash
memory (EEPROM) according to still another embodiment of the
present invention during a manufacturing process.
[0083] FIG. 63 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 62.
[0084] FIG. 64 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 63.
[0085] FIG. 65 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 64.
[0086] FIG. 66 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 65.
[0087] FIG. 67 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 66.
[0088] FIG. 68 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 67.
[0089] FIG. 69 is a schematic cross-sectional view of the flash
memory (EEPROM) showing during a manufacturing process subsequent
to the process shown in FIG. 68.
[0090] FIG. 70 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 69.
[0091] FIG. 71 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 70.
[0092] FIG. 72 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 71.
[0093] FIG. 73 is a schematic cross-sectional view of the flash
memory (EEPROM) during a manufacturing process subsequent to the
process shown in FIG. 72.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0094] Now, embodiments of the present invention will be explained
in detail according to the figures.
[0095] For better understanding of the embodiments, those elements
having the same functions are referred by the same numerals through
all the diagrams, and the detailed descriptions thereof will not be
repeated.
[0096] In the preferred embodiments of the present invention, a
field-effect transistor generally refers a MISFET or MOSFET (metal
oxide semiconductor field-effect transistor). As used herein,
MOSFET is simply referred to as "MOS", accordingly, a p-channel
type MOS.cndot.FET is referred to as "pMOS", and an n-channel type
MOS.cndot.FET is referred to as "nMOS". Similarly, a MIS.cndot.FET
is simply referred to as "MIS", accordingly, a p-channel type
MIS.cndot.FET is referred to as "pMIS", and an n-channel type
MIS.cndot.FET is referred to as "nMIS". For the purpose of
explanation, the term "MOS" as used in the following description
refers both MIS and MOS.
[0097] [Embodiment 1]
[0098] In the first embodiment of the present invention, the
present invention is explained as being applied to a flash memory
(EEPROM) having a memory capacity of 512 megabits. However, the
present invention is not limited to the one having a capacity of
512 megabits, and the present invention may also be applied to
various types of memories such as those having smaller capacities
(i.e. 256 megabits) or larger capacities (i.e. larger than 512
megabits).
[0099] FIG. 1 shows a block diagram of such a flash memory (EEPROM)
according to one embodiment. First, with reference to this figure,
the configuration and operation of the flash memory (EEPROM)
according to Embodiment 1 will be outlined.
[0100] As shown in FIG. 1, the flash memory (EEPROM) of Embodiment
1 comprises a memory cell array MARY as its fundamental component,
and further includes an X-address decoder XD, a sense amplifier
data latch SADL, Y-gate circuit YG and Y-address decoder YD that
constitute the direct peripheral circuits thereto.
[0101] The memory array MARY is arranged over a major portion of
the principal surface of a semiconductor substrate (a small thin
plate made of a semiconductor having a shape of a flat square,
which herein referred to as a semiconductor chip), and as later
explained, the array has a given number of word lines arranged in
parallel to the horizontal direction of the diagram, a given number
of bit lines arranged in parallel to the vertical direction of the
diagram, and a large number of memory cells having the double-level
gate structure arranged in a matrix substantially at the
intersections of these word lines and bit lines. These memory cells
are grouped into cell units, each of which includes m+1 cells
arranged in a same column, and every n+1 cell units constitutes a
memory cell block. The flash memory (EEPROM) in Embodiment 1
employs a hierarchical bit line scheme, so that the bit lines of
the memory array MARY comprises sub-bit lines each constituted by
commonly coupling the drains of m+1 memory cells which form each
cell unit, and main bit lines to which p+1 sub-bit lines arranged
in a same column are selectively connected via drain-side selection
MOSs.
[0102] The sources of m+1 memory cells which constitute each cell
unit of the memory cell array MARY are commonly coupled to a
corresponding local source line respectively, and these local
source lines are coupled to common source lines via corresponding
source-side selection MOSS. The control gates of n+1 memory cells
arranged in a same row of the memory array MARY are commonly
coupled to a corresponding word line respectively, and the gates of
the selection MOSs on the side of drains and on the side of sources
are commonly coupled respectively to corresponding bits of p+1
block selection signal lines on the side of the drains or on the
side of the sources that are arranged in parallel to the word
lines.
[0103] In Embodiment 1, each cell unit of the memory array MARY
further comprises an n-channel type short MOS provided between the
sub-bit lines and the local source lines, that is between the
drains and sources of m+1 memory cells that have been commonly
coupled. The gates of each n+1 short MOSs arranged on the same row
are commonly coupled to a corresponding block selection signal line
for the short MOSs. A specific configuration and the operation of
the memory array MARY and the effect and the device structure etc.
of the short MOS provided to each cell unit will later be explained
in detail.
[0104] The word lines of the memory array MARY, which comprise
drain-side block selection signal lines, source-side block
selection signal lines and short MOS block selection signal lines,
are coupled, on their left side, to the X-address decoder XD, and
each of them is selectively set in a selected level or a
non-selected level. To the X-address decoder XD, internal X-address
signals having a given bits are supplied from the X-address buffer
XB. Moreover, internal control signals XDG are supplied from the
memory control circuit MC, and various internal voltages are
supplied from the internal voltage generating circuit VG. X-address
signals are supplied to the X-address buffer XB from data
input/output terminals IO0 through IO7 via a data input/output
circuit IO and a multiplexer MX, and internal control signals XL1,
XL2 are supplied from the memory control circuit MC.
[0105] Although it is not limited, in Embodiment 1, an X-address
signal holds more than 8 bits, and it is supplied time-divisionally
from the data input/output terminals IO0-IO7 in two cycles. The
lower order bits of the X-address signal inputted by the first
cycle are taken according to the internal control signal XL1, thus
into the lower order bits of the x-address buffer XB, and the
higher order bits of the X-address signal inputted by the second
cycle are taken into the internal control signal XL2, thus into the
higher order bits of the X-address buffer XB. The X-address buffer
XB forms internal X-address signals comprising inverted and
non-inverted signals based on these X-address signals and supplies
them to the X-address decoder XD.
[0106] The X-address decoder XD decodes the internal X-address
signals supplied from the X-address buffer XB and selectively sets
the corresponding word lines of the memory array MARY to a given
selection level, and at the same time, sets the above-mentioned
drain-side block selection signal lines, source-side block
selection signal lines and short MOS block selection signal lines
to a given valid level in order to selectively activate specified
memory cell blocks.
[0107] Next, the main bit lines which form the memory array MARY
are coupled, at their bottom ends, to corresponding unit circuits
of the sense amplifier data latch SADL. The sense amplifier data
latch SADL comprises n+1 unit circuits provided correspondingly to
the respective main bit lines of the memory array MARY, and each
unit circuit includes a unit sense amplifier serving as a read
circuit and a unit data latch which holds read or write data, and
at the same time, serves as a write circuit. The input/output
terminals on one side of unit circuits of the sense amplifier data
latch SADL are coupled to corresponding main bit lines of the
memory array MARY, and the input/output terminals on the other side
are coupled to the multiplexer MX via Y-gate circuit YG selectively
by each 8 terminals, that is, by each 1 byte.
[0108] Now, the multiplexer MX comprises a first input/output
terminal provided on the left side thereof, and second and third
output terminals and a fourth input/output terminal provided on the
right side thereof. Among them, the fourth input/output terminal
which is provided on the right side is selectively connected to the
other input/output terminals of specified 8 unit circuits of the
sense amplifier data latch SADL via Y-gate circuit YG, and the
first input/output terminal provided on the left side is coupled to
the right side input/output terminal of the data input/output
circuit IO. The second output terminal is coupled to an input
terminal of the command register CR, and the third output terminal
is coupled to the input terminal of the X-address buffer XB. The
left-side input/output terminals of the data input/output circuit
IO are coupled to the data input/output terminals IO0-IO7.
[0109] To the unit sense amplifier included in each of the unit
circuits of the sense amplifier data latch SADL, an internal
control signal SA (not shown) is commonly supplied from the memory
control circuit MC, and to the unit data latch, an internal control
signal TR (not shown) is supplied from the memory control circuit
MC. To the command register CR, an internal control signal CL is
supplied from the memory control circuit MC, and a bit-line
selection signal (not shown) of a given bit is supplied to the
Y-gate circuit YG from Y-address decoder YD. To the Y-address
decoder YD, an internal Y address signal of a given bit is supplied
from the Y-address counter YC, and an internal control signal YDG
is supplied from the memory control circuit MC.
[0110] When the flash memory is in a read mode, each of the unit
sense amplifiers of the sense amplifier data latch SADL is
activated selectively according to the internal control signal SA,
amplifies a read signal outputted from n+1 memory cells coupled to
a selected word line of the memory array MARY via a corresponding
main bit line, and determines its logic level to transmit it to the
corresponding unit data latch. These read data are sequentially
selected by every 1 byte, or 8 bits, via the Y-gate circuit YG, and
outputted to an external accessing device from the multiplexer MX
via the data input/output circuit IO and the data input/output
terminals IO0-1O7.
[0111] On the other hand, where the flash memory (EEPROM) is in a
write mode, each of the unit data latches of the sense amplifier
data latch SADL sequentially receives and holds write data inputted
serially by every 1 byte, or 8 bits, from an external accessing
device via the data input/output terminals IO0-1O7, the data
input/output circuit IO, the multiplexer MX and the Y-gate circuit
YG, and when capturing of the write data of n+1 bits is completed,
it converts these write data into a given write signal, and writes
at once into the n+1 selection memory cells coupled to the selected
word line of the memory array MARY via each of the main bit
lines.
[0112] In the flash memory (EEPROM) according to Embodiment 1, the
data writing operation is performed by utilizing i.e. FN tunneling
effect, and during this write operation, a write voltage supplied
to each of the main bit lines of the memory array MARY is set at a
first write voltage such as ground potential VSS, or 0V, when the
corresponding bit of the write data is logic 1, in other words,
when writing is to be practically performed to a selected memory
cell. On the other hand, when the corresponding bit of the write
data is logic 0, or when writing should not practically occur to
the selected memory cell, then the voltage is set at a second write
voltage such as +6V, for example. The writing operation of the
flash memory (EEPROM) will be described later in detail.
[0113] The Y-address counter YC performs a stepping operation
according to an internal clock signal (not shown), and by forming
an internal Y-address signal having a given bits and decoding the
internal Y-address signal supplied form the Y-address counter YC,
the bit lines corresponding to a bit line selection signal for the
Y-gate circuit YG are sequentially turned into a high level
alternatively. Furthermore, the Y-gate circuit YG, in response to
the alternative high level of the bit line selection signal,
sequentially selects corresponding 8 unit circuits of the sense
amplifier data latch SADL to selectively provide a connection
between the multiplexer MX and the data input/output circuit
IO.
[0114] The data input/output circuit IO transmits the X-address
signal, write data and command data inputted from the external
accessing device via the data input/output terminals IO0-IO7 to the
multiplexer MX, and at the same time, outputs the read data
transmitted from the Y-gate circuit YG via the multiplexer MX to
the external accessing device via the data input/output terminals
IO0-IO7. Multiplexer MX transmits the X-address signal, write data
and command data supplied from the data input/output circuit IO to
the corresponding X-address buffer XB, the Y-gate circuit YG or the
command register CR, and at the same time, transmits 8-bit read
data outputted from specified 8 unit circuits of the sense
amplifier data latch SADL via the Y-gate circuit YG to the data
input/output circuit IO.
[0115] The command register CR receives and holds the 8-bit command
data inputted from the data input/output terminals IO0-IO7 via the
data input/output circuit IO and the multiplexer MX according to
the internal control signal CL, and at the same time, transmits the
data to the memory control circuit MC. The memory control circuit
MC is constituted by a microprogram-type state machine, and
selectively forms the various internal control signals based on the
serial clock signal SC, chip enable signal CEB (herein, those
inverted signals etc. which are selectively set at a low level when
they are valid are indicated by the suffix "B" after their
symbols), write enable signal WEB, output enable signal OEB, reset
control signal RESB and command data enable signal CDEB supplied by
the external accessing device as execution control signals, and the
command data supplied by the command register CR, and then supplies
them to the each sections of the flash memory (EEPROM). It also
selectively generates a ready/busy signal R/BB to inform the
external accessing device of the availability of the flash memory
(EEPROM).
[0116] The internal voltage generating circuit HVD selectively
generates various internal voltages representing the selected or
unselected level of the word lines, drain-side block selection
signal lines, source-side block selection signal lines, and short
MOS block selection signal lines based on the power source voltage
VCC on the higher potential side supplied via an external terminal
(bonding pad BP VCC) and the ground potential VSS on the lower
potential side supplied via an external terminal (bonding pad BP
VSS), and supplies them to the X-address decoder XD etc.
[0117] FIG. 2 shows a partial schematic circuit diagram of one
embodiment of the memory array MARY included in the flash memory
(EEPROM) of FIG. 1. With reference to the diagram, a specific
configuration of the memory array MARY according to Embodiment 1
will be explained. In FIG. 2, those MOSs having arrows at their
channel sections (back gates) are pMOSs, and those without arrows
are nMOSs.
[0118] As shown in FIG. 2, the memory array MARY of the flash
memory (EEPROM) according to Embodiment 1 includes p+1 memory cell
blocks MCB0-MCBp (FIG. 2 only shows the memory cell blocks MCB0,
MCB1 and MCB2 and elements related to these memory cell blocks),
and each of the memory cell blocks includes m+1 word lines W00-W0m
through Wp0-Wpm arranged in parallel to the horizontal direction of
the diagram and n+1 main bit lines MB0-MBn(MB) arranged in parallel
to the vertical direction of the diagram. At the substantial
intersections of these word lines and the main bit lines,
(m+1).times.(n+1) memory cells MC having the double-level gate
structure are arranged in a matrix.
[0119] Although it is not limited, the memory array MARY has, for
example, an AND-type array structure, and the memory cells MC
forming the memory cell blocks MCB0-MCBp are grouped respectively
into n+1 cell units CU00-CU0n through CUp0-CUpn, each of the units
having m+1 memory cells arranged in one column. The drains of the
m+1 memory cells MC forming each of these cell units are commonly
coupled to a corresponding one of the sub-bit lines SB00-SB0n
through SBp0-SBpn, and the sources thereof are commonly coupled to
a corresponding one of the local source lines SS00-SS0n through
SSp0-SSpn. The sub-bit lines SB00-SB0n through SBp0-SBpn for the
respective cell units are coupled to the corresponding main bit
lines MB0-MBn via n-channel type drain-side selection MOSs N1 whose
gates are coupled to the corresponding drain-side block selection
signal lines MD0-MDp, and the local source lines SS00-SS0n through
SSp0-SSpn are coupled to the common source lines SL via n-channel
type source side selection MOSs N3 whose gates are coupled to the
corresponding source-side block selection signal lines MS0-MSp.
[0120] In the embodiment, each of the cell units of the memory cell
blocks MCB0-MCBp further includes an n-channel type short MOS N2
provided between the commonly coupled drains of the corresponding
m+1 memory cells MC, or the sub-bit line SB00-SB0n through
SSp0-SSpn, and the commonly coupled sources of the corresponding
m+1 memory cells MC, or the local source line SS00-SS0n through
SSp0-SSpn. The gates of the n+1 short MOSs N2 included in each of
the memory cell blocks are commonly coupled to a corresponding one
of the short MOS block selection signal lines SC0-SCp
respectively.
[0121] FIG. 3 indicates a waveform diagram of the signals in the
flash memory (EEPROM) of FIG. 1 according to one embodiment while
it is in the write mode. With reference to this diagram, the
specific operations and the characteristics of the flash memory
(EEPROM) of the present embodiment during the write mode will now
be explained.
[0122] Herein, the description will mainly be provided for the
write operation. In FIG. 3, the memory cell MC which forms a part
of the cell unit CU00 of the memory cell block MCB0, and is coupled
to the word line W00 will be explained as a representative example
of the selected memory cell which is subject to the write
operation. Accordingly, the main bit line MB0 and the sub-bit line
SB00 to which this selected memory cell is coupled are explained as
representative examples of the selected main bit line and selected
sub-bit line, and the adjacent main bit line MB1 and sub-bit line
SB01 are explained as representative examples of the unselected
main bit line and the unselected sub-bit line to which selection
memory cells that are not subject to writing are couple. In
addition, the word line W00 is explained as a representative
example of the selected word line, and the word line W01 which
forms a part of the same memory cell block MCB0 is explained as a
representative example of the unselected word line. Moreover, the
short MOS block selection signal line MS0 to which the gate of the
short MOS N2 forming a part of the memory cell block MCB0 is
coupled is explained as a representative example of the short MOS
block selection signal lines MS0-MSp. The source-side block
selection signal line MS0 to which the gate of the selection MOSN3
in its source side is coupled is exemplified as a representative
example of the source-side block selection signal lines MS0-MSP.
The following provides specific descriptions using these
examples.
[0123] In FIG. 3, when the flash memory (EEPROM) is in the
unselected state, the drain-side block selection signal lines
MD0-MDp, the short MOS block selection signal lines SC0-SCp, the
word lines W00-W0m through Wp0-Wpm and the source-side block
selection signal lines MS0-MSp of the memory array MARY are
altogether at the unselected level such as the ground potential
VSS, or 0V. Therefore, the drain-side selection MOSs N1, short MOSs
N2 and the source-side selection MOSs N3 of all the cell units in
the memory array MARY are altogether in the OFF state, with the
memory cell MC being in the OFF state as well, so that the data
retained up to this point would be continued to be retained.
[0124] The threshold voltage of the memory cell MC which forms a
part of a cell unit of the memory array MARY is set at a value
lower than i.e. +3V while the memory cell MC is in an erased-state
and it holds a data of logic "0", and at a relatively high value
higher than i.e. +3V while the memory cell is in a written-state
and it holds a data of logic "1".
[0125] When the flash memory is turned into the selected state at
the write mode, at the timing T1, in the flash memory, a first
write voltage (first voltage) having a relatively small absolute
value such as 0V is supplied to the selected main bit line MB0 from
the sense amplifier data latch SADL, and to the unselected main bit
line MB1, a second write voltage (second voltage) having a
relatively large absolute value such as +6V is supplied. These
write voltages would not yet be transmitted to the sub-bit lines
SB00 and SB01 since the drain-side selection MOS N1 of each of the
cell units is in the OFF state.
[0126] Next, at the timing T2, the short MOS block selection signal
line SC0 corresponding to the memory cell block MCB0 is
alternatively turned into the selected level (second voltage) such
as +6V, and at the same time, the selected word line W00 is turned
into an intermediate selected level (third voltage) such as +4V,
and the unselected word line W01 is turned into an unselected level
(fourth voltage) such as +2V. The third voltage should be higher
than the fourth voltage and lower than the second voltage, and the
fourth voltage should be higher than the first voltage.
[0127] In this way, in the memory cell block MCB0 of the memory
array MARY, the short MOSs N2 in respective cell units are turned
into the ON state at once in response to the selected level of the
short MOS block selection signal line SC0, and the commonly coupled
drains of the m+1 memory cells MC forming each of the cell units,
or the sub-bit lines SB00-SB0n and the commonly coupled sources, or
local source lines SS00-SS0n are short-circuited. The selected word
line W00 is first tuned into the intermediate selected level (third
voltage) such as +4V before it is turned into a complete selected
level such as +16V for the purpose to prevent a drastic potential
change in the word line to suppress the generation of hot carriers.
Voltage of +2V (forth voltage) is applied to the unselected word
line W01 in order to reduce voltage between the channel floating
gate of the unselected memory cell to present the generation of
errors in writing and erasing.
[0128] On the other hand, at the timing T3, the drain-side block
selection signal line MD0 corresponding to the memory cell block
MCB0 is alternatively turned into a selected level higher than the
second voltage such as +10V, and in response to this, the
drain-side selection MOSs N1 which constitute a part of the cell
units CU00-CU0n of the memory cell block MCB0 are turned into the
ON state at once. Accordingly, to the selected sub-bit line SB00 of
the cell unit CU00, 0V (first voltage) of the corresponding main
bit line MB0 is transmitted, and to the unselected sub-bit line
SB01 of the cell unit CU01, +6V (second voltage) of the
corresponding main bit line MB1 is transmitted as it is without
being affected by the threshold voltage of the drain-side selection
MOS N1.
[0129] When a write voltage (second voltage) of +6V is transmitted
to the unselected sub-bit line SB01, in a flash memory which does
not include the short MOSs N2, the source-side selection MOS N3
would be turned into the OFF state in response to the low level of
the source-side block selection signal line MS0, and the local
source line SS01 would be turned into a floating state. Therefore,
the potential of the local source line SS01 which has initially
been at the unselected level of 0V (first voltage) would be charged
via the corresponding memory cells MC in response to the potential
change of the sub-bit line SB01 to +6V (second voltage), and charge
current temporarily occurs in these memory cells MC. As a result,
hot electrons are generated in the proximity of the drains of the
memory cells MC, causing errors in writing.
[0130] However, in the flash memory (EEPROM) of Embodiment 1, the
short MOS N2 is provided between the commonly coupled drains, or
one of the sub-bit lines SB00-SB0n, and the commonly coupled
sources, or one of the local source lines SS00-SS0n, for each m+1
memory cells MC constituting each of the cell units CU00-CU0n of
the memory cell block MCB0, and these short MOSs N2 turn into the
ON sate immediately before the timing T2, that is, the timing at
which the drain-side selection MOSs N1 are turned into the ON
state. Therefore, by the time when the write voltage (second
voltage) of +6V is applied to the unselected sub-bit line SB01, the
drain and the source of the selected memory cells which are not
subject to writing would have been short-circuited so that charge
current dose not occur via these selected memory cells, thus errors
in writing due to hot carriers, would not occur.
[0131] Next, at the timing T4, the selected word line W00 is turned
into the state with a relatively larger absolute value such as +16V
than the second voltage, or complete selected level. In the memory
cell block MCB0, m+1 memory cells MC of a cell unit CU00-CU0n
coupled to the word line W00 are selected, and writing is
practically performed selectively according to the write voltage
potential applied to their drains, or the sub-bit line SB00-SB0n,
in other words, the writing is done according to the logic value of
a corresponding bit of a write data.
[0132] That is, in the selected memory cell MC located at the
intersection between i.e. the word line W00 and the main bit line
MB0, or the sub-bit line SB00, which is subject to the write
operation, 16V corresponding to the absolute value of the selected
level of the word line W00 is applied between its control gate and
the drain, and its source is turned into the floating state, thus
the FN tunneling effect is promoted, so that the electron injection
takes place from its channel to the floating gate due to the tunnel
current. Therefore, the threshold voltage of the selected memory
cell MC increases, and changes to a relatively large value, such as
a value that exceeds +3V.
[0133] On the other hand, in the selected memory cell MC placed at
the intersection of i.e. the word line W00 and the unselected main
bit line MB1, or the unselected sub-bit line SB01, which is not
subject to the write operation, 10V which corresponds to the
difference between the selected level +16V of the word line W00 and
the write voltage +6V (first voltage) is applied between its
control gate and the memory channel, but the FN tunneling effect
would not occur as its absolute values is small. Accordingly, the
electron injection into the floating gate of this selected memory
cell MC would not take place, so that the threshold voltage would
be retained unchanged at a lower value, for example, the value
smaller than +3V.
[0134] When the write operation to the selected memory cell MC is
completed, in the flash memory at the timing T5, the drain-side
block selection signal line MD0 is brought back to the unselected
level of 0V, and at the same time, the word line W00 is brought
back to the intermediate selected level (third voltage) such as
+4V. Within the memory cell block MCB0, the drain-side selection
MOS N1 is turned into the OFF state in response to the drain-side
block selection signal line MD0 to be turned back to the unselected
level, and the sub-bit lines SB00-SB0n are turned into the floating
state while retaining the write voltage of 0V or +6V. The practical
writing operation to the selected memory cell MC would terminate in
response to the potential change of the word line W00 to the
intermediate level, and the reason why the selected word line W00
is first brought back to the intermediate selected level such as
+4V (third voltage) before it is fully turned into the complete
unselected level of 0V (first voltage) is to suppress the drastic
potential change in the word line in order to restrain the
generation of hot carriers.
[0135] Next at the timing T6, the selected word line W00 is brought
back to the complete unselected level such as 0V (first voltage)
from +4V (third voltage), and at the same time, the source-side
block selection signal line MS0 corresponding to the memory cell
block MCB0 is alternatively turned into the selected level such as
+6V (second voltage). At the slightly later timing T7, the short
MOS block selection signal line SC0 is brought back to the
unselected level such as 0V (first voltage), and at the same time,
the source-side block selection signal line MS0 is brought back to
the unselected level such as 0V (first voltage).
[0136] In the memory cell block MCB0, in response to the word line
W00 having been turned into the unselected level, the corresponding
n+1 memory cells MC are turned into the OFF state. Also, in
response to the alternative selected level of the source-side block
selection signal line MS0, n+1 source-side selection MOSs N3
included in the memory cell block MCB0 are turned into the ON state
at once, and the potential of the sub-bit lines SB00-SB0n and the
local source lines SS00-SS0n which has been set at +6V are
discharged to 0V via the common source line SL.
[0137] Furthermore, at a slightly later timing, the main bit lines
MB0-MBn are turned into 0V at once, and this would cause the
termination of the first writing. Thereafter, while performing
verifying operation for reification, similar write operations are
repeated until the threshold voltage of the selected memory cell MC
which is subject to writing operation becomes a value sufficiently
lower than, for example, +3V.
[0138] In a flash memory (EEPROM) that does not include the short
MOSs N2, the drain-side selection MOSs N1 are turned into the OFF
state, and the source-side selection MOSs N3 are turned into the ON
state, thus discharge current flows from the sub-bit lines
SB00-SB0n which have been turned into the floating state while
being retained at +6V into the source lines SS00-SS0n that have
been turned to 0V, so that there is a risk of incurring hot
carriers that may cause writing errors similar to those that might
occur immediately before the writing. On the contrary, in the case
of Embodiment 1 of the present invention, since the short MOSs N2
are held in the ON state for a length of time including the period
during which the discharge current occurs, hot carriers would not
be generated so that the writing errors may be prevented.
[0139] As explained above, in the flash memory (EEPROM) of
Embodiment 1, an n-channel type short MOS N2 is provided in
parallel to every m+1 memory cells MC constituting each of the cell
units of the memory cell blocks MCB0-MCBp of the memory array MARY,
and these short MOSs N2 are held in the ON state during the write
operation, or during a period from the time immediately after the
write voltage of 0V or +6V corresponding to the write data is
supplied to the main bit lines MB0-MBn, to the end of the discharge
of the sub-bit lines SB00-SB0n and the local source lines SS00-SS0n
via the source-side selection MOSs.
[0140] In this way, the generation of hot carriers caused by the
sub-bit lines SB00-SB0n being selectively set at +6V while the
local source lines SS00-SS0n being in the floating state during the
initial period of the write operation, may be restrained, and at
the same time, the generation of hot carriers caused by the local
source lines SS00-SS0n being set at 0V while the sub-bit lines
SB00-SB0n being in the floating state after the termination of the
write operation, may also be restrained. As a result, erroneous
writing into selected memory cells that are not subject to writing
may be prevented without adversely affecting the required write
time, and thus the reliability of the flash memory (EEPROM) as a
product can be improved without causing performance
degradation.
[0141] FIGS. 4, 5 and 6 show examples of input/output circuits in
the flash memory (EEPROM) of Embodiment 1. In each of the diagrams,
the bonding pad BP represents an external terminal on the
semiconductor chip for electrically connecting the internal
circuits (or flash memory (EEPROM)) to the circuits external to the
semiconductor chip.
[0142] FIGS. 4 and 5 illustrate exemplary input circuits, and in
either case, the key portion is constituted by i.e. a CMOS
(complementary MOS) inverter circuit INV. In FIG. 4, this inverter
circuit INV is constituted by a pMOS QINVp and an nMOS QINVn that
are electrically connected between a wiring for the power source
voltage VCC and a wiring for the ground potential VSS. At the input
of the inverter circuit INV, the bonding pad BP is electrically
connected via a protective resistor Rip and a protective nMOS Qipn.
These protective resistor Rip and nMOS Qipn are protective elements
for protecting the inverter circuit INV and the aforementioned
internal circuits from being exposed to any high voltages due to
electrostatic discharge etc. The protective nMOS Qipn is
diode-connected between the input of the inverter circuit INV and
the wiring to the ground potential VSS. A given circuit among the
aforementioned internal circuits is electrically connected to the
output of the inverter circuit INV.
[0143] Turning now to FIG. 5, besides the protective nMOS Qipn, a
protective pMOS Qipp is also electrically connected to the input of
the inverter circuit INV. This protective pMOS Qipp is a protective
element which is diode-connected between the input of the inverter
circuit INV and the wiring to the power source voltage VCC. Also
provided between the pMOS QINVp and nMOS QINVn, is an nMOS QINVS
for switching. This nMOS QINVS for switching serves to suppress the
leak current between the wiring to the source voltage VCC and the
wiring to the ground potential VSS while the inverter circuit INV
switches between ON and OFF, so as to reduce the power consumption.
Other than the above, it essentially has the same configuration as
the input circuit of FIG. 4.
[0144] The signals etc. transmitted from the outside of the
semiconductor chip are sent via the bonding pad BP to the input
circuit shown in FIGS. 4 and 5 from which the signals are sent to
the internal circuit after being processed into a state suitable
for the internal circuit.
[0145] FIG. 6 shows a bidirectional input/output circuit. On the
right side of the bonding pad BP in FIG. 6, a portion of the input
circuit is shown. Although the input circuit is not illustrated in
whole in FIG. 6, it should be understood that an input circuit
similar to that shown in FIG. 5, for example, is incorporated. On
the other hand, on the left side of the bonding pad BP, an output
circuit is illustrated. This output circuit comprises a pMOS Qout
for outputting, a protective nMOS Qopn1, nMOSs Qon1, Qon2 for
stabilizing the input potential, and protective nMOS Qopn2 and
resistors Ro1, Ro2. The protective nMOS Qopn1 has a function to
protect the internal circuit by absorbing the charge due to hot
carriers etc. In Embodiment 1 of the present invention, this
protective nMOS Qopn1 has a configuration substantially identical
to that of the memory cells of the flash memory (EEPROM) as will be
explained later in detail. That is, by forming the protective
device in a structure identical to the memory cells that can
provide a high electrostatic breakdown resistivity as it inherently
has a low withstanding voltage (especially at the drain edge), a
highly protective nMOS Qopn1 may be obtained.
[0146] With reference to FIGS. 7 through 12, the arrangements and
the structures of the elements in the flash memory (EEPROM)
according to Embodiment 1 of the present invention will now be
explained. FIG. 7 is a schematic plan view of the aforementioned
memory array MARY, FIG. 8 is a schematic plan view showing a layout
layer above, but in the same two-dimensional area shown in FIG. 7,
FIG. 9 is a cross-sectional view of FIG. 7 taken along the line A-A
(a line cutting through a word line W along the direction in which
the word line extends), FIG. 10 is a cross-sectional view of FIG. 7
taken along the line B-B (a line cutting through the channel
regions of the memory cells in a direction perpendicular to the
word lines, or Y-direction), FIG. 11 is a cross-sectional view of
FIG. 7 taken along the line C-C (a line cutting through the source
regions of the memory cells in the Y-direction, or a direction in
which the local source lines extend), and FIG. 12 is a
cross-sectional view of FIG. 7 taken along the line D-D (a line
cutting through the drain regions of the memory cells in the
Y-direction, or a direction in which the bit lines extend).
Although the following explains mainly with reference to the
cross-sectional views of FIGS. 9 though 12, the reference shall be
made also to FIGS. 7 and 8 as necessary for those descriptions
associated to the two-dimensional structures. The later explained
FIG. 24 corresponds to the cross-sectional view of FIG. 7 taken
along the line A-A, and the later explained FIG. 25 corresponds to
the cross-sectional view of FIG. 7 taken along the line B-B.
[0147] A semiconductor substrate 1 constituting the above
semiconductor chip is made of, for example, P-type
single-crystalline silicon, and in this semiconductor substrate 1,
a p-type well PWm is formed. This p-type well PWm is formed by the
introduction of, for example, boron (B), and over this region, the
above-explained memory cells MC as well as the elements for the
peripheral circuits such as the short MOSs N2 (SMOS) and selection
MOSs N1 (SlMOS), N3 (SlMOS) etc. are formed. This p-type well PWm
is surrounded by an embedded n-type well NWm layer formed below and
an n-type well formed on the sides of the p-type well PWm, so that
the p-type well PWm is electrically isolated from the semiconductor
substrate 1. The embedded n-type well NWm and the n-type well are
formed by introducing, for example, phosphorus (P) or arsenic (As)
into the semiconductor substrate 1, and have the functions to
restrain or prevent noises from the other elements on the
semiconductor substrate 1 from entering the p-type well PWm (that
is, memory cells MC) via the semiconductor substrate 1, and to set
the potential of the p-type well PWm to a given value independently
from the semiconductor substrate 1.
[0148] On the principal surface of the semiconductor substrate 1,
trench-type isolation regions SGI are formed. These isolation
regions SGI are formed by an insulating film filled within the
trenches having a band-like two-dimensional shape extending along
the Y-direction so as to provide electrical isolation between a
plurality of memory cells MC arranged in the direction in which the
word lines W extend (X-direction). The insulating film for the
isolation regions SGI may be, for example, a silicon oxide film
etc. and its top surface is made flat so as to substantially match
with the principal surface of the semiconductor substrate 1. In
order to provide the electrical isolation between a plurality of
memory cells MC arranged in the Y-direction, such trench-type
isolation regions may be formed in the semiconductor substrate 1
also in the areas between those memory cells MC arranged in the
Y-direction, or p-type semiconductor regions may be formed in the
regions of the semiconductor substrate 1 between those memory cells
MC by introducing i.e. boron into those regions.
[0149] Each of the memory cells MC comprises a pair of n-type
semiconductor regions 2S, 2D formed over the semiconductor
substrate 1, an insulating film 3a (a first insulating film) formed
over the principal surface (active region) of the semiconductor
substrate 1, a conductive film 4 for a floating gate electrode (a
first gate electrode) formed thereon, an interlayer film 5 (a
second insulating film) formed thereon, and a conductive film 6 for
a control gate electrode (a second gate electrode) formed
thereon.
[0150] The n-type semiconductor region 2S of a memory cell MC is a
region for forming a source region, and is a portion of the
above-explained local source line SS. Similarly, the n-type
semiconductor region 2D is a region for forming a drain region, and
is a portion of the above-explained sub-bit line SB. The local
source line SS and the sub-bit line SB in a band-like
two-dimensional shape extend in parallel to each other in the
Y-direction so as to surround therebetween the plurality of the
memory cells MC arranged along the Y-direction, and serve as common
regions of these plurality of surrounded memory cells MC. In
Embodiment 1 of the present invention, the n-type semiconductor
region 2S (local source line SS) and the n-type semiconductor
region 2D (sub-bit line SB) are formed by introducing, for example,
arsenic (As) into the semiconductor substrate 1 to a concentration
in the order of, for example, 10.sup.14/cm.sup.3. This realizes
shallow junctions of the semiconductor regions 2S, 2D, and also
allows the impurity concentration to be increased while restraining
or preventing the occurrence of short-channel effects etc., thus in
turn, provides further minimization, the assurance of reliability,
and the reduction of resistivity (sheet resistance) The local
source line SS is electrically connected to the common source line
SL (FIG. 2) formed of a metal film etc. via a selection MOS N3, and
the sub-bit line SB is electrically connected to a main bit line MB
formed of a metal film etc. via a selection MOS N1.
[0151] The insulating film 3a forming a part of the memory cells MC
is made of silicon oxide etc. in a thickness of i.e. approximately
9-10 nm, and forms electron passage regions (tunnel insulating
film) used for injecting electrons that contribute to the formation
of data from the semiconductor substrate 1 to the conductive film 4
constituting the floating gate electrodes, and for emitting the
electrons held by the conductor film 4 into the semiconductor
substrate 1.
[0152] The conductive film 4 for constituting the floating gate
electrode is constructed by sequentially forming two layers of
conductive films 4a and 4b from the bottom. The conductive films 4a
and 4b are both made of polycrystalline silicon with a low
resistivity which has been added with an impurity, and the
conductive film 4a has a thickness in the order of i.e. 70 nm and
the conductive film 4b has a thickness in the order of i.e. 40 nm.
The conductive film 4, however, is formed in a T-shape in its cross
section as shown in the cross-sectional view along the X-direction
(FIG. 9), so that the upper conductive film 4b has a larger width
than that of the lower conductive film 4a. This enables to increase
the area of the conductive film 4 as the floating gate electrode
facing to the conductive film 6 as the control gate electrode while
retaining the short channel length of the memory cell MC, thus the
capacitance formed between these gate electrodes may be increased.
Accordingly, the operation efficiency of the memory cell MC can be
improved without increasing its size. It should be understood
however, the present invention itself is also applicable to an
implementation having the floating gate electrode with an I-shaped
cross section. Between the conductive film 4b of the conductive
film 4 for the floating gate electrode and the semiconductor
substrate 1, an insulating film 7 made of i.e. silicon oxide etc.
is interposed so as to provide the isolation between the pair of
n-type semiconductor regions 2S, 2D and the conductive film 4b.
[0153] The surface of the conductive film 4b of the memory cell MC
is covered by the interlayer film 5 which isolates the conductive
film 4 for the floating gate electrode from the conductive film 6
for the control gate electrode. The interlayer film 5 is
constituted by forming a silicon oxide film over a silicon oxide
film via a silicon nitride film, and has a thickness in the order
of i.e. 15 nm. The conductive film 6 for the control gate electrode
forms an electrode for performing read, write and erasure of data,
and constituted by a portion of the word line W. The word line W is
formed in a two-dimensional pattern of a band-like shape extending
in the X-direction, and a plurality of them are arranged in
parallel in the Y-direction with a minimum process pitch (i.e.
approximately 0.30 .mu.m). This conductive film 6 (word line W)
constituting the control gate electrode is constructed by
sequentially forming i.e. two layers of conductive films 6a and 6b
from the bottom. The conductive film 6a at the bottom is made of
i.e. polycrystalline silicon with a low resistivity in a thickness
of approximately 100 nm. The conductive film 6b at the top is made
of i.e. tungsten silicide (Wsi.sub.x) in a thickness of 80 nm, and
is formed on the bottom conductive film 6a in an electrically
connected manner. The provision of this conductive film 6b allows
the reduction of the electrical resistance of the word line W, thus
allows the operation speed of the flash memory (EEPROM) to be
improved. However, the structure of the conductive film 6 is not
limited to this particular example, and may be modified in various
ways. For example, it may have a structure in which a metal film
made of tungsten etc. is formed over the polycrystalline silicon
layer having a low resistivity via a barrier conductive film made
of tungsten nitride etc. In this case, the electrical resistivity
of the word line W may be substantially reduced, so that the
operation speed of the flash memory (EEPROM) may be further
improved. Over this word line W, a cap insulating film 8 made of
i.e. silicon oxide is formed.
[0154] In Embodiment 1 of the present invention, the structures of
the elements serving as the peripheral circuits such as short MOSs
N2 (SMOS) and selection MOSs N1 (SlMOS), N3 (SlMOS) (refer also
FIG. 2) etc. also have the structures substantially similar to the
structure of the memory cells MC. Especially, the gate electrodes 9
of the short MOSs N2 (SMOS) and the gate electrodes 10 of the
selection MOSs N1 (SlMOS) and N3 (SlMOS) have the same structure as
the structure in which the conductive film 6 for the control gate
electrode is formed over the conductive film 4 for the floating
gate electrode via the interlayer film 5. More particularly, they
are constructed in the following way.
[0155] The short MOS N2 (SMOS) is constituted by i.e. an nMOS, and
comprises a pair of semiconductor regions 2S and 2D formed in a
semiconductor substrate 1, an insulating film 3a formed over the
principal surface of the semiconductor substrate 1, and a gate
electrode 9 formed thereon. The pair of the n-type semiconductor
regions 2S and 2D of the short MOS N2 (SMOS) are integral
respectively with the pairs of the n-type semiconductor regions 2S
and 2D of the aforementioned memory cells MC. The insulating film
3a of the short MOS N2 (SMOS) is a member constituting a gate
insulating film and has the same configuration (in terms of the
thickness and material) as that of the insulating layer 3a of the
aforementioned memory cells MC. Furthermore, the gate electrode 9
of the short MOS N2 (SMOS) is constituted by the two layers of the
conductive films 4 and 6 that are stacked via the interlayer film 5
of the aforementioned memory cells MC. However, the conductive
films 4 and 6 constituting the gate electrode 9 of the short MOS N2
(SMOS) are electrically connected through a contact hole SC
provided in the interlayer film 5 therebetween. This allows the
substantial reduction in the resistivity of the gate electrode 9.
The details of the layout of this contact hole SC will be explained
later. The conductive film 6 forming a part of the gate electrode 9
of the short MOS N2 (SMOS) is formed to have a larger width than
the conductive film 6 of the memory cells MC.
[0156] The selection MOS N1 (SlMOS) is constituted by i.e. an nMOS,
and comprises a pair of n-type semiconductor regions 11 (2D), 11 as
a source and a drain formed in a semiconductor substrate 1, an
insulating film 3b formed over the principal surface of the
semiconductor substrate 1, and a gate electrode 10 formed thereon.
The pair of the n-type semiconductor regions 11 of the selection
MOS N1 (SlMOS) are formed by introducing i.e. phosphorous, and the
impurity doping process thereof is performed separately from the
doping process of the pairs of n-type semiconductor regions 2S, 2D
of the aforementioned memory cells MC. However, one of the n-type
semiconductor regions 11 is overlapped with the n-type
semiconductor region 2D. The formation process and the
configuration of this pair of semiconductor regions 11 (2D), 11
will be later explained in detail. The insulating film 3b of the
selection MOS N1 (SlMOS) is a member constituting a gate insulating
film. This insulating film 3b is made of the same material as the
aforementioned insulating film 3a, however, the thickness thereof
is larger than the insulating film 3a, such as in the order of 25
nm. The formation method of this insulating film 3b also will be
explained later in detail. Furthermore, also in the selection MOS
N1 (SlMOS), the gate electrode 10 is constructed by stacking the
conductive films 4 and 6 of the aforementioned memory cells MC,
however, in the same way as in the short MOS N2, its conductive
films 4 and 6 are electrically connected through a contact hole SC
provided in the interlayer film 5 located therebetween. The
conductive film 6 forming a part of the gate electrode 10 of the
selection MOS N1 (SlMOS) is formed to have a larger width than the
conductive film 6 of the memory cells MC. Since the structure of
the selection MOS N3 (SlMOS) is identical to that of the selection
MOS N1 (SlMOS), the explanation thereof will be omitted.
[0157] The use of the structure in which the conductive film 6 is
formed over the conductive film 4 via the interlayer film 5, as the
structure of the gate electrodes 9 and 10 of the short MOSs N2
(SMOS) and the selection MOSs N1 and N2 (SlMOS) that are formed
within the memory array MARY, allows improving the flatness across
the memory array MARY. It is possible of course to improve the
flatness across the entire plane of the semiconductor chip by
employing the same MOS structure as the memory cells MC for the
peripheral circuits outside the memory array MARY. Now, the
reference shall be made to FIG. 13 which is a schematic
cross-sectional view of the memory array MARY during a patterning
process of the word lines W. On the conductive film 6, a photo
resist pattern PR for the formation of the word lines W and the
gate electrodes 9 and 10 is formed via an antireflection film BA.
Since, in this case, the flatness may be retained, it is possible
to apply the antireflection film BA in a substantially same
thickness in both the memory array region (left side of the
semiconductor region 2D in FIG. 13) and the peripheral circuit
region (right side of the n-type semiconductor region 2D in FIG.
13). This allows the further minimization of the pitch between the
adjacent word lines W. On the other hand, for the purpose of
comparison, FIG. 14 illustrates an example in which the gate
electrodes of a short MOS (SMOS) and selection MOSs (SlMOS) formed
within a memory array on a semiconductor substrate 50 have a
single-layer structure. In this example, there is a step 51 at the
boundary between the memory cell formation region and the short MOS
(SMOS) and selection MOS (SlMOS) formation region. Thus, there is a
step in a semiconductor film 52 for forming the word lines and the
gate electrodes. Accordingly, an antireflection film 53 over the
conductive film 52 is thicker in the region above the short MOS
(SMOS) and the selection MOS (SlMOS) formation region than the
region above the memory cell formation region. With this structure,
when patterning is performed over the conductive film 52 by etching
using a photo resist pattern 54 as a mask, the photo resist pattern
54 on the word line side becomes narrower while patterning the gate
electrodes due to the large thickness of the antireflection film 53
on the side of the short MOS (SMOS) and the selection MOS (SlMOS)
formation region, and this would result in substantially narrow
word lines W. Accordingly, the initial setting of the width of the
word lines has to be made larger by the expected narrowing amount,
so that the pitch of the adjacent word lines also has to be made
wider, thereby resulting in an increased area of the memory
array.
[0158] On the side surfaces of the conductive film 4 for the
floating gate electrode, the conductive film 6 for the control gate
electrode, gate electrodes 9 and 10 and a cap insulating film 8, an
insulating film 12a made of i.e. silicon oxide is deposited.
Especially, the intervals between the word lines W adjacent to each
other in the Y-direction are filled with this insulating film 12a.
Over the insulating film 12a and the conductive film 6, an
insulating film 12b made of i.e. silicon oxide is deposited. Over
this insulating film 12b, a first-level wiring layer L1 made of
i.e. tungsten is formed. The given first-level wiring layer L1 is
electrically connected with the n-type semiconductor region 11 of
the selection MOS N1 via a contact hole CON1 provided in the
insulating layer 12b. Furthermore, an insulating film 12c made of
i.e. silicon oxide is deposited over the insulating film 12b,
thereby covering the surface of the first-level wiring layer L1.
Over this insulating film 12c, a second-level wiring layer L2 is
formed. The second-level wiring layer L2 is constructed by
sequentially depositing i.e. titanium nitride (TiN), aluminum (Al)
and titanium nitride (TiN) from the bottom, and is electrically
connected to the first-level wiring layer L1 via a through hole TH1
provided in the insulating layer 12c. The surface of this
second-level wiring layer is covered by an insulating film 12d made
of i.e. silicon oxide.
[0159] Now, with reference to FIGS. 15 through 19, examples of the
layout of the contact holes SC provided in a MOS constituting a
peripheral circuit will be explained. In FIGS. 15 through 19, the
(b) diagrams are the cross-sectional views of respective (a)
diagrams taken along the line A-A.
[0160] In Embodiment 1 of the present invention, there are
essentially two types of contact-hole SC layouts for the MOSs
constituting peripheral circuits according to the gate lengths of
the respective MOSs. FIGS. 15 and 16 diagrammatically illustrate
examples of two types of MOSs QA and QB constituting peripheral
circuits. Since the present invention can be applied to either pMOS
or nMOS, the conductivity types of the channels of the MOSs QA and
QB are not particularly specified in this description in order to
simplify the explanation. Also, the pair of the semiconductor
regions for the source and drain of the MOS QA are representatively
indicated by codes "SA" and "DA", and the gate electrode of the MOS
QA is representatively indicated by a code "GA". The pair of the
semiconductor regions for the source and drain of the MOS QB are
representatively indicated by codes "SB" and "DB", and the gate
electrode of the MOS QB is representatively indicated by a code
"GB". In the MOS QA and MOS QB, the numerals "LA" and "LB"
represent active areas, and the outside thereof represents
isolation areas.
[0161] First, the MOS QA shown in FIG. 15 represents a MOS having a
relatively long gate length (horizontal direction in FIG. 15 (a))
and gate width (vertical direction in FIG. 15 (a)). This MOS QA is
used as an element for forming i.e. a power circuit, a boosting
transformer, a word line driver and a decoding circuit. For
example, the input circuits nMOS Qipn, QINVn, QINVS and pMOS Qipp,
and the output circuit pMOS Q0out, short MOS N2, selection MOSs N1
and N3 preferably have this structure.
[0162] In the case where the MOS QA forms a high-voltage circuit in
which a high voltage (i.e. 18V) would be applied to the gate
electrode GA, the gate insulating film is required to have a high
withstand voltage, so that in the MOS QA shown in FIG. 15 (b), the
relatively thick insulating film 3b is used as the gate insulating
film.
[0163] Although a large driving power is not required, in this type
of MOS QA, it is necessary to provide a long gate length. To this
end, the edge-to-edge distance of the gate electrode GA has to be
made long, and that would result in an increase in the resistivity.
An increase in the resistivity means an increase in the through
current, and that in turn causes the increase in the power
consumption of the flash memory (EEPROM). In Embodiment 1 of the
present invention, the gate electrode of a peripheral circuit MOS
is constructed by forming a stack of the conductive film 4 for the
floating gate electrode and the conductive film 6 for the control
gate electrode as in the memory cells MC and electrically
connecting these films via contact holes, however, when a same rule
is simply applied to the layout of the contact holes SC of the all
the MOSs for the peripheral circuits, the above problem would
occur. On the other hand, when attempting to solve this problem
without providing the contact holes SC, it would be difficult to
lay out the gate electrode GA and the contact holes CON1 for the
reduction in the resistivity of the gate electrode GA.
[0164] Accordingly, in Embodiment 1 of the present invention, in
this type of MOSQA, as exemplified in FIG. 15, a plurality of
contact holes SC are arranged at a given interval over the surface
of the gate electrode GA in a region which two-dimensionally
overlaps the active area LA along the direction in which the gate
electrode extends. In other words, the conductive film 6 and the
conductive film 4 are electrically connected through the contact
holes SC at a plurality of locations in region of the gate
electrode GA above the active area LA. In this embodiment, a
plurality of contact holes SC are also provided in the widened
sections at the both ends of the top surface of the gate electrode
GA where they are two-dimensionally overlap ped with the isolation
areas. In other words, the conductive film 6 and the conductive
film 4 are electrically connected through the contact holes SC also
at a plurality of locations in the widened sections. By arranging
the contact holes SC in this way (providing the contact holes SC in
the gate electrode GA mainly at the region which two dimensionally
overlaps the active area LA), the resistivity of the gate electrode
GA can be substantially reduced. Thus the generation of through
current due to resistivity increase of the gate electrode GA can be
suppressed or prevented, and this in turn, can suppress or prevent
the increase in the power consumption of the flash memory (EEPROM).
This also would make it easy to design the layout of such MOSs QA
including the contact holes CON1 and SC. That is, this would allow
an easier transition from circuit designing to devise
designing.
[0165] The diameter of the contact holes SC may be equal to that of
the contact holes CON1, however, they may be made larger than the
diameter of the contact holes CON1 in consideration of the
resistivity reduction and simpler manufacturing processes since it
is independent of the size of the memory cell. Although it is not
limited, the diameter of the contact holes SC may be in the order
of i.e. 0.3 .mu.m, and the diameter of the contact holes CON1 may
be in the order of i.e. 0.24 .mu. to 0.26 .mu.m. Also, exemplary
dimensions of respective components other than the above are as
follows although they are not limited. That is, the gate length of
the gate electrode GA may be in the order of 0.9 .mu.m to 1 .mu.m
and the gate width may be in the order of 5 .mu.m to 20 .mu.m.
[0166] FIG. 15 (a) illustrates an example in which two contact
holes SC are arranged on each widened end of the gate electrode GA
which two-dimensionally overlaps the isolation area, so as that
they are aligned in a direction orthogonal to the current flow. The
contact holes CON1 provided in the widened section of the gate
electrode GA for connecting the first-level wiring layer and the
gate electrode GA are arranged at locations in proximity of, or
that two-dimensionally overlap with, the contact holes SC provided
in the same widened section in order to minimize the area occupied
by the gate electrode GA and to reduce the resistivity. Also in the
semiconductor regions SA and DA of the MOS QA, contact holes CON1
are arranged in a manner that they two-dimensionally correspond to
the contact holes SC arranged in the region of the gate electrode
GA which overlaps the active area LA. The example shown in FIG. 15
(b) employs a so-called LDD (lightly doped drain) structure in
which the semiconductor regions SA and DA for the source and drain
are provided with regions containing relatively low concentrations
of impurities on the sides adjacent to the channel, and regions
containing relatively high concentrations of the impurities in
other locations.
[0167] Next, the MOS QB shown in FIG. 16 is a MOS representing the
one having a relatively short gate length (the dimension in the
horizontal direction in FIG. 16(a)) and a gate width (the dimension
in the vertical direction in FIG. 16(a)). This MOS QB is used as an
element for constituting a circuit having a relatively high
operation speed such as i.e. a logic circuit, control circuit or
output circuit. The example shown in 16 (b) uses the aforementioned
relatively thin insulating film 3a as the gate insulating film of
MOSQB for improving the operation speed by an increased driving
power.
[0168] In this type of MOS QB, a large driving power is required,
but the gate width may be short. In most cases, the gate width
itself may be shortened to an extent which would not cause narrow
channel effect (reverse short channel effect). Therefore, the
attention does not have to be paid for the resistivity increase of
the gate electrode GB as much as in the case of the gate electrode
GA of MOS QA. On the other hand, since the gate electrode GB
generally has a short gate length, the aforementioned arrangement
rule of the contact holes SC of the gate electrode GA cannot be
applied to this example as it is.
[0169] Accordingly, in Embodiment 1 of the present invention, in
this type of MOSQB, as exemplified in FIG. 16, contact holes SC are
provided, not in the region of the top surface of the gate
electrode GB which two-dimensionally overlaps the active area LB,
but in the widened sections which two-dimensionally overlap with
the isolation areas. That is, the conductive film 6 and the
conductive film 4 are electrically connected through the contact
holes SC at a plurality of locations on the gate electrode GB in
the regions above the isolation areas. By arranging the contact
holes SC in this way, the resistivity of the gate electrode GB may
be sufficiently reduced. Accordingly, the generation of through
current due to the increase in the resistivity of the gate
electrode GB may be suppressed or prevented, and this in turn,
suppress or prevent the increase in the power consumption of the
flash memory (EEPROM). This also would make it easier to design the
layout of the MOSs QB including the contact holes CON1 and SC. That
is, this would allow an easier transition from circuit designing to
devise designing.
[0170] In this example of MOS QB, two contact holes SC are provided
in each widened end of the gate electrode GB that two-dimensionally
overlaps the isolation area, so as that they are aligned in a
direction orthogonal to the direction of the current flow. The
diameters of the contact holes SC and CON1 in the MOSQB may be the
same as those in the priorly mentioned MOS QA. Although it is not
particularly limited, exemplary dimensions of the other components
may be given as follows. That is, the gate length of the gate
electrode GB may be in the order of i.e. 0.4 .mu.m to 0.5 .mu.m,
and the gate width may be in the order of i.e. 2 .mu.m to 10
.mu.m.
[0171] Again in FIG. 16 (a), the contact holes CON1 provided in the
widened sections of the gate electrode GB may be arranged at
locations in the proximity of, or that overlap with, the contact
holes SC provided in the widened sections in order to reduce the
resistivity. Here, regarding the semiconductor regions SSB and DB
for the source and drain, shown in FIG. 16 (b) is an example having
an LDD structure, as similar to the semiconductor regions SA and DA
as priorly mentioned.
[0172] FIG. 17 shows a modified version of the aforementioned MOS
QA. Here, a contact hole SC extends, in a continuous manner, across
almost the entire surface of the gate electrode GA in the direction
in which the gate electrode extends. In this way, the contact area
of the conductive film 4 and the conductive film 6 may be
increased, thus the resistivity of the gate electrode GA may
further be reduced. Also, since the area of the contact hole SC is
large, the formation of the hole can be performed in a easier
manner. In this example, two contact holes CON1 are shown as being
aligned so as to overlap two-dimensionally with a portion of the
contact hole SC within a widened section of the gate electrode GA
above the isolation area. The contact hole SC may be provided as a
hole which two-dimensionally extends across a region that overlaps
only the active area LA.
[0173] FIG. 18 shows another modified version of the aforementioned
MOS QA. In this example, the two-dimensional shape and the
dimensions of the gate electrode GA are identical to those of the
contact hole SC, but a contact hole SC is arranged so as that it
two-dimensionally overlaps and matches with the pattern of the gate
electrode GA. This would cause the conductive film 4 and the
conductive film 6 of the gate electrode GA to be stacked together
in a direct contact within the entire plane of the each film. Since
this would allow further increase in the contact area between the
conductive film 4 and the conductive film 6, the resistivity of the
gate electrode GA can be substantially reduced. This structure may
be implemented in only the MOS QA or in both the MOS QA and MOS QB.
The formation method of such the structure will be explained
according to Embodiment 2.
[0174] FIG. 19 shows still another modified version of the
aforementioned MOS QA. In this example, the two-dimensional layout
is identical to that in FIG. 15 (a), but in its cross-section, as
shown in FIG. 19 (b), the structure has the contact holes SC that
are provided through the conductive film 6a of the conductive film
6 and the interlayer film 5, thereby electrically connecting the
conductive film 6b above the conductive film 6a to the conductive
film 4 via the contact holes SC. That is, in this example, after
the deposition of the conductive film 6a over the interlayer film
5, the contact hole SC is formed by a dry etching method using a
photo resist pattern as an etching mask. In this way, the photo
resist pattern for forming the contact hole SC would not be brought
into a direct contact with the interlayer film 5 during the
formation of the contact holes SC, so that the contamination of the
interlayer film 5 which contributes to the storage function of the
memory cell MS may substantially be reduced. Accordingly, since the
risk of failures or the degradation of reliability due to such
contamination may be reduced, the yield and the reliability of the
flash memory (EEPROM) may be improved.
[0175] Next, shown in FIG. 20 is an exemplary structure of the nMOS
Qopn1 for protecting the above-explained output circuit according
to Embodiment 1 of the present invention. As priorly explained, in
Embodiment 1, the structure of the protective NMOS Qopn1 is almost
identical to that of the memory cells MC of the flash memory
(EEPROM). This means that, a highly protective nMOS Qopn1 may be
obtained by forming this protective element in the same structure
as the memory cells which can provide a high electrostatic
breakdown resistivity as it inherently has a low withstand voltage
(of drain edge). One example may be given as follows.
[0176] A p-type well PWo is formed in a semiconductor substrate 1,
and within this region, the above-mentioned protective nMOS Qopn1
is formed. The protective nMOS Qopn1 comprises a pair of n-type
semiconductor regions 13 for the source and drain, an insulating
film 3a and a gate electrode 14. In the example shown, there are
two gate electrodes 14 two-dimensionally overlapping one active
area LO, and the middle semiconductor region 13 serves as a common
region for the nMOSs Qopn1 on the left and right.
[0177] The pair of the n-type semiconductor regions 13 of the
protective nMOS Qopn1 are formed by introducing i.e. arsenic, and
they are formed during the same impurity doping process as the pair
of the n-type semiconductor regions 2S, 2D of the memory cells MC.
Therefore, the impurity profile of the n-type semiconductor regions
13 is the same as that of the n-type semiconductor regions 2S, 2D
of the memory cells MC.
[0178] Similarly, the p-type well PWo is formed during the same
impurity doping process as the p-type well PWm of the memory cells
MC, so that it has the same impurity profile as that of the p-type
well PWm. Over this p-type well PWo, a p.sup.+-type semiconductor
region 15 is formed. This P.sup.+-type semiconductor region 15
having a band-like two-dimensional shape is formed so as that it
extends along a direction parallel to the direction in which the
gate electrode 14 extends. A plurality of contact holes CON1
connecting the first-level wiring layer L1 and the p.sup.+-type
semiconductor region 15 are aligned along the direction the
p.sup.+-type semiconductor region 15 extends. The potential to the
p-type well PWo is applied through the p.sup.+-type semiconductor
region 15.
[0179] The gate electrode 14 is constructed by over-laying a
conductive film 6 for forming a control gate electrode on the
conductive film 4 for forming a floating gate electrode via an
interlayer film 5 in the manner fundamentally similar to that of
the memory cells MC, and the conductive film 4 is formed to have a
T-shape in its cross section in the same way as the memory cells
MC. However, in the protective nMOS Qopn1, the conductive film 4
and the conductive film 6 of the gate electrode 14 are electrically
connected through contact holes SC. The example shown in FIG. 20
(a) is illustrated as having the contact holes SC provided in the
widened sections at the both ends of the gate electrode 14, which
two-dimensionally overlap with the isolation areas, however, they
may be arranged as illustrated in FIGS. 15, 17, 18 or 19. The
contact holes CON1 electrically connecting the first-level wiring
layer L1 and the gate electrode 14 are disposed so as to
two-dimensionally overlap and match the locations of the contact
holes SC. In this way, the minimization of the area occupied by the
gate electrode 14 and the reduction of the resistivity may be
attempted. Between a portion of the conductive film 4 of the gate
electrode 14 and the semiconductor substrate 1, an insulating film
7 is interposed in the similar manner as in the memory cells MC.
Over the top surface of the gate electrode 14, a cap insulating
film 8 is formed, and over the side surfaces thereof, an insulating
film 12a is formed. The plurality of contact holes CON1 for
electrically connecting the first-level wiring layer L1 and the
n-type semiconductor region 13 are arranged side by side along the
direction in which the gate electrode 14 extends.
[0180] Next, shown in FIGS. 21 and 22 is an exemplary structure of
a capacitor element incorporated in a part of the flash memory
(EEPROM) of Embodiment 1. FIG. 22 is a cross-sectional view of FIG.
21 taken along the line A-A.
[0181] The capacitor element C is constructed by providing an upper
electrode 17 over a p-type well PWc of a semiconductor substrate 1
via an insulating film 3a (or an insulating film 3b). In the
semiconductor substrate 1, two active areas LC, LC are arranged via
a trench-type isolation area SGI. The p-type well PWc within the
active area LC constitutes a lower electrode of the capacitor
element C. The active area LC is divided into two areas in order to
reduce the resistivity of the lower electrode (p-type well PWc) and
also for the convenience of the layout of contact holes CON1b for
the upper electrode 17 which will be later described. In the top
portion of this p-type well PWc at locations near the edges of the
bottom of the upper electrode 17, P.sup.--type semiconductor
regions 18a and p.sup.+-type semiconductor regions 18b are formed.
To the P.sup.--type semiconductor regions 18a and p.sup.+-type
semiconductor regions 18b, boron, for example, has been doped. The
P.sup.+-type semiconductor regions 18b are formed at locations
separated from the edges of the bottom of the top electrode 17
farther than the locations of P.sup.--type semiconductor regions
18a by the width of the insulating film 12a. These p.sup.+-type
semiconductor regions 18b are electrically connected with the
first-level wiring layer L1 through contact holes CON1a provided in
the insulating film 12b. A plurality of the contact holes CON1a are
arranged side by side along the longitudinal sides of the top
electrode 17.
[0182] The insulating film 3a (or 3b) of the capacitor element C
forms a capacitance insulating film of the capacitor element C. In
Embodiment 1 of the present invention, this capacitor element C
also has a similar structure as that of the memory cells MC. That
is, its upper electrode 17 is constructed by electrically
connecting the conductive film 4 for the floating gate electrode of
the memory cell MC and the conductive film 6 for the control gate
electrode of the memory cell MC provided thereon via the insulating
film 5, through the contact holes SC opened in the interlayer film
5. A plurality of the contact holes SC are arranged side by side
along the direction of the width of the upper electrode 17 over
column lines that are arranged at a given interval in a
longitudinal direction of the upper electrode 17. The contact holes
SC are provided both over the active area LC of the semiconductor
substrate 1 that constitutes the lower electrode and over the
trench-type isolation area SGI between the adjacent active areas
LC.
[0183] This upper electrode 17 is electrically connected to the
first-level wiring layer L1 through the contact holes CON1b
provided within the insulating film 12b. These contact holes CON1b
are not provided over the active areas LC, but provided only over
the trench-type isolation section (isolation area) SGI between the
adjacent active areas LC. This is because of, for example, the
following reason. That is, these contact holes CON1b are formed in
the same process as the priorly-mentioned contact holes CON1a, so
that it is possible that the contact holes CON1b are to be formed
excessively deep while the contact holes CON1a are perforated since
the contact holes CON1a have to be deeper than the contact holes
CON1b. Accordingly, the contact holes CON1b are provided over the
trench-type isolation section (isolation area) SGI so that such
excessive deepening would not cause the failure of the capacitor
element C. For the purpose of the explanation, here, the contact
holes CON1 are described as being the separate contact holes CON1a
and CON1b, however, these contact holes CON1a and CON1b are
substantially identical to the contact holes CON1.
[0184] Such a capacitor element C is used in i.e. a booster circuit
(charge pump circuit), and a delay circuit etc. When the capacitor
element C is used in a booster circuit, since that would form a
high voltage of i.e. 3.3V to 18V, it is preferable to use the
relatively thick insulating film 3b as the capacitance insulating
film. On the other hand, when the capacitor element C is used in a
delay circuit of a logic circuit etc., a relatively thin insulating
film 3a may be used as the capacitance insulating film since only a
low voltage would be applied.
[0185] The contact holes SC may also be provided only at locations
that two-dimensionally overlap with the active areas LC, or only at
locations that two-dimensionally overlap with the isolation section
SGI.
[0186] In the following, one example of the manufacturing method of
the flash memory (EEPROM) of Embodiment 1 will be explained.
[0187] FIGS. 23 through 25 are diagrams of the flash memory
(EEPROM) of Embodiment 1 during manufacturing processes. FIG. 23 is
a schematic plan view of the section corresponding to the one shown
in FIG. 7. FIG. 24 is a schematic cross-sectional view including
the memory array MARY and peripheral circuit region of the flash
memory (EEPROM), and the view of the memory array shown here
corresponds to an A-A cross section of FIG. 7. FIG. 25 corresponds
to a B-B cross section of FIG. 7. The Vpp NMOS and PMOS are the
MOSs for forming the peripheral circuits in a high-voltage-system
using a relatively high driving voltage in the order of, for
example, 8V. The Vcc NMOS and PMOS are the MOSs for forming
peripheral circuits in a low-voltage-system using a relatively low
driving voltage in the order of, for example, 1.8V to 3.3V. Such
conditions are assumed also in the subsequent figures.
[0188] First as shown in FIGS. 23 through 25, trench-type isolation
areas SGI, and active areas Lm etc. surrounded by the isolation
areas SGI are formed in the principal surface of a semiconductor
substrate 1 (at this point of time, this is a semiconductor thin
plate having a circular two-dimensional shape, called a
semiconductor wafer). That is, after forming the isolation trenches
at given locations of the semiconductor substrate 1, an insulating
film made of i.e. silicon oxide is deposited over the principal
surface of the semiconductor substrate 1, and by polishing it by a
chemical mechanical polish (CMP) method etc. so as to leave the
insulating film only within the isolation trenches, the isolation
areas SGI are formed.
[0189] Next, by selectively doping given impurities to the given
sections of the semiconductor substrate 1 at given energies by an
ion implantation method etc., an embedded n-type well NWm, p-type
well PWm, p-type wells NWp1, PWp2 and n-type wells NWp1, NWp2 are
formed.
[0190] FIG. 26 is a schematic cross-sectional view of the section
shown in FIG. 24 during a subsequent manufacturing process, and
FIG. 27 is a schematic cross-sectional view of the section shown in
FIG. 25 during the subsequent manufacturing process. Herein, two
types of insulating films 3a and 3b having different thicknesses
are formed as shown in FIGS. 26 and 27, for example, in the
following manner.
[0191] First, over the principal surface of the semiconductor
substrate 1, an insulating film having a large thickness in the
order of, for example, 20 nm is formed through a thermal oxidation
method etc. This is followed by the formation of a photo resist
pattern which exposes a memory array region and low-voltage MOS
regions (exemplarily indicated as Vcc PMOS and Vcc NMOS) on the
thick insulating film and covers all other regions, and the exposed
portions of the thick insulating film are etched away via a wet
etch method etc. using the photo resist pattern as the etching
mask. Thereafter, the photo resist pattern is eliminated, and a
thermal oxidation treatment is then performed over the
semiconductor substrate 1 for forming a tunnel oxide film on the
memory array. In this way, the relatively thin gate insulating film
3a having a thickness in the order of i.e. 9 nm is formed in the
memory array region (including short MOS region) and the
low-voltage MOS regions, and the relatively thick insulating film
3b having a thickness in the order of i.e. 25 nm is formed in the
high-voltage MOS regions (exemplarily indicated as Vpp PMOS and Vpp
NMOS) and the selection MOS region.
[0192] FIG. 28 is a schematic plan view of the same section as that
shown in FIG. 23 during a subsequent manufacturing process, FIG. 29
is a schematic cross-sectional view of the same section as that
shown in FIG. 24 during the subsequent manufacturing process, and
FIG. 30 is a schematic cross-sectional view of the same section as
that shown in FIG. 25 during the subsequent manufacturing
process.
[0193] Over the principal surface of the semiconductor substrate 1,
a conductive film 4a made of polycrystalline silicon having a low
resistivity in a thickness in the order of i.e. 70 nm, and an
insulating film 19 made of silicon nitride etc. are sequentially
formed from the bottom by a CVD method etc., and by processing the
insulating film 19 and the conductive film 4a by photolithographic
and dry-etching techniques, the conductive film 4a which forms the
floating gate electrodes (first gate electrodes) is patterned in
the memory array. At this time, the peripheral circuit region
(high-voltage MOS regions, low-voltage MOS regions, and selection
MOS region etc.) is being entirely covered by the conductive film
4a and the insulating film 19. Thereafter, by introducing an
impurity (i.e. arsenic) for forming the drain and source of the
memory cells in the semiconductor substrate 1 through an ion
implantation method, pairs of n-type semiconductor regions 2S and
2D (local source lines SS and sub-bit lines SB) are formed. At this
point, the high-voltage MOS regions, low-voltage MOS regions and
selection MOS region etc. are being covered by the conductive film
4a. In this way, the gate length of the short MOSs can be
determined only by the conductive film 4a.
[0194] FIG. 31 is a schematic cross-sectional view of the same
section as that shown in FIG. 24 during a subsequent manufacturing
process, and FIG. 32 is a schematic cross-sectional view of same
the section as that shown in FIG. 25 during the subsequent
manufacturing process. In this process, after depositing an
insulating film 7 made of, for example, silicon oxide, over the
principal surface of the semiconductor substrate 1 via a CVD
method, this insulating film 7 is polished by a CMP method so as
that the insulating film 7 is left within the recesses in the
principal surface of the semiconductor substrate 1, and it is
further etched by a dry etching method. In this way, the principal
surface of the semiconductor substrate 1 is made flat. This would
also prevent the conductive film for the later-described floating
gate electrode to be deposited thereon from being connected with
the n-type semiconductor regions 2S and 2D forming the sources and
drains of the memory cells. At this point, the insulating film 19
is also eliminated, and this serves to protect the layer below.
[0195] FIG. 33 is a schematic plan view of the same section as that
shown in FIG. 23 during a subsequent manufacturing process, FIG. 34
is a schematic cross-sectional view of the same section as that
shown in FIG. 24 during the subsequent manufacturing process, and
FIG. 35 is a schematic cross-sectional view of the same section as
that shown in FIG. 25 during the subsequent manufacturing
process.
[0196] After depositing a conductive film 4b made of i.e.
polycrystalline silicon having a low resistivity in a thickness in
the order of 40 nm over the principal surface of the semiconductor
substrate 1, a photo resist pattern PR1 is formed thereon by a
photolithographic technique, and by eliminating the exposed
portions of the conductive film 4b through a dry etching method
etc. using the photo resist pattern as the etching mask, floating
gate electrodes constituted by the conductive films 4a and 4b are
formed. In the photolithography (exposure process) for the
formation of the photo resist pattern PR1, a phase-shift mask
(half-tone mask) is used to minimize the spacing between adjacent
portions of the conductive film 4b. It is so done in order to
improve the coupling ratio between the floating gate electrodes and
the control gate electrodes (second gate electrodes) by maximizing
the area of the conductive film 4b by making the spacing S between
adjacent portions of the conductive film 4b as narrow as possible
so as to be able to satisfy the given rewrite characteristic
requirement even if the memory cells are further miniaturized in
the memory array regions. At this point of time, the high-voltage
MOS regions, low-voltage MOS regions, short MOS region and
selection MOS region are entirely covered by the conductive film
4b.
[0197] FIG. 36 is a schematic plan view of the same section as that
shown in FIG. 23 during a subsequent manufacturing process, FIG. 37
is a schematic cross-sectional view of the same section as that
shown in FIG. 24 during the subsequent manufacturing process, and
FIG. 38 is a schematic cross-sectional view of the same section as
that shown in FIG. 25 during the subsequent manufacturing
process.
[0198] In this process, an interlayer film 5 (second insulating
film) is formed in a thickness in the order of, for example, 15 nm
by sequentially depositing by CVD method i.e. a silicon oxide film,
a silicon nitride film and a silicon oxide film from the bottom
over the semiconductor substrate 1, and thereon, a photo resist
pattern PR2 for the formation of the contact holes SC is then
formed by a photolithographic technique. Thereafter, by eliminating
the exposed portions of the interlayer film 5 by a dry etching
method using this photo resist pattern PR2 as the etching mask,
contact holes SC are formed within the interlayer film 5. In FIG.
36, the contact holes SC in the upper row are provided over the
gate electrode formation regions of the selection MOSs, and the
contact holes SC in the lower row are provided over the gate
electrode formation regions of the short MOSs. In FIG. 37, there is
no indication of the contact holes SC over the high-voltage MOS
regions and the low-voltage MOS regions, but the contact holes SC
exposing the portions of the conductive film 4b are formed over the
gate electrode formation regions of those MOSs at the locations
that are not shown in the cross section of FIG. 37.
[0199] FIG. 39 is a schematic plan view of the same section as that
shown in FIG. 23 during a subsequent manufacturing process, FIG. 40
is a schematic cross-sectional view of the same section as that
shown in FIG. 24 during the subsequent manufacturing process, and
FIG. 41 is a schematic cross-sectional view of the same section as
that shown in FIG. 25 during the subsequent manufacturing
process.
[0200] In this process, a conductive film 6a made of, for example,
polycrystalline silicon having a low resistivity, a conductive film
6b made of tungsten silicide etc., and a cap insulating film 8 made
of silicon oxide etc. are sequentially deposited on the
semiconductor substrate 1 from the bottom by a CVD method etc., and
thereafter, these films are patterned by photolithographic and dry
etching techniques. In this manner, control gate electrodes (word
lines) are formed in the memory array region, and in any other
regions (the high-voltage MOS regions, low-voltage MOS regions,
short MOS region and selection MOS region), portions of the gate
electrodes of the respective MOSs are formed. In this etching
process, the interlayer film 6 functions as an etching stopper. In
Embodiment 1 of the present invention, there is no step between the
memory array region and the peripheral circuit region, so that the
word lines W may be formed with a small pitch.
[0201] FIG. 42 is a schematic cross-sectional view of the same
section as that shown in FIG. 24 during a subsequent manufacturing
process, and FIG. 43 is a schematic cross-sectional view of the
same section as that shown in FIG. 25 during the subsequent
manufacturing process. In this process, using the cap insulating
film 8 and the conductive film 6 as an etching mask, the interlayer
film 5 and the conductive films 4b and 4a are etched away by a dry
etching method etc.
[0202] In this way, within the memory array region, the control
gate electrodes and the floating gate electrodes for the memory
cells MC are formed, in other words, the double-level gate
electrode structure is completed, in which the conductive film 6
for the control gate electrode is formed over the conductive film 4
for the floating gate electrode via the interlayer film 5. The
floating gate electrode and the control gate electrode of each
memory cell MC are completely insulated.
[0203] In the peripheral circuit region, (low-voltage MOS regions,
high-voltage MOS regions, short MOS region and selection MOS
region), the gate electrodes 20n, 20p, 21n, 21p, 9, 10 of the
respective MOSs are formed. In each of the gate electrodes 20n,
20p, 21n, 21p, 9, 10, the conductive film 4 and the conductive film
6 are electrically connected through a contact hole SC.
[0204] FIG. 44 is a schematic cross-sectional view of the same
section as that shown in FIG. 24 during a subsequent manufacturing
process, and FIG. 45 is a schematic cross-sectional view of the
same section as that shown in FIG. 25 during the subsequent
manufacturing process. Here, the semiconductor regions 22na, 22pa,
23na, 23pa, 11na of the respective MOSs, which include relatively
low concentrations of impurities, are formed separately. To the
semiconductor regions 11na, 22na, 23na, i.e. arsenic is doped, and
to the semiconductor regions 22pa, 23pa, i.e. boron is doped. This
is followed by the deposition of an insulating film made of i.e.
silicon oxide over the principal surface of the semiconductor
substrate 1 by a CVD method, and by etching back this film by an
anisotropic dry etching method, the insulating film 12a is left on
the side surfaces of the gate electrodes 20n, 20p, 21n, 21p, 9, 10.
The spaces between adjacent word lines W are filled with this
insulating film 12a.
[0205] FIG. 46 is a schematic cross-sectional view of the same
section as that shown in FIG. 24 during a subsequent manufacturing
process, and FIG. 47 is a schematic cross-sectional view of the
same section as that shown in FIG. 25 during the subsequent
manufacturing process. Here, the semiconductor regions 22nb, 22pb,
23nb, 23pb, 11nb of the respective MOSs, which include relatively
high concentrations of impurities, are separately formed. To the
semiconductor regions 11nb, 22nb, 23nb, i.e. arsenic is doped, and
to the semiconductor regions 22pb, 23pb, i.e. boron is doped. In
this way, the pairs of n-type semiconductor regions 11, 22n, 23n
and the pairs of p-type semiconductor regions 22p, 23p are formed
for the use as the sources and drains of the nMOSs QLn and pMOSs
QLp in the low-voltage system, nMOSs QHn and pMOSs QHp in the
high-voltage system, and the selection MOSs N1, N3.
[0206] FIG. 48 is a schematic plan view of the same section as that
shown in FIG. 23 during a subsequent manufacturing process, FIG. 49
is a schematic cross-sectional view of the same section as that
shown in FIG. 24 during the subsequent manufacturing process, and
FIG. 50 is a schematic cross-sectional view of the same section as
that shown in FIG. 25 during the subsequent manufacturing process.
Here, an insulating film 12b made of silicon oxide, for example, is
deposited over the semiconductor substrate 1 by a CVD method etc.,
and in this insulating film 12b, contact holes CON1 are formed
through photolithographic and dry etching techniques so as to
expose the portions of the semiconductor substrate 1 (the source
and drain regions of the respective MOSs), the portions of the word
lines, and the portions of the gate electrodes of specific MOSs.
Over this semiconductor substrate 1, a metal film made of tungsten,
for example, is deposited by a sputtering method etc., and this is
then patterned by photolithographic and dry etching techniques to
form a first-level wiring layer L1 (including the common source
line). The first-level wiring layer L1 is electrically connected,
accordingly, with the pairs of the semiconductor regions serving as
the sources and drains of the respective MOSs, the gate electrodes
and the word lines W via the contact holes CON1.
[0207] FIG. 51 is a schematic plan view of the same section as that
shown in FIG. 23 during a subsequent manufacturing process, FIG. 52
is a schematic cross-sectional view of the same section as that
shown in FIG. 24 during the subsequent manufacturing process, and
FIG. 53 is a schematic cross-sectional view of the same section as
that shown in FIG. 25 during the subsequent manufacturing process.
Here, an insulating film 12c made of silicon oxide, for example, is
deposited over the semiconductor substrate 1 by a CVD method etc.,
and in this insulating film 12c, through holes TH1 are formed using
photolithographic and dry etching techniques so as to expose the
portions of the first-level wiring layer L1. Over this
semiconductor substrate 1, a metal film made of tungsten, for
example, is deposited by a spattering method or a CVD method etc.,
and this film is then polished by a CMP method etc. so as to leave
the metal film only within the through holes TH1 to form plugs 24
in the through holes TH1. Thereafter, i.e. titanium nitride,
aluminum and titanium nitride are sequentially deposited on the
semiconductor substrate 1 from the bottom via a sputtering method
etc., and by patterning these films using photolithographic and dry
etching techniques, a second-level wiring layer L2 (including the
main bit lines) is formed. The second-level wiring layer L2 is
electrically connected with the first-level wiring layer L1 through
the plugs 24.
[0208] FIG. 54 is a schematic cross-sectional view of the same
section as that shown in FIG. 24 during a subsequent manufacturing
process, and FIG. 55 is a schematic cross-sectional view of the
same as that section shown in FIG. 25 during the subsequent
manufacturing process. Here, an insulating film 12d made of silicon
oxide, for example, is deposited over the semiconductor substrate 1
by a CVD method etc., and through holes TH2 are formed within this
insulating film 12d in the same manner as the through holes TH1 so
as to expose the portions of the second-level wiring layer L2. This
is followed by the formation of plugs 25 made of tungsten etc.
within the through holes TH2 in the same manner as the plugs 24,
and a third-level wring layer L3 is formed over the semiconductor
substrate 1 by sequentially depositing the films of, for example,
titanium nitride, aluminum and titanium nitride in the same manner
as the second-level wiring layer L2. The third-level wiring layer
L3 is in electrical connection with the second-level wiring layer
L2 through the plugs 25. There after, a surface protection film is
formed over the semiconductor substrate 1, and openings are formed
in the portions of the protection film so as to expose the portions
of the third-level wiring layer L3 to form bonding pads, thereby
completing the flash memory (EEPROM).
[0209] The major effects provided by Embodiment 1 of the present
invention are as follows.
[0210] (1) By employing the same gate electrode structure as the
memory cells MC for the gate electrode structure of the peripheral
circuit MOSs of the flash memory (EEPROM), the formation of a step
at the boundary between the peripheral circuit region and the
memory cell region may be prevented when the word lines of the
memory cells MC are formed.
[0211] (2) Since the spacing between adjacent word lines W may be
minimized due to the effect of (1), the area of the memory array
regions can be redued and the miniaturization of the size of the
semiconductor chip may be further advanced.
[0212] (3) By employing the same gate electrode structure as the
memory cells MC for the gate electrode structure of the peripheral
circuit MOSs, and for those MOSs having a long gate length (i.e.
high-voltage MOS), by providing contact holes SC for connecting the
conductive films 4 and 6 within the plane of the gate electrode
also at the locations over the active areas, the resistivity of the
gate electrodes of those MOSs may be reduced.
[0213] (4) By the effect of (3), the power consumption of the flash
memory (EEPROM) may be reduced.
[0214] (5) By varying the layouts of the contact holes SC for
connecting the conductive films 4 and 6 according to the types of
the MOSs arranged over the semiconductor substrate 1, the layouts
of the respective patterns (i.e. contact holes CON1) of the MOSs
may be designed more easily.
[0215] (6) By varying the layout of the contact holes SC for
connecting the conductive films 4 and 6 according to the types of
the MOSs arranged over the semiconductor substrate 1, the device
may be designed without incurring inconveniences for the circuitry,
so that the transition from the circuit designing to the device
designing can be made more easily.
[0216] (7) By arranging the contact holes CON1 for connecting the
first-level wiring layer L1 and the p.sup.+-type semiconductor
regions 18b over the isolation areas when the gate electrode
structure of the memory cells MC is employed for the capacitor
elements formed over the semiconductor substrate 1, the occurrence
of failures in the capacitor elements may be minimized.
[0217] (8) Due to the effect of (7), the yield and the reliability
of the flash memory (EEPROM) may be improved.
[0218] [Embodiment 2]
[0219] Embodiment 2 of the present invention is provided for
illustrating a manufacturing method for forming the structure shown
in FIG. 18 that has been explained according to Embodiment 1.
[0220] FIGS. 56 and 57 illustrating Embodiment 2 of the present
invention are schematic cross-sectional views of the semiconductor
substrate 1 after being processed through the manufacturing
processes explained with reference to FIGS. 23 through 35 in
Embodiment 1. FIG. 56 shows a schematic cross-sectional view of the
same section as that shown in FIG. 24 during a process subsequent
to the process of FIG. 35, and FIG. 55 shows a schematic
cross-sectional view of the same section as that shown in FIG. 25
during a process subsequent to the process of FIG. 35.
[0221] Here, as priorly mentioned, after the interlayer 5 is formed
over the semiconductor substrate 1, a photo resist pattern PR3 is
formed thereon. This photo resist pattern PR3 is formed in a manner
so as to entirely cover the memory cell formation region, but to
cover only the area other than particular portions (contact hole SC
formation regions) in the gate electrode formation region of the
short MOSs. The photo resist pattern PR3 is formed so as to leave
any other peripheral circuit regions uncovered. Next, using this
photo resist pattern PR3 as an etching mask, the exposed portions
of the interlayer film 5 are etched off. In this way, the contact
holes SC are formed in the short MOS region, and the surface of the
conductive film 4b is entirely exposed in the other peripheral
circuit regions. The photo resist pattern PR3 is then removed.
[0222] FIG. 58 is a schematic cross-sectional view of the same
section as that shown in FIG. 24 during a subsequent manufacturing
process, and FIG. 59 shows a schematic cross-sectional view of the
same section as that shown in FIG. 25 during the subsequent
manufacturing process. Here, the conductive film 6 and a cap
insulating film 8 are sequentially deposited from the bottom over
the semiconductor substrate 1 by a CVD method etc., and a photo
resist pattern for the formation of the gate electrodes and the
word lines is formed over the cap insulating film 8. After
patterning the cap insulating film 8 using this photo resist
pattern, the photo resist pattern is eliminated. Using the
remaining cap insulating film 8 as an etching mask, the conductive
films 6 and 4 are patterned, thereby forming the double-level gate
electrodes of the memory cells MC and the gate electrodes 9, 10,
20n, 20p, 21n, 21p of the respective peripheral circuit MOSs. In
Embodiment 2, the conductive film 4 and the conductive film 6 in
the gate electrodes 10, 20n, 20p, 21n, 21p are electrically
connected, being in direct contact across the entire plane of the
gate electrode pattern. Accordingly, the resistivity of the gate
electrodes 10, 20n, 20p, 21n and 21p may be further reduced. In
this etching process, the cap insulating film 8 and the insulating
films 3a and 3b made of silicon oxide are utilized as an etching
stopper.
[0223] FIG. 60 shows a schematic cross-sectional view of the same
section as that shown in FIG. 24 during a subsequent manufacturing
process, and FIG. 61 shows a schematic cross-sectional view of the
same section as that shown in FIG. 25 during that subsequent
manufacturing process. Here, after forming a photo resist pattern
PR4 over the semiconductor substrate 1 so as to cover the areas
other than the intervals between adjacent word lines W by a
photolithographic technique, and using this as a mask, by
performing ion implantation of i.e. boron into the semiconductor
substrate 1, punch through stoppers are formed for the word lines W
arranged adjacently to each other over the semiconductor substrate
1. Since the subsequent processes are identical to those explained
with reference to FIGS. 44 and later of Embodiment 1, the detailed
descriptions thereof will be omitted.
[0224] [Embodiment 3]
[0225] Embodiment 3 of the present invention is provided for
illustrating a manufacturing method when providing the protective
MOS shown in FIG. 20 explained according to Embodiment 1.
[0226] First, as shown in FIG. 62, after forming the trench-type
isolation sections SGI and active areas Lm (refer FIG. 23) in the
principal surface of the semiconductor substrate 1 in the same
manner as Embodiment 1, the embedded n-type well NWm, p-type well
PWm, p-type wells PWp2, PWo and n-type well NWp2 are formed by
selectively doping particular impurities with a given energy within
given sections of the semiconductor substrate 1 by an ion
implantation method etc. FIG. 62 is a schematic cross-sectional
view of the semiconductor substrate 1 during the same manufacturing
process of FIG. 24, showing the same section as that shown in FIG.
24 except for the protective MOS formation region (Vcc MSDMOS).
Those figures later than FIG. 62 used in Embodiment 3 are
cross-sectional views of the same section as that shown FIG. 62,
but in different manufacturing processes. The cross-sectional view
corresponding to the section taken along the line B-B of FIG. 7
during the manufacturing process of FIG. 62 is identical to that
shown in FIG. 25.
[0227] As shown in FIG. 63, a relatively thin insulating film 3a
and a relatively thick insulating film 3b are formed over the
principal surface of the semiconductor substrate 1 in the same
manner as Embodiment 1. Within the protective MOS formation region,
the thin insulating film 3a is formed. The cross-sectional view
corresponding to the section taken along the line B-B of FIG. 7
during the manufacturing process of FIG. 63 is identical to that
shown in FIG. 27.
[0228] Thereafter, as shown in FIG. 64, the patterns of the
conductive film 4 and the insulating film 19 are formed over the
principal surface of the semiconductor substrate 1 in the same
manner as Embodiment 1. Here, in the protective MOS formation
region, the conductive film 4a is patterned in the shape of the
gate electrode, so as to expose the sources and drains of the
protective MOSs. Other than this region, the conductive film 4a is
patterned in the same manner as Embodiment 1. The impurity (i.e.
arsenic) for the formation of the sources and drains of the memory
cells is doped into the source and drain regions of the memory
cells and the source and drain regions of the protective MOSs in
the semiconductor substrate 1 by an ion implantation method etc. to
form the pairs of the n-type semiconductor regions 2S, 2D (local
source lines SS and sub-bit lines SB) for forming the sources and
drains of the memory cells and pairs of n-type semiconductor
regions 13, 13 for forming the sources and drains of the protective
MOSs. In other words, in Embodiment 3, the n-type semiconductor
regions 13, 13 forming the sources and drains of the protective
MOSs are formed in conjunction with the formation of the pairs of
n-type semiconductor regions 2S, 2D forming the sources and drains
of the memory cells, using the same impurity. This means that the
impurity concentration profile of the arsenic in the n-type
semiconductor regions 13 forming the sources and drains of the
protective MOSs is identical to that of the n-type semiconductor
regions 2S, 2D forming the sources and drains of the memory cells.
Other than that, the process is identical to Embodiment 1. The
cross-sectional view corresponding to the section taken along the
line B-B of FIG. 7 during the manufacturing process of FIG. 64 is
identical to that shown in FIG. 30.
[0229] Next, as shown in FIG. 65, an insulation film 7 is formed in
a recess on the principal surface of the semiconductor substrate 1
in the same manner as embodiment 1. The cross-sectional view
corresponding to the section taken along the line B-B of FIG. 7
during the manufacturing process of FIG. 65 is identical to that
shown in FIG. 32.
[0230] Next as shown in FIG. 66, after depositing a conductive film
4b over the semiconductor substrate 1 in the same manner as
Embodiment 1, this conductive film 4b is patterned using a photo
resist pattern PR1 to form the floating gate electrodes constituted
by the conductive films 4a and 4b. At this point, the high-voltage
MOS regions, protective MOS region, short MOS region and the
selection MOS region etc. are entirely covered by the conductive
film 4b. The cross-sectional view corresponding to the section
taken along the line B-B of FIG. 7 during the manufacturing process
of FIG. 66 is identical to that shown in FIG. 35.
[0231] Next, as shown in FIG. 67, after forming an interlayer film
5 over the semiconductor substrate 1 in the same manner as
Embodiment 1, using the photo resist pattern PR2 formed thereon as
an etching mask, the exposed portions of the interlayer film 5 are
eliminated by a dry etching method etc. to form contact holes SC
within the interlayer film 5. In FIG. 67, although there is no
indication of contact holes SC in the high-voltage MOS regions and
the protective MOS region, there are contact holes formed over the
gate electrode formation regions of those MOSs, exposing the
portions of the conductive film 4b, that are located in the
positions that cannot be seen from the cross-sectional view of FIG.
67. The cross-sectional view corresponding to the section taken
along the line B-B of FIG. 7 during the manufacturing process of
FIG. 67 is identical to that shown in FIG. 38.
[0232] Thereafter, as shown in FIG. 68, conductive films 6a and 6b
and a cap insulating film 8 are sequentially deposited from the
bottom over the semiconductor substrate 1 by a CVD method etc. in
the same manner as Embodiment 1, and they are then patterned using
photolithographic and dry etching techniques. This process forms
the control gate electrodes (word lines W) in the memory array, and
portions of the gate electrodes of respective MOSs in other regions
including the high-voltage MOS regions, protective MOS region,
short MOS region and selection MOS region etc. Again in this
Embodiment 3, there is no step formed between the memory array
region and the peripheral circuit region, so that the word lines W
may be processed with a small pitch. The cross-sectional view
corresponding to the section taken along the line B-B of FIG. 7
during the manufacturing process of FIG. 68 is identical to that
shown in FIG. 41.
[0233] Next, as shown in FIG. 69, using the cap insulating film 8
and the conductive film 6 as an etching mask, the interlayer film 5
and the conductive films 4b and 4a thereunder are etched away by a
dry etching method etc. in the same manner as Embodiment 1. This
process completes the control gate electrodes and floating gate
electrodes of the memory cells MC in the memory array. And at the
same time, in the peripheral circuit region (high-voltage MOS
region, protective MOS region, short MOS region and selection MOS
region), the gate electrodes 21n, 21p, 14, 9 and 10 are completed.
In each of the gate electrodes 21n, 21p, 14, 9 and 10 of respective
MOSs, the conductive film 4 and the conductive film 6 are in
electrical connection via a contact hole SC. In this manner, the
protective nMOS Qopn1 are formed. The cross-sectional view
corresponding to the section taken along the line B-B of FIG. 7
during the manufacturing process of FIG. 69 is identical to that
shown in FIG. 43.
[0234] Next, as shown in FIG. 70, semiconductor regions 23na, 23pa,
11na (see FIG. 45) of the respective MOSs having relatively low
concentrations of impurities are formed respectively by separate
impurity doping processes using different photo resist patterns as
masks, and an insulating film 12a is then formed on the side
surfaces of the gate electrodes 14, 21n, 21p, 9 and 10 in the same
manner as Embodiment 1. The intervals between the adjacent word
lines W are filled with this insulating film 12a. The
cross-sectional view corresponding to the section taken along the
line B-B of FIG. 7 during the manufacturing method of FIG. 70 is
identical to that shown in FIG. 45.
[0235] Next, as shown in FIG. 71, semiconductor regions 23nb, 23pb,
11nb of the respective MOSs having relatively high concentrations
of impurities are formed respectively by separate impurity doping
processes using different photo resist patterns as masks in the
same manner as Embodiment 1. This process forms pairs of n-type
semiconductor regions 11, 23n and pairs of p-type semiconductor
regions 23p for forming the sources and drains of the nMOSs QHn and
pMOSs QHp in the high-voltage system and the selection MOSs N1 and
N3. The cross-sectional view corresponding to the section taken
along the line B-B of FIG. 7 during the manufacturing process of
FIG. 71 is identical to that shown in FIG. 47.
[0236] Next, as shown in FIG. 72, an insulating film 12 b (this
corresponds to the insulating films 12b and 7 in the protective MOS
region) is deposited over the semiconductor substrate 1, and
contact holes CON1 are provided thereto so as to expose the
portions of the semiconductor substrate 1 (source and drain regions
of respective MOSs), portions of the word lines W and portions of
the gate electrodes of given MOSs using photolithographic and dry
etching techniques, and a first-level wiring layer L1 (including
common source lines) is then formed over the insulating film 12b in
the same manner as Embodiment 1. The first-level wiring layer L1 is
electrically connected, accordingly, with the pairs of the
semiconductor regions forming the sources and drains, the gate
electrodes and the word lines W of the respective MOSs via the
contact holes CON 1. The cross-sectional view corresponding to the
section taken along the line B-B of FIG. 7 during the manufacturing
process of FIG. 72 is identical to that shown in FIG. 50.
[0237] Thereafter, as shown in FIG. 73, plugs 24, a second-level
wiring layer L2, plugs 25 and a third-level wiring layer L3 etc.
are formed in the same manner as Embodiment 1. The cross-sectional
view corresponding to the section taken along the line B-B of FIG.
7 during the manufacturing process of FIG. 73 is identical to that
shown in FIG. 55 In this way the flash memory (EEPROM) is
manufactured.
[0238] In Embodiment 3 of the present invention, the electrostatic
breakdown resistivity of the protective MOS Qop1 may be improved as
explained in Embodiment 1.
[0239] The present invention invented by the present inventor has
been explained heretofore in detail according to the embodiments,
however, it should be appreciated that the present invention is not
limited to Embodiment 1-3, and various modifications may be
possible without departing from the principle of the present
invention.
[0240] For example, a silicide layer may be formed over the top
surfaces of the source and drain regions of the memory cells of
Embodiment 1-3. This allows the reduction in the contact resistance
between the wiring and the source and drain regions, so that the
operation speed of the memory may be improved.
[0241] When doping an impurity to the channels of the memory cells,
the impurity may be ion-implanted in a diagonal direction from the
source side to offset the drain side. This would allow the
extension of the drain disturb margin.
[0242] In the above description, the present invention invented by
the present inventor was explained as being applied to a single
flash memory (EEPROM) which is the background field of use of the
present invention, however, the present invention is not limited
thereto, and it may also be applied to, for example, a
composite-type semiconductor integrated circuit device in which the
flash memory (EEPROM) and logics are provided on a single
semiconductor substrate.
[0243] Following explains some of the effects obtained by a
representative invention of the inventions disclosed herein.
[0244] (1) According to the present invention, in a field-effect
transistor for a peripheral circuit having the same structure as
the double-level gate electrode of a nonvolatile memory cell, a
hole for connecting its two layers of the gate electrode is
provided at a location which two-dimensionally overlaps the active
region within the plane of the gate electrode, thus, the
resistivity of the gate electrode of this field-effect transistor
may be reduced.
[0245] (2) Due to the effect of (1), the power consumption of a
semiconductor integrated circuit device having the nonvolatile
memories may be reduced.
[0246] (3) According to the present invention, in a field-effect
transistor for a peripheral circuit having the same structure as
the double-level gate electrode of a nonvolatile memory cell, a
hole for connecting its two layers of the gate electrode is
provided at a location which two-dimensionally overlaps the active
region within the plane of the gate electrode, so that designing of
the layout of the peripheral circuit elements of a semiconductor
integrated circuit device having nonvolatile memory cells may be
simplified.
[0247] (4) Due to the effect of (3), the transition from the
circuit designing to the device designing of a semiconductor
integrated circuit device having the nonvolatile memory cells may
be made more easily.
* * * * *