U.S. patent application number 09/221300 was filed with the patent office on 2001-09-20 for processor that executes control signals included in operand section of control instruction.
Invention is credited to BOMBACI, FRANCESCO, MAMMOLITI, FRANCESCO NINO, PAPPALARDO, FRANCESCO, TESI, DAVIDE.
Application Number | 20010023481 09/221300 |
Document ID | / |
Family ID | 8230919 |
Filed Date | 2001-09-20 |
United States Patent
Application |
20010023481 |
Kind Code |
A1 |
PAPPALARDO, FRANCESCO ; et
al. |
September 20, 2001 |
PROCESSOR THAT EXECUTES CONTROL SIGNALS INCLUDED IN OPERAND SECTION
OF CONTROL INSTRUCTION
Abstract
A processor is provided with a set of instructions formed, in
general, of an operation section and an operand section. For at
least one of the instructions, the operand section represents
operation control signals of the processor. In this way, an
extension of the set of instructions can be achieved for tailoring
the set of instructions to the user's own requirements.
Consequently, the processor control unit should be capable of
coupling its outputs to its inputs upon receiving one such
instruction, thereby to transfer such internal operation control
signals without interpretation.
Inventors: |
PAPPALARDO, FRANCESCO;
(PATERNO, IT) ; TESI, DAVIDE; (FERNEY VOLTAIRE,
FR) ; MAMMOLITI, FRANCESCO NINO; (DASA, IT) ;
BOMBACI, FRANCESCO; (MESSINA, IT) |
Correspondence
Address: |
SEED INTELLECTUAL PROPERTY LAW GROUP PLLC
701 FIFTH AVE
SUITE 6300
SEATTLE
WA
98104-7092
US
|
Family ID: |
8230919 |
Appl. No.: |
09/221300 |
Filed: |
December 23, 1998 |
Current U.S.
Class: |
712/245 ;
712/209; 712/E9.028; 712/E9.035 |
Current CPC
Class: |
G06F 9/30145 20130101;
G06F 9/30003 20130101; G06F 9/30181 20130101 |
Class at
Publication: |
712/245 ;
712/209 |
International
Class: |
G06F 009/30 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 24, 1997 |
EP |
97830716.3 |
Claims
1. A processor arranged to execute instructions from a
predetermined set of instructions of which at least one is formed
of an operation section and an operand section, wherein the set
includes at least one instruction having an operand section
representing control signals controlling operation of the
processor.
2. A processor according to claim 1, wherein the processor includes
internal control signals and the at least one instruction includes
an instruction whose operand section represents all of the internal
control signals of the processor operation.
3. A processor according to claim 1, wherein the processor includes
a program counter register and internal control signals and the at
least one instruction includes an instruction whose operand section
represents all of the internal control signals of the processor
operation, excepting signals controlling the program counter
register.
4. A processor according to claim 1, wherein the at least one
instruction includes a number of instructions whose respective
operand sections represent distinct sets of internal control
signals of the processor operation.
5. A processor, comprising: a plurality of operating blocks having
operation control inputs; and a control unit having instruction
inputs, and having control outputs connected to said control
inputs, said unit being adapted to interpret instructions received
on its inputs and to generate, in consequence, at its outputs
operation control signals of said operating blocks, whereinsaid
control unit is also adapted to couple its outputs to its inputs
for transferring information from the inputs to the outputs.
6. A processor according to claim 5, wherein said control unit
comprises buffer logic circuitry (BUF-1, . . . , BUF-6), and
wherein said coupling is effected through said circuitry such that
the transfer of information from the inputs to the circuitry will
take place at successive time phases and the transfer of
information from the circuitry to the outputs will take place at a
single time phase.
7. A processor according to claim 5, wherein said control unit
comprises decoding logic circuitry, and wherein said coupling is
effected through said circuitry.
8. A processor according to claim 5, wherein said control unit
comprises an instruction interpreter arranged to interpret a set of
instructions of which at least one is formed of an operation
section and an operand section, the operand section representing
values of said operation control signals.
9. A semiconductor integrated circuit including a processor
according to claim 5.
10. A processing system including at least one processor according
to claim 5.
11. A method of instruction processing, comprising: receiving a
computer instruction having an operation code; determining whether
the operation code indicates an instruction from among a primary
set of instructions or is a control code indicating an extended set
of instructions; if the operation code indicates an instruction,
then executing the instruction indicated; if the operation code is
a control code, then obtaining from an operand associated with the
operation code an indication of which instruction from the extended
set of instructions should be executed, and executing the
instruction indicated.
12. The method of claim 11 wherein the determining act includes
determining whether the operation code is a first control code
indicating a first extended set of instructions or a second control
code indicating a second extended set of instructions, and the
method further includes executing an instruction from the first
extended set if the operation code is the first control code and
executing an instruction from the second extended set if the
operation code is the second control code.
13. The method of claim 11 wherein the method is executed by a
processor having a control unit and an operating block, the method
further comprising sending the operand associated with the control
code from the control unit to the operating block, the operand
itself being an internal control signal.
14. The method of claim 11 wherein the method is executed by a
processor having a control unit and an operating block, the method
further comprising decoding the operand in the control unit to
determine which instruction of the extended set was intended to be
executed and sending the instruction decoded from the operand to
the operating block.
15. The method of claim 11 wherein the method is executed by a
processor having a control unit and an operating block, the method
further comprising transferring the operand into plural buffers of
the control unit in successive time phases and transferring the
operand from the plural buffers to the operating block in a single
time phase.
16. The method of claim 11 wherein the method is executed by a
processor having a control unit with an input for receiving
instructions and an output, the method further comprising coupling
the input to the output in response to determining that the
operation code is the control code.
Description
TECHNICAL FIELD
[0001] This invention relates to computer processors, and more
particularly, to a processor that is adaptable according to users
preferences.
BACKGROUND OF THE INVENTION
[0002] A reference book on processor architectures is, for example,
L. Ciminiera and A. Valenzano, "Advanced Microprocessor
Architectures", Addison-Wesley, 1987, wherein both traditional and
advanced architectures, such as CISC (Complex Instruction Set) and
RISC (Reduced Instruction Set) configurations, are illustrated.
[0003] In fact, to enhance the calculating capabilities of
processors, there are two opposite courses that can be followed: a
first course consists of providing the processors with plural
complex instructions (CISC), quite powerful but slow to execute,
and the second consists of providing the processors with few simple
instructions (RISC), less powerful but quickly executed.
[0004] An obvious solution is that of making each instruction the
most convenient compromise (of instruction complexity versus speed
of execution) for the user of the processor. However, this cannot
be carried into effect exhaustively, and in consequence, different
processors are offered on the market for different types of
applications.
SUMMARY OF THE INVENTION
[0005] An embodiment of this invention solves the problem outlined
above by providing a processor with a set of instructions which can
be easily expanded and/or customized by the user.
[0006] The processor of the embodiment is provided with at least
one control instruction wherein the operand section represents
control signals for controlling the processor operation; in this
way, an extension of the set of instructions can be simulated.
[0007] Accordingly, the control unit of the processor of the
embodiment is capable of coupling its outputs to its inputs, upon
receiving an instruction as above, so as to transfer such internal
operation control signals without any interpretation.
[0008] According to another aspect, another embodiment of the
invention is directed to an integrated circuit and a processing
system in which the processor can be advantageously included.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 shows schematically a block diagram of a prior art
processor.
[0010] FIG. 2 is a partial diagram of a set of instructions in a
processor according to the invention.
[0011] FIG. 3 is a block diagram of a control unit in a processor
according to the invention.
[0012] FIG. 4 shows schematically a state transition diagram of the
control unit in FIG. 3.
DETAILED DESCRIPTION
[0013] Considering the example of FIG. 1, a prior art processor
comprises a plurality HPD of operating blocks which have operation
control inputs CO, current address outputs CA and current data
inputs/outputs CD, and a control unit UC having instruction inputs
II and control outputs CO connected to said control inputs CO;
provided within the processor are a control bus BC, a data bus BD,
and an address bus BA, in general all bidirectional. These internal
buses are connected to corresponding external buses, with the
control bus BC being connected to the control unit UC, the data bus
BD connected to the instruction inputs II and the current data
I/O's CD, and the address bus BA connected to the current address
outputs CA.
[0014] The plurality HPD of operating blocks include, for example,
an accumulator register ACC, a program count register PC, a few
working registers (of which two, REG1 and REG2, are shown), an
arithmetic and logic calculating unit ALU, and a timing unit TIM.
These operating blocks are each provided with one or more operation
control inputs (collectively designated CO), and connected to the
data I/O's CD and/or the address outputs CA according to the
operations that they are to perform.
[0015] The basic duty of the control unit UC is to interpret
instructions received on its inputs II, and consequently generate,
on its outputs CO, suitable internal operation control signals for
the operating blocks. The duty of the control bus BC and the
meaning conveyed by the external control signals being propagated
therethrough will be no further discussed herein because foreign to
this invention and well known from literature.
[0016] Referring to FIG. 2, the set of instructions of the
processor in FIG. 1 may include, for example, the instructions ADD,
LOAD, INC-ACC, JMP-REL, JMP-ABS, and many more. These instructions
are formed of an operation section S1 of fixed length--e.g., 1 byte
(8 bits) of an operational code OPC--and an operand section S2 of
varying length--e.g., 1, 2, 3 data DAT or address ADR bytes, or
bytes of a generic operand OP--excepting the instruction INC-ACC
which requires no operand, as explained hereinafter.
[0017] The instructions convey the following meanings:
[0018] ADD--add together the contents of the register corresponding
to the first operand OP1 and the contents of the register
corresponding to the second operand OP2, and place the result into
the accumulator register;
[0019] LOAD--load the memory contents identified by the
corresponding address to the operand ADR, into the accumulator
register;
[0020] INC-ACC--increase the contents of the accumulator
register;
[0021] JMP-REL--jump to executing the instruction included in the
memory word identified by the address being the sum of the program
count register PC contents and the operand DAT;
[0022] JMP-ABS--jump to executing the instruction included in the
memory word identified by the corresponding address to the operand
ADR.
[0023] In the processor of this invention, there is at least one
instruction, designated CNTR in FIG. 2 and being formed of an
operation section S1 and an operand section S2, wherein the operand
section, corresponding to 7 bytes in FIG. 2, represents internal
(and external, if any) operation control signals of the
processor.
[0024] With the instruction CNTR, any new operation can be
performed (as allowed by the operating blocks and the connections
inside the plurality HPD), using as the operand data corresponding
to values of the control signals which would implement that new
operation. For example, using an instruction CNTR, the registers
REG1 and REG2 can be loaded simultaneously from the memory. The
step of acquiring an instruction CNTR would obviously take longer
than the steps for the other instructions (in the example of FIG.
2, 6 bytes must be acquired instead of 4 bytes at most), but is
compensated by the almost complete absence of instruction
interpreting activity.
[0025] In this way, each user is enabled to add specific
instructions to the standard set of instructions, as the user's
particular application may require.
[0026] This extension is achieved neither at the expense of the
efficiency of standard instruction execution, nor of circuit
complexity of the processor instruction interpreter.
[0027] Of the various viable courses, the simplest implemented is
one where the operand section would represent all the (typically)
internal processor operation control signals.
[0028] In this case, if the control of the program execution flow
is to be taken away from the programmer, then it is more convenient
to have the operand section represent all the internal control
signals of the processor operation, but for control signals to the
program count register PC; the register PC would then be managed
conventionally by the control unit UC.
[0029] Alternatively, a number of instructions may be provided
whose respective operand sections represent discrete sets of
(typically) internal processor operation control signals; thus, the
lengths of the control instructions can be greatly reduced. These
sets may be separate or partly cross one another
[0030] Referring to FIG. 3, the control unit UC may be a finite
state machine in an otherwise conventional processor, and may
include proximate state logic circuitry SSL having first inputs
connected to the inputs II of the unit UC, a state memory SSM
having inputs connected to the outputs of the circuitry SSL and
outputs connected to second inputs of the circuitry SSL, as well as
output logic circuitry OL having first inputs connected to the
inputs II of the unit UC and second inputs connected to the outputs
of the memory SSM; the memory SSM also has an input CLK for a clock
signal. The outputs of the circuitry OL may either be connected to
the outputs CO of the unit UC directly, or through a latching
arrangement as shown in FIG. 3. The latching arrangement comprises
a multiplexer MUX2 having first inputs coupled to the outputs of
the circuitry OL and having a selection input SEL2 connected to a
particular output of the circuitry OL, an output memory OM having
inputs connected to the outputs of the multiplexer MUX2 and outputs
connected to both the outputs CO and to the second inputs of the
multiplexer MUX2. The memory OM also has an input CLK for a clock
signal.
[0031] Alternatively, the control unit could be
micro-programmed.
[0032] In the processor of this invention, a circuit section (DEC,
BUF-0 . . . BUF-6, MUX1) is added in the control unit UC for
coupling the outputs CO to the inputs II such that information can
be transferred from the inputs to the outputs.
[0033] Since, in general, the number of outputs CO--56 in the
example of FIG. 3--would be much larger than the number of inputs
II--8 in the example of FIG. 3--it may be arranged for the control
unit UC to include buffer logic circuitry BUF-0 . . . BUF-6. The
coupling of the inputs II and outputs CO may then be established
through this circuitry such that the transferal of information from
the inputs II to the circuitry BUF will take place at successive
time phases, and the transferal of information from the circuitry
BUF to the outputs CO at one time phase.
[0034] In order to reduce the length of the control instructions
CNTR, it could be conceived of encoding the control signals. For
example, if the calculating unit ALU can effect eight different
arithmetic and logic operations, and has eight corresponding
operation control inputs available, three bits encoded in the
instruction CNTR would be sufficient. In this case, the control
unit UC would require decoding logic circuitry (omitted from the
example in FIG. 3), and the inputs II and outputs CO would be
coupled through this circuitry.
[0035] Of course, the control unit UC must be capable of
discriminating between the control instruction CNTR and the other
instructions. For that purpose, it includes an instruction
interpreter (SSL, SSM, OL) arranged to interpret a set of
instructions of which at least one is formed of an operation
section and an operand section, the operand section representing
values of operation control signals.
[0036] In the embodiment of FIG. 3, the 8 inputs II are connected
in parallel to 7 buffers BUF-0, BUF-1, BUF-2, BUF-3, BUF-5, BUF-6;
the outputs of the buffers BUF are connected to 56 first inputs of
a multiplexer MUX1; 56 second inputs of the multiplexer MUX1 are
connected to the outputs of the circuitry OL, and one selection
input SEL1 of this multiplexer is connected to a particular output
of the circuitry OL; the outputs of the multiplexer MUX1 are
connected to the first inputs of the multiplexer MUX2; the buffers
BUF also have inputs CLK (omitted from FIG. 3 for simplicity) for a
clock signal, and activation inputs respectively connected to a
decoder DEC. The decoder DEC has three inputs connected to
particular outputs of the circuitry OL, and eight outputs, of which
one is not used and is omitted from FIG. 3. It should be noted that
the circuitry OL is provided with a particular separate output for
the increase control signal INC-PC to the program count register
PC.
[0037] The operation of the control unit UC is more clearly
explained with the aid of the state transition diagram of FIG.
4.
[0038] At startup, the unit is in the state ST00.
[0039] Upon receiving an instruction CNTR, the unit goes over to
the state ST10, SEL1 is set to "0", SEL2 is set to "0", DEC is set
to "000", and INC-PC is set active; the memory is now
addressed.
[0040] Upon a clock pulse, the unit goes over to the state ST11,
SEL1 and SEL2 and DEC remain stable, and INC-PC is set inactive;
the first byte is now stored into the buffer BUF-0.
[0041] Upon a clock pulse, the unit goes over to the state ST10,
SEL1 is set to "0", SEL2 is set to "0", DEC is set to "001", and
INC-PC is set active; the memory is now addressed.
[0042] The states ST10 and ST11 are reiterated until all the
buffers BUF are loaded with data; thereafter, the unit will go over
to the state ST12, SEL1 will be set to "0", SEL2 set to "1", and
INC-PC set active; the control signals are now supplied to the
outputs CO and preparations are made for acquiring the next
instruction from the memory.
[0043] Upon a clock pulse, the unit is restored to its initial
state ST00, SEL2 is set to "0", and INC-PC is set inactive; the
operating code OPC of the instruction, as just acquired, is then
decoded.
[0044] Upon a clock pulse, and dependent on the result of the
decoding operation, the unit goes over to either the state ST10 or
the state ST20.
[0045] When an ordinary instruction is received, the unit goes over
to the state ST20, SEL1 is set to "1", SEL2 is set to "0", and
INC-PC is set active; the memory is now addressed.
[0046] Upon a clock pulse, the unit goes over to the state ST21,
SEL1 and SEL2 remain stable, and INC-PC is set inactive; the first
byte of the operand is presently acquired.
[0047] Upon a clock pulse, the unit goes over to the state ST20,
SEL1 is set to "1", SEL2 is set to "0", and INC-PC is set active;
the memory is presently addressed.
[0048] The states ST20 and ST21 are iterated until the instruction
is fully acquired; subsequently to this, the unit will go over to
the state ST22, SEL1 will be set to "1", SEL2 set to "1", and
INC-PC set active; thus, the control signals are supplied to the
outputs CO, and preparations are made for acquiring the next
instruction from the memory.
[0049] Upon a clock pulse, the unit is restored to its initial
state ST00, SEL2 is set to "0", and INC-PC is set inactive; the
operating code OPC of the instruction just acquired is then
decoded.
[0050] The above repeats itself throughout the processor
operation.
[0051] It will be appreciated that this processor may be connected
to advantage in a semiconductor integrated circuit, or in a single-
or multi-processor type of processing system.
[0052] From the foregoing it will be appreciated that, although
specific embodiments of the invention have been described herein
for purposes of illustration, various modifications may be made
without deviating from the spirit and scope of the invention.
Accordingly, the invention is not limited except as by the appended
claims.
* * * * *