U.S. patent application number 09/836171 was filed with the patent office on 2001-09-13 for interconnect structure of semiconductor device and method for manufacturing same.
This patent application is currently assigned to NEC Corporation. Invention is credited to Yasuda, Makoto.
Application Number | 20010021578 09/836171 |
Document ID | / |
Family ID | 18476933 |
Filed Date | 2001-09-13 |
United States Patent
Application |
20010021578 |
Kind Code |
A1 |
Yasuda, Makoto |
September 13, 2001 |
Interconnect structure of semiconductor device and method for
manufacturing same
Abstract
An interconnect structure of a semiconductor device includes: a
bottom interconnect layer formed in a dielectric layer overlying a
silicon substrate; a top interconnect layer having aluminum as a
main component and connected with the bottom interconnect layer by
way of a via plug formed in the dielectric layer; and a first
barrier metal layer having higher <111> orientation. The
higher <111> orientation degree of the first barrier metal
layer aluminum suppresses occurrence and growth of
electro-migration provide a reliable interconnect structure.
Inventors: |
Yasuda, Makoto; (Tokyo,
JP) |
Correspondence
Address: |
YOUNG & THOMPSON
745 SOUTH 23RD STREET 2ND FLOOR
ARLINGTON
VA
22202
|
Assignee: |
NEC Corporation
|
Family ID: |
18476933 |
Appl. No.: |
09/836171 |
Filed: |
April 18, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09836171 |
Apr 18, 2001 |
|
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09466811 |
Dec 20, 1999 |
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Current U.S.
Class: |
438/622 ;
257/758; 257/763; 257/765; 257/773; 257/E21.576; 257/E21.584;
257/E23.16; 438/618; 438/683 |
Current CPC
Class: |
H01L 21/7685 20130101;
H01L 2221/1078 20130101; H01L 21/76841 20130101; H01L 23/53223
20130101; H01L 21/2855 20130101; H01L 21/76843 20130101; H01L
21/76829 20130101; H01L 2924/0002 20130101; H01L 2924/0002
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
438/622 ;
257/758; 257/773; 257/763; 257/765; 438/683; 438/618 |
International
Class: |
H01L 023/528; H01L
031/0392; H01L 023/532; H01L 021/768; H01L 023/049 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 21, 1998 |
JP |
10-362468 |
Claims
What is claimed is:
1. An interconnect structure of a semiconductor device comprising:
a silicon substrate; a bottom interconnect layer formed in a
dielectric layer overlying the silicon substrate; a top
interconnect layer having aluminum as a main component and
connected with the bottom interconnect layer by way of a via plug
formed in the dielectric layer; and a <111> oriented first
barrier metal layer disposed between the via plug and the top
interconnect layer.
2. The interconnect structure as defined in claim 1, wherein the
first barrier metal layer is a stacked film including a Ti layer
and a TiN layer disposed thereon.
3. The interconnect structure as defined in claim 1, wherein the
via plug includes a second barrier metal layer and a tungsten
layer, and the top interconnect layer is made of an Al--Cu
alloy.
4. The interconnect structure as defined in claim 2, wherein
thicknesses of the Ti layer and the TiN layer of the first barrier
metal layer are not less than 20 nm and not less than 25 nm,
respectively.
5. The interconnect structure as defined in claim 1, wherein a top
layer of the dielectric layer is made of plasma oxide.
6. A method for manufacturing an interconnect structure of a
semiconductor device, comprising the steps of: forming a bottom
interconnect layer underlying a dielectric layer and overlying a
silicon substrate; forming a through-hole in the dielectric layer
to expose the bottom interconnect layer; depositing a first barrier
metal layer overlying the dielectric layer and on an inner wall of
the through-hole; depositing a metal layer on the first barrier
metal layer for filling the through-hole; etching the metal layer
and the first barrier metal layer until the dielectric film is
exposed to thereby form a via plug of the metal layer and the
barrier metal layer; depositing a second barrier metal layer on the
dielectric film and the via plug; and depositing an interconnect
layer of which a main component is aluminum on the second barrier
metal layer.
7. The method as defined in claim 6, wherein the second barrier
metal layer is formed by sequentially depositing a Ti layer and a
TiN layer by sputtering.
8. The method as defined in claim 6, wherein CMP polishing is
employed for removing the metal layer and the first barrier metal
layer in the via plug forming step.
9. The method as defined in claim 7, wherein the TiN layer is
continuously deposited by sputtering after the deposition of the Ti
layer.
10. The method as defined in claim 7, wherein the interconnect
layer is continuously deposited by sputtering after the deposition
of the TiN layer.
11. The method as defined in claim 7 further comprising a Ti layer
and a TiN layer on the interconnect layer which are deposited after
the interconnect layer is cooled for a specified period of time
upon the completion of the interconnect layer depositing step.
12. The method as defined in claim 6, wherein the interconnect
layer is made of an Al--Cu alloy.
13. The method as defined in claim 6, wherein the interconnect
layer is <111> oriented.
Description
BACKGROUND OF THE INVENTION
[0001] (a) Field of the Invention
[0002] The present invention relates to an interconnect structure
of a semiconductor device and a method for manufacturing the same,
more in detail, to the multiple-layered interconnect structure
having aluminum as a main component which can suppress occurrence
and growth of electro-migration (EM) the method of manufacturing
the same.
[0003] (b) Description of the Related Art
[0004] With the advance of high integration of semiconductor
devices, the multi-layered interconnect structure in which a
plurality of interconnect layers are connected to one another is
more and more complicated.
[0005] An example of a method for manufacturing a conventional
multi-layered interconnect structure will be described referring to
FIGS. 1A to 1F.
[0006] A bottom interconnect layer 14 is deposited on an undercoat
dielectric film 12 overlying a silicon substrate (not shown), and
an interlayer dielectric film 16 made of a plasma oxide is formed
and flattened on the bottom interconnect layer 14 as shown in FIG.
1A.
[0007] The bottom interconnect layer 14 includes, for example, an
Al--Cu alloy film 14a constituting a main interconnect body, a Ti
layer 14b formed thereon and having a thickness of 25 nm, and a
first TiN layer 14c having a thickness of 50 nm formed as a
reflection preventing film in a photolithographic process. The Ti
layer is formed for preventing formation of AlN during deposition
of a first TiN layer As shown in FIG. 1B, a through-hole 18 is
formed in the interlayer dielectric film 16 to reach to the bottom
interconnect layer 14 by a lithographic and etching process.
[0008] Then, as shown in FIG. 1C, a second TiN layer 20 is formed
as a barrier metal layer on the entire surface of the wafer
including the walls of the connection aperture 18 followed by
formation of a tungsten (W) layer 22 on the second TiN layer
20.
[0009] Then, as shown in FIG. 1D, the tungsten layer 22 is
etched-back by employing a plasma etching method until the second
TiN layer 20 is exposed, thereby forming a plug 24 of tungsten.
[0010] Then, as shown in FIG. 1E, a third TiN layer 26 having a
thickness of 40 nm is deposited as a barrier metal layer on the
second TiN layer 20, followed by deposition of an Al--Cu alloy
layer 28 on the third TiN layer 26 by sputtering at a temperature
of 340.degree. C. After the Al--Cu alloy layer 28 is cooled for 50
seconds, a Ti layer 30 having a thickness of 25 nm and a TiN layer
32 having a thickness of 50 nm are sequentially deposited on the
Al--Cu alloy layer 28 by sputtering to form a top interconnect
layer 34.
[0011] The TiN layer 26 prevents excessive increase of a contact
resistance between the Al--Cu alloy layer 28 and the tungsten layer
22 even if a void is formed in the Al--Cu alloy layer 28 on the
plug 24 due to the EM.
[0012] Patterning of the TiN layer 32, the Ti Layer 30, the Al--Cu
alloy layer 28, the third TiN layer 26 and the second TiN layer 20
by a lithographic and dry-etching treatment provides top
interconnects 34 having a desired interconnect pattern.
[0013] In the above conventional interconnect structure, with the
miniaturization thereof, the lifetime of the interconnect is
considerably reduced due to the EM of the Al--Cu alloy layer to
increase the interconnect resistance during the operation, and
finally an interconnect deficiency such as a break down may be
generated.
[0014] Since current is likely to be concentrated to the
interconnect right above the plug, migration of the aluminum due to
the EM may easily occur to make a void.
SUMMARY OF THE INVENTION
[0015] In view of the foregoing, an object of the present invention
is to provide an interconnect structure which can suppress
occurrence and growth of the EM of the aluminum and a method for
manufacturing the same.
[0016] The present invention provides, in a first aspect thereof,
an interconnect structure of a semiconductor device including: a
silicon substrate; a bottom interconnect layer formed in a
dielectric layer overlying the silicon substrate; a top
interconnect layer having aluminum as a main component and
connected with the bottom interconnect layer by way of a via plug
formed in the dielectric layer; and a <111> oriented first
barrier metal layer disposed between the via plug and the top
interconnect layer.
[0017] The present invention provides, in a second aspect thereof,
a method for manufacturing an interconnect structure of a
semiconductor device, including the steps of: forming a bottom
interconnect layer underlying a dielectric layer and overlying a
silicon substrate; forming a through-hole in the dielectric layer
to expose the bottom interconnect layer; depositing a first barrier
metal layer overlying the dielectric layer and on an inner wall of
the through-hole; depositing a metal layer on the first barrier
metal layer for filling the through-hole; etching the metal layer
and the first barrier metal layer until the dielectric film is
exposed to thereby form a via plug of the metal layer and the
barrier metal layer; depositing a second barrier metal layer on the
dielectric film and the via plug; and depositing an interconnect
layer of which a main component is aluminum on the second barrier
metal layer.
[0018] In accordance with the interconnect structure of the present
invention and fabrication from the method of the present invention,
the increased <111> orientation of the aluminum of the top
interconnects suppress the occurrence and the growth of the EM of
the aluminum. Accordingly, substantially no interconnect
deficiencies due to the EM are generated to provide a reliable
interconnect structure.
[0019] The above and other objects, features and advantages of the
present invention will be more apparent from the following
description.
BRIEF DESCRIPTION OF DRAWINGS
[0020] FIGS. 1A to 1F are vertical sectional views sequentially
showing a series of steps of manufacturing a conventional
semiconductor device.
[0021] FIG. 2 is a graph showing relations between an average
trouble occurring period and <111> orientation of aluminum
and between the average trouble occurring period and an average
particle size of aluminum particles.
[0022] FIG. 3 shows graphs regarding a relation between a
composition of a barrier metal layer and the <111>
orientation of the aluminum.
[0023] FIG. 4 is a vertical sectional view showing a semiconductor
device having a stacked structure in accordance with a first
embodiment of the present invention.
[0024] FIGS. 5A to 5F are vertical sectional views sequentially
showing a series of manufacturing steps in accordance with a second
embodiment of the present invention.
PREFERRED EMBODIMENTS OF THE INVENTION
[0025] As a result of investigating reasons of the growth of the EM
of aluminum in a conventional interconnect structure, the present
inventor has found that the EM grows because <111>
orientation of the aluminum in an Al--Cu alloy layer with respect
to a silicon substrate having the interconnect structure is
extremely low.
[0026] A mean time to failure (MTTF) is closely related with the
<111> orientation of the aluminum as shown in a line (L1) in
a graph of FIG. 2 in which the MTTF is plotted on ordinate and a
function of the <111> orientation of the aluminum
{(S/.sigma.) log[Al(111)/Al(200)]} on abscissa. As shown therein,
the MTTF increases with the increase of <111> orientation of
the aluminum. The relation of the above graph was obtained by
employing an alloy interconnect of Al-0.5% Cu at a temperature of
80.degree. C. and a current density of 1.times.10.sup.5
A/cm.sup.2.
[0027] The trouble of the multi-layered interconnect structure
having the Al--Cu alloy is mainly caused by the growth of the EM of
the aluminum which is delayed with the increase of the particle
size of the aluminum crystal. Thus, it is estimated that the growth
of the EM the aluminum can be effectively suppressed with the
increase of the <111> orientation of the aluminum which
increases a particle size of the aluminum crystal.
[0028] As shown by a line (L2) in the graph of FIG. 2, the MTTF
increases with the increase of the particle lo size of the aluminum
crystal.
[0029] The present inventor has further found that a relation such
as shown in graphs of FIGS. 3A and 3B holds between the composition
of the barrier metal layer positioned between the Al--Cu
interconnect and the via plug and the <111> orientation of
the aluminum in the Al--Cu interconnect. In the graphs, FIG. 3A and
3B show XRD analysis results which are obtained by plotting
2.theta. on abscissa and diffraction strength of X-rays on
ordinate. A certain plane direction of a certain material can be
determined from the value of 2.theta. at which the diffraction
strength of X-rays has a peak, and a degree of the orientation of
the plane direction can be determined from the peak value of the
diffraction strength of X-rays.
[0030] It can be seen from FIGS. 3A and 3B that when the barrier
metal layer includes only the TiN layer, the <111>
orientation of the TiN layer and the aluminum is low and that when
the barrier metal layer includes the Ti layer and the TiN layer,
the <111> orientation of the TiN layer and the aluminum is
largely elevated.
[0031] In the present invention, the number of the layers of the
interconnect structure is not restricted as far as the top
interconnects are made of a metal or an alloy of which a main
component is aluminum. For example, in case of a three-layered
interconnect structure, a second level interconnect layer is
selected as a bottom interconnect layer and a third level
interconnect layer is selected as a top interconnect layer.
[0032] The first barrier metal layer in the present invention is
preferably a stacked film including a TiN layer and a TiN layer
formed thereon. The via plug preferably includes a second barrier
metal layer and a tungsten layer. The top interconnect layer is
preferably made of an Al--Cu alloy.
[0033] Thicknesses of the Ti layer and the TiN layer included in
the lower portion of the first barrier metal layer are 20 nm or
more and 25 nm or more, respectively. The thicknesses of the above
layers below the specified values reduce the effect of suppressing
the occurrence and the growth of the EM of the aluminum.
[0034] The top layers of the dielectric film is preferably made of
plasma oxide which has an excellent CMP-polished ability and an
effect of preventing contamination of the substrate with a
metal.
[0035] Now, the present invention is more specifically described
with reference to accompanying drawings.
[0036] Embodiment with Respect to Interconnect Structure
[0037] An interconnect structure 40 overlying a semiconductor
substrate (not shown) of a semiconductor device in accordance with
a first embodiment shown in FIG. 4 includes an undercoat dielectric
film 42, bottom interconnects 44 formed thereon, an interlayer
dielectric film 46 formed around the bottom interconnects 44, a via
plug 48 penetrating the interlayer dielectric film 46 and top
interconnects 50 connected to the bottom interconnects 44 by way of
the via plug 48.
[0038] The bottom interconnects 44 and the top interconnects 50 are
patterned in accordance with respective specified patterns.
[0039] The bottom interconnects 44 include a first Al--Cu alloy
layer 44a constituting an interconnect body, a first Ti layer 44b
having a thickness of 25 nm for preventing formation of AlN during
deposition of a first TiN layer, and the first TiN layer 44c having
a thickness of 50 nm formed as a reflection preventing film in a
photolithographic treatment for patterning an interconnect
layer.
[0040] The interlayer dielectric film 46 includes a bottom layer
BPSG film 46a and CVD oxide, for example, a SiOF film 46a formed on
the BPSG film 46a by a plasma CVD method.
[0041] The SiOF film 46a has an excellent CMP polished ability for
forming the via plug 48 and traps, by gettering, a metal, for
example, phosphorous (P) in a polishing agent employed in the CMP
polishing to effectively prevent contamination of the substrate
with the metal.
[0042] The via plug 48 is formed by filling a connection aperture,
with a via plug forming material, partially penetrating the
interlayer dielectric film 46 to expose the bottom interconnects
44, and includes a second TiN layer 48a formed as a barrier metal
layer on the wall of the connection aperture including the bottom
surface, and a tungsten layer 48b formed by filling the connection
aperture.
[0043] The top interconnects 50 include a first stacked barrier
metal layer 52 having a second Ti layer 52a of a thickness of 20 nm
and a third TiN layer 52b on the second Ti layer 52a deposited on
the via plug 48, a second Al--Cu alloy layer (top interconnect
layer) 50a constituting a main interconnect of the top
interconnects 50, a third Ti layer 50b for preventing formation of
AlN during deposition of a fourth TiN layer on the second Al--Cu
alloy layer 50a and the fourth TiN layer 50c formed as a reflection
preventing film in a photolithographic treatment for patterning an
interconnect layer.
[0044] The second Al--Cu alloy layer 50a consists of, for example,
0.5% in weight of copper and a balance of aluminum.
[0045] Thicknesses of the second Al--Cu alloy layer 50a, the third
Ti layer 50b and the fourth TiN layer 50c are 450 nm, 25 nm and 50
nm, respectively.
[0046] Since the first stacked barrier metal layer 52 of the top
interconnects 50 in the interconnect structure 40 of the first
embodiment includes the second Ti layer 52a and the third TiN layer
52b having higher <111> orientation, the <111>
orientation of the aluminum in the second Al--Cu alloy layer 50a of
the top interconnects 50 is extremely high to noticeably suppress
the occurrence and the growth of the EM of the aluminum.
Substantially no interconnect deficiency due to the EM provides the
interconnect structure having high reliability.
[0047] After an interconnect sample was manufactured having a
similar structure to the interconnect structure 40 of the first
embodiment shown in FIG. 4, a life test of the sample was
conducted. It was observed that an average trouble occurring period
was prolonged to about 2.5 times compared with that of the
conventional interconnect structure shown in FIGS. 1A to 1F.
[0048] Embodiment with Respect to Manufacture of Interconnect
Structure
[0049] An example of manufacturing the interconnect structure of
the first embodiment shown in FIG. 4 will be described, as a second
embodiment, referring to FIGS. 5A to 5F sequentially showing the
respective steps of the manufacture.
[0050] At first, the bottom interconnects 44 are formed on the
undercoat dielectric film 42 overlying the silicon substrate (not
shown) as shown in FIG. 5A.
[0051] As the bottom interconnects 44, the first Al--Cu alloy layer
44a constituting the main interconnect, the first Ti layer 44b
having a thickness of 25 nm and the first TiN layer 44c having a
thickness of 50 nm are sequentially deposited by sputtering.
[0052] The BPSG film 46a and the SiOF film 46b are sequentially
formed on the bottom interconnects 44 to provide the interlayer
dielectric film 46. The SiOF film 46b is formed by a plasma CVD
method and thereafter flattened The SiOF film 46a has an excellent
CMP polished ability for forming the via plug 48 and traps a metal
to effectively prevent contamination of the substrate with the
metal.
[0053] As shown in FIG. 5B, the connection aperture 47 is formed
partially penetrating the interlayer dielectric film 46 including
the SiOF film 46b and the BPSG film 46a to reach to the bottom
interconnects 44 by means of a lithographic etching treatment.
[0054] Then, as shown in FIG. 5C, the second TiN layer 48a as a
second barrier metal layer is formed on the entire surface of the
substrate including the wall of the connection aperture 47, and the
tungsten layer 48b is formed on the second TiN layer 48a.
[0055] Thereafter, the tungsten layer 48b and the second TiN layer
48a are removed by CMP polishing until the SiOF film 46b is exposed
for forming the via plug 48 as shown in FIG. 5D.
[0056] The barrier metal layer, when formed on the SiOF film 46b
flattened by the CMP polishing having a high degree of flatness,
has higher <111> orientation.
[0057] Then, as shown in FIG. 5E, the stacked barrier metal layer
52 including the second Ti layer 52a having a thickness of 20 nm
and the third TiN layer 52b having a thickness of 40 nm is
deposited, as the barrier metal layer, on the via plug 48 and the
SiOF film 46b by sputtering.
[0058] The second Ti layer 52a is deposited by sputtering without
back-heating while an argon gas is flown at 35 sccm, and after the
formation of the second Ti layer 52a, the third TiN layer 52b is
continuously deposited by sputtering without back-heating while an
argon gas and a nitrogen gas are flown at 57 sccm and 85 sccm,
respectively. The "continuos deposition" in the present invention
means that the latter deposition is conducted in the same
sputtering apparatus as that employed in the former deposition or
the latter deposition is conducted without any other treatment
after the wafer is conveyed from the sputtering apparatus to
another in a non-oxidative ambient.
[0059] After the formation of the third TiN layer 52b, the second
Al--Cu alloy layer 50a having a thickness of 450 nm constituting
the main interconnect of the top interconnects 50 is continuously
deposited on the third TiN layer 52b while an argon gas is flown at
35 sccm by sputtering at a temperature of 340.degree. C. The second
Al--Cu alloy layer 50a consists of, for example, 0.5% in weight of
copper and a balance of aluminum.
[0060] After the deposition of the second Al--Cu alloy layer 50a,
cooling is conducted by leaving the wafer in a cooling chamber for
about 60 seconds until the temperature in the chamber is lowered to
200.degree. C.
[0061] On the second Al--Cu alloy layer 50a, another stacked
barrier metal layer including the third Ti layer 50b having a
thickness of 25 nm for preventing formation of AlN during the
deposition of the fourth TiN layer 50c and the fourth TiN layer 50c
having a thickness of 50 nm formed as a reflection preventing film
in a photolithographic treatment for patterning an interconnect
layer is deposited by sputtering.
[0062] The third Ti layer 50b can be formed without back-heating
while an argon gas is flown at 35 sccm, and the fourth TiN layer
50c can be deposited by sputtering without back-heating while an
argon gas and a nitrogen gas are flown at 57 sccm and 85 sccm,
respectively.
[0063] Then, the fourth TiN layer 50c, the third Ti layer 50b, the
second Al--Cu alloy layer 50a, the third TiN layer 52b and the
second Ti layer 52a are patterned by a lithographic dry etching
treatment to form the top interconnects 50 having a desired
interconnect pattern as shown in FIG. 5F.
[0064] Since the above embodiments are described only for examples,
the present invention is not limited to the above embodiments and
various modifications or alternations can be easily made therefrom
by those skilled in the art without departing from the scope of the
present invention.
* * * * *