U.S. patent application number 09/771448 was filed with the patent office on 2001-09-06 for multilevel conductive interconnections including capacitor electrodes for integrated circuit devices.
Invention is credited to Kim, Ki-Nam, Koo, Bon-Jae.
Application Number | 20010019143 09/771448 |
Document ID | / |
Family ID | 19546724 |
Filed Date | 2001-09-06 |
United States Patent
Application |
20010019143 |
Kind Code |
A1 |
Koo, Bon-Jae ; et
al. |
September 6, 2001 |
Multilevel conductive interconnections including capacitor
electrodes for integrated circuit devices
Abstract
Conductive plugs are formed in a first insulating layer on an
integrated circuit substrate. A first conductive layer, a capacitor
dielectric film and a second conductive layer are formed on the
first insulating layer including on the conductive plugs. The
second conductive layer, the capacitor dielectric film and the
first conductive layer are patterned to define capacitors, each
including a portion of the first conductive layer, a portion of the
capacitor dielectric film thereon and a portion of the second
conductive layer thereon, and to define a plurality of first
conductive layer patterns that are free of the capacitor dielectric
film and the second conductive layer thereon. At least a first of
the capacitors is electrically connected to a conductive plug and
at least a second of the capacitors is not electrically connected
to a conductive plug. A second insulating layer is formed on the
first insulating layer, on the capacitors and on the first
conductive patterns. The second insulating layer includes therein
first contact holes that selectively expose the first conductive
layer patterns. A first level interconnection is formed in the
first contact holes and on the second insulating layer to
electrically contact the first conductive patterns and to
selectively electrically interconnect selected ones of the first
conductive patterns to one another on the second insulating layer.
A third insulating layer is formed on the second insulating layer
and on the first level interconnection. The third insulating layer
includes therein second contact holes that selectively expose the
first level interconnection and selected ones of the capacitors. A
second level interconnection is formed in the second contact holes
and on the third insulating layer to selectively electrically
interconnect the at least one of the first capacitors, to
selectively electrically contact the first level interconnection
and to selectively electrically interconnect selective ones of the
at least a second of the capacitors to one another and to the first
level interconnection.
Inventors: |
Koo, Bon-Jae; (Kyunggi-do,
KR) ; Kim, Ki-Nam; (Kyunggi-do, KR) |
Correspondence
Address: |
MYERS BIGEL SIBLEY & SAJOVEC
PO BOX 37428
RALEIGH
NC
27627
US
|
Family ID: |
19546724 |
Appl. No.: |
09/771448 |
Filed: |
January 26, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09771448 |
Jan 26, 2001 |
|
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09369991 |
Aug 6, 1999 |
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6262446 |
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Current U.S.
Class: |
257/296 ;
257/E21.009; 257/E21.066; 257/E21.37; 257/E21.582; 257/E21.646;
257/E21.648; 257/E29.104; 257/E29.183 |
Current CPC
Class: |
H01L 29/66234 20130101;
H01L 29/1608 20130101; H01L 29/66068 20130101; H01L 21/76838
20130101; H01L 27/10852 20130101; H01L 2924/0002 20130101; H01L
28/55 20130101; H01L 27/10844 20130101; H01L 29/732 20130101; H01L
2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/296 |
International
Class: |
H01L 029/94; H01L
029/76; H01L 027/108 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 7, 1998 |
KR |
98-32234 |
Claims
What is claimed is:
1. A method of forming a conductive interconnection for an
integrated circuit device wherein the semiconductor memory device
comprises a transistor and a capacitor composed of a lower
electrode, a dielectric film and an upper electrode, the metal
interconnection being made of the same material as a lower and
upper electrodes.
2. The method according to claim 1, wherein the dielectric film is
made of a ferroelectric material.
3. A method according to claim 2, wherein the metal interconnection
is made of at least one material selected from a group consisting
of a refractory metal, a conductive oxide electrode and a
combination thereof.
4. A method according to claim 3, wherein the refractory metal
comprises one selected from the group consisting of a platinum,
iridium, ruthenium, gold and palladium and the conductive oxide
electrode comprises one selected from the group consisting of
iridium dioxide and ruthenium dioxide.
5. A method of forming a conductive interconnection for an
integrated circuit device comprising: forming a plurality of
conductive plugs in a first insulating layer on a semiconductor
substrate, the semiconductor substrate including a cell array
region and a peripheral region; forming a first conductive layer, a
capacitor dielectric film and a second conductive layer on the
first insulating layer including the conductive plugs; patterning
the second conductive layer, the capacitor dielectric film and the
first conductive layer to define a plurality of capacitors and a
plurality of first conductive patterns, the capacitors comprising a
portion of the first conductive layer, a portion of the capacitor
dielectric film and a portion of the second conductive layer
thereon, the first conductive patterns that are free of the
capacitor dielectric film and the second conductive layer thereon,
such that the capacitors at the cell array region is electrically
connected to the conductive plugs, the capacitors at the peripheral
region is not electrically connected to the conductive plug, and at
least one of the first conductive pattern is electrically connected
to the conductive plugs; forming a second insulating layer on the
first insulating layer including the capacitors and the first
conductive patterns; forming a first level conductive
interconnection on the second insulating layer to electrically
contact the first conductive patterns and to electrically
interconnect selected ones of the first conductive patterns to one
another; forming a third insulating layer on the second insulating
layer including the first level interconnection; forming a second
level interconnection on the second insulating layer to
electrically contact the capacitors and the first level
interconnection.
6. The method according to claim 5, wherein the second level
interconnection electrically contacts selected ones of the
capacitor at the peripheral region to one another and contacts the
first level interconnection to the capacitors at the peripheral
region.
7. The method according to claim 5, wherein the first and second
conductive layers and the first and second level interconnections
all comprise same material.
8. The method according to claim 5, wherein the first and second
interconnections comprise at least one of a refractory metal, a
conductive oxide and a combination thereof.
9. The method according to claim 8, wherein the refractory metal
comprises one selected from the group consisting of a platinum,
iridium, ruthenium, gold and palladium and the conductive oxide
electrode comprises one selected from the group consisting of
iridium dioxide and ruthenium dioxide.
10. The method according to claim 5, wherein the capacitor
dielectric film is made of a ferroelectric material.
11. A conductive interconnection for an integrated circuit device,
comprising: a first insulating layer formed on a semiconductor
substrate, the first insulating layer including therein a plurality
of conductive plugs; a plurality of capacitors formed on the first
insulating layer, each capacitor comprising a first portion of a
first conductive layer, a portion of a capacitor dielectric film
and a portion of a second conductive layer in this order, wherein
at least a first of the plurality of capacitors is electrically
connected to a conductive plug and at least a second of the
plurality of capacitors is not electrically connected to a
conductive plug; a plurality of first conductive layer patterns
formed on the first insulating layer, the first conductive layer
patterns comprising a second portion of the first conductive layer
that is free of the capacitor dielectric film and the second
conductive layer thereon; a second insulating layer formed on the
first insulating layer including the plurality of capacitors and
the plurality of first conductive patterns; a first level
interconnection formed on the second insulating layer to be
electrically contacted to the plurality of conductive patterns, and
that selectively electrically interconnecting selected ones of the
first conductive patterns to one another on the second insulating
layer; a third insulating layer formed on the second insulating
layer and on the first level interconnection; and a second level
interconnection formed on the third insulating layer, that
selectively electrically contacts the at least one of the first
capacitors, that selectively electrically connects the first level
interconnection and that selectively electrically interconnects
selected ones of the at least a second of the plurality of
capacitors to one another and to the first level
interconnection.
12. The conductive interconnection according to claim 11, wherein
the first conductive layer, the second conductive layer, the first
level interconnection and the second level interconnection all
comprise same material.
13. The conductive interconnection according to claim 12, wherein
the capacitor dielectric film is made of a ferroelectric
material.
14. The conductive interconnection according to claim 11, further
comprising: a plurality of third contact holes in the second
insulating layer that underlie selected ones of the second contact
holes and that selectively expose the first and second
capacitors.
15. The conductive interconnection according to claim 11: wherein
the integrated circuit is an integrated circuit memory device
including a cell array region and a peripheral region; wherein the
at least a first of the plurality of capacitors is located in the
cell array region and the at least a second of the plurality of
capacitors is located in the peripheral region; and wherein the
plurality of first conductive layer patterns is located in the
peripheral region.
16. A conductive connection for an integrated circuit device,
comprising: a first insulating layer on an integrated circuit
substrate; a plurality of capacitors on the first insulating layer,
each capacitor comprising a first portion of a first conductive
layer, a portion of a capacitor dielectric film thereon and a
portion of a second conductive layer thereon; a plurality of first
conductive layer patterns on the first insulating layer, the first
conductive layer patterns comprising a second portion of the first
conductive layer that is free of the capacitor dielectric film and
the second conductive layer thereon; a second insulating layer on
the first insulating layer, on the plurality of capacitors and on
the plurality of first conductive patterns, the second insulating
layer including therein a plurality of first contact holes that
selectively expose the plurality of first conductive layer
patterns; a first level interconnection in the plurality of first
contact holes and on the second insulating layer that electrically
contacts the plurality of first conductive patterns; a third
insulating layer on the second insulating layer and on the first
level interconnection, the third insulating layer including therein
a plurality of second contact holes that selectively expose the
first level interconnection and selected ones of the plurality of
capacitors; and a second level interconnection formed on the third
insulating layer to be selectively electrically contacted to the at
least one of the first capacitors and to be selectively
electrically contacted to the first level interconnection.
17. The conductive interconnection according to claim 16, wherein
the first conductive layer, the second conductive layer, the first
level interconnection and the second level interconnection all
comprise same material
18. The conductive interconnection according to claim 17, wherein
the capacitor dielectric film is made of a ferroelectric
material.
19. A conductive connection for an integrated circuit device,
comprising: a first insulating layer including therein a plurality
of first conductive plugs on a semiconductor substrate; a plurality
of capacitors on the first insulating layer, each capacitor
comprising a portion of a first conductive layer, a portion of a
capacitor dielectric film thereon and a portion of a second
conductive layer thereon, wherein at least a first of the plurality
of capacitors is electrically connected to a first conductive plug
and at least a second of the plurality of capacitors is not
electrically connected to a first conductive plug; a second
insulating layer on the first insulating layer and on the plurality
of capacitors, the second insulating layer including therein a
plurality of contact holes that expose the at least a first and a
second of the plurality of capacitors; and a plurality of second
conductive plugs in the plurality of contact holes.
20. The conductive connection according to claim 19, wherein the
capacitor dielectric film is made of a ferroelectric material.
21. The conductive connection according to claim 20, wherein the
integrated circuit comprising a semiconductor memory device
including a cell array region and a peripheral region, wherein the
at least a first of the plurality of capacitors is located in the
cell array region and the at least a second plurality of capacitors
is located in the peripheral region.
Description
FIELD OF THE INVENTION
[0001] This invention relates to integrated circuit devices and
fabrication methods therefor and more particularly to conductive
interconnections for integrated circuit devices and fabrication
methods therefor.
BACKGROUND OF THE INVENTION
[0002] Integrated circuits are widely used in consumer and
commercial products. As the integration density of integrated
circuit devices continues to increase, it may become desirable to
increase the integration density of the conductive interconnections
that are formed on an integrated circuit substrate. Moreover, it
also may be desirable to provide more efficient processes for
forming the high-density interconnections.
[0003] High-density interconnections are particularly desirable for
integrated circuit memory devices such as integrated circuit
Dynamic Random Access Memory (DRAM) devices. As is well known to
those having skill in the art, an integrated circuit memory device
generally includes a cell array region wherein an array of memory
cells is provided, and a peripheral region that provides control
and other circuits for the cell array region. In DRAM devices, data
is stored by storing charge on integrated circuit capacitors.
Accordingly, it may be desirable to integrate these capacitors with
the high-density conductive interconnections for the integrated
circuit memory device.
[0004] As also is well known to those having skill in the art, DRAM
devices may use silicon dioxide, silicon nitride and/or other
insulators as the dielectric film for the memory cell capacitors.
It also is known to use a ferroelectric film, comprising for
example barium titanate and/or other materials, instead of a
conventional dielectric film. When a ferroelectric material is used
for the dielectric film, a non-volatile memory device may be
produced. Thus, the ferroelectric film allows a remnant
polarization to be stored in the ferroelectric material so that the
memory cell can repeatedly switch between two stable polarization
states by means of voltage pulses, thereby providing a non-volatile
memory device.
[0005] In ferroelectric memory devices, it is known to use
refractory metal such as platinum for the capacitor electrodes.
Interconnections may be provided using a single level or double
level interconnection process using different materials from those
of the electrodes. See, for example, the publication entitled
Highly Reliable Ferroelectric Memory Technology with Bismuth Layer
Structure Thin Film (Y-1 Family) to Fuji et al., IEDM, Vol. 97, pp.
597-600, 1997, wherein a double level metal process is
disclosed.
[0006] Notwithstanding these and other advances, it continues to be
desirable to provide high-density, multilevel conductive
interconnections for integrated circuit devices and efficient
methods of fabricating the same. It is particularly desirable to
provide high-density interconnections for integrated circuit memory
devices such as integrated circuit memory devices that use
ferroelectric capacitors, and efficient methods of fabricating the
same.
SUMMARY OF THE INVENTION
[0007] It therefore is an object of the present invention to
provide improved methods of forming conductive interconnections for
integrated circuit devices, and interconnections so formed.
[0008] It is another object of the present invention to provide
conductive interconnections for integrated circuit memory devices
that can integrate capacitors therein, and methods of forming the
same.
[0009] It is still another object of the present invention to
provide conductive interconnections for integrated circuit memory
devices that can integrate ferroelectric capacitors therein, and
methods of forming the same.
[0010] These and other objects are provided, according to an
embodiment of the present invention, by forming a first conductive
layer, a capacitor dielectric film and a second conductive layer on
a first insulating layer on an integrated circuit substrate. The
second conductive layer, the capacitor dielectric film and the
first conductive layer are patterned to define a plurality of
capacitors, each comprising a portion of the first conductive
layer, a portion of the capacitor dielectric film thereon and a
portion of the second conductive layer thereon, and to define a
plurality of first insulating layer patterns that are free of the
capacitor dielectric film and the second conductive layer thereon.
A second insulating layer is formed on the first insulating layer,
on the plurality of capacitors and on the plurality of first
conductive patterns. The second insulating layer includes therein a
plurality of first contact holes that selectively expose the
plurality of first conductive layer patterns.
[0011] A first level interconnection is formed in the plurality of
first contact holes and on the second insulating layer to
electrically contact the plurality of first conductive patterns. A
third insulating layer is formed on the second insulating layer and
on the first level interconnection. The third insulating layer
includes therein a plurality of second contact holes that
selectively expose the first level interconnection and selected
ones of the plurality of capacitors. A second level interconnection
is formed in the plurality of second contact holes and on the third
insulating layer to selectively electrically contact the plurality
of capacitors and to selectively electrically contact the first
level interconnection. The first conductive layer, the second
conductive layer, the first level interconnection and the second
level interconnection preferably comprise the same material, and
the capacitor dielectric film preferably comprises a ferroelectric
film.
[0012] Accordingly, a multilevel interconnection may be fabricated
of the same material as the ferroelectric capacitor electrodes.
Moreover, formation of the ferroelectric capacitor and formation of
the interconnections may be implemented in the same process chamber
to thereby provide an in-situ process that can be efficient.
[0013] In preferred embodiments of methods according to the present
invention, a plurality of conductive plugs are formed in a first
insulating layer on an integrated circuit substrate. A first
conductive layer, a capacitor dielectric film and a second
conductive layer are formed on the first insulating layer including
on the conductive plugs. The second conductive layer, the capacitor
dielectric film and the first conductive layer are patterned to
define a plurality of capacitors, each comprising a portion of the
first conductive layer, a portion of the capacitor dielectric film
thereon and a portion of the second conductive layer thereon, and
to define a plurality of first conductive layer patterns that are
free of the capacitor dielectric film and the second conductive
layer thereon. At least a first of the plurality of capacitors is
electrically connected to a conductive plug and at least a second
of the plurality of capacitors is not electrically connected to a
conductive plug.
[0014] A second insulating layer is formed on the first insulating
layer, on the plurality of capacitors and on the plurality of first
conductive patterns. The second insulating layer includes therein a
plurality of first contact holes that selectively expose the
plurality of first conductive layer patterns. A first level
interconnection is formed in the plurality of first contact holes
and on the second insulating layer to electrically contact the
plurality of first conductive patterns and to selectively
electrically interconnect selected ones of the first conductive
patterns to one another on the second insulating layer.
[0015] A third insulating layer is formed on the second insulating
layer and on the first level interconnection. The third insulating
layer includes therein a plurality of second contact holes that
selectively expose the first level interconnection and selected
ones of the plurality of capacitors. A second level interconnection
is formed in the plurality of second contact holes and on the third
insulating layer to selectively electrically interconnect the at
least one of the first capacitors, to selectively electrically
contact the first level interconnection and to selectively
electrically interconnect selective ones of the at least a second
of the plurality of capacitors to one another and to the first
level interconnection. Accordingly, by providing the second
capacitors that are not electrically connected to a conductive
plug, the top electrode of the capacitors may be used in a
multilevel interconnection, and the capacitors also can reduce
topography differences in an integrated circuit.
[0016] According to another aspect of the invention, conductive
interconnections for an integrated circuit memory device are
fabricated by forming a plurality of first conductive plugs in a
first insulating layer on an integrated circuit substrate and
forming a first conductive layer, a capacitor dielectric film and a
second conductive layer on the first insulating layer including on
the first conductive plugs. The second conductive layer, the
capacitor dielectric film and the first conductive layer are
patterned to define a plurality of capacitors, each comprising a
portion of the first conductive layer, a portion of the capacitor
dielectric film thereon and a portion of the second conductive
layer thereon, such that at least a first of the plurality of
capacitors is electrically connected to a first conductive plug and
at least a second of the plurality of capacitors is not
electrically connected to a first conductive plug. A second
insulating layer is formed on the first insulating layer and on the
plurality of capacitors. The second insulating layer includes
therein a plurality of contact holes that expose the at least a
first and second of the plurality of capacitors. A plurality of
second conductive plugs is formed in the plurality of contact
holes. Accordingly, by providing the second capacitors that are not
electrically connected to a first conductive plug, the top
electrode of the capacitors may be used in an interconnection, and
the capacitors also can reduce topography differences in an
integrated circuit.
[0017] When the integrated circuit devices are integrated circuit
memory devices that include a cell array region and a peripheral
region, the plurality of capacitors preferably is defined in the
cell array region and in the peripheral region, each comprising a
portion of the first conductive layer, a portion of the capacitor
dielectric film thereon and a portion of the second conductive
layer thereon. The plurality of first conductive layer patterns
preferably is defined in the peripheral region, that are free of
the capacitor dielectric film and the second conductive layer
thereon. Thus, at least a first of the plurality of capacitors in
the cell array region is electrically connected to a conductive
plug and at least a second of the plurality of capacitors in the
peripheral region is not electrically connected to a conductive
plug. The capacitors in the peripheral region may be used as part
of the multilevel conductive interconnections and also may be used
to reduce topography differences between the cell array region and
the peripheral region of an integrated circuit memory device.
[0018] Conductive interconnections for integrated circuit devices
according to embodiments of the invention comprise a first
insulating layer on an integrated circuit substrate, the first
insulating layer including therein a plurality of conductive plugs.
A plurality of capacitors is provided on the first insulating
layer. Each capacitor comprises a first portion of the first
conductive layer, a portion of the capacitor dielectric film
thereon and a portion of the second conductive layer thereon. At
least a first of the plurality of capacitors is electrically
connected to a conductive plug and at least a second of the
plurality of capacitors is not electrically connected to a
conductive plug. A plurality of first conductive layer patterns is
provided on the first insulating layer. The first conductive layer
patterns comprise a second portion of the first conductive layer
that is free of the capacitor dielectric film and the second
conductive layer thereon.
[0019] A second insulating layer is provided on the first
insulating layer, on the plurality of capacitors and on the
plurality of first conductive patterns. The second insulating layer
includes therein a plurality of first contact holes that
selectively expose the plurality of first conductive layer
patterns. A first level interconnection is provided in the
plurality of first contact holes and on the second insulating
layer, that electrically contacts the plurality of first conductive
patterns and that selectively electrically interconnects selected
ones of the first conductive patterns to one another on the second
insulating layer.
[0020] A third insulating layer is provided on the second
insulating layer and on the first level interconnection. The third
insulating layer includes therein a plurality of second contact
holes that selectively expose the first level interconnection and
selected ones of the plurality of capacitors. A second level
interconnection is provided in the plurality of second contact
holes and on the third insulating layer, that selectively
electrically contacts the at least one of the first capacitors,
that selectively electrically contacts the first level
interconnection and selectively electrically interconnects selected
ones of the at least the second of the plurality of capacitors to
one another and to the first level interconnection. A plurality of
third contact holes also may be provided in the second insulating
layer that underlies selected ones of the second contact holes and
that selectively expose the first and second capacitors
therein.
[0021] The first conductive layer, the second conductive layer, the
first level interconnection and the second level interconnection
preferably all comprise the same material, and the capacitor
dielectric film preferably is a ferroelectric film. When the
integrated circuit is an integrated circuit memory device including
a cell array region and a peripheral region, the at least a first
of the plurality of capacitors preferably is located in the cell
array region and the at least a second of the plurality of
capacitors preferably is located in the peripheral region. The
plurality of first conductive layer patterns preferably is located
in the peripheral region.
[0022] Accordingly, in the cell array region, ferroelectric
capacitors are formed that are electrically connected to the
underlying contact plugs. In the peripheral region, lower electrode
patterns that are electrically connected to the contact plugs may
be formed. Pseudo-ferroelectric capacitors, which are not
electrically connected to the underlying contact plugs and are made
of the same components as the ferroelectric capacitors in the cell
array region, may be formed in the peripheral region. These
electrode patterns and pseudo-ferroelectric capacitors may be used
as conductive pads for a multilevel conductive interconnection.
Since the pseudo-capacitors may be tall, step differences between
the cell array region and the peripheral region may be reduced and
the aspect ratio of later formed contact openings that reach
thereto may be reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIGS. 1-4 are cross-sectional views of integrated circuit
substrates including conductive interconnections according to an
embodiment of the present invention during intermediate fabrication
steps.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0024] The present invention now will be described more fully
hereinafter with reference to the accompanying drawings, in which
preferred embodiments of the invention are shown. This invention
may, however, be embodied in many different forms and should not be
construed as limited to the embodiments set forth herein; rather,
these embodiments are provided so that this disclosure will be
thorough and complete, and will fully convey the scope of the
invention to those skilled in the art. In the drawings, the
thickness of layers and regions are exaggerated for clarity. Like
numbers refer to like elements throughout. It will be understood
that when an element such as a layer, region or substrate is
referred to as being "on" another element, it can be directly on
the other element or intervening elements may also be present. In
contrast, when an element is referred to as being "directly on"
another element, there are no intervening elements present.
[0025] FIG. 1 schematically shows a cross-section of an integrated
circuit substrate such as a semiconductor substrate 10 that already
has undergone several process steps according to the present
invention. A cell array region and a peripheral region are defined
on the semiconductor substrate 10. A first insulating layer 12, for
example, comprising an oxide layer, is formed on the semiconductor
substrate 10, for example by deposition. Although not shown for
clarity, a conventional CMOS transistor process may be performed in
the substrate 10 prior to the formation of the first insulating
layer 12.
[0026] Selected portions of the first insulating layer 12 are
etched to form a plurality of contact holes that expose the
substrate, preferably at source/drain regions of the CMOS
transistors. A conductive material is formed in the contact holes
and on the first insulating layer 12, for example using a
well-known Chemical Vapor Deposition (CVD) technique. The
conductive material is planarized to form a plurality of contact
plugs, for example, contact plugs 14a in the cell array region and
contact plugs 14b to 14e on the peripheral region. The conductive
material may be polysilicon, tungsten and/or copper. Other suitable
conductive materials also may be used.
[0027] A lower electrode layer (first conductive layer) 16, a
capacitor dielectric film 17 and an upper electrode layer (second
conductive layer) 18 are sequentially formed on the substrate 10.
The lower and upper electrode layers 16 and 18 may comprise
material selected from the group consisting of a refractory metal,
conductive oxide and a combination thereof. The refractory metal
may include Pt (platinum), Ir (iridium), Ru (ruthenium), Au (gold)
and/or Pd (palladium). The conductive oxide may include
IrO.sub.2(iridium dioxide) and RuO.sub.2(ruthenium dioxide). The
dielectric film 17 preferably comprises a ferroelectric material
such as PZT, PLZT, SBT and/or BST. Other conventional materials
also may be used for the lower and upper electrode layers and the
capacitor dielectric films.
[0028] Referring now to FIG. 2, selected portions of the stacked
layers 16, 17 and 18 are patterned to form predetermined patterns
at the cell array region and peripheral region. More specifically,
in the cell array region, a ferroelectric capacitor 20 is formed
from lower electrode pattern 16a, ferroelectric film pattern 17a
and upper electrode pattern 18a. The ferroelectric capacitor in the
cell array region is electrically connected to the contact plug
14a.
[0029] On the other hand, in the peripheral region, lower electrode
patterns 16b, 16c, 16d, 16e and 16g and pseudo-capacitors 21, 22
and 23 are formed. Although the pseudo-capacitors 21, 22 and 23
also are formed at the peripheral region, they are not electrically
connected to an underlying contact plug. Therefore, these capacitor
patterns 21, 22 and 23 do not serve as capacitors. However, upper
electrode patterns 18b, 18c and 18d of the pseudo-capacitors 21, 22
and 23, respectively, can serve as conductive pads for later-formed
interconnections. Some of the lower electrode patterns may be
selectively electrically connected to the contact plugs as shown by
dashed contact plugs 14b, 14c, and 14d and by the solid contact
plug 14e. These lower electrode patterns also can serve as
conductive pads.
[0030] Referring now to FIG. 3, a second insulating layer 30 is
formed on the substrate 10, for example by deposition. Selected
portions of the second insulating layer 30 are patterned to form
first openings that expose the lower electrode patterns 16b, 16c,
16d, 16e and 16g in the peripheral region. Patterning may take
place by etching, for example using chemical-mechanical polishing.
A first level interconnection 32a to 32d is completed by forming a
conducive material in the first openings and on the second
insulating layer 30 and then patterning thereof into a
predetermined configuration. The first level interconnection
preferably is made of the same material that was already used as
the lower and upper electrode layers 16 and 18, respectively.
[0031] Referring now to FIG. 4, a third insulating layer 34 is
formed on the first level interconnection and on the second
insulating layer 30. Selected portions of the third insulating
layer 34 and the second insulating layer 30 thereunder are etched
to form second openings that expose the upper electrode pattern 18a
of the ferroelectric capacitor 20 in the cell array region and
expose some 32c and 32d of the first level interconnections 32a to
32d and the upper electrode patterns 18b to 18d of the capacitor
patterns 21 to 23 in the peripheral region. A second level
interconnection 36a to 36d is completed by forming conductive
material in the second openings and on the third insulating layer
34 and then patterning thereof into a predetermined configuration.
Patterning may take place by etching, for example using
chemical-mechanical polishing. The second level interconnection
preferably is made of the same material that was already used as
the lower and upper electrode layers 16 and 18 respectively.
[0032] The resulting interconnection structure in the peripheral
region is as follows: The lower electrode pattern 16b is
electrically connected to the first level interconnection 32a. The
lower electrode pattern 16b may be electrically connected to a
source/drain region of a CMOS transistor through the contact plug
14b. The lower electrode patterns 16c and 16d are electrically
connected to each other through the first level interconnection
32b. One of the lower electrode patterns 16a and 16c may be
electrically connected to the source/drain region of a CMOS
transistor.
[0033] The lower electrode pattern 16e is electrically connected to
the upper electrode pattern 18b of the pseudo-capacitor 21. In
particular, the lower electrode pattern 16e is connected to the
first level interconnection 32c and the first level interconnection
32c is electrically connected to the upper electrode pattern 18b
through the second level interconnection 36b. The lower electrode
pattern 16e may be electrically connected to the source/drain
region of a CMOS transistor.
[0034] The lower electrode pattern 16g is electrically connected to
a source/drain region of a CMOS transistor through the contact plug
14e, and also is electrically connected to the second level
interconnection 36c through the first level interconnection
32d.
[0035] Adjacent pseudo-capacitors 22 and 23 are electrically
connected to each other through the second level interconnection
36d. However, since these pseudo-capacitors 22 and 23 are not
electrically connected to the source/drain regions of CMOS
transistors, they do not function as a capacitor. In particular,
adjacent upper electrode patterns 18c and 18d are electrically
connected to each other through the second level interconnection
36d.
[0036] Accordingly, the aspect ratio of the contact openings can be
reduced due to the presence of the pseudo-capacitors, thereby
allowing improved step coverage of the interconnection. Also, the
multi-level interconnection can be implemented using the same
material as the capacitor electrodes, to thereby allow simplified
fabrication.
[0037] In the drawings and specification, there have been disclosed
typical preferred embodiments of the invention and, although
specific terms are employed, they are used in a generic and
descriptive sense only and not for purposes of limitation, the
scope of the invention being set forth in the following claims.
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