U.S. patent application number 09/751941 was filed with the patent office on 2001-08-30 for method for fabricating a semiconductor device.
Invention is credited to Choi, Jun Gi, Kim, Seon Soon.
Application Number | 20010018243 09/751941 |
Document ID | / |
Family ID | 19635060 |
Filed Date | 2001-08-30 |
United States Patent
Application |
20010018243 |
Kind Code |
A1 |
Kim, Seon Soon ; et
al. |
August 30, 2001 |
Method for fabricating a semiconductor device
Abstract
A method for fabricating a semiconductor device is disclosed. In
a process for fabricating a CMOS transistor of a high integrated
semiconductor device and a cell of a DRAM, a process for forming a
dual gate electrode having a layered structure of a tungsten layer
and a polysilicon layer includes the steps of forming a gate
electrode shape from an undoped polysilicon layer, forming an
insulating film spacer at sidewalls of the polysilicon layer,
forming an LDD region, removing a portion of the undoped
polysilicon layer to leave a predetermined thickness and to form an
opening in which the tungsten layer will be formed, and
respectively implanting different impurity ions into the undoped
polysilicon layer respectively formed in the PMOS region and the
NMOS region before forming the tungsten layer. Thus, it is possible
to prevent etching residue from occurring and also prevent the
semiconductor substrate from being damaged. In addition, it is
possible to prevent the tungsten layer from being oxidized due to a
high temperature process such as an ion plantation process for
forming the LDD region and the source/drain region, thereby
improving operational characteristics of the device and process
yield.
Inventors: |
Kim, Seon Soon;
(Kyoungki-do, KR) ; Choi, Jun Gi; (Kyoungki-do,
KR) |
Correspondence
Address: |
Pillsbury Winthrop LLP
Intellectual Property Group
Ninth Floor
1100 New York Avenue, NW.
Washington
DC
20005-3918
US
|
Family ID: |
19635060 |
Appl. No.: |
09/751941 |
Filed: |
January 2, 2001 |
Current U.S.
Class: |
438/221 ;
257/E21.637; 257/E21.654; 257/E21.66; 438/231; 438/592 |
Current CPC
Class: |
H01L 27/10873 20130101;
H01L 21/823842 20130101; H01L 27/10894 20130101 |
Class at
Publication: |
438/221 ;
438/231; 438/592 |
International
Class: |
H01L 021/8238; H01L
021/3205; H01L 021/4763 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 31, 1999 |
KR |
1999-67972 |
Claims
What is claimed is:
1. A method for fabricating a semiconductor device comprising the
steps of: forming a gate insulating film on a semiconductor
substrate provided with a cell region and a peripheral circuit
region where NMOS and PMOS regions will be formed; forming an
undoped polysilicon layer pattern of a gate electrode shape on the
gate insulating film; forming an oxide film having a predetermined
thickness on an upper portion of an entire surface; respectively
forming an LDD region in the semiconductor substrate at both sides
of the undoped polysilicon layer pattern of both the PMOS region in
the peripheral circuit region and the NMOS regions in the cell
region and the peripheral circuit region; forming a nitride film
having a predetermined thickness on the upper portion of the entire
surface; etching the nitride film and the oxide film by entire
etching process to form a spacer having a double structure of a
nitride film and an oxide film at sidewalls of the undoped
polysilicon layer pattern; implanting a heavy concentration of
impurity ions into both spacers of the NMOS region and the PMOS
region in the peripheral circuit region to form source/drain
regions; forming an interlayer insulating film on the upper portion
of the entire surface and then planarizing the interlayer
insulating film to expose the undoped polysilicon layer pattern;
removing a portion of the exposed undoped polysilicon layer pattern
by etching to leave a predetermined thickness and to form a groove;
implanting impurity ions into the undoped polysilicon layer pattern
of the NMOS and PMOS regions in the cell region and the peripheral
circuit region, to form a gate electrode pattern comprising a doped
polysilicon; forming a diffusion prevention film and a metal layer
in a lower portion of the groove; and forming a mask insulating
film pattern in a remaining portion of the groove.
2. The method of claim 1, wherein the oxide film is formed by
thermal oxidation process.
3. The method of claim 1, wherein the diffusion prevention film
comprises WN.
4. The method of claim 1, wherein the metal layer is formed of a
material selected from a group consisting of tungsten, TiSi.sub.x
and WSi.sub.x.
5. The method of claim 1, wherein the interlayer insulating film
comprises an oxide film or a nitride film.
6. The method of claim 1, wherein forming the mask insulating film
pattern further comprises forming a nitride film on the upper
portion of the entire surface and then planarizing the nitride film
by chemical mechanical polishing (CMP) using the interlayer
insulating film as an etching barrier.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for fabricating a
semiconductor device, and more particularly, to a method for
forming a gate electrode by a semi-damascene process to prevent a
metal layer from being oxidized when a gate electrode having a
layered structure of the metal layer and a polysilicon layer is
formed in a CMOS transistor of a high integrated device such as a
DRAM cell.
[0003] 2. Background of the Related Art
[0004] In a prior art method for fabricating a dual gate electrode
device, a n.sup.+ gate and a p.sup.+ gate are respectively
deposited and patterned on an upper portion of an undoped
polysilicon layer using a mask and dual implantation method
(n.sup.+: As.P, p.sup.+: B.BF.sub.2), or an in-situ doping
method.
[0005] The dual implantation method has a relatively simple
process, but it is difficult to achieve high doping levels. Also,
in the dual implantation method, it is likely that gate depletion
will occur as a result of the dopant profile characteristics.
[0006] In the in-situ doping method it is necessary to set up
respective process steps, because the gate electrodes for the
n.sup.+ and p.sup.+ polysilicon layers should be formed
separately.
[0007] A prior art method for fabricating a semiconductor device
will be described with reference to the accompanying drawings.
[0008] FIGS. 1A to 1C are sectional views showing prior art process
steps for fabricating a semiconductor device.
[0009] As shown in FIG. 1A, a device isolation film 12 is formed to
define active regions on a semiconductor substrate 10.
[0010] A p-type well is formed in a portion where an NMOS device
will be formed (NMOS region I), and an n-type well is formed in a
portion where a PMOS device will be formed (region II).
[0011] Subsequently, a gate insulating film 14 is formed on the
upper portion of the entire surface, and a polysilicon layer is
formed on the gate insulating film 14. A first photoresist film
pattern is then formed on the polysilicon layer to expose the NMOS
region I. An n.sup.+ polysilicon layer is formed by an n-type
impurity ion implantation using the first photoresist film pattern
as an ion implantation mask.
[0012] Afterwards, the first photoresist film pattern is removed. A
second photoresist film pattern is then formed on the polysilicon
layer to expose the PMOS region II. A p.sup.+ polysilicon layer 16a
is formed by a p-type impurity ion implantation using the second
photoresist film pattern as an ion implantation mask. Then, the
second photoresist film pattern is removed.
[0013] Next, a diffusion prevention film 18a, a metal layer 20a,
and a mask insulating film 22a are sequentially formed on the upper
portion of the entire surface to form a layered structure.
[0014] As shown in FIG. 1B, the layered structure and the
polysilicon layer into which the impurity ions were implanted are
etched using a gate electrode mask that which protects a portion
where a gate electrode will be formed as an etching mask. Thus, a
mask insulating film pattern 22b, a metal layer pattern 20b, a
diffusion prevention film pattern 18b, an n.sup.+ gate electrode
15b, and a p.sup.+ gate electrode 16b are formed.
[0015] Afterwards, the n.sup.+ gate electrode 15b, the p.sup.+ gate
electrode 16b, and the exposed semiconductor substrate 10 are
selectively oxidized to form a buffer insulating film 24.
[0016] Subsequently, a mask process is respectively performed in
the NMOS region I and the PMOS region II, so that a lightly doped
impurity ion implants can be made into the NMOS region I and the
PMOS region II. Thus, an n-LDD region 26a and a p-LDD region 26b
are formed.
[0017] As shown in FIG. 1C, a double structure of an oxide film
spacer 28 and a nitride film spacer 30 is formed at the sidewalls
of the mask insulating film pattern 22b, the metal layer pattern
20b, the diffusion prevention film pattern 18b, and the n.sup.+
gate electrode 15b/the p.sup.+ gate electrode 16b respectively.
[0018] Subsequently, a mask process is respectively performed in
the NMOS region I and the PMOS region II, so that a heavily doped
impurity ion is implanted into the NMOS region I and the PMOS
region II. Thus, an n.sup.+ source/drain region 27a and a p.sup.+
source/drain region 27b are formed. The nitride film spacer 30 will
act as an etching barrier in a later self-aligned contact
process.
[0019] Afterwards, an interlayer insulating film 32 is formed on
the upper portion of the entire surface and then planarized.
[0020] The aforementioned related art method for fabricating a
semiconductor device has several problems.
[0021] The metal layer pattern constituting the gate electrode
expands during later annealing processes. The metal layer pattern
also expands due to etching selectivity differences between the
mask insulating film and the metal layer pattern during etching
process for forming the gate electrode. For this reason, the
impurity ion is not implanted into a corner portion of the gate
electrode during the subsequent ion implantation process for
forming the LDD regions. Furthermore, lifting of the gate electrode
can occur due to oxidation of the metal layer pattern. This
deteriorates the device characteristics, yield and reliability.
SUMMARY OF THE INVENTION
[0022] Accordingly, the present invention is directed to a method
for fabricating a semiconductor device that substantially overcomes
one or more of the problems limitations and disadvantages of the
prior.
[0023] An object of the present invention is to provide a method
for fabricating a semiconductor device which prevents a metal layer
from being oxidized during subsequent high temperature processes
such as an ion implantation process, by forming a conductive layer
pattern of polysilicon or amorphous silicon in a gate electrode
shape, forming an insulating film spacer at the sidewalls of the
conductive layer pattern, forming an LDD region by a lightly doped
impurity ion implantation, removing a predetermined thickness of
the conductive layer pattern to form a metal layer pattern, and
then forming a gate electrode.
[0024] Additional advantages, objects, and features of the
invention will be set forth in part in the description which
follows and in part will become apparent to those having ordinary
skill in the art upon examination of the following or may be
learned from practice of the invention. The objects and advantages
of the invention may be realized and attained as particularly
pointed out in the appended claims.
[0025] To achieve these and other advantages and in accordance with
the purpose of the present invention, as embodied and broadly
described, a method for fabricating a semiconductor device
according to the present invention includes the steps of: forming a
gate insulating film on a semiconductor substrate provided with a
cell region and a peripheral circuit region where NMOS and PMOS
regions will be formed; forming an undoped polysilicon layer
pattern having a gate electrode shape on the gate insulating film;
forming an oxide film having a predetermined thickness on an upper
portion of the entire surface; respectively forming an LDD region
in the semiconductor substrate at both sides of the undoped
polysilicon layer pattern of both in PMOS region in the peripheral
circuit region and the NMOS regions in the cell region and the
peripheral circuit region; forming a nitride film having a
predetermined thickness on the upper portion of the entire surface;
etching the nitride film and the oxide film without patterning to
form a spacer having a double structure of a nitride film and an
oxide film at sidewalls of the undoped polysilicon layer pattern;
respectively implanting a heavily doped impurity ion into both
spacers of the NMOS region and the PMOS region in the peripheral
circuit region to form a source/drain region; forming an interlayer
insulating film on the upper portion of the entire surface and then
planarizing the interlayer insulating film to expose the undoped
polysilicon layer pattern; removing a portion of the exposed
undoped polysilicon layer pattern by the entire etching process to
leave a predetermined thickness and form a groove; respectively
implanting impurity ions into the undoped polysilicon layer pattern
of the NMOS and PMOS regions in the cell region and the peripheral
circuit region, to form a gate electrode of doped polysilicon;
forming a diffusion prevention film and a metal layer having a
predetermined depth in an upper portion of the groove; and forming
a mask insulating film pattern buried in the upper portion of the
exposed groove.
[0026] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are intended to provide further explanation of
the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The invention will be described in detail with reference to
the following drawings in which like reference numerals refer to
like elements wherein:
[0028] FIGS. 1A to 1C are sectional views illustrating related art
process steps of fabricating a semiconductor device; and
[0029] FIGS. 2A to 2I are sectional views illustrating process
steps of fabricating a semiconductor device according to the
present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0030] Reference will now be made in detail to the preferred
embodiments of the present invention, examples of which are
illustrated in the accompanying drawings.
[0031] As shown in FIG. 2A, a device isolation insulating film 101
is formed to define an active region of a semiconductor substrate
100.
[0032] A first photoresist film pattern 102 is formed on upper
portion of an entire surface to expose a portion where an NMOS
region III of a cell region will be formed in the semiconductor
substrate 100. A p-type impurity ion is implanted into the
semiconductor substrate 100 using the first photoresist film
pattern 102 as an ion implantation mask to form a p-type well.
[0033] The above process steps are repeated, so that a p-type well
and an n-type well are formed in an NMOS region I and a PMOS region
II in a peripheral circuit region of the semiconductor substrate
100.
[0034] As shown in FIG. 2B, the first photoresist film pattern 102
is removed and a layered structure of a gate insulating film 103
and an undoped polysilicon layer 104a is formed on the upper
portion of the entire surface. At this time, the undoped
polysilicon layer 104a has the same thickness as that the stacked
conductive layer, metal layer and mask insulating film that will be
formed later. The conductive layer, the metal layer and the mask
insulating film later will be used to form the gate electrode.
[0035] As shown in FIG. 2C, the undoped polysilicon layer 104a is
etched using a gate electrode mask, which protects a portion where
a gate electrode will be formed, as an etching mask, to form an
undoped polysilicon layer pattern 104b.
[0036] Then, an oxide film 105a having a predetermined thickness is
formed on the upper portion of the entire surface by a thermal
oxidation process both to compensate for the semiconductor
substrate 100 damaged during the etching process and to prevent the
semiconductor substrate 100 and the undoped polysilicon layer
pattern 104b from being damaged during the subsequent formation of
a nitride film.
[0037] Subsequently, a second photoresist film pattern 106 is
formed on the oxide film 105a to protect the PMOS region II. An
n-LDD region 107a is formed by implanting an n type lightly doped
impurity ion using the second photoresist film pattern 106 as an
ion implantation mask.
[0038] As shown in FIG. 2D, the second photoresist film pattern 106
is removed, and a p-LDD region 107b is formed in the PMOS region II
in the same manner as above. A nitride film 108a is then formed on
the upper portion of the entire surface to a predetermined
thickness.
[0039] As shown in FIG. 2E, the nitride film 108a and the oxide
film 105a are etched to form a layered structure of a nitride film
spacer 108b and an oxide film spacer 105b at the sidewalls of the
undoped polysilicon layer pattern 104b.
[0040] Subsequently, a third photoresist film pattern 109 is formed
on the upper portion of the entire surface to expose the PMOS
region II of the peripheral circuit region.
[0041] Afterwards, a heavily doped p.sup.+ source/drain region 10b
is formed by implanting a high dose of a p-type doped impurity ion
into the semiconductor substrate 100 at both sides of the layered
structure using the third photoresist film pattern 109 as an ion
implantation mask.
[0042] The third photoresist film pattern 109 is then removed, and
a heavily doped n.sup.+ source/drain region 110a is formed by
implanting a high dose of an n-type impurity ion into the NMOS
region I of the peripheral circuit region in the same manner as
above.
[0043] As shown in FIG. 2F, an interlayer insulating film 111 is
formed on the upper portion of the entire surface and is then
removed by a chemical mechanical polishing (CMP) process to expose
the uppermost portion of the undoped polysilicon layer pattern
104b. The interlayer insulating film 111 may comprise an oxide film
or a nitride film.
[0044] As shown in FIG. 2G, a portion of the undoped polysilicon
layer pattern 104b is removed by selective etching process, leaving
a desired thickness of the polysilicon, forming a groove between
the oxide film spacers 105b and exposing a portion where the gate
electrode will be formed.
[0045] A fourth photoresist film pattern 112 is formed on the upper
portion of the entire surface to protect the PMOS region II.
[0046] Next, an n.sup.+ polysilicon layer pattern 104c is formed by
implanting an n-type impurity ion into the exposed undoped
polysilicon layer pattern 104b using the fourth photoresist film
pattern 112 as an ion implantation mask.
[0047] As shown in FIG. 2H, the fourth photoresist film pattern 112
is removed, and a p.sup.+ polysilicon layer pattern 104d is formed
by implanting a p-type impurity ion into the undoped polysilicon
layer pattern 104b of the PMOS region II in the same manner as
above.
[0048] Subsequently, a diffusion prevention film 113a is formed on
the upper portion of the entire surface at a predetermined
thickness, and a metal layer 114a is formed on the diffusion
prevention film 113a to completely fill the groove. It is preferred
that, the diffusion prevention film 113a is formed of WN having a
thickness 50A.about.150A to prevent the metal layer 114a from being
oxidized. The metal layer 114a is preferably formed from tungsten
layer, TiSi.sub.x or WSi.sub.x layer.
[0049] As shown in FIG. 2I, the majority of metal layer 114a and
the diffusion prevention film 113a are removed by etching to form a
metal layer pattern 114b and a diffusion prevention film pattern
113b in the lower portion of the groove and to expose the upper
portion of the groove to a predetermined depth.
[0050] Afterwards, a mask insulating film is formed on the upper
portion of the entire surface and then substantially removed by a
CMP process. The CMP process is performed using the interlayer
insulating film 111 as an etching barrier to form a mask insulating
film pattern 115 which will fill the exposed upper portion of the
groove.
[0051] As noted above, the method for fabricating a semiconductor
device according to the present invention has various
advantages.
[0052] In the process for fabricating a CMOS transistor of a high
integrated semiconductor device and a cell of a DRAM, a process for
forming a dual gate electrode having a layered structure of a
tungsten layer and a polysilicon layer includes the steps of
forming a gate electrode shape of an undoped polysilicon layer,
forming an insulating film spacer at sidewalls of the polysilicon
layer, forming an LDD region, removing the undoped polysilicon
layer at a predetermined thickness to expose a portion where the
tungsten layer will be formed, and respectively implanting
different impurity ions into the undoped polysilicon layer
respectively formed in the PMOS region and the NMOS region to form
the tungsten layer. Thus, it is possible to prevent etching residue
from occurring and also prevent the semiconductor substrate from
being damaged. In addition, it is possible to prevent the tungsten
layer from being oxidized due to a high temperature process such as
an ion plantation process for forming the LDD region and the
source/drain region, thereby improving operational characteristics
of the device and process yield.
[0053] The foregoing embodiments and advantages are merely
exemplary and are not to be construed as limiting the present
invention. The present method can be readily applied to other types
of apparatuses. The description of the present invention is
intended to be illustrative, and not to limit the scope of the
claims. Many alternatives, modifications and variations will be
apparent to those skilled in the art. In the claims,
means-plus-function clauses are intended to cover the structures
described herein as performing the recited function and not only
structural equivalents but also equivalent structures.
* * * * *