U.S. patent application number 09/751927 was filed with the patent office on 2001-08-30 for circuit and a method for extending the output voltage range of an integrator circuit.
This patent application is currently assigned to STMicroelectronics S.r.I.. Invention is credited to Mazzucco, Michelangelo, Poletto, Vanni, Protti, Melano Carlo Lorenzo.
Application Number | 20010017564 09/751927 |
Document ID | / |
Family ID | 8243735 |
Filed Date | 2001-08-30 |
United States Patent
Application |
20010017564 |
Kind Code |
A1 |
Mazzucco, Michelangelo ; et
al. |
August 30, 2001 |
Circuit and a method for extending the output voltage range of an
integrator circuit
Abstract
A circuit extends the output voltage range of an integrator
circuit wherein the input signal is used to produce an output
signal, and the voltage of the output signal develops monotonically
within a predetermined range of possible values. The integrator
circuit is driven within an integration time period such that each
time the signal at its output reaches a limit of the range of
values, the integrator circuit starts a subsequent integration
stage of the input signal in which the output signal develops again
within the above-mentioned range. This takes place by resetting the
integrator circuit or by a reversal of the characteristic slope of
the output signal. This is combined with storing the number of
occasions on which these interventions have occurred as determined
by a counter. This enables the actual voltage value of the signal
resulting from the integration to be calculated by a relatively
straightforward mathematical operation from the reading of the
counter, and from the signal currently present at the output of the
integrator at the end of the integration period.
Inventors: |
Mazzucco, Michelangelo;
(Santa Maria Del Tempio, IT) ; Poletto, Vanni;
(Casale Monferrato, IT) ; Protti, Melano Carlo
Lorenzo; (Pavia, IT) |
Correspondence
Address: |
CHRISTOPHER F. REGAN
Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
P.O. Box 3791
Orlando
FL
32802-3791
US
|
Assignee: |
STMicroelectronics S.r.I.
|
Family ID: |
8243735 |
Appl. No.: |
09/751927 |
Filed: |
December 29, 2000 |
Current U.S.
Class: |
327/336 |
Current CPC
Class: |
G01L 23/225 20130101;
G06J 1/00 20130101 |
Class at
Publication: |
327/336 |
International
Class: |
G06G 007/18 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 30, 1999 |
EP |
99830814.2 |
Claims
That which is claimed is:
1. A circuit for extending the output voltage range of an
integrator circuit wherein the input signal is such as to produce
an output signal the voltage of which develops monotonically within
a predetermined range of possible values, said circuit comprising:
control circuit means for controlling the integrator circuit in a
manner such that, within an integration time period, each time the
output signal of the integrator circuit reaches a limit of the
range of values, the integration circuit starts a subsequent
integration stage of the input signal in which the signal output by
the integrator develops again within the same range; and counting
means associated with the control means for counting and outputting
the number of times the output signal of the integrator circuit has
reached a limit value, the number being correlated with the number
of times the output signal has covered the said range of values,
the actual voltage value reached at the end of the integration
period being calculable from a final voltage value of the output
signal of the integrator circuit reached at the end of the
integration period, and from the number of times the signal has
reached a limit value.
2. A circuit according to claim 1, wherein the control circuit
means comprise: comparator means for comparing the voltage of the
output signal of the integrator circuit with at least one reference
voltage corresponding to a limit of the range of values, the means
being able to emit at least one respective control signal as a
result of the reaching of said limit during the development of the
output signal; and drive means for driving the integrator circuit,
the drive means being associated with the comparator means and
being arranged to cause a subsequent integration stage of the input
signal to start in dependence on the control signals received from
the comparator means.
3. A circuit according to claim 2, wherein the comparator means
comprise a threshold comparator circuit to the non-inverting input
of which a reference voltage is applied and to the inverting input
of which the output signal of the integrator circuit is applied,
and the drive means comprise a monostable multivibrator circuit
which is arranged to receive, at a control input, a control signal
emitted by the threshold comparator circuit, and which can emit,
towards the integrator circuit, a resetting pulse of predetermined
duration each time the comparator circuit detects that the output
signal has reached a limit value.
4. A circuit according to claim 3, wherein the counting means can
be coupled at their output to a processing unit which can read its
content and which can receive a datum relating to the final voltage
value of the output signal of the integrator circuit, the
processing unit being arranged to calculate the actual voltage
value reached at the end of the integration period in accordance
with the equation: V.sub.out=N.times.V.sub.sup+V.sub.o in which:
V.sub.sup is the value of the reference voltage of the threshold
comparator.
5. A circuit according to claim 2, wherein the comparator means
comprise: a first threshold comparator circuit to the inverting
input of which a first reference voltage corresponding to an upper
limit of the range of possible values for the output voltage signal
of the integrator circuit is applied, and to the non-inverting
input of which the voltage of the output signal of the integrator
circuit is applied, and a second threshold comparator circuit to
the non-inverting input of which a second reference voltage
corresponding to a lower limit of the range of possible values for
the output signal of the integrator circuit is applied, and to the
inverting input of which the voltage of the output signal of the
integrator circuit is applied.
6. A circuit according to claim 5, comprising control circuit means
for controlling the gain of the integrator circuit, the control
circuit means being associated with the integrator circuit and
being arranged to invert its gain in dependence on a control input
signal.
7. A circuit according to claim 6, wherein the drive means comprise
a bistable multivibrator circuit which is arranged to receive, at
its control input and at its resetting input, control signals
emitted by the first and by the second threshold comparator
circuits, respectively, and which can emit towards the gain control
means a respective control signal such as to invert the gain each
time a comparator circuit detects that the voltage of the output
signal has reached a limit value, so as to reverse the trend of the
output signal of the integrator circuit.
8. A circuit according to claim 6, wherein the gain control means
of the integrator circuit comprise a pair of amplifier circuits
with unitary gain of the inverting and non-inverting type,
respectively.
9. A circuit according to claim 7 or claim 8, wherein the counting
means can be coupled at their output to a processing unit which can
read its content and which can receive a datum relating to the
final value of the output voltage signal of the integrator circuit,
the processing unit being arranged to calculate the actual voltage
value reached at the end of the integration period in accordance
with the equation:
V.sub.out=N.times.(V.sub.sup-V.sub.inf)+(V.sub.sup-V.sub.o).times.SGAIN+(-
V.sub.o-V.sub.inf).times.(1-SGAIN)+V.sub.inf in which: V.sub.sup is
the value of the first reference voltage of the respective first
threshold comparator, V.sub.inf is the value of the second
reference voltage of the respective second threshold comparator,
and SGAIN is the logic value adopted by the control signal of the
gain control means of the integrator circuit at the end of the
integration period.
10. A circuit according to claim 1, further comprising resetting
means connected to a resetting input of the integrator circuit and
arranged to receive, at a control input, a signal for controlling
the integration operation and to emit, towards the integrator
circuit, a resetting signal.
11. A circuit according to claim 10, wherein the resetting means
comprise a monostable multivibrator circuit which can emit a
resetting pulse of predetermined duration towards the integrator
circuit at the beginning of an integration period.
12. A method of extending the range of the output voltage of an
integrator circuit wherein the input signal is such as to produce
an output signal the voltage of which develops monotonically within
a predetermined range of possible values, the method comprising the
steps of: comparing the voltage of the output signal of the
integrator circuit with at least one reference voltage
corresponding to a limit of the range of values, driving the
integrator circuit, after the limit has been reached during the
development of the output signal during an integration period, in a
manner such that said circuit starts a subsequent integration stage
of the input signal in which the output signal develops again
within the same range, counting the number of times the output
signal of the integrator circuit has reached a limit value so that
a subsequent integration stage has been started, the number being
correlated with the number of times the output signal has covered
the range of values, and calculating the actual voltage value
reached at the end of the integration period from a final value of
the voltage of the output signal of the integrator circuit and from
the number of times the signal has reached a limit value.
13. A method according to claim 12, wherein the step of driving the
integrator circuit includes resetting of the circuit each time its
output signal has reached a limit value of the range of possible
values.
14. A method according to claim 13, wherein the actual voltage
value reached at the end of the integration period is calculated in
accordance with the equation: V.sub.out=N.times.V.sub.sup+V.sub.c
in which: V.sub.sup is the value of the reference voltage.
15. A method according to claim 12, wherein the voltage of the
output signal of the integrator circuit is compared with a pair of
reference voltages, that is, a first reference voltage
corresponding to an upper limit of the range of values and a second
reference voltage corresponding to a lower limit of the range of
values, respectively.
16. A method according to claim 15, wherein the step of driving the
integrator circuit includes the inversion of the gain of the
circuit each time the voltage of the output signal has reached one
of the upper and lower limit values, so as to reverse the trend of
the signal.
17. A method according to claim 16, wherein the actual voltage
value reached at the end of the integration period is calculated in
accordance with the equation:
V.sub.out=N.times.(V.sub.sup-V.sub.inf)+(V.sub.sup-V.s-
ub.o).times.SGAIN+(V.sub.o-V.sub.inf).times.(1-SGAIN)+V.sub.inf in
which: V.sub.sup is the value of the first reference voltage,
V.sub.inf is the value of the second reference voltage, and SGAIN
is a logic value determined in dependence on the gain of the
integrator circuit at the end of the integration period.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a circuit and to a method
for extending the range of the output voltage of an integrator
circuit beyond its supply voltage. More particularly, the present
invention relates to a circuit of this type associated with an
integrator circuit used in automotive applications, and, more
specifically, in detecting knocking in internal combustion
engines.
BACKGROUND OF THE INVENTION
[0002] In a system for detecting knocking in an internal combustion
engine, one or more wide-band accelerometric knock sensors are
provided, and advantageously are disposed on the engine block in
the vicinity of the cylinders. These sensors register variations in
pressure on the cylinder walls and translate them into electrical
signals which are processed in a control unit to distinguish the
pressure contributions due to knocking from those relating to
operation with correct combustion.
[0003] During this processing, the electrical signal coming from
the sensor is amplified and filtered, and after being rectified, is
sent to an integration stage which outputs a voltage signal. This
voltage signal is proportional to the energy of the initial
electrical signal, is within the filtering band, and is
proportional to the integration period.
[0004] At the end of the integration period, the value of the
voltage signal reached by an integrator circuit of the integration
stage is stored, for example, in a sample/hold circuit and made
available as an output to further processing stages. These further
processing stages are arranged to identify the occurrence of
knocking from the value of this signal and to provide feedback
control to a system controlling ignition in the engine.
[0005] It can easily be understood that the value of the voltage
signal output by the integrator circuit may reach high levels if
the integration time is long. Conventional integrator circuits
formed with operational amplifiers and capacitive feedback
components have a maximum limit for their output voltage, which may
increase or decrease monotonically within the integration time
period. This limit cannot be passed and is determined by the supply
voltage supplied to the circuit, or by the supply voltages if there
are two, that is, one positive and one negative.
[0006] When an operational amplifier is required to have an output
voltage close to or greater than this limit, it ceases to operate
linearly and reaches a saturation condition in which the voltage no
longer increases (decreases) as the integration time passes.
Instead, the voltage adopts a maximum (minimum) limit value which
is substantially constant and is within the limits imposed by the
supply voltage.
[0007] The approaches according to the prior art, which are
referred to in the technical literature as "rail-to-rail" circuits,
do not provide for these limits to be exceeded, but only to be
approached as closely as possible.
SUMMARY OF THE INVENTION
[0008] An object of the present invention is to provide a system
which enables the range of the output voltage of an integrator
circuit to be artificially extended beyond the limits imposed by
the supply voltage.
[0009] According to the present invention, this object is achieved
by a circuit having the characteristics recited in claim 1. A
further subject of the invention is a method having the
characteristics recited in claim 12.
[0010] In summary, the present invention is based on the principle
of monitoring the development of the voltage signal generated by an
integrator circuit according to the prior art and resetting the
circuit (or, in an alternative embodiment, reversing the
characteristic slope of the output signal) each time its output
voltage reaches a predetermined limit close to the saturation
condition.
[0011] This is combined with the step of memorizing the number of
occasions on which these interventions have occurred by using a
counter which is connected to the integrator circuit, and which is
incremented each time the integrator is reset (or the slope of the
output signal is reversed).
[0012] At the end of the predetermined integration period, the
content of the counter will thus indicate how many times the
voltage signal generated by the integrator has covered the entire
range naturally available during its increasing or decreasing
development. This will enable the actual voltage value of the
signal resulting from the integration to be calculated by a simple
mathematical operation from the reading of the counter and from the
signal currently present at the output of the integrator, as will
be described further in the following examples.
[0013] The embodiment according to the present invention thus
enables a substantially unlimited, although fictitious, output
voltage range to be provided in an integrator circuit. In a circuit
of the type used, for example, in control systems for detecting the
degree of knocking in internal combustion engines, this enables
simpler control systems to be produced. These control systems are
advantageously produced which operate from a single voltage supply
(for example, 5 V) both for the active elements of the integrator
circuit and for the logic circuits, and any micro-controllers
present in the engine electronic control unit.
[0014] A further advantage is that the integration period can be
extended at will and more efficient engine control algorithms can
be established. The greater efficiency achieved enables an engine
of the same type to have lower consumption and greater power than
with current approaches.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Further characteristics and advantages of the invention will
be explained in greater detail in the following detailed
description of different embodiments thereof, given by way of
non-limiting examples, with reference to the appended drawings, in
which:
[0016] FIG. 1 is a block diagram of a system for detecting knocking
in an internal combustion engine according to the present;
[0017] FIG. 2 is a circuit diagram of a first embodiment of an
integration circuit stage comprising a circuit according to the
present invention,
[0018] FIG. 3 is a series of graphs indicative of the quantities
representative of the operation of the integration circuit stage
illustrated in FIG. 2;
[0019] FIG. 4 is a circuit diagram of a second embodiment of an
integration circuit stage comprising a circuit according to the
present invention; and
[0020] FIG. 5 is a series of graphs indicative of the quantities
representative of the operation of the integration circuit stage
illustrated in FIG. 4.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0021] In a system for detecting knocking in an internal combustion
engine, a wide-band accelerometric knock sensor 10 is disposed on
the engine block in the vicinity of the cylinders. The sensor 10
registers variations in pressure on the walls of the cylinders and
translates them into an electrical voltage signal, which is
indicated as V.sub.k in the circuit diagram of FIG. 1 and is
proportional to the acoustic energy detected.
[0022] An amplifier block 12 is coupled to the sensor 10 and
receives and amplifies the signal V.sub.k.A band-pass filter 14
previously tuned to the characteristic knock frequency of the
engine in question is downstream of the amplifier block 12. The
amplified and filtered voltage signal V.sub.F is a signal
proportional to the amplitude of the knocking alone. A rectifier
stage 16 is downstream of the filter 14 and has an output voltage
signal V.sub.r substantially corresponding to the envelope of the
signal V.sub.F.
[0023] An integration stage 18 is coupled to the output of the
rectifier stage 16 by a first input (or signal input) and has its
output connected to a first input of a comparator circuit 20. The
output of the comparator circuit 20 corresponds to the output of
the knocking detection system as a whole.
[0024] The integration stage 18 comprises a conventional
operational-amplifier integrator circuit 22, a circuit for
extending the output voltage range of the integrator circuit, and a
sample/hold circuit 24. The sample/hold circuit 24 is for the
temporary storage of the voltage value reached at the output of the
integrator circuit 22 at the end of the integration period. This
value is proportional to the knock energy.
[0025] When the system is in operation, the signal V.sub.r output
by the rectifier stage 16 is integrated within a predetermined
period of time T.sub.1 to derive an output signal V.sub.out. The
integration period Ti is determined by a control logic signal GATE
supplied to a second input (or control input) of the integration
stage 18 so as to correspond to the period of time in which the
intensity of knocking is greater than the background noise. The
selection of the duration of this period of time determines the
efficiency of the knocking detection.
[0026] The comparator circuit 20 has a second input which receives
a reference signal V.sub.th indicative of a knock intensity
threshold, and is arranged to emit an output signal V.sub.c
indicative of the occurrence of knocking. As is well known to one
skilled in the art, this signal may be made available to a circuit
controlling ignition advance in a conventional closed-loop
system.
[0027] A first embodiment of an integration stage 18 according to
the invention is described in detail with reference to FIG. 2. The
integrator circuit 22 receives the rectified voltage signal V.sub.r
by a first input (or signal input) of the integration stage 18, and
has its output coupled to the sample/hold circuit 24. The control
input of the sample/hold circuit 24 receives the control logic
signal GATE from the second input (or control input) of the
integration stage.
[0028] The output of the sample/hold circuit 24, at which the
output signal V.sub.o is produced by the integrator circuit 22, is
connected to the inverting input of a threshold comparator 30. The
non-inverting input of the threshold comparator 30 receives a
reference voltage V.sub.sup. The function of the comparator 30 is
to detect when the voltage of the signal V.sub.o exceeds the value
V.sub.sup.
[0029] The output of the threshold comparator 30 is connected to
the control input TR1.sub.i of a first monostable multivibrator 32,
the transition of which from the stable state to the quasi-stable
state is induced by the trailing edge of the signal output by the
comparator. The multivibrator 32 in turn is coupled to a resetting
input of the integrator circuit 22 by an AND logic gate 34.
[0030] The control logic signal GATE is present at the control
input TR2.sub.i of a second monostable multivibrator 36, the
transition of which from the stable state to the quasi-stable state
is induced by the leading edge of the signal GATE. The output
TR2.sub.o of the multivibrator 36 is also coupled to the resetting
input of the integrator circuit 22 by the AND logic gate 34.
[0031] A counter 38 is coupled to the output TR2.sub.o of the
second multivibrator 36 by its own resetting input CL, and has its
own drive input CK coupled directly to the output of the comparator
30. The increment of the counter is induced by the trailing edge of
the signal present at the drive input. A plurality of output
terminals b0, b1, . . . , bn, and OV is provided for presenting the
content of the counter and for indicating a possible overflow
condition thereof, respectively. The monostable multivibrators 32,
36 and the counter 38 are together indicated as the control circuit
40 of the integrator circuit 22.
[0032] The operation of the integration stage 18 as a whole will
now be described in detail with reference to FIG. 3. At the
beginning of an integration period T.sub.1 determined by the signal
GATE at a high logic level, both the integrator circuit 22 and the
sample/hold circuit 24 are reset. The resetting of the integrator
circuit 22 is controlled by a signal RESET which has a pulse (logic
zero) of predetermined time duration produced by the multivibrator
36, and which is excited by the active edge of the signal GATE.
[0033] The sample/hold circuit 24 is operated in its sampling stage
so as to transmit to its output the signal currently present at the
output of the integrator V.sub.o. At the same time, the content of
the counter 38 is cleared. The curves of the signals GATE and RESET
against time are shown in the third and fifth graphs of FIG. 3,
respectively.
[0034] In the example shown, the signal V.sub.r input to the
integrator circuit 22 is a rectified sinusoidal signal. The
integrator circuit 22 generates a substantially ramp-like output
signal V.sub.o. When this signal has reached the reference voltage
V.sub.sup it causes the output signal COMP of the threshold
comparator 30 to switch (see the fourth graph of FIG. 3) from a
first logic level (high level) to a second logic level (low
level).
[0035] The trailing edge of the signal COMP increases the content
of the counter, and at the same time, brings about the transition
of the multivibrator 32 to the quasi-stable state so that the
multivibrator 32 sends a resetting pulse to the integrator circuit
22. When resetting has taken place, the signal V.sub.o can start to
increase again in dependence on the signal V.sub.r, and obviously
the output signal COMP of the threshold comparator 30 switches back
to the first logic level.
[0036] The process described may be repeated any number of times,
basically in dependence on the preselected duration of the
integration time period T.sub.i. The limit of the operation of the
control circuit 40 is imposed exclusively by the capacity of the
counter 38 used. An overflow condition of the counter may be
indicated by a high level signal at the output terminal OV.
[0037] At the end of the integration period T.sub.i, the control
signal GATE switches to a low logic level and the sample/hold
circuit 24 stores the voltage value V.sub.o reached at that moment
at the output of the integrator circuit 22.
[0038] The actual value of the voltage of the output signal
V.sub.out of the integration stage 18 can thus be derived
mathematically from the voltage value V.sub.o reached at the output
of the integrator circuit at the end of the integration period
(final value) and from the content of the counter. That is, from
the number N of times (encoded in binary form by the bits b0, b1, .
. . , bn) the signal V.sub.o has covered the entire range available
at the output of the integrator circuit during its increasing
development. This value is given by the expression:
V.sub.out=N.times.V.sub.sup+V.sub.o
[0039] The variable V.sub.sup is the value of the reference voltage
of the threshold comparator corresponding to the upper value of the
output voltage range of the integrator circuit.
[0040] This operation can easily be performed by a conventional
processing unit (not shown) arranged to convert the analog signal
V.sub.o into a digital signal, and to perform the programmed
arithmetic calculation.
[0041] In an alternative embodiment, the control circuit 40 may be
implemented as a single digital circuit, for example, a finite
state machine. This finite state machine is arranged to receive the
input signals GATE and COMP, and advantageously generates the
resetting signals for the integrator circuit 22, the control
signals for the sample/hold circuit 24, and the output signal of
the counter 38 while maintaining substantially the same timings as
described above.
[0042] With the circuit arrangement described by way of example,
the output voltage range of the integration stage 18 is thus
extended artificially by resetting the integrator circuit 22 each
time its output voltage reaches a predetermined limit close to the
saturation condition, and by counting the number of resettings.
[0043] Alternatively, an approach is provided in which the range is
extended by varying the gain of the integrator circuit so as to
reverse the characteristic slope of its output signal each time its
output voltage reaches a predetermined upper or lower limit close
to the saturation condition, and by counting how many times this
reversal operation has taken place.
[0044] A second embodiment which can bring about this behavior is
described in detail with reference to FIG. 4. Elements identical or
functionally equivalent to those illustrated in FIG. 2 have been
indicated by the same references already used in the description of
the previous embodiment.
[0045] The integrator circuit 22 is coupled to an amplifier block
50 with unitary gain. The input of the amplifier block 50 receives
the rectified voltage signal Vr that is also input to the
integration stage. The integrator circuit 22 is also coupled to the
sample/hold circuit 24 which is downstream therefrom, and the
control input of which receives the control logic signal GATE from
the second input of the integration stage 18.
[0046] The task of the amplifier block 50 is simply to transfer the
signal V.sub.r input to the integrator circuit 22 in a direct or
inverted manner, advantageously establishing a gain of +1 or -1, as
required. The block 50 may be formed as a set of two amplifiers
with unitary gain of the inverting type and of the non-inverting
type, respectively, which can be selected by associated switches.
Alternatively, the block 50 may be incorporated in the integrator
circuit 22 if it is of the type with switched capacitors so that
the selection of a positive or negative gain takes place by
suitable driving of the switches provided.
[0047] The output of the sample/hold circuit 24 provides the signal
V.sub.o which is applied to the non-inverting input of a first
threshold comparator 52 which has an inverting input receiving a
first reference voltage V.sub.sup, and to the inverting input of a
second threshold comparator 54 which has a non-inverting input
receiving a second reference voltage V.sub.inf. The function of the
comparators 52 and 54 is to detect when the voltage of the signal
V.sub.o exceeds the value V.sub.sup or falls below the value
V.sub.inf, respectively.
[0048] The outputs of the first and second threshold comparators
52, 54 are connected, respectively, to the resetting input R and to
the control input S of a bistable multivibrator or RS flip-flop 56
which in turn is connected to a control input of the amplifier
block 50.
[0049] The control logic signal GATE establishes at the control
input TR.sub.1 of a monostable multivibrator 36, the transition of
which from the stable state to the quasi-stable state is induced by
the leading edge of the signal GATE. The output TR.sub.o of the
multivibrator 36 is coupled to the resetting input of the
integrator circuit 22.
[0050] A counter 38 is coupled to the output TR.sub.o of the
multivibrator 36 by its own resetting input CL and has its own
drive input CK coupled to the outputs of the comparators 52, 54 by
an OR logic gate 58. The increment of the counter is induced by the
leading edge of the signal present at the drive input. A plurality
of output terminals b0, b1, . . . , bn, and OV is provided for
presenting the content of the counter and for indicating a possible
overflow condition thereof, respectively.
[0051] The monostable multivibrator 36, the flip-flop 56, and the
counter 38 are together indicated as the control circuit 40 of the
integrator circuit 22. The operation of the integration stage 18 as
a whole, according to this embodiment will now be described in
detail with reference to FIG. 5.
[0052] At the beginning of an integration period Ti, determined by
the signal GATE at a high logic level, both the integrator circuit
22 and the sample/hold circuit 24 are reset. The resetting of the
integrator circuit is controlled by the signal RESET which has a
pulse (logic one) of predetermined time duration. This pulse is
produced by the multivibrator 36 excited by the active edge of the
signal GATE. The sample/hold circuit 24 is operated in its sampling
stage as in the previous embodiment. At the same time, the content
of the counter 38 is cleared. The curves of the signals GATE and
RESET against time are shown in the third and seventh graphs of
FIG. 5, respectively.
[0053] As a result of the resetting of the integrator circuit, the
output signal V.sub.o initially has a voltage lower than both of
the reference voltages V.sub.inf and V.sub.sup, so that the signal
C2 output to the threshold comparator 54 is at a high logic level
and brings about, by the control input S, the transition of the
flip-flop 56 to a first state. In this state, the flip-flop emits a
control logic signal SGAIN to the amplifier block 50 such as
initially to establish a positive gain value (for example,
SGAIN=1).
[0054] It will be clear to one skilled in the art, however, that
this transition of the signal C2 is not noticed at the drive input
CK of the counter 38 since the latter simultaneously receives a
resetting signal at the input CL.
[0055] In the embodiment shown, the signal V.sub.r input to the
integrator circuit 22 is again a rectified sinusoidal signal so
that the integrator circuit generates a substantially ramp-like
output signal V.sub.o. When this signal has reached the first
reference voltage V.sub.sup, it causes the output signal Cl of the
threshold comparator 52 to switch (see the fourth graph of FIG. 5)
from a first logic level (low level) to a second logic level (high
level).
[0056] The leading edge of the signal Cl increases the content of
the counter 38, and at the same time, brings about by the resetting
input R the transition of the flip-flop 56 to a second state in
which the flip-flop consequently emits a control logic signal SGAIN
to the amplifier block 50 such as to establish a negative gain
value (for example, SGAIN=0).
[0057] When the gain of the amplifier block has been changed, the
signal V.sub.o develops with a decreasing amplitude, again in
dependence on the signal V.sub.r. The output signal Cl of the
threshold comparator 52 switches back to the first logic level.
When the signal V.sub.o reaches the second reference voltage
V.sub.inf, it causes the output signal C2 of the threshold
comparator 54 to switch (see the fifth graph of FIG. 5) from a
first logic level (low level) to a second logic level (high
level).
[0058] The leading edge of the signal C2 increases the content of
the counter 38 again, and at the same time brings about by the
control input S the transition of the flip-flop 56 to the first
state. This causes the emission of a control signal SGAIN to the
amplifier block 50 such as to re-establish a positive gain value
(for example, SGAIN=1 again).
[0059] The process described above may be repeated any number of
times in dependence on the preselected duration of the integration
period T.sub.i. As in the previous embodiment, the limit of the
operation of the control circuit 40 is imposed exclusively by the
capacity of the counter 38 used, and any overflow condition is
indicated by a high level signal at the output terminal OV. At the
end of the integration period T.sub.i, the control signal GATE
switches to a low logic level and the sample/hold circuit 24 stores
the voltage value V.sub.o reached at that moment at the output of
the integrator circuit 22.
[0060] The actual value of the voltage of the output signal
V.sub.out of the integration stage 18 can thus be derived
mathematically from the voltage value V.sub.o reached at the output
of the integrator circuit at the end of the integration period
(final value) and from the content of the counter. That is, from
the number N of times (encoded in binary form by the bits B0, b1, .
. . , bn) the signal V.sub.o has covered the entire range available
at the output of the integrator circuit during its increasing and
decreasing development. This value is given by the expression:
V.sub.out=N.times.(V.sub.sup-V.sub.inf)+(V.sub.sup-V.sub.o).times.SGAIN+
(V.sub.o-V.sub.inf).times.(1-SGAIN)+V.sub.inf
[0061] The variable V.sub.sup is the value of the first reference
voltage of the threshold comparator 52 corresponding to the upper
value of the output voltage range of the integrator circuit. The
variable V.sub.inf is the value of the second reference voltage of
the threshold comparator 54 corresponding to the lower value of the
output voltage range of the integrator circuit. The variable SGAIN
is the logic value adopted by the control signal of the amplifier
at the end of the integration period. That is, 1 if the gain of the
amplifier is positive (+1) and 0 if it is negative (-1).
[0062] In the above expression, the last addition takes account of
the fact that, initially, when the integrator circuit 22 is reset,
its output voltage V.sub.0 adopts a substantially zero starting
value which is generally different from the value of the second
reference voltage value V.sub.inf. As already described with
reference to the previous embodiment, this operation can easily be
performed by a conventional processing unit (not shown).
[0063] In an alternative embodiment, the control circuit 40 may be
implemented as a single digital circuit, for example, a finite
state machine arranged to receive the input signals GATE, C1 and
C2. The finite state machine advantageously generates the resetting
signal for the integrated circuit 22, the control signal for the
sample/hold circuit 24, the control signal for the amplifier block
50, and the output signal of the counter 38 while maintaining
substantially the same timings as described above.
[0064] It is clear from the examples described that, with the use
of a circuit according to the invention, it is possible to
advantageously use a low supply voltage, for example 5 V, for the
active elements of the integrator circuit. By using "rail-to-rail"
integrator circuits, it is possible to set values of about 0.5 V
and 4.5 V for the reference voltages V.sub.inf and V.sub.sup,
respectively, but without limiting the range of the voltage
V.sub.out which can be reached by the integration stage as a whole
to 4 V.
[0065] Naturally, the principle of the invention remains the same,
the forms of embodiment and details of implementation may be varied
widely with respect to those described and illustrated purely by
way of non-limiting examples, without thereby departing from the
scope of protection of the present invention. In particular,
although the examples relate to embodiments in which the output
voltage of the integrator circuit adopts exclusively positive
values, one skilled in the art will have no problem in
appreciating, in the light of the foregoing description, that these
embodiments may be extended to a situation in which the integrator
circuit has a symmetrical dual supply.
* * * * *