U.S. patent application number 09/778772 was filed with the patent office on 2001-08-30 for pulse generator.
Invention is credited to Kim, Kang Yong.
Application Number | 20010017563 09/778772 |
Document ID | / |
Family ID | 27349772 |
Filed Date | 2001-08-30 |
United States Patent
Application |
20010017563 |
Kind Code |
A1 |
Kim, Kang Yong |
August 30, 2001 |
Pulse generator
Abstract
A pulse generator, which only occupies a small area in a circuit
chip by using a characteristic that the potential in both ends of a
capacitor is maintained. The pulse generator comprises a voltage
level control unit for controlling a voltage level of a first node
according to the state of input signal; a first switching unit for
controlling a voltage level of a second node by performing a
switching operation according to the state of the input signal; a
second switching unit for changing a voltage level of the second
node by performing another switching operation, opposite to the
first switching means according to the state of the input signal; a
charge/discharge unit for charging/discharging a voltage between
the first and the second nodes according to the switching state of
the first and the second switching means; and an output unit for
outputting a pulse signal according to the charging/discharging
state of the charge/discharge means.
Inventors: |
Kim, Kang Yong;
(Kyoungki-do, KR) |
Correspondence
Address: |
JACOBSON HOLMAN PLLC
400 SEVENTH STREET N.W.
SUITE 600
WASHINGTON
DC
20004
US
|
Family ID: |
27349772 |
Appl. No.: |
09/778772 |
Filed: |
February 1, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09778772 |
Feb 1, 2001 |
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09342524 |
Jun 29, 1999 |
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6211709 |
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Current U.S.
Class: |
327/333 |
Current CPC
Class: |
H03K 5/1534
20130101 |
Class at
Publication: |
327/333 |
International
Class: |
H03L 005/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 29, 1998 |
KR |
1998-24818 |
Dec 29, 2000 |
KR |
2000-86310 |
Claims
What is claimed is:
1. A pulse generator comprising: means for receiving an input
signal; a first node; a second node; a voltage level control means
for controlling a voltage level of the first node according to a
state of the input signal; a first switching means for controlling
a voltage level of the second node by performing a switching
operation according to the state of the input signal; a second
switching means for changing a voltage level of the second node by
performing another switching operation, opposite to the first
switching means according to the state of the input signal; a
charge/discharge means for charging/discharging a voltage between
the first and the second nodes according to a switching state of
the first and the second switching means; and an output means for
outputting a pulse signal according to the charging/discharging
state of the charge/discharge means.
2. The pulse generator according to claim 1, wherein the voltage
level control means comprises: a first pull-up unit for receiving
the input signal through its gate terminal and the power voltage
through its source terminal; and a second pull-up unit of receiving
the power voltage through its source terminal, wherein the drain
terminal thereof is commonly connected to that of the first pull-up
unit and the gate terminal thereof is connected to the common drain
terminal and is further connected to the first node.
3. The pulse generator according to claim 1, wherein the voltage
level control means comprises: a first pull-up unit for receiving
the input signal through its gate terminal, wherein the source
terminal thereof is connected to an end of the charge/discharge
means; and a second pull-up unit of receiving the power voltage
through its source terminal, wherein the drain terminal thereof is
commonly connected to that of the first pull-up unit and, the gate
terminal thereof is connected to the common drain terminal and is
further connected to the first node.
4. The pulse generator according to claim 1, wherein the first
switching means comprises: a pull-up unit for receiving the input
signal through its gate terminal wherein the source terminal
thereof is connected to the power voltage terminal and the drain
terminal thereof is connected to an end of the charge/discharge
means through the second node.
5. The pulse generator according to claim 4, wherein the second
switching means comprises: a pull-down unit, which is connected
between an end of the charge/discharge means and the ground voltage
terminal, for receiving the input signal through its gate
terminal.
6. The pulse generator according to claim 4, wherein the second
switching means comprises: an inverter for inverting the input
signal; and a pull-up unit, which is connected between the
charge/discharge means and the ground voltage terminal, for
receiving the input signal inverted from the inverter through its
gate terminal.
7. The pulse generator according to claim 1, wherein the first
switching means comprises: a pull-down unit of receiving the input
signal through its gate terminal, wherein the drain terminal
thereof is connected to the power voltage terminal and the source
terminal thereof is connected to an end of the charge/discharge
means through the second node.
8. The pulse generator according to claim 7, wherein the second
switching means comprises: a pull-up unit, which is connected
between the charge/discharge means and the ground voltage terminal,
for receiving the input signal through its gate terminal.
9. The pulse generator according to claim 1, wherein the first
switching means comprises: an inverter for inverting the input
signal ; and a pull-down unit of receiving the input signal
inverted from the inverter through its gate terminal, wherein the
drain terminal thereof is connected to the ground voltage terminal
and the source terminal thereof is connected to an end of the
charge/discharge means through the second node.
10. The pulse generator according to claim 9, wherein the second
switching means comprises: a pull-down unit, which is connected
between the charge/discharge means and the ground voltage terminal,
for receiving the input signal through its gate terminal.
11. The pulse generator according to claim 1, wherein the first
switching means comprises: an inverter for inverting the input
signal ; and a pull-up unit of receiving the input signal inverted
from the inverter through its gate terminal, wherein the source
terminal thereof is connected to the power voltage terminal and the
drain terminal thereof is connected to an end of the
charge/discharge means through the second node.
12. The pulse generator according to claim 11, wherein the second
switching means comprises: a pull-up unit, which is connected
between the charge/discharge means and the ground voltage terminal,
for receiving the input signal through its gate terminal.
13. The pulse generator according to claim 1, wherein the
charge/discharge means is a capacitor.
14. The pulse generator according to claim 1, wherein the output
means is an inverter for inverting the voltage of the first
node.
15. The pulse generator according to claim 1, wherein the voltage
level control means comprises: a first pull-down unit for receiving
the input signal through its gate terminal, wherein the source
terminal thereof is connected to the ground voltage terminal; and a
second pull-down unit, the drain terminal of which is commonly
connected to that of the first pull-down unit, the gate terminal of
which is connected to the common drain terminal and is further
connected to the first node, and the source terminal of which is
connected to the ground voltage terminal.
16. The pulse generator according to claim 1, wherein the voltage
level control means comprises: a first pull-down unit of receiving
the input signal through its gate terminal, wherein the source
terminal thereof is connected to an end of the charge/discharge
means; and a second pull-down unit, the drain terminal of which is
commonly connected to that of the first pull-down unit, the gate
terminal of which is connected to the common drain terminal and is
further connected to the first node, and the source terminal of
which is connected to the ground voltage terminal.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a pulse generator, in
particular to a pulse generator for generating a pulse signal,
which, as a circuit element, only occupies a small area by making
use of a characteristic that the potential in both ends of a
capacitor is maintained.
[0003] 2. Description of the Background Art
[0004] In general, a Synchronous Dynamic Random Access Memory
(SDRAM) is a memory device for controlling input/output of data
synchronized with a clock (CLK) signal, in which internal pulse
signals are generated regularly, thereby controlling input/output
of data according to the CLK signal.
[0005] FIG. 1 is a view illustrating a conventional pulse
generator.
[0006] Referring to FIG. 1, the pulse generator comprises a delay
unit 1 for receiving an input signal Sin, delaying it by a certain
time interval and then outputting the delayed signal as a delay
signal D, and a NAND gate 2 for receiving the input signal Sin and
the delay signal D applied from the delay unit 1. The NAND gate
performs a NAND operation and then outputs a pulse signal Sout.
[0007] The delay unit 1 of FIG. 1 can be constructed as shown in
FIGS. 2a or 2b.
[0008] The delay unit 1, as shown in FIG. 2a, can be made by
serially connecting an odd number of inverters IVO in order to
delay the input signal Sin. The delay unit 1, as shown in FIG. 2b,
may also be made by serially connecting an odd number of inverters
IVO through the medium of a resistor R1 in order to delay the input
signal Sin.
[0009] As shown in FIG. 3, a conventional pulse generator having
the above-mentioned construction outputs a pulse signal Sout that
is synchronized with a low level when the input signal Sin
transitions from low to high.
[0010] FIG. 1 shows an example of generation of a pulse being
synchronized with a rising time of the input signal Sin. Unlike
this, a circuit for generating a pulse being synchronized with a
falling time of the input signal Sin is disclosed in FIG. 4.
[0011] Referring to FIG. 4, the pulse generator comprises a delay
unit 3 for receiving an input signal Sin, delaying it by a certain
time interval and then outputting the delayed signal as a delay
signal D, and an NOR gate 4 for receiving the input signal Sin and
the delay signal D applied from the delay unit 1. The NOR gate
performs a NOR operation and then outputting a pulse signal
Sout.
[0012] As shown in FIG. 5, the conventional pulse generator having
a construction as shown in FIG. 4, outputs a pulse signal Sout that
is synchronized with a high level when the input signal Sin
transitions from high to low.
[0013] According to the conventional pulse generator shown in FIGS.
1 and 4, the delay unit 1 has at least six or more transistors for
constructing an odd number of inverters IVO. Also, the NAND gate 2
or NOR gate 4 consists of at least 2 transistors. Furthermore, the
delay unit 1 has a plurality of capacitors or resistors for
lengthening the delay time of the input signal Sin.
[0014] As a result, the conventional pulse generator has at least
eight transistors and a plurality of capacitors or resistors. In
general, the total number of the elements used for constructing the
pulse generator sums between 14 and 18.
[0015] However, the conventional pulse generator as mentioned above
has a disadvantage of occupying a large area when constructing a
semiconductor memory device, because the pulse generator consists
of many elements.
SUMMARY OF THE INVENTION
[0016] Accordingly, it is an object of the present invention to
provide a pulse generator which generates a pulse signal by making
use of a characteristic of a capacitor that a potential at both
ends of the capacitor is maintained, thereby implementing a pulse
generator in a small area.
[0017] In order to achieve the above-described object and one
aspect of the present invention, a pulse generator comprises: a
voltage level control means for controlling a voltage level of a
first node according to the state of an input signal; a first
switching means for controlling a voltage level of a second node,
which is switched in accordance with the state of the input signal;
a second switching means for changing the voltage level of the
second node which is switched opposite to the first switching means
according to the state of the input signal; a charge/discharge
means for charging/discharging a voltage between the first node and
the second node according to a switching state of the first and the
second switching means; and an output means for outputting a pulse
signal according to the charging/discharging state of the
charge/discharge means.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The present invention will become better understood with
reference to the accompanying drawings, which are given only by way
of illustration and thus do not limit the present invention,
wherein:
[0019] FIG. 1 is a circuit diagram illustrating a pulse generator
in accordance with conventional art;
[0020] FIG. 2a is a detailed circuit diagram illustrating an
example of a delay unit of FIG. 1;
[0021] FIG. 2b is a detailed circuit diagram illustrating another
example of a delay unit of FIG. 1;
[0022] FIG. 3 is a timing chart for the pulse generator of FIG.
1;
[0023] FIG. 4 is a circuit diagram illustrating another pulse
generator in accordance with conventional art;
[0024] FIG. 5 is a timing chart for the pulse generator of FIG.
4;
[0025] FIG. 6 is a circuit diagram illustrating the first preferred
embodiment of a pulse generator in accordance with the present
invention;
[0026] FIG. 7 is a detailed circuit diagram of the pulse generator
of FIG. 6;
[0027] FIG. 8 is a detailed circuit illustrating a modified
embodiment of the first embodiment in accordance with the present
invention;
[0028] FIG. 9 is a timing chart of the embodiments of FIGS. 7 and
8;
[0029] FIGS. 10 to 13 are detailed circuits illustrating other
modified embodiments of the first embodiment in accordance with the
present invention;
[0030] FIG. 14 is a circuit diagram illustrating the second
embodiment of a pulse generator in accordance with the present
invention;
[0031] FIG. 15 is a detailed circuit diagram of the pulse generator
of FIG. 14;
[0032] FIG. 16 is a detailed circuit diagram illustrating a
modified embodiment of the second embodiment in accordance with the
present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0033] A pulse generator in accordance with preferred embodiments
of the present invention will now be described with reference to
the accompanying drawings.
[0034] The present invention generates a pulse signal by using a
characteristic that a potential of both ends of a capacitor is
maintained and by selectively controlling the switching unit
according to the state of an input signal. That is, changing a
voltage level of both ends of the capacitor generates the pulse
signal.
[0035] FIG. 6 is a circuit diagram illustrating the first preferred
embodiment of a pulse generator in accordance with the present
invention.
[0036] Referring to FIG. 6, the present invention comprises a
voltage level control unit 10 for controlling a voltage level of a
node 1 according to the state of input signal Sin, a first
switching unit 20 for controlling a voltage level of a node 0 by
performing a turn-on/turn-off switching operation according to the
state of input signal Sin, a second switching unit 30 for changing
the voltage level of node 0 by performing another switching
operation opposite to the first switching unit 20 according to the
state of input signal Sin, a capacitor C1, which is connected
between node 1 and node 0, for performing charging/discharging
operation according to a potential difference occurring at both
ends of node 0 and node 1, and an inverter IV1 for inverting the
charge/discharge voltage of the capacitor C1 and outputting a pulse
signal Sout.
[0037] FIG. 7 is a detailed circuit diagram of FIG. 6.
[0038] Referring to FIG. 7, the voltage level control unit 10
comprises a PMOS transistor P2 for receiving an input signal Sin
through its gate terminal, the source terminal of which is
connected to a power voltage terminal Vcc, and a PMOS transistor P1
receiving a power voltage Vcc through its source terminal, the
drain terminal of which is connected to node 1 in common with the
drain terminal of the PMOS transistor P2, and the gate terminal of
PMOS transistor P1 is connected to node 1 together with the common
drain terminals.
[0039] Here, the PMOS transistor P2 is for switching the voltage
being applied to the node 1 and the PMOS transistor P1 is for
maintaining a voltage at node 1.
[0040] The first switching unit 20 comprises a PMOS transistor P3
for receiving an input signal Sin through its gate terminal, the
source terminal of which is connected to the power voltage terminal
Vcc and the drain terminal of which is connected to node 0.
[0041] The second switching unit 30 comprises an NMOS transistor
N1, which is connected between node 0 and a ground voltage terminal
Vss, for receiving an input signal Sin through its gate
terminal.
[0042] A capacitor C1 is constructed between node 1 and the common
drain terminal of PMOS transistors P1 and P2, and node 0 as the
common drain terminal of the PMOS transistor P3 and NMOS transistor
N1. The charge/discharge voltage of the capacitor C1 is outputted
as a pulse signal Sout through the inverter IV1 connected to node
1.
[0043] Here, a resistor (not shown) may be connected respectively
between the source terminal of the PMOS transistor P1 and the power
voltage terminal Vcc, between the drain terminal of the PMOS
transistor P1 and node 1, or between the gate terminal of the PMOS
transistor P1 and node 1.
[0044] In the pulse generator of FIG. 7, the source terminal of
PMOS transistor P2 of the voltage level control unit 10 may be
connected to an end of the capacitor C1 and node 0 as shown in FIG.
8.
[0045] Referring to FIG. 8, a resistor (not shown) may be connected
respectively between the source terminal of the PMOS transistor P1
and the power voltage terminal Vcc, between the drain terminal of
the PMOS transistor P1 and node 1, or between the gate terminal of
the PMOS transistor P1 and node 1.
[0046] Hereinafter, operations of the embodiments of FIGS. 7 and 8
having the above-mentioned construction will be described with
reference to the timing chart of FIG. 9.
[0047] As shown in FIGS. 7 and 8, the pulse generator outputs a
pulse signal Sout that is synchronized with a high level when the
input signal Sin transitions from low to high.
[0048] At an initial state, when the input signal Sin is low, the
NMOS transistor N1 is turned off and the PMOS transistors P1, P2
and P3 are turned on and therefore, node 0 and node 1 become high
by applying the power voltage Vcc.
[0049] Here, when the input signal Sin transitions from low to
high, the PMOS transistors P2 and P3 are turned off and the NMOS
transistor N1 is turned on and therefore, node 0 transitions from
high and low.
[0050] At this time, the capacitor C1 is in a charged state by the
voltage of node 1.
[0051] Accordingly, node 1 becomes low, like node 0, by field the
effect generated at both ends of the capacitor C1, and the signal
disabled to low by the inverter IV1 is inverted. AS a result, a
high signal is outputted as a pulse signal Sout.
[0052] Here, since the capacitor C1 connected to node 1 by the PMOS
transistor P1 has been charged high, the signal charged by the
capacitor C1 is inputted to the inverter IV1 as a high signal and
inverted at the threshold voltage of the inverter IV1 and therefore
a low pulse is outputted as a pulse signal Sout.
[0053] Lastly, when the input signal Sin transitions again to low,
all operations return to the initial condition.
[0054] The voltage waveform of the input signal Sin and pulse
signal Sout is illustrated in FIG. 9.
[0055] Referring to FIG. 9, the pulse width is 2 nsec.
[0056] In the present invention, the main factors affecting the
pulse width of the pulse signal Sout are the size of the transistor
of the second switching unit 30, the capacitance of the capacitor,
the size of PMOS transistor of the voltage level control unit 10
and the threshold voltage of the inverter.
[0057] Accordingly, in the present invention, it is possible to
change the pulse width of the pulse signal Sout by controlling
these sizes.
[0058] FIG. 10 is a circuit diagram of the pulse generator
illustrating another modified embodiment of the first embodiment in
accordance with the present invention.
[0059] Referring to FIG. 10, the first switching unit 20 of the
present invention comprises an NMOS transistor N2 for receiving an
input signal Sin through the transistor's gate terminal, where the
drain terminal thereof is connected to the power voltage terminal
Vcc and the source terminal thereof is connected to node 0.
[0060] The second switching unit 30 comprises a PMOS transistor P4,
which is connected between node 0, an end of the capacitor C1, and
the ground voltage terminal Vss, for receiving an input signal Sin
through its gate terminal.
[0061] FIG. 11 is another modified embodiment of the pulse
generator in accordance with the present invention.
[0062] Referring to FIG. 11, the first switching unit 20 of the
present invention comprises an inverter IV2 for inverting an input
signal Sin, and an NMOS transistor N3 for receiving the input
signal Sin inverted by the inverter IV2 through its gate terminal,
where the drain terminal thereof is connected to the power voltage
terminal Vcc and the source terminal thereof is connected to node
0.
[0063] The second switching unit 30 comprises an NMOS transistor
N4, which is connected between node 0, an end of the capacitor C1,
and the ground voltage terminal Vss, for receiving an input signal
Sin through its gate terminal.
[0064] FIG. 12 is another modified embodiment of the pulse
generator in accordance with the present invention.
[0065] Referring to FIG. 12, the first switching unit 20 of the
present invention comprises an inverter IV3 for inverting an input
signal Sin, and a PMOS transistor P5 for receiving the input signal
Sin inverted by the inverter IV3 through its gate terminal, where
the source terminal thereof is connected to the power voltage
terminal Vcc and the drain terminal thereof is connected to node
0.
[0066] The second switching unit 30 comprises a PMOS transistor P6,
which is connected between node 0, an end of the capacitor C1 and
the ground voltage terminal Vss, for receiving an input signal Sin
through its gate terminal.
[0067] FIG. 13 is another modified embodiment of the pulse
generator in accordance with the present invention.
[0068] Referring to FIG. 13, the first switching unit 20 of the
present invention comprises a PMOS transistor P7 for receiving the
input signal Sin through its gate terminal, where the source
terminal thereof is connected to the power voltage terminal Vcc and
the drain terminal thereof is connected to node 0.
[0069] The second switching unit 30 comprises an inverter IV4 for
inverting an input signal Sin, and a PMOS transistor P8, which is
connected between the capacitor C1 and the ground voltage terminal
Vss, for receiving the input signal Sin inverted by the inverter
IV4 through its gate terminal.
[0070] As mentioned above, the operation of the embodiments of
FIGS. 10 to 13 is the same as that of FIGS. 7 and 8. Also a pulse
signal Sout is outputted as shown in FIG. 9.
[0071] FIG. 14 is a circuit diagram illustrating the second
embodiment of a pulse generator in accordance with the present
invention. Referring to FIG. 14, when the input signal Sin
transitions from high to low, the pulse signal Sout synchronized
with a high level is outputted, which is opposite to that of the
pulse generator of FIG. 6.
[0072] Referring again to FIG. 14, the present invention comprises
a voltage level control unit 40, connected between the input
terminal and the ground voltage terminal Vss, for controlling a
voltage level of node 1 according to the state of input signal Sin,
a first switching unit 50 for controlling a voltage level of node 0
by performing the turn-on/turn-off switching operation according to
the state of the input signal Sin, a second switching unit 60 for
changing the voltage level of node 0 by performing another
switching operation opposite to the first switching unit 50
according to the state of input signal, a capacitor C2 for
performing charging/discharging operation of the voltage between
node 1 and node 0 according to switching states of the first and
the second switching units 50 and 60, and an inverter IV5 for
inverting the output voltage being applied from the capacitor C2
and outputting a pulse signal Sout.
[0073] FIG. 15 is a detailed circuit diagram of the pulse generator
of FIG. 14.
[0074] Referring to FIG. 15, the voltage level control unit 40
comprises an NMOS transistor N5, the source terminal of which is
connected to a ground voltage terminal Vss, for receiving an input
signal Sin through its gate terminal, and an NMOS transistor N6,
where the drain terminal thereof is commonly connected to the NMOS
transistor N5, the gate terminal is connected to the common drain
terminal and is further connected to node 1, and the source
terminal is connected to the ground voltage terminal Vss.
[0075] The first switching unit 50 comprises an NMOS transistor N7
for receiving the input signal Sin through its gate terminal, where
the source terminal thereof is connected to the ground voltage
terminal Vss and the drain terminal is connected to an end of the
capacitor C2 through node 0.
[0076] The second switching unit 60 comprises a PMOS transistor P9,
which is connected between the power voltage terminal Vcc and node
0 of an end of the capacitor C2, for receiving the input signal Sin
through its gate terminal.
[0077] The capacitor C2 is connected between node 1 as a common
drain terminal of the NMOS transistors N5 and N6 and node 0 as a
common drain terminal of the PMOS transistor P9 and the NMOS
transistor N7, and an inverter IV5 is connected to the output
terminal of the capacitor C2 and node 1.
[0078] As shown in FIG. 16, the source terminal of the NMOS
transistor N5 of the voltage level control unit 40, as mentioned
above, may be connected to an end of the capacitor C2.
[0079] Here, a resistor (not shown) may be connected respectively
between the source terminal of the NMOS transistor N6 and the
ground voltage terminal Vss, between the drain terminal of the NMOS
transistor N6 and node 1 or between the gate terminal of the NMOS
transistor N6 and node 1.
[0080] Hereinafter, the operations of the pulse generators of FIGS.
15 and 16 as above-constructed will be described as follows.
[0081] At an initial state, when the input signal Sin is high, the
PMOS transistor P9 is turned off and the NMOS transistors N5, N6
and N7 are turned on and therefore, node 0 and node 1 become high
by connecting to the ground voltage terminal Vss. Here, when the
input signal Sin transitions from high to low, the NMOS transistors
N5 and N7 are turned off and the PMOS transistor P9 is turned on
and therefore, node 0 transitions from high and low.
[0082] Accordingly, node 1 goes low, like node 0, by field the
effect generated at both ends of the capacitor C2, the low signal
is inverted by the inverter IV5 and then a high signal is outputted
as a pulse signal Sout.
[0083] Node 1 goes high by the NMOS transistor N6 and then the
capacitor C2 is charged, the high signal charged in the capacitor
C2 is inputted to the inverter IV5 and then inverted at the
threshold voltage of the inverter IV5 and therefore a low pulse is
outputted as a pulse signal Sout.
[0084] As a result, in the embodiments of the present invention,
the number of the elements being used totals to seven including six
transistors and one capacitor.
[0085] Accordingly, using elements fewer than those of the
conventional pulse generating circuit can still generate the pulse
signal.
[0086] On the other hand, although the capacitor used in the
present invention is an MOS capacitor, it is possible to use all
capacitors including those used in DRAM cells, etc. In particular,
using a capacitor for DRAM cell is very effective, since it allows
large capacitance in a small area.
[0087] As described above, the pulse generator of the present
invention effectively generates a pulse through a pulse generator
occupying a small area.
[0088] As the present invention may be embodied in several forms
without departing from the spirit or essential characteristics
thereof, it should also be understood that the above-described
embodiment is not limited by any of the details of the foregoing
description, unless otherwise specified, but rather should be
construed broadly within its spirit and scope as defined in the
appended claims, and therefore all changes and modifications that
fall within the meets and bounds of the claims, or equivalences of
such meets and bounds are therefore intended to be embraced by the
appended claims.
* * * * *