U.S. patent application number 09/048587 was filed with the patent office on 2001-08-16 for automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor.
Invention is credited to HIRAGA, TAKEFUMI.
Application Number | 20010014965 09/048587 |
Document ID | / |
Family ID | 13581133 |
Filed Date | 2001-08-16 |
United States Patent
Application |
20010014965 |
Kind Code |
A1 |
HIRAGA, TAKEFUMI |
August 16, 2001 |
AUTOMATIC GLOBAL ROUTING DEVICE FOR EFFICIENTLY DETERMINING OPTIMUM
WIRING ROUTE ON INTEGRATED CIRCUIT AND GLOBAL ROUTING METHOD
THEREFOR
Abstract
Automatic routing device which automatically conducts placement
and routing of integrated circuits on an integrated circuit chip,
including a wire capacitance calculating unit, a degree of wire
congestion calculating unit and a routing checking unit for
determining whether routing of a desired net is possible or not
based on degree of wire congestion at each global routing cell
boundary formed by the division of a logic circuit chip to be
processed into global routing cells, and a number of grids
calculating unit, a grid use rate calculating unit and a grid use
rate checking unit for determining whether routing of a desired net
is possible or not based on a state of the use of a routing track
grid in each global routing cell formed on the logic circuit
chip.
Inventors: |
HIRAGA, TAKEFUMI; (TOKYO,
JP) |
Correspondence
Address: |
FOLEY & LARDNER
WASHINGTON HARBOUR
3000 K STREET NW SUITE 500
P O BOX 25696
WASHINGTON
DC
200078696
|
Family ID: |
13581133 |
Appl. No.: |
09/048587 |
Filed: |
March 27, 1998 |
Current U.S.
Class: |
716/129 |
Current CPC
Class: |
G06F 30/394
20200101 |
Class at
Publication: |
716/13 ;
716/14 |
International
Class: |
G06F 017/50 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 27, 1997 |
JP |
9-075609 |
Claims
What is claimed is:
1. Automatic routing device for automatically conducting placement
and routing of integrated circuits on an integrated circuit chip to
be processed, comprising: first determination means for determining
whether routing of a desired net is possible or not based on degree
of wire congestion at each global routing cell boundary formed by
the division of said logic circuit chip into global routing cells;
and second determination means for determining whether routing of a
desired net is possible or not based on a state of the use of a
routing track grid in each global routing cell formed on said logic
circuit chip.
2. The automatic routing device as set forth in claim 1, wherein
said second determination means determines whether routing of said
desired net is possible or not based on, out of grids as points of
intersection between said routing tracks, the number of grids
usable for routing.
3. The automatic routing device as set forth in claim 1, wherein
said second determination means comprising number of usable grids
calculating means for calculating, out of grids as points of
intersection between said routing tracks, the number of grids
usable for routing, number of grids to be used calculating means
for calculating, based on a passing route of wires passing in said
global routing cell, the number of grids to be used by the wires
out of said grids, and routing possibility/impossibility
determining means for determining whether routing of said desired
net is possible or not based on a ratio of said number of grids
usable for routing to said number of grids to be used by the
wires.
4. The automatic routing device as set forth in claim 1, wherein
said second determination means comprising number of usable grids
calculating means for calculating, out of grids as points of
intersection between said routing tracks, the number of grids
usable for routing, number of grids to be used calculating means
for calculating, based on a passing route of wires passing in said
global routing cell, the number of grids to be used by the wires
out of said grids, and determination means for comparing said
number of grids usable for routing and said number of grids to be
used by wires to determine that the routing is impossible when said
number of grids to be used by wires is larger.
5. An automatic routing device for automatically conducting
placement and routing of integrated circuits on an integrated
circuit chip to be processed, comprising: floor plan determining
means for conducting floor plan processing; basic cell placement
means for conducting basic cell placement processing; global
routing route determining means for conducting global routing
processing; and detailed routing route determining means for
conducting detailed routing processing; said global routing route
determining means comprising first determination means for
determining whether routing of a desired net is possible or not
based on degree of wire congestion at each global routing cell
boundary formed by the division of said logic circuit chip into
global routing cells, and second determination means for
determining whether routing of a desired net is possible or not
based on a state of the use of a routing track grid in each global
routing cell formed on said logic circuit chip.
6. The automatic routing device as set forth in claim 5, wherein
said second determination means determines whether routing of said
desired net is possible or not based on, out of grids as points of
intersection between said routing tracks, the number of grids
usable for routing.
7. The automatic routing device as set forth in claim 5, wherein
said second determination means comprising number of usable grids
calculating means for calculating, out of grids as points of
intersection between said routing tracks, the number of grids
usable for routing, number of grids to be used calculating means
for calculating, based on a passing route of wires passing in said
global routing cell, the number of grids to be used by the wires
out of said grids, and routing possibility/impossibility
determining means for determining whether routing of said desired
net is possible or not based on a ratio of said number of grids
usable for routing to said number of grids to be used by the
wires.
8. The automatic routing device as set forth in claim 5, wherein
said second determination means comprising number of usable grids
calculating means for calculating, out of grids as points of
intersection between said routing tracks, the number of grids
usable for routing, number of grids to be used calculating means
for calculating, based on a passing route of wires passing in said
global routing cell, the number of grids to be used by the wires
out of said grids, and determination means for comparing said
number of grids usable for routing and said number of grids to be
used by wires to determine that the routing is impossible when said
number of grids to be used by wires is larger.
9. An automatic routing method of automatically conducting
placement and routing of integrated circuits on an integrated
circuit chip to be processed, comprising the steps of: conducting
floor plan processing; conducting basic cell placement processing;
conducting global routing processing; and conducting detailed
routing processing; said global routing processing step comprising
the steps of dividing said logic circuit chip into global routing
cells, calculating a wire capacitance of each global routing cell
boundary formed at said division step, out of grids as points of
intersection between routing tracks in each global routing cell
formed at said division step, calculating the number of grids
usable for routing, based on a passing route of wires passing in
said global routing cell, calculating the number of grids to be
used by the wires out of said grids, comparing said number of grids
usable for routing calculated at said number of usable grids
calculating step and said number of grids to be used by the wires
calculated at said number of grids to be used calculating step,
determining a routing route of every net such that at least the
cost of said degree of wire congestion calculated at said wire
capacitance calculating step and the cost of said grid use rate for
routing calculated at said number of usable grids calculating step
are minimum, determining whether routing according to a routing
route determined at said routing route determining step is possible
or not based on said wire capacitance calculated at said wire
capacitance calculating step, and determining whether routing
according to a routing route determined at said routing route
determination step is possible or not based on a comparison result
obtained at said number of grids comparing step.
10. The automatic routing method as set forth in claim 9, wherein
said step of determining whether routing is possible or not based
on a wire capacitance comprises the steps of: determining whether
there exists said global routing cell boundary through which a
larger number of wires pass than said wire capacitance calculated
at said wire capacitance calculating step, and when determination
is made at said determination step that there exists said global
routing cell boundary through which a larger number of wires pass
than said wire capacitance, ripping up a net passing through the
global routing cell boundary to return the processing to said route
determination step.
11. The automatic routing method as set forth in claim 9, wherein
said step of determining whether routing is possible or not based
on a ratio of said number of grids usable for routing to said
number of grids to be used for the wires comprises the steps of:
determining whether there exists said global routing cell in which
said number of grids to be used for the wires is larger than said
number of grids usable for routing, and when determination is made
at said determination step that there exists said global routing
cell in which said number of grids to be used for the wires is
larger than said number of grids usable for routing, ripping up a
net passing through the global routing cell to return the
processing to said route determination step.
12. The automatic routing method as set forth in claim 9, wherein
said step of determining whether routing is possible or not based
on a wire capacitance comprises the steps of: determining whether
there exists said global routing cell boundary through which a
larger number of wires pass than said wire capacitance calculated
at said wire capacitance calculating step, and when determination
is made at said determination step that there exists said global
routing cell boundary through which a larger number of wires pass
than said wire capacitance, ripping up a net passing through the
global routing cell boundary to return the processing to said route
determination step, and said step of determining whether routing is
possible or not based on a ratio of said number of grids usable for
routing to said number of grids to be used for the wires comprises
the steps of: determining whether there exists said global routing
cell in which said number of grids to be used for the wires is
larger than said number of grids usable for routing, and when
determination is made at said determination step that there exists
said global routing cell in which said number of grids to be used
for the wires is larger than said number of grids usable for
routing, ripping up a net passing through the global routing cell
to return the processing to said route determination step.
13. A computer readable memory storing a control program for
controlling an automatic routing device which automatically places
and wires integrated circuits on an integrated circuit chip to be
processed, said control program comprising the steps of: conducting
floor plan processing; conducting basic cell placement processing;
conducting global routing processing; and conducting detailed
routing processing; said global routing processing step comprising
the steps of dividing said logic circuit chip into global routing
cells, calculating a wire capacitance of each global routing cell
boundary formed at said division step, out of grids as points of
intersection between routing tracks in each global routing cell
formed at said division step, calculating the number of grids
usable for routing, based on a passing route of wires passing in
said global routing cell, calculating the number of grids to be
used by the wires out of said grids, comparing said number of grids
usable for routing calculated at said number of usable grids
calculating step and said number of grids to be used by the wires
calculated at said number of grids to be used calculating step,
determining a routing route of every net such that at least the
cost of said degree of wire congestion calculated at said wire
capacitance calculating step and the cost of said grid use rate for
routing calculated at said number of usable grids calculating step
are minimum, determining whether routing according to a routing
route determined at said routing route determining step is possible
or not based on said degree of wire congestion calculated at said
wire capacitance calculating step, and determining whether routing
according to a routing route determined at said routing route
determination step is possible or not based on a comparison result
obtained at said number of grids comparing step.
14. The storage medium as set forth in claim 13, wherein said step
of said control program for determining whether routing is possible
or not based on a wire capacitance comprises the steps of:
determining whether there exists said global routing cell boundary
through which a larger number of wires pass than said wire
capacitance calculated at said wire capacitance calculating step,
and when determination is made at said determination step that
there exists said global routing cell boundary through which a
larger number of wires pass than said wire capacitance, ripping up
a net passing through the global routing cell boundary to return
the processing to said route determination step.
15. The storage medium as set forth in claim 13, wherein said step
of said control program for determining whether routing is possible
or not based on a ratio of said number of grids usable for routing
to said number of grids to be used for the wires comprises the
steps of: determining whether there exists said global routing cell
in which said number of grids to be used for the wires is larger
than said number of grids usable for routing, and when
determination is made at said determination step that there exists
said global routing cell in which said number of grids to be used
for the wires is larger than said number of grids usable for
routing, ripping up a net passing through the global routing cell
to return the processing to said route determination step.
16. The storage medium as set forth in claim 13, wherein said step
of said control program for determining whether routing is possible
or not based on a wire capacitance comprises the steps of:
determining whether there exists said global routing cell boundary
through which a larger number of wires pass than said wire
capacitance calculated at said wire capacitance calculating step,
and when determination is made at said determination step that
there exists said global routing cell boundary through which a
larger number of wires pass than said wire capacitance, ripping up
a net passing through the global routing cell boundary to return
the processing to said route determination step, and said step of
determining whether routing is possible or not based on a ratio of
said number of grids usable for routing to said number of grids to
be used for the wires comprises the steps of: determining whether
there exists said global routing cell in which said number of grids
to be used for the wires is larger than said number of grids usable
for routing, and when determination is made at said determination
step that there exists said global routing cell in which said
number of grids to be used for the wires is larger than said number
of grids usable for routing, ripping up a net passing through the
global routing cell to return the processing to said route
determination step.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an automatic global routing
device, in a CAD system which designs and develops a large-scale
integrated circuit (LSI) and a logic circuit by means of a
computer, for automatically placement and routing component cells
on LSI chips or printed boards so as to minimize the entire size or
minimize a routing length and a global routing method therefor.
[0003] 2. Description of the Related Art
[0004] Automatic placement and routing processing of this kind for
placement and routing integrated circuit chips by an automatic
routing device using a CAD system is executed in four steps, floor
plan processing, placement processing, global routing processing
and detailed routing processing.
[0005] In the following, conventional automatic placement and
routing methods will be described with reference to FIGS. 7 and 8.
First, at the floor plan processing, place macro cells on an
integrated circuit to be processed, as well as determining a region
in which basic cells are to be placed as shown in FIG. 8(A) (Step
701). This floor plan processing is conducted semi-automatically.
Next, determination is made whether routing processing is possible
for the integrated circuit subjected to the floor plan processing
(Step 702). When the determination is made that routing is
impossible, the routine returns to Step 701 to execute the floor
plan processing over again.
[0006] When the determination is made at Step 702 that routing is
possible, place desired basic cells at the basic cell placement
region as shown in FIG. 8(B) (Step 703). Then, determination is
made whether routing processing is possible for the integrated
circuit subjected to the basic cell placement processing (Step
704). When the determination is made that routing is impossible,
the routine returns to Step 703 to conduct the placement processing
over again. When the determination is still made at Step 704 that
routing is impossible even after further trials of the placement
processing preset times, the routine returns to Step 701 to start
over with the floor plan processing.
[0007] When the determination is made at Step 704 that routing is
possible, divide the integrated circuit chip to be processed into
rectangles (global routing cells) and determine a routing route of
each net on a divisional unit basis as shown in FIG. 8(C) (Step
705). "Net" here represents a route from an output terminal of an
arbitrary gate circuit to an input terminal of other gate circuit.
For each net, net information indicating which terminals are to be
connected is defined. Global routing processing at Step 705 is
conducted based only on a wire capacitance of a global routing cell
boundary (degree of wire congestion) as will be described later.
Next, determination is made whether routing processing is possible
for the integrated circuit subjected to the global routing
processing (Step 706). When the determination is made that routing
is impossible, the routine returns to Step 705 to conduct the
global routing processing over again. When the determination is
still made at Step 706 that routing is impossible even after
further trials of the global routing processing preset times, the
routine returns to Step 703 to conduct the placement processing
over again. Furthermore, when the determination is still made at
Step 706 that routing is impossible even after further trial of the
placement processing preset times, the routine returns to Step 701
to start over with the floor plan processing.
[0008] When the determination is made at Step 706 that routing is
possible, determine a detailed routing route within each global
routing cell as shown in FIG. 8(D) (Step 707). Then, see if there
is a shorted net or an unrouted net (Step 708). When there is a
shorted net or an unrouted net, the routine returns to Step 707 to
conduct the detailed routing processing over again. If a shorted
net or an unrouted net is still detected at Step 708 even after
further trials of the detailed routing processing preset times, the
routine returns to Step 705 to conduct the global routing
processing over again. Further, when a shorted place or a place yet
to be wired is still detected at Step 708 even after further
executions of the global routing processing preset times, the
routine returns to Step 703 to start over with the placement
processing. Further, if a shorted place or a place yet to be wired
is still detected at Step 708 even after further executions of the
placement processing preset times, the routine returns to Step 701
to start over with the floor plan processing. Then, when there
remains neither a shorted place nor a place yet to be wired (yes at
Step 708), the automatic placement and routing processing is
completed.
[0009] Next, with reference to FIG. 9, detailed description will be
made of the global routing processing (FIG. 7, Step 705) and the
following routing possibility/impossibility determination
processing (FIG. 7, Step 706) at the conventional automatic
placement and routing processing. Conventional global routing
processing of this kind is disclosed, for example, in Japanese
Patent Laying-open (Kokai) No. Heisei 3-278446, entitled "Automatic
Routing Method for Semiconductor Device".
[0010] First, as shown in FIG. 10(A), divide a chip into rectangles
(global routing cells) (Step 901). In FIG. 10(A), a black square
represents a terminal, while a region denoted by slant lines
represents a global route for the connection of terminals. "Global
routing cell" is also called a unit routing region. In the figure,
a boundary between adjacent global routing cells is called a
"global routing cell boundary". More specifically, each global
routing cell has four global routing boundaries in the upper,
lower, right and left directions.
[0011] Next, calculate a wire capacitance which indicates how many
wires can pass through each global routing cell boundary (Step
902). With reference to FIG. 11, a method of calculating a wire
capacitance will be described. In FIG. 11, one specific global
routing cell is denoted by solid lines and a routing track is
denoted by a dotted line. Here, "routing track" represents a
passage on which routing can be made. "Wire capacitance" is
therefore equal to the number of routing tracks passing through a
global routing cell boundary. In addition, a routing inhibited
region is denoted as a block of slant lines. In practice, routing
is made over a plurality of layers. In other words, routing tracks
and routing inhibited regions exist individually on each layer in
practice. In this example, description will be made of one-layer
routing for the purpose of simplicity. In the example illustrated
in FIG. 11, five routing tracks exist in the right-and-left
direction and five routing tracks also exist in the up-and-down
direction. In this case, if there exists no routing inhibited
region within the global routing cell and on the global routing
cell boundaries, a wire capacitance of each global routing cell
boundary will be 5.
[0012] However, since a routing inhibited region exists in practice
as illustrated in FIG. 11, a wire capacitance of each global
routing cell boundary will be less than 5 which is a value derived
from the number of routing tacks. In the example shown in FIG. 11,
the symbol ".smallcircle." on a global routing cell boundary
denotes a passable track, and a wire capacitance of the upper
global routing cell boundary is 3, that of the lower global routing
cell boundary is 4, that of the left-side global routing cell
boundary is 4 and that of the right-side global routing cell
boundary is 3. Here, according to the above literature, a wire
capacitance is obtained as the number of routing tracks allowing
routing which is estimated based on a distribution of obstructions
within the global routing cell (routing inhibited region). In the
global routing processing, therefore, a routing route is selected
such that a wire capacitance will not exceed an estimated value at
each global routing cell boundary.
[0013] Next, based on a wire capacitance of a global routing cell
boundary and already determined global routes, calculate a degree
of congestion of wires which indicates how many wires can be
actually passed through a global routing cell boundary (Step 903).
With a global route set as shown in FIG. 10(A), a global routing
cell boundary through which a wire passes is denoted by an arrow in
FIG. 10(B) and a global routing cell through which a wire passes is
denoted as a block of heavy solid lines. This calculation of a
degree of wire congestion is made per one net yet to be wired,
using the following expression:
[degree of wire congestion]=[the number of passing global
routes]-[wire capacitance].
[0014] Therefore, the higher a value of the degree of wire
congestion is, that is, the closer to zero the value is, the more
wires congest. Zero value of the degree of wire congestion
indicates that no more routing is possible on the global routing
cell boundary. With reference to FIGS. 12 and 13 in addition to
FIG. 11, a method of calculating a degree of wire congestion will
be described. FIG. 12 shows already determined global routes. In
this example, two global routes pass through the upper global
routing cell boundary, one passes through the lower global routing
cell boundary, two pass through the left-side global routing cell
boundary and three pass through the right-side global routing cell
boundary. Calculation of a degree of wire congestion based on the
wire capacitances shown in FIG. 11 and the global routes shown in
FIG. 12 results in that the degree of wire congestion on the upper
global routing cell boundary will be -1 (=2-3) as shown in FIG. 13
because the number of passing global routes is two and the wire
capacitance is 3. Similarly, the degree of wire congestion on the
lower global routing cell boundary will be -3 (=1-4), that of the
left-side global routing cell boundary will be -2 (=2-4) and that
of the right-side global routing cell boundary will be 0
(=3-3).
[0015] Next, based on the cost of distance, the cost of a degree of
wire congestion on a global routing cell boundary, the cost of bend
and other various kinds of costs, determine a routing route
minimizing these costs (Step 904). Then, Steps 903 and 904 will be
repeated until there remains no more unrouted net (Step 905). In
other words, determination of a route minimizing these costs is
made through Steps 903, 904 and 905 taking wire capacitances into
consideration until no unrouted net wired is left.
[0016] When there no more remains a net yet to be wired (no at Step
905), determination is made whether there exists a global routing
cell boundary at which the number of passing wires exceeds its wire
capacitance (that is, a global routing cell boundary with a
positive value of the degree of wire congestion) (Step 906). Here,
when there exists a global routing cell boundary at which the
number of passing wires exceeds its wire capacitance, rip up a net
which passes through the global routing cell boundary (Step 907) to
return to Step 904. On the other hand, when there exists no global
routing cell boundary at which the number of passing wires exceeds
its wire capacitance, the global routing processing is
completed.
[0017] The automatic placement and routing processing by a
conventional automatic routing device, however, has the following
drawback because global routing processing is conducted taking only
a wire capacitance of a global routing cell boundary into
consideration, that is, based only on a degree of wire congestion
as mentioned above.
[0018] Consideration will be given of a global routing cell with
three routing tracks existing in the right-and-left direction and
three routing tracks also in the up-and-down direction as
illustrated in FIG. 14(A). It is assumed that in this global
routing cell, a region denoted by slant lines and including a point
of intersection between the central routing track in the
right-and-left direction and the central routing track in the
up-and-down direction (hereinafter referred to as a central point
of intersection) is a routing inhibited region. In such a case,
wire capacitances of the respective global routing cell boundaries
are all 3.
[0019] With this global routing cell, to pass three wires as a
global route in the right-and-left direction as shown in FIG. 14(B)
results in having such degrees of wire congestion on the global
routing cell boundaries as shown in FIG. 14(C), none of which has a
positive value. In other words, the number of nets passing through
the global routing cell boundary does not exceed a wire
capacitance. Determination is therefore made here that the routing
in question is possible. However, since routing that passes through
the central point of intersection is actually impossible because of
the existence of the routing inhibited region, even if
determination is made at the global routing processing that routing
is possible, routing error will occur at the subsequent detailed
routing processing as shown in FIG. 14(D). This is because two nets
are shorted as illustrated in FIG. 14(D). As a result, the global
routing processing or the preceding placement processing and floor
plan processing should be conducted over again.
[0020] In brief, automatic routing and placement processing by a
conventional automatic routing device has a disadvantage in taking
much time because even when determination is made at global routing
processing that routing is possible, it is highly probable that
determination will be made at detailed routing processing that
routing is impossible.
SUMMARY OF THE INVENTION
[0021] An object of the present invention is to provide an
automatic routing device enabling reduction in time required for
automatic placement and routing processing by lessening a
probability that routing determined to be possible at global
routing processing will be determined to be impossible at detailed
routing processing.
[0022] According to the first aspect of the invention, automatic
routing device for automatically conducting placement and routing
of integrated circuits on an integrated circuit chip to be
processed, comprises
[0023] first determination means for determining whether routing of
a desired net is possible or not based on a wire capacitance at
each global routing cell boundary formed by the division of the
logic circuit chip into global routing cells, and
[0024] second determination means for determining whether routing
of a desired net is possible or not based on a state of the use of
a routing track grid in each global routing cell formed on the
logic circuit chip.
[0025] In the preferred construction, the second determination
means determines whether routing of the desired net is possible or
not based on, out of grids as points of intersection between the
routing tracks, the number of grids usable for routing.
[0026] In the preferred construction, the second determination
means comprises number of usable grids calculating means for
calculating, out of grids as points of intersection between the
routing tracks, the number of grids usable for routing, number of
grids to be used calculating means for calculating, based on a
passing route of wires passing in the global routing cell, the
number of grids to be used by the wires out of the grids, and
routing possibility/impossibility determining means for determining
whether routing of the desired net is possible or not based on a
ratio of the number of grids usable for routing to the number of
grids to be used by the wires.
[0027] In the preferred construction, the second determination
means comprises number of usable grids calculating means for
calculating, out of grids as points of intersection between the
routing tracks, the number of grids usable for routing, number of
grids to be used calculating means for calculating, based on a
passing route of wires passing in the global routing cell, the
number of grids to be used by the wires out of the grids, and
determination means for comparing the number of grids usable for
routing and the number of grids to be used by wires to determine
that the routing is impossible when the number of grids to be used
by wires is larger.
[0028] According to the second aspect of the invention, an
automatic routing device for automatically conducting placement and
routing of integrated circuits on an integrated circuit chip to be
processed, comprises
[0029] floor plan determining means for conducting floor plan
processing,
[0030] basic cell placement means for conducting basic cell
placement processing,
[0031] global routing route determining means for conducting global
routing processing, and
[0032] detailed routing route determining means for conducting
detailed routing processing,
[0033] the global routing route determining means comprising
[0034] first determination means for determining whether routing of
a desired net is possible or not based on a wire capacitance at
each global routing cell boundary formed by the division of the
logic circuit chip into global routing cells, and
[0035] second determination means for determining whether routing
of a desired net is possible or not based on a state of the use of
a routing grid track in each global routing cell formed on the
logic circuit chip.
[0036] In the preferred construction, the second determination
means determines whether routing of the desired net is possible or
not based on, out of grids as points of intersection between the
routing tracks, the number of grids usable for routing.
[0037] In the preferred construction, the second determination
means comprises number of usable grids calculating means for
calculating, out of grids as points of intersection between the
routing tracks, the number of grids usable for routing, number of
grids to be used calculating means for calculating, based on a
passing route of wires passing in the global routing cell, the
number of grids to be used by the wires out of the grids, and
routing possibility/impossibility determining means for determining
whether routing of the desired net is possible or not based on a
ratio of the number of grids usable for routing to the number of
grids to be used by the wires.
[0038] In another preferred construction, the second determination
means comprises number of usable grids calculating means for
calculating, out of grids as points of intersection between the
routing tracks, the number of grids usable for routing, number of
grids to be used calculating means for calculating, based on a
passing route of wires passing in the global routing cell, the
number of grids to be used by the wires out of the grids, and
determination means for comparing the number of grids usable for
routing and the number of grids to be used by wires to determine
that the routing is impossible when the number of grids to be used
by wires is larger.
[0039] According to the third aspect of the invention, an automatic
routing method of automatically conducting placement and routing of
integrated circuits on an integrated circuit chip to be processed,
comprising the steps of:
[0040] conducting floor plan processing,
[0041] conducting basic cell placement processing,
[0042] conducting global routing processing, and
[0043] conducting detailed routing processing,
[0044] the global routing processing step comprising the steps
of
[0045] dividing the logic circuit chip into global routing
cells,
[0046] calculating a wire capacitance of each global routing cell
boundary formed at the division step,
[0047] out of grids as points of intersection between routing
tracks in each global routing cell formed at the division step,
calculating the number of grids usable for routing,
[0048] based on a passing route of wires passing in the global
routing cell, calculating the number of grids to be used by the
wires out of the grids,
[0049] comparing the number of grids usable for routing calculated
at the number of usable grids calculating step and the number of
grids to be used by the wires calculated at the number of grids to
be used calculating step,
[0050] determining a routing route of every net such that at least
the cost of the degree of wire congestion calculated at the wire
capacitance calculating step and the cost of grid use rate for
routing calculated at the number of usable grids calculating step
are minimum,
[0051] determining whether routing according to a routing route
determined at the routing route determining step is possible or not
based on the degree of wire congestion calculated at the wire
capacitance calculating step, and
[0052] determining whether routing according to a routing route
determined at the routing route determination step is possible or
not based on a comparison result obtained at the number of grids
comparing step.
[0053] In the preferred construction, the step of determining
whether routing is possible or not based on a wire capacitance
comprises the steps of:
[0054] determining whether there exists the global routing cell
boundary through which a larger number of wires pass than the wire
capacitance calculated at the wire capacitance calculating step,
and when determination is made at the determination step that there
exists the global routing cell boundary through which a larger
number of wires pass than the wire capacitance, ripping up a net
passing through the global routing cell boundary to return the
processing to the route determination step.
[0055] In the preferred construction, the step of determining
whether routing is possible or not based on a ratio of the number
of grids usable for routing to the number of grids to be used for
the wires comprises the steps of:
[0056] determining whether there exists the global routing cell in
which the number of grids to be used for the wires is larger than
the number of grids usable for routing, and
[0057] when determination is made at the determination step that
there exists the global routing cell in which the number of grids
to be used for the wires is larger than the number of grids usable
for routing, ripping up a net passing through the global routing
cell to return the processing to the route determination step.
[0058] In another preferred construction, the step of determining
whether routing is possible or not based on a wire capacitance
comprises the steps of:
[0059] determining whether there exists the global routing cell
boundary through which a larger number of wires pass than the wire
capacitance calculated at the wire capacitance calculating step,
and
[0060] when determination is made at the determination step that
there exists the global routing cell boundary through which a
larger number of wires pass than the wire capacitance, ripping up a
net passing through the global routing cell boundary to return the
processing to the route determination step, and
[0061] the step of determining whether routing is possible or not
based on a ratio of the number of grids usable for routing to the
number of grids to be used for the wires comprises the steps
of:
[0062] determining whether there exists the global routing cell in
which the number of grids to be used for the wires is larger than
the number of grids usable for routing, and
[0063] when determination is made at the determination step that
there exists the global routing cell in which the number of grids
to be used for the wires is larger than the number of grids usable
for routing, ripping up a net passing through the global routing
cell to return the processing to the route determination step.
[0064] According to another aspect of the invention, a computer
readable memory storing a control program for controlling an
automatic routing device which automatically places and wires
integrated circuits on an integrated circuit chip to be
processed,
[0065] the control program comprising the steps of:
[0066] conducting floor plan processing,
[0067] conducting basic cell placement processing,
[0068] conducting global routing processing, and
[0069] conducting detailed routing processing,
[0070] the global routing processing step comprising the steps
of
[0071] dividing the logic circuit chip into global routing
cells,
[0072] calculating a wire capacitance of each global routing cell
boundary formed at the division step,
[0073] out of grids as points of intersection between routing
tracks in each global routing cell formed at the division step,
calculating the number of grids usable for routing,
[0074] based on a passing route of wires passing in the global
routing cell, calculating the number of grids to be used by the
wires out of the grids,
[0075] comparing the number of grids usable for routing calculated
at the number of usable grids calculating step and the number of
grids to be used by the wires calculated at the number of grids to
be used calculating step,
[0076] determining a routing route of every net such that at least
the cost of the wire capacitance calculated at the wire capacitance
calculating step and the cost of the number of grids usable for
routing calculated at the number of usable grids calculating step
are minimum,
[0077] determining whether routing according to a routing route
determined at the routing route determining step is possible or not
based on the wire capacitance calculated at the wire capacitance
calculating step, and
[0078] determining whether routing according to a routing route
determined at the routing route determination step is possible or
not based on a comparison result obtained at the number of grids
comparing step.
[0079] Other objects, features and advantages of the present
invention will become clear from the detailed description given
herebelow.
BRIEF DESCRIPTION OF THE DRAWINGS
[0080] The present invention will be understood more fully from the
detailed description given herebelow and from the accompanying
drawings of the preferred embodiment of the invention, which,
however, should not be taken to be limitative to the invention, but
are for explanation and understanding only.
[0081] In the drawings:
[0082] FIG. 1 is a block diagram showing structure of an automatic
routing device according to one embodiment of the present
invention.
[0083] FIG. 2 is a flow chart showing operation of global routing
processing in the present embodiment.
[0084] FIG. 3 is a diagram for use in explaining a method of
calculating the number of usable grids.
[0085] FIG. 4 is a diagram for use in explaining a method of
calculating an estimated number of grids to be used in the present
embodiment.
[0086] FIG. 5 is a diagram showing calculation examples of an
estimated number of grids to be used and a grid use rate.
[0087] FIG. 6 is a diagram showing an example of application of
global routing processing according to the present embodiment.
[0088] FIG. 7 is a flow chart showing a flow of integrated circuit
automatic placement and routing processing in outline.
[0089] FIG. 8 is a diagram for use in explaining each processing of
four steps to be executed in the automatic placement and routing
processing shown in FIG. 7.
[0090] FIG. 9 is a flow chart specifically showing the contents of
global routing processing in conventional automatic placement and
routing processing.
[0091] FIG. 10 is a global diagram showing a global route, global
routing cell boundaries and global routing cells.
[0092] FIG. 11 is a diagram for use in explaining a wire
capacitance calculation method.
[0093] FIG. 12 is a diagram showing one example of a global
route.
[0094] FIG. 13 is a diagram showing one example of a degree of wire
congestion.
[0095] FIG. 14 is a diagram showing an example of application of
the global routing processing in the conventional automatic
placement and routing processing.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0096] The preferred embodiment of the present invention will be
discussed hereinafter in detail with reference to the accompanying
drawings. In the following description, numerous specific details
are set forth in order to provide a thorough understanding of the
present invention. It will be obvious, however, to those skilled in
the art that the present invention may be practiced without these
specific details. In other instance, well-known structures are not
shown in detail in order to unnecessary obscure the present
invention.
[0097] FIG. 1 is a block diagram showing structure of an integrated
circuit automatic routing device according to one embodiment of the
present invention. A flow of automatic placement and routing
processing according to the present embodiment, similar to that of
the conventional processing described with reference to FIG. 7, is
in outline executed in four steps, floor plan processing, placement
processing, global routing processing and detailed routing
processing. In addition, as a flow of entire processing, when
determination is made that routing is impossible or that there
exists a shorted net or unrouted net after the execution of each
step of the floor plan processing, the placement processing, the
global routing processing and the detailed routing processing, the
immediately preceding processing is first conducted over again and
if the execution of the processing achieves no improvement,
processing is sequentially conducted over again retroactively to
the preceding processing, similarly to the conventional automatic
placement and routing processing shown in FIG. 7.
[0098] With reference to FIG. 1, an automatic routing device of the
present embodiment includes a floor plan determining unit 10 for
executing floor plan processing, a basic cell placement unit 20 for
executing basic cell placement processing, a global routing route
determining unit 30 for executing global routing processing and a
detailed routing route determining unit 40 for executing detailed
routing processing. In FIG. 1, illustration is made only of a
characteristic part of the structure of the present embodiment and
that of the remaining part is omitted.
[0099] Each of the above-described components is implemented by a
processing device under control of a computer program at a computer
system such as a work station or a personal computer. The control
program is provided as storage in a storage medium such as a
magnetic disk or a semiconductor memory and is loaded into the
processing device of the computer system to execute the function of
each component.
[0100] In the above-described structure, the floor plan determining
unit 10 conducts the same floor plan processing as that of the
conventional automatic placement and routing processing, the basic
cell placement unit 20 conducts the same placement processing as
that of the conventional automatic placement and routing processing
and the detailed routing route determining unit 40 conducts the
same detailed routing processing as that of the conventional
automatic placement and routing processing.
[0101] The global routing route determining unit 30, as shown in
FIG. 1, includes a wire capacitance calculating unit 31 for
calculating a wire capacitance of a global routing cell boundary, a
number of grids calculating unit 32 for calculating the number of
grids which can be wired in a global routing cell, a degree of wire
congestion calculating unit 33, a grid use rate calculating unit 34
and a minimum cost route determining unit 35 for the determination
of a global route, and a routing checking unit 36 and a grid use
rate checking unit 37 for the determination of routing
possibility/impossibility.
[0102] The wire capacitance calculating unit 31 calculates a wire
capacitance at each global routing cell boundary formed by the
division of the chip into global routing cells. The wire
capacitance calculating method is the same as that in conventional
global routing processing.
[0103] The number of grids calculating unit 32 calculates the
number of grids usable for routing in each global routing cell
formed on the chip. Grid here represents a point of intersection
between routing tracks in a global routing cell. A total number of
grids in each global routing cell is equal to [the number of
routing tracks in the right-and-left direction].times.[the number
of routing tracks in the up-and-down direction] of the global
routing cell. Since there is a case where a routing inhibited
region exists within a global routing cell, the number of grids
usable for routing is less than or equal to the total number of
grids in a global routing cell in question, which is obtained by
the following expression:
[the total number of grids]-[the number of grids which can not be
used because of the existence of routing inhibited region].
[0104] The degree of wire congestion calculating unit 33 calculates
a degree of wire congestion based on a wire capacitance of a global
routing cell boundary and already determined global routes. The
method of calculating a degree of wire congestion is the same as
that in the conventional global routing processing and is obtained
by the following expression:
[the number of passing global routes]-[wire capacitance].
[0105] The grid use rate calculating unit 34 calculates a grid use
rate in each global routing cell based on the number of usable
grids in the global routing cell calculated by the number of grids
calculating unit 32 and an estimated number of grids to be used for
already determined global routes. Estimated number of grids to be
used represents the number of grids to be used by wires in question
within a global routing cell in question calculated based on a
route of the wires passing through the global routing cell. Grid
use rate represents a ratio of an estimated number of grids to be
used in a global routing cell to the number of usable grids in the
global routing cell, which is defined by [the estimated number of
grids to be used in global routing cell]/[the number of usable
grids in global routing cell]. Routing to have a grid use rate
higher than 1 is therefore impossible.
[0106] The minimum cost route determining unit 35 determines, based
on the cost of distance, the cost of a degree of wire congestion on
a global routing cell boundary, the cost of a grid use rate, the
cost of bend and other various kinds of costs, a routing route
minimizing these costs. The method of determining such route is the
same as the minimum cost route determining method in the
conventional automatic placement and routing processing with the
only difference being that the cost of a grid use rate is taken
into consideration.
[0107] The routing checking unit 36, after routing is conducted
with respect to all the nets through the processing by the degree
of wire congestion calculating unit 33, the grid use rate
calculating unit 34 and the minimum cost route determining unit 35,
sees if the number of wires passing through each global routing
cell boundary exceeds a wire capacitance of the global routing cell
boundary. Then, when there is a global routing cell boundary at
which the number of passing wires exceeds its wire capacitance, a
net passing through the global routing cell boundary is tore away
to again cause the degree of wire congestion calculating unit 33,
the grid use rate calculating unit 34 and the minimum cost route
determining 35 to conduct their processing.
[0108] The grid use rate checking unit 37, after routing is
conducted with respect to all the nets through the processing by
the degree of wire congestion calculating unit 33, the grid use
rate calculating unit 34 and the minimum cost route determining
unit 35, sees if a grid use rate at each global routing cell is
higher than 1. Then, if there is a global routing cell whose grid
use rate is higher than 1, a net passing through the global routing
cell is tore away to again cause the degree of wire congestion
calculating unit 33, the grid use rate calculating unit 34 and the
minimum cost route determining unit 35 to conduct their
processing.
[0109] Next, global routing processing according to the present
embodiment will be described with reference to the flow chart of
FIG. 2 and FIGS. 3 to 5. In the global routing route determining
unit 30, first, the wire capacitance calculating unit 31 divides a
chip to be processed into global routing cells (Step 201) to
calculate a wire capacitance at each global routing cell boundary
(Step 202). Next, the number of grids calculating unit 32
calculates the number of grids usable for routing at each global
routing cell (Step 203). With reference to FIG. 3, a method of
calculating the number of grids usable for routing will be
specifically described.
[0110] FIG. 3 is a diagram showing grids usable for routing at a
global routing cell having the same structure as that shown in FIG.
11. In FIG. 3, a region surrounded by solid lines corresponds to
one global routing cell. A routing track is denoted by a dotted
line and a routing inhibited region is denoted by slant lines. In
the global routing cell illustrated in FIG. 3, five routing tracks
exist in the right-and-left direction and five routing tracks exist
in the up-and-down direction. The total number of grids is
therefore 25 (=5.times.5) (in an actual global routing cell,
approximately 20 routing tracks exist both in the right-and-left
direction and in the up-and-down direction and the total number of
grids is approximately 400 (=20.times.20)). However, since a
routing inhibited region exists, the number of grids usable for
routing will be less than the above described total number of
grids, 25. In FIG. 3, usable grids within the global routing cell
are indicted by white rounds. The actual number of usable grids
will be 18 (=25-7), which is a value obtained by subtracting 7, the
number of grids included in the routing inhibited region, from 25,
the above-described total number of grids.
[0111] Next, the degree of wire congestion calculating unit 33
calculates a degree of wire congestion at each global routing cell
boundary (Step 204). Then, the grid use rate calculating unit 34
calculates a grid use rate at each global routing cell (Step 205).
With reference to FIGS. 4 and 5, a method of calculating an
estimated number of grids to be used and a grid use rate will be
specifically described.
[0112] In FIG. 4(A) to (D), at a global routing cell denoted by
solid lines, a number x of routing tracks exist in the
right-and-left direction and a number y of routing tracks exist in
the up-and-down direction (see FIG. 4(A)). In this state, possible
patterns of wires passing through the global routing cell are
three, a passing pattern on which one wire is provided in the
right-and-left direction (FIG. 4(B), hereinafter referred to as a
right-and-left passing pattern), a passing pattern on which one
wire is provided in the up-and-down direction (FIG. 4(C),
hereinafter referred to as an up-and-down passing pattern) and a
passing pattern on which one wire turns at a right angle (passing
through two adjacent global routing cell boundaries) within the
global routing cell (FIG. 4(D), hereinafter referred to as an
adjacent passing pattern). The right-and-left passing pattern uses
a number y of grids for one wire to pass through the global routing
cell. The up-and-down passing pattern uses a number x of grids for
one wire to pass through the global routing cell. The adjacent
passing pattern uses a number (x/2+y/2) of grids for one wire to
pass through the global routing cell. Although FIG. 4(D)
illustrates one passing pattern on which a wire passes through the
right and the lower global routing cell boundaries (hereinafter
referred to as a lower right passing pattern), this is also the
case with a passing pattern on which a wire passes through the
lower and the left global routing cell boundaries (hereinafter
referred to as a lower left passing pattern), a passing pattern on
which a wire passes through the left and the upper global routing
cell boundaries (hereinafter referred to as an upper left passing
pattern) and a passing pattern on which a wire passes through the
upper and the right global routing cell boundaries (hereinafter
referred to as an upper right passing pattern). Then, an estimated
number of grids to be used within the global routing cell is
obtained by calculating the following equation with respect to all
the passing routes and adding the calculation results:
[an estimated number of grids to be used for each passing
route]=[the number of grids to be used for one wire determined
according to the passing route].times.[the number of wires passing
through the passing route].
[0113] On the foregoing premises, an estimated number of grids to
be used and a grid use rate in the global routing cell shown in
FIG. 5 are calculated. In the example shown in FIG. 5, five routing
tracks exist in the right-and-left direction and five routing
tracks exist in the up-and-down direction. Then, two wires pass
through a passing route 501 as an upper right passing pattern, one
passes through a passing route 502 as a right-and-left passing
pattern and one passes through a passing route 503 as a lower left
passing pattern. In this case, an estimated number of grids to be
used for each passing route is obtained by the following
expressions:
passing route 501: (5/2+5/2).times.2=10
passing route 502: 5.times.1=5
passing route 503: (5/2+5/2).times.1=5.
[0114] An estimated number of grids to be used in the global
routing cell therefore totals 20 (=10+5+5). When the number of
usable grids in the global routing cell is 18 as shown in FIG. 3
and the estimated number of grids to be used in the global routing
cell is 20 as shown in FIG. 5, a grid use rate will be 1.11
(=20/18).
[0115] Next, the minimum cost route determining unit 35, taking
various costs including the cost of distance, the cost of a degree
of wire congestion on a global routing cell boundary and the cost
of a grid use rate into consideration, determines a route
minimizing these costs (Step 206).
[0116] The foregoing processing at Step 204 to Step 206 will be
repeated until routing of all the nets is completed (Step 207).
More specifically, the operation at Steps 204 to 207 will determine
a route minimizing costs based on a grid use rate in addition to a
wire capacitance until no unrouted net remains.
[0117] Next, the routing checking unit 36 sees if there exists a
global routing cell boundary on which the number of passing wires
exceeds its wire capacitance and if such a global routing cell
boundary exists, a net passing through the global routing cell
boundary is tore away to return to Step 204 (Steps 208 and
209).
[0118] When there exists no global routing cell boundary on which
the number of passing wires exceeds a wire capacitance, the grid
use rate checking unit 37 next sees if there exists a global
routing cell having a grid use rate is higher than 1 and if such a
global routing cell exists, a net passing through the global
routing cell is tore away to return to Step 204 (Steps 210 and
211). For example, the grid use rate calculated with reference to
FIG. 5 is 1.11, a value higher than 1, and therefore, a net having
such routing as illustrated in FIG. 5 will be tore away.
[0119] Thus, when there exists no net whose routing is determined
to be possible based neither on a wire capacitance nor on a grid
use rate, the global routing processing is completed. Although in
the above-described operation example, a check on a grid use rate
is made after a check on a wire capacitance (Steps 208 and 210),
either may be made first because these two are independent
processing.
[0120] Next, functions of the global routing processing according
to the present embodiment will be specifically described with
reference to FIG. 6. FIG. 6 shows a state of global routing
processing conducted according to the present embodiment with
respect to a global routing cell having the same structure as that
illustrated in FIG. 14. More specifically, three routing tracks
exist in the right-and-left direction and three routing tracks
exist also in the up-and-down direction as shown in FIG. 6(A). In
this global routing cell, a region including one grid as a central
point of intersection and denoted by slant lines is a routing
inhibited region. In such a case as this, wire capacitances at the
respective global routing cell boundaries are all 3 as has been
described in the Related Art. The number of grids usable for
routing is eight, which is a value obtained by subtracting one, the
number of grids within the routing inhibited region, from nine
(=3.times.3), the total number of grids.
[0121] At the global routing cell illustrated in FIG. 6(A), to pass
three wires as a global route in the right-and-left direction as
illustrated in FIG. 6(B) will result in having such degrees of wire
congestion on the global routing cell boundaries as shown in FIG.
6(C), among which no positive value exists. Based only on a degree
of wire congestion, therefore, determination can be made that
routing is possible because the number of nets passing through each
global routing cell boundary does not exceed the wire
capacitance.
[0122] Next, calculate a grid use rate. In this global routing
cell, an estimated number of grids to be used per wire is three and
an estimated number of grids to be used within the global routing
cell is nine (3.times.3) accordingly. In addition, the number of
grids usable for routing is eight as mentioned above. As a result,
a grid use rate will be 1.12 (=9/8), a value higher than 1, and
determination is therefore made that the routing in question is
impossible.
[0123] As described in the foregoing, according to the global
routing processing of the present embodiment, the determination
based on a grid use rate can in some cases eliminate routing which
might be erroneously determined to be possible based only on a wire
capacitance. In this case, it is possible to prevent a probability
that routing error as illustrated in FIG. 6(E) will occur at the
detailed routing processing. As a result, the probability can be
drastically reduced that routing determined to be possible at the
global routing processing will be determined to be impossible at
the detailed routing processing.
[0124] The present invention is not limited to the above-described
embodiment but allows various modifications and variations within
the spirit and scope of the present invention. For example, while
the above-described embodiment employs the number of usable grids,
it is clear that an area of an unused region in each global routing
cell may be employed in place of it. In addition, as long as at
least the cost of a degree of wire congestion on a global routing
cell boundary and the cost of a grid use rate are employed as the
costs to be taken into consideration for determining a minimum cost
route, not all the costs set forth above are necessary.
[0125] As described in the foregoing, since the automatic routing
device of the present invention and a routing method thereof
determine a routing route of each net based on a grid use rate in
addition to a wire capacitance on a global routing cell boundary, a
probability can be drastically lessened that routing determined to
be possible at the global routing processing will be determined to
be impossible at the detailed routing processing. As a result, time
required for automatic placement and routing processing can be
reduced.
[0126] Although the invention has been illustrated and described
with respect to exemplary embodiment thereof, it should be
understood by those skilled in the art that the foregoing and
various other changes, omissions and additions may be made therein
and thereto, without departing from the spirit and scope of the
present invention. Therefore, the present invention should not be
understood as limited to the specific embodiment set out above but
to include all possible embodiments which can be embodies within a
scope encompassed and equivalents thereof with respect to the
feature set out in the appended claims.
* * * * *