U.S. patent application number 08/973425 was filed with the patent office on 2001-08-16 for memory structure.
Invention is credited to SODERQUIST, INGEMAR.
Application Number | 20010014930 08/973425 |
Document ID | / |
Family ID | 20398571 |
Filed Date | 2001-08-16 |
United States Patent
Application |
20010014930 |
Kind Code |
A1 |
SODERQUIST, INGEMAR |
August 16, 2001 |
MEMORY STRUCTURE
Abstract
The invention relates to a new memory structure specially
adapted for the storage of memory vectors. Each of the storage
positions (#1, Mi-#M, Mi) of the memory has a length adapted to the
length of large vectors and is parallelly arranged extending from
an input and/or output for information and deeper into the memory.
In this way each vector is stored undivided in a sequential order
with the beginning of the vector at the input and/or output of the
memory (memory field F1 in memory plane Mi). Addressing is made to
the input and/or output of the memory. There are means (1IB-MIB,
1UB-MUB) acting like shift registers for the inputting and
outputting of information in undivided sequence to/from the storage
positions in the memory.
Inventors: |
SODERQUIST, INGEMAR;
(LINKOPING, SE) |
Correspondence
Address: |
POLLOCJ, VANDE SANDE & PRIDDY, RLLP
1900 M STREET, N.W.
SUITE 800
WASHINGTON,
DC
20036
|
Family ID: |
20398571 |
Appl. No.: |
08/973425 |
Filed: |
December 8, 1997 |
PCT Filed: |
June 5, 1996 |
PCT NO: |
PCT/SE96/00748 |
Current U.S.
Class: |
711/109 ;
711/170; 712/4 |
Current CPC
Class: |
G06F 12/04 20130101 |
Class at
Publication: |
711/109 ;
711/170; 712/4 |
International
Class: |
G06F 012/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 9, 1995 |
SE |
9502113-5 |
Claims
1. Memory structure for the storage of memory vectors in at least
one storage place, characterized in that each of the storage places
in the memory (#1 Qi-#M,Qi) after configuring has a length adapted
to the length of the large vectors and are arranged parallel
extending from an input for information and deeper into the memory
so that each vector is arranged to be undividedly stored in a
sequential order with the beginning of the vector at the input to
the memory (memory field F1 in the memory plane #1 Qi); addressing
is arranged to be made to the input to the memory; there are means
(1IB-MIB) acting like shift registers for the inputting of
information in unbroken sequence to the storage positions in the
memory.
2. Memory structure according to claim 1, characterized in that the
memory is divided transversely into memory blocks (#1-#M), so that
all the storage positions have each a part in each memory
block.
3. Memory structure according to claim 2, characterized in that the
storage positions in the memory are extendable through coupling
together one or more memory blocks.
4. Memory structure according to claim 2 or 3, characterized in
that each memory block comprises: as each means acting like a shift
register: an input buffer (jIB) with serial inputting of data
analogous with a shift register; as storage positions: a plurality
of data memory fields (F1-FP) in which information from the input
buffer are entered sequentially or parallelly; and that a control
logic (iS) is arranged in every memory block, which control logic
controls the inputting of information in the memory fields via the
input buffers; which memory blocks are cascade coupled with each
other through the input buffers in them being cascade coupled with
each other so that information is serially feedable through several
of the buffers in the different memory blocks after one another;
and that the control logic in each memory block is arranged to
inform the control logic in the next memory block when the memory
fields in its own memory block are filled with or read of
information, so that the control logic in the next memory block can
take over the work of the reading in of the information in the
memory fields in that memory block.
5. Memory structure according to any of the previous claims,
characterized in that there are means (1UB-MUB) acting like shift
registers for the output of information in undivided sequence from
the storage positions in the memory.
6. Memory structure according to claim 5, characterized by an
output buffer (jUB) with serial outputting of data analogous with a
shift register; information in the computer memory fields (F1-FP)
during the outputting of data being transferred sequentially to the
output buffer; which control logic (iS) in each memory block is
arranged to control the output of information in the memory fields
via the output buffers and to inform the control logic in the next
memory block when the memory in its own memory block is emptied of
information so that this can take over the work of reading out the
memory in the memory fields in the memory block.
6. Memory structure according to any of the previous claims,
characterized in that the means acting like shift registers are
such that they handle the serial feeding of bytes.
7. Memory structure according to any of claims 4-6, characterized
in that the transferring between memory fields and buffers takes
place parallelly with the whole information content simultaneously
controlled by the control logic in the memory block in question
when transferring takes place.
8. Memory structure according to any of claims 4-7, characterized
in that the information during in- and/or outputting is arranged to
be transferred continuously to input and/or output buffers in the
different memory blocks without any handshaking operations between
them.
9. Memory structure according to any of claims 4-8, characterized
in that the means (1IB-MIB, 1UB-MUB) acting like shift registers
for the in- and/or outputting are arranged parallel with each other
and are controllable independently of each other which permits
simultaneous in- and outputting of information to/from the storage
positions in the memory.
10. Memory structure according to any of the previous claims,
characterized by means for the phase shifting of the reading period
in relation to the writing period by a selective number of clock
pulses.
11. Memory structure according to claim 10, characterized in that
the phase shifting means comprises an adjustable delay circuit with
a delay corresponding to the desired phase delay.
12. Memory structure according to any of the previous claims,
characterized in that the information stored in the different
memory blocks is readable parallelly to each of its processing
arrangements.
13. Memory structure according to claim 12, characterized in that
the processed information is restorable in the memory block after
processing.
14. Memory structure according to claim 12 or 13, characterized in
that the processed information is transferable to a result unit
which combines the processed information from the processing
arrangements of the memory blocks to a result.
Description
[0001] The present invention relates to a memory structure of the
type which is stated in the preamble of Claim 1.
BACKGROUND TO THE INVENTION
[0002] The development of memories has occurred simultaneously with
the development of computer processors. This means that the
development of processors has guided the development of memory.
Therefore it has been traditional that information in a memory is
arbitrarily divided into bit groups (called bytes from now on),
with a fixed number of bits, most often being addressed
independently of earlier selected information. This leads to the
address decoder having to be able to reach an arbitrary position in
the memory within a certain access time in order to read or to
write information there. The data transfer speed is inversely
proportional to the access time. The access time is naturally
dependent on which sort of manufacturing technology is used for the
memory. VLSI-technology (VLSI=Very Large Scale Integration) is used
and efforts are made to minimize the size and complexity of the
circuits. For a given technology the size of the memory is always
limited by the propagation speed of the signals. At the same time
there is also the relationship that for traditional architecture
increased memory area implies increased access time because the
complexity of the address decoder increases when the memory
increases. The demand for data processing speed is constantly
increasing. Since the complexity of the address decoder increases
and the propagation speed is constant, then the total storage
space, that is to say the addressable surface where information can
be stored, always decreases with increased computer speed.
[0003] In many fields of use which have become of immediate
importance in the last years, such as telecommunications, radar,
bulk memories for computers etc., information is not handled in the
form of bytes but as sequences of bytes which are called vectors.
In modern digital telephone systems and in data communication
systems packets of information, ATM, are used. In radar the
information is in the form of pulses. After digitalization the
pulse can be considered as being a large vector, defined by the
start point and length.
[0004] In many applications large blocks of connected bytes are
handled in the same way, for example a block of text in a word
processor. Another example is swap memory in computers. These have
in common that a large amount of information (vector) is handled as
a whole. Addressing at the byte level is not used.
OBJECT OF THE INVENTION
[0005] An object of the invention is to produce a memory structure
which is adapted for storing vectors.
[0006] Another object of the invention is to produce a memory
structure which gives fast and continuous access to storage places
for the reading and/or writing of vectors.
[0007] A further object of the invention is to produce a structure
where the writing of a vector can take place at the same time as,
and independently of, the reading of a vector is taking place.
[0008] Yet a further object of the invention is to produce a memory
structure where the writing of a vector can take place almost
simultaneously with the reading of it.
[0009] Yet another object of the invention is to produce a memory
structure where the time for outputting written data can be
controlled right down to the clock period.
[0010] Yet another object of the invention is to produce a memory
structure which can be used as a complement to the current type of
memory structure for a computer.
[0011] A further object of the invention is to produce a memory
structure which permits the treatment of a stored vector parallelly
by a plurality of storage positions for vectors in order to either
reposition the processed vector or to get out a processing
result.
BRIEF SUMMARY OF THE INVENTION
[0012] The above objects are achieved with a memory structure which
has the characteristics stated in Claim 1. Further features and
further developments of the invention are stated in the other
claims.
[0013] According to the invention, after configuration each of the
storage positions in the memory has a length adapted for the length
of the large vectors and are arranged parallelly, extending from an
information input and deeper into the memory so that each vector is
arranged to be stored undivided in consecutive order with the
beginning of the vector by the input of the memory, whereby
addressing is arranged to take place to the input of the memory.
There are means acting as shift registers for the inputting of
information in undivided order to the storage positions in the
memory.
[0014] The memory is preferably divided transversely into memory
blocks, so that all storage positions each have a part in each
memory block. The storage positions in the memory can be
lengthenable through joining together of one or more memory blocks.
Each memory block can comprise:
[0015] as means acting like shift register;
[0016] an input buffer with serial inputting of data analoguosly
with a shift register;
[0017] as storage positions:
[0018] a number of data memory fields in which information from the
input buffer can be sequentially inputted.
[0019] In this connection a control logic is arranged in each
memory block, which control logic controls the input of information
in memory fields via the input buffer whereby the memory blocks are
cascade coupled with each other through the input buffers in them
being cascade coupled with each other, so that information is
serially stepwise feedable through a number of the buffers in the
different memory blocks after one another, and the control logic in
each memory block is arranged to inform the control logic in the
next memory block when the memory fields in its own memory block
are filled with information or all information in them is read out,
so that the control logic in the next memory block can take over
the job of writing the information to this memory block. There can
be means acting like shift registers for the outputting of
information in undivided order from the storage positions in the
memory. Moreover there can be means for data processing of data
parallely stored in the different memory blocks.
ADVANTAGES WITH THE INVENTION
[0020] The memory structure according to the invention permits the
setting up of a large and expandable storage space for information,
continuous data transfer and at the same time extremely high
transfer speeds. Expansion of the storage space for a vector, and
thereby the size of the memory, can be performed without affecting
the data transfer speed as the interface with the memory seen from
outside is unchanged.
[0021] With the memory structure according to the invention a
continuous data transfer can be performed at approximately 0.5-1
Gbytes/sec compared with todays 30-100 Mbytes/sec. This implies a
factor of ten times faster with the use of corresponding basic
technology. The memory structures in themselves are not dependent
on the technology used but can be used for arbitrary storage
technologies (RAM, magnetic memory, optical memory etc.).
SHORT DESCRIPTION OF THE DRAWINGS
[0022] The invention is described in more detail below with
reference to the appended drawings, where
[0023] FIG. 1 shows in general the principle for a memory structure
according to the invention,
[0024] FIG. 2 shows a first embodiment of the memory structure
according to the invention,
[0025] FIG. 3 shows the internal structure of a memory block in
more detail than in FIG. 2,
[0026] FIG. 4 shows a flow diagram for the overall control logic
for the memory,
[0027] FIG. 5 shows a flow diagram for the control logic in a
memory block,
[0028] FIG. 6 shows a second embodiment of the memory structure
according to the invention, and
[0029] FIG. 7 shows a third embodiment of the memory structure
according to the invention.
DESCRIPTION OF THE EMBODIMENTS
Definitions
[0030] Stored information Refers to a number of vectors which each,
seen from outside, are treated continuously and in undivided
form.
[0031] Vector Refers to the whole continuous amount of information
which is to be processed in one piece. A vector is defined from
outside with the help of a starting point, or identity, and
length.
[0032] Byte group Part of a vector adapted to size of a memory
field. A vector can be described as a sum of byte groups.
[0033] Memory structure Refers to the whole of the system according
to FIG. 2. The memory structure consists of one or more memory
blocks, the converter units 5, 6 and control logic 4.
[0034] Memory block Refers to a unit with a well-defined function
which only communicates with the nearest neighbors, see FIG. 2. The
memory structure is always expanded with a whole number of new
memory blocks.
[0035] Storage position Refers to the part of the memory
structure's total memory area which after configuration is adapted
to the length of the current vector. The storage positions are
distributed from memory block #1 and inwardly, see FIG. 1.
[0036] Memory plane The part of a memory block which after
configuring is being allotted to a certain vector (the
identity).
[0037] Memory field The part of a memory plane which is processed
in one piece. The size corresponds to that of the
input/output-buffers.
DESCRIPTION OF THE DRAWINGS
[0038] FIG. 1 shows a number of memory blocks #1, #2, . . . #M,
which are cascade coupled with each other. Each memory block has an
information part 1I, 2I, . . . MI, and input buffer 1IB
respectively 2IB . . . respectively MIB, an output buffer 1UB
respectively 2UB . . . respectively MUB and a control logic 1S
respectively 2S . . . respectively MS. Each memory block can be on
a separate chip and a selectively number of chips can be coupled
together with each other in order to form an selectively large
memory. It is also possible and appropriate to have several memory
blocks on one chip whereby several multiblock chips can be coupled
together in cascade. Each of the storage positions in the memory
has a length adapted to the length of large vectors. The blocks are
arranged in parallel extending from an in/output for information
and deeper into the memory so that each vector is arranged to be
stored undivided in consecutive order via the input buffers with
the beginning of the vector at the input/output of the memory and
similarly to be outputted in consecutive order via the output
buffers when the need for this occurs (see the embodiment in FIG.
7). Addressing is made to the in/output of the memory.
[0039] In the embodiment shown in FIG. 2 the memory structure
comprises a number of cascade coupled units or memory blocks #1-#M,
control logic 4 and where appropriate converter units 5, 6. The
memory blocks shown here have each a constituant block with several
memory planes #11-#1N respectively "M1-#MN lying behind one another
which each comprise a number of memory fields F1-FP. It should be
noted that from now on in the description a special memory field in
the memory has a reference which identifies which memory block and
which memory plane it belongs to, for example #m, Qi, Fj for a
memory field Fj in the memory plane Qi in the memory block #m. This
reference system has been applied throughout.
[0040] It is, however, obvious that the memory blocks in practice
can have a surface structure with the planes arranged spread-out at
different positions on the surface or arranged as memory fields one
after another, so that for example in the case of a chip with
several blocks the memory fields in memory blocks #2/memory plane
#Q1 are arranged as a direct continuation of the memory fields in
the memory block #1/memory plane #Q1 etc.
[0041] As can be seen from FIG. 3 the memory structure has several
addressable storage positions or memory planes Q1 . . . Qi . . . QN
(i=1 . . . N). Each memory block #m has a number of memory fields
F1 to FP allocated to each addressable memory plane Qi.
[0042] Each memory block #m is physically organised in W.sub.m rows
(corresponding to N.times.P in FIG. 3) and a.times.b columns. Each
row forms a memory field and contains a number of byte groups or
words (a) each with a suitable number of bits (b). The memory block
#m is therefore W.sub.m.times.a.times.b bits large. The memory
structure has a total size of (W.sub.1+W.sub.2+ . . .
+W.sub.M).times.a.times.b bits. It is also possible to conceive the
special case where a, b and W vary between memory blocks but this
is not taken up here.
[0043] A vector Vi with the length L.sub.i words is stored as
L.sub.i/a partial vectors in memory fields M1, F1, . . . , M1, FP;
M2 F1, . . . , M2 FP; . . . , MN F1, . . . , MN FP. After
configuration it is valid that L.sub.i=a.times.(O.sub.i1+O.sub.i2+
. . . +O.sub.iM) words, where O.sub.im is the contents of Mi Fm
(i=1-N, m=1-P). The size of vector Vi is consequently a.times.b
.times.(O.sub.i1+O.sub.i2+ . . . +O.sub.iM) bits. For each memory
block it is also valid that the number of rows always corresponds
to the sum of the number of memory fields,
W.sub.m=O.sub.1m+O.sub.2m+ . . . +O.sub.Nm.
[0044] Vectors of varying lengths can be stored at the same time in
the memory structure.
[0045] The memory structure can be configured in various ways. Seen
from outside the vectors are addressed only from the starting point
(the identity) #1 Mi F1 where i is any number between 1 and N, and
F1 is the first memory field in the memory block #1 in the memory
plane Mi. The length of the vectors L.sub.i is defined by the
configuration. The configuration can be static or dynamic.
[0046] In static configuration all the O.sub.im are predetermined.
The control logic 4 has knowledge of the number N of storage
positions Mi as well as the length of the respective storage
positions L.sub.i. The control logic 1S-MS in the memory blocks has
knowledge of starting point #1 Qi F1 and the length O.sub.im for
the respective memory block. The end point #m Qi Fj is defined
indirectly by the starting point and length.
[0047] In dynamic configuration the length of the current memory
plane or storage position Mi is changed during writing. The
information vector is assumed from outside to be followed by
information on the length as well as other global information. This
information can alternatively be found in the first byte group as a
head of the vector Vi. The control logic can then read, use and
change this information in accordance to how it extends further
into the memory structure. After the head the information follows
sequentially.
[0048] With static configuration it is assumed that the information
vector which is read from or written into a storage position Qi has
a length which corresponds to the configuration. With static
configuration the head can be left out.
[0049] Every memory block #i has an input buffer iIB with a buffer
store comprising a number of storage bits for each storage memory
field in the memory plane for incoming information and an output
buffer iUB with the same buffer storage size as the input buffer
for outputting information. There is furthermore a control logic iS
in order to control the writing and reading of information in the
memory plane and thereby in which of the memory field or fields
therein.
[0050] The computer unit which via interface 5, 6 (see FIG. 2) is
connected to the memory structure according to the invention loads
incoming information through the information inport and takes out
outputted information from the information outport in the form of
vectors, for example data packets. Each vector can be equipped with
a head containing identity, length etc. Alternatively the necessary
information can be given to the interface by any other way which is
obvious for the man skilled in the art. A control logic 4 is
coupled to the interface in order to control the memory in
accordance with what has been read from it. The control logic 4 can
furthermore be equipped with an internal memory (not shown) for
storing data concerning the stored vectors and where these are
stored in the memory and where new vectors can be stored. Thus the
addressing to memory takes place under the influence of control
logic 4. This can be seen from FIG. 4A.
[0051] FIGS. 4A-4C show a flow diagram of an embodiment of the way
of the control logic works, partly during activation (FIG. 4A),
partly during writing into the memory (FIG. 4B) and partly during
reading from the memory (FIG. 4C). The flow diagrams are so clear
that a close description of the different stages does not need to
be made.
[0052] As will be described in more detail below the inputted
information to the memory is suitably of parallel type, that is to
say in the form of parallel bytes of suitable length, for example
8, 16, 32 bits. If pure serial information is inputted then a
conversion from the bit form to parallel byte form takes place in
the converter unit 5. Similarly a conversion from parallel bytes to
bits should be performed in the converter unit 6 if this is
necessary. It should be noticed that there is nothing which
prevents that the input information in the information inport being
in serial bit form and the information in the information outport
being in parallel byte form or vice versa in which case only one
converter unit 5 or 6 is necessary.
[0053] During dynamic configuration (see FIG. 4B) the head of each
information vector which is to be written in is read. The
information in this is used partly to determine how much memory
space the vector will take up and partly in order to activate the
control logic 1S in the first memory block #1 and to give it
information on how many of the following control logics iS in the
other memory blocks #i will need to be activated.
[0054] In practice every stored vector will have its beginning in
memory field F1 in one of the planes Qi in memory block #1 and to
extend from there deeper in to the memory. One can consider the
storage of a vector being performed as a single continuous string.
The vectors will in this way be parallelly arranged and addressing
to them will take place to the beginning of the different planes in
the memory block #1. Many of the memory fields F1-FP will actually
be used in each memory block for storage so that the storage can be
considered as being folded but in practice in fact the whole vector
will lie arranged in an unbroken sequence from beginning to end
from memory block to memory block.
[0055] Every control logic in the memory blocks has inside it a
memory with information on which memory planes and which memory
fields in them are empty or are already filled. When vectors which
have to be stored arrive, a search is first made either in control
logic 4 or in control logic 1S to find an available storage
plane.
[0056] As is evident from FIG. 5 which shows an embodiment of the
flow diagram for each control logic 1S-MS in the memory blocks, the
writing begins when the information, the vector, passes the
interface (see FIG. 2). The configuration does not have to be
completed for all the memory blocks because this is performed
successively in accordance with the propagation of the information
down in the memory. Assume that plane Qi where i is a number
between 1 and N, is shown to be empty. It should be observed that a
vector is always stored in the same plane, for example Qx, where x
is a number between 1 and N, in all the different blocks that is to
say in plane #1 Qx; #2 Qx; #2 Qx and so on. The incoming vector
begins to be fed into the input buffer 1IB. As soon as it is filled
with a byte group a transfer of this to the first storage memory
field F1 in plane #1 Qx takes place. The input buffer is filled in
a manner analogous with a shift register but output to the memory
fields can take place either serially or parallelly, and preferably
parallelly so that the whole of the memory content of the input
buffer is emptied.
[0057] In analogy with a shift register a direct refilling takes
place whereafter the whole contents of the memory is emptied to the
next memory field F2 in plane #1 Qx and so on until the last memory
field FP in the plane #1 Qx is filled. The control logix 1S has in
this connection an input-field pointer (not shown) which gives the
memory field which is current for writing.
[0058] Subsequently the input buffer 1IB is controlled to begin
filling input buffer 2IB, in analogy with a shift register,
serially, that is to say parallel byte after parallel byte until
this is filled. The whole of the serial length of the shift
resister used as the buffer will be called from now on a serial
byte, because it represents the number of clock signals, which is
necessary in order to fill the buffer that is to say it represents
the serial length of a parallel byte group.
[0059] When the input buffer is filled, it fills in the first
memory field F1 in plane #2 Qx and the different following memory
fields there are then filled in in the same way as the memory field
in memory plane #1 Qx, i.e. controlled by the input-field pointer
from the control logic. When the memory plane #1 Qx is filled,
information in the input buffer 2IB of memory block #2 continues to
be transferred over to the input buffer of the next memory block
and subsequently from this to the memory fields in the next memory
plane #3 Qx in this memory block and so on. It should be noted that
it is possible to have many input and output buffers, for example
in order to serve several memory planes simultaneously, even if
this is not shown in any of the figures. The control unit can also
be duplicated.
[0060] It should be noted that information can be inputted to the
input buffers in the form of sequential parallel bytes, whereby
each buffer in fact comprises as many parallel shift registers as
there are bits in each byte. The expression parallel byte group is
used for the number of bytes which fill an input/output buffer.
When an input buffer is emptied to a memory field in a plane there
is therefore a very large quantity of data which is transferred.
Each memory field therefore comprises an extremely large number of
parallel byte groups.
[0061] Data can be read and outputted from a memory field
immediately after it has been written in.
[0062] As is evident from the flow diagram in FIG. 5 during reading
the content of one memory field at a time is transferred parallelly
with the whole parallel byte group in the first field in the plane
in question 1i to the output buffer 1UB and outputted serially,
i.e. parallel byte after parallel byte.
[0063] When the transfer to the output buffer of the next to last
memory field in plane #1 Qi has taken place the control logic 1S
activates control logic 2s to transfer the contents in the first
memory field #2 Qi to the output buffer 2UB. Directly after the
last memory field FP has been transferred over to the output buffer
1UB and this has outputted its content of parallel bytes serially,
an output buffer 2UB outputs its contents parallel byte after
parallel byte serially to the output buffer 1UB so that this
follows directly after the earlier contents of buffer 1UB.
[0064] In this manner there is no break in the outputted
information. The information in the memory fields in plane #2. Qi
is outputted step by step to the output buffer 2UB, controlled by
an output field pointer (not shown) from the control logic 2S and
outputted from it serially via buffer 1UB. When the next to last
memory field FP in plane 2i is transferred to the output buffer
2UB, the control logic is activated for the next memory block in
order that the memory field information shall be transferred to the
output buffer of the memory block etc.
[0065] In the above described embodiment each output buffer in the
different blocks serially outputs its contents, a parallel byte
group, parallel byte after parallel byte to the next output buffer.
This means that the controlling takes place parallel byte after
parallel byte in both the input and output. Each parallel byte
group can contain a relatively large number of parallel bytes in
this case which means that the start of the output of a vector with
data can take place with the relatively long time interval of a
number of clock periods which is given by the length of the
parallel byte group.
[0066] There are, however, applications when the controlling of the
data output should be down at the clock period for the system in
which the memory according to the invention forms a part. The head
logic of the memory has information about in which parallel byte
group the output shall take place and also the phase displacement
which is needed within the time length of the parallel byte group
for the outputting to take place at the exact desired time.
[0067] An embodiment of the memory with a control logic to achieve
this is shown in FIG. 6. It is possible to have outputting of the
same memory contents to different parts of the system at
independently controllable time points and in that case it is
possible to have many output buffers coupled to the memory planes.
However, in the figures only one output buffer OUTBUFF is shown.
Each output buffer comprises an intermediate buffer MBUFF in which
during controlling the contents are transferable to shift register
sk. The way of functioning for each output buffer is course similar
whereby the description concerning OUTBUFF is valid for all of
them.
[0068] When the local control arrangement in a memory block
receives an indication that the memory contents in a memory plane
are to be outputted via an output buffer OUTBUFF, the first memory
field in this memory plane is loaded down in intermediate buffer
MBUFF by means of a control signal C-1 for it. At the appropriate
clock signal for the actual outputting the contents of the
intermediate buffer is transferred by means of a control signal C-2
to the shift register sk for the timed outputting directly with
controlling on the clock input CLK of the shift register. The
contents in the next memory field is transferred to the
intermediate buffer OUTBUFF either directly after the transfer from
the intermediate buffer to the shift register or, preferably, at
the beginning of the next whole parallel byte group period. There
is, however, nothing which prevents the transfer to the
intermediate buffer taking place any time during the interval
before the transfer to the shift register sk, for example during
the clock period directly before the transfer from the intermediate
memory to the shift register.
[0069] Once the whole memory block is empty, just like described
above, information continues to be inputted into the output buffer
for further transfer to the output. This data, because of the same
controlling for the next following block, will come directly as a
correctly timed continued serial byte group inputting in continuous
order in the shift register sk on its serial input coupled to the
shift register for the following output buffer in order to be
outputted through the shift register to the output or the
memory.
[0070] An example of a control means for the first output buffer
OUTBUFF for the memory block for outputting the respective
transfers from the respective memory fields in the memory plane to
the intermediate buffer MBUFF and then from the memory buffer to
the shift register sk is shown at the bottom of FIG. 6. When
controlling concerning that data is to be outputted in the memory
planes starting at a special point of time enters logic 10, this
points first with an output field pointer to the first memory field
in the memory planes after having passed through a small gate
circuit 11, which allows through signals from the logic in the
presence of a control signal CKL/b, where b is the number of
parallel byte steps in the shift register SK counted by a counter
12. The output field pointer moves to the next memory field at the
next control signal CLK/b and to the next with the next control
signal etc. This is illustrated by the oval 13. Furthermore the
phase displacement with respect to the phase for the output field
pointer is illustrated in the upper part of the figure for the
different positions P1-Pa, where a is the position length of a
memory field, in the different fields Fi and F(i+1) whereby C-1 in
this embodiment comes at the beginning of the output field pointer
and C-2 is controllably displaced to the desired position, for
example P2.
[0071] The output from the counter 12 together with an output from
the logic 11 are inputted to a second logic 14 concerning the
change of fields. The logic 14 then emits, according to the shown
embodiment, the signal C-1 on its output which in the case shown
controls the data transfer from the selected memory field to the
intermediate buffer MBUFF via a small gate circuit 15 which emits
the signal at the next clock signal CLK. The signal C-1 is also fed
to the input of a delay unit 16 which on one control input has a
signal 17 from logic 10 which signal, preferably in digital form,
states the current delay for data in the intermediate buffer before
transferal to the shift register SK1. This continues until the
output field pointer has come to the last field in the memory plane
which is to be outputted. The signal from logic 14 from logic 10
then no longer occurs. Instead at the next to last output field
pointer position logic 10 provides an output to the next block to
activate the control logic there.
[0072] Although this is not shown many controllable delays separate
from logic 10 can be arranged either in order to if necessary give
the signal C-1 with the desired delay and/or in order to give
different delays to different output buffers or the like.
[0073] In all of the above described embodiments of the memory the
input and output data has been inputted respectively outputted on
the same side of the memory block. FIG. 7 shows an embodiment where
whole stored vectors can either be outputted according to the above
described embodiment and also or alternatively it is possible to
perform signal processing on data stored in different memory blocks
simultaneously, i.e. parallelly.
[0074] The signal processing can for example concern the
replacement of special symbols throughout a stored text string in
order to later output the whole of the stored vector through the
output buffers shown in dashed lines. In such a case the data is
transferred after processing back to the memory field in the memory
plane from which it was taken. Alternatively or as a complement a
more sophisticated signal processing can be performed. An advantage
with this embodiment is that the signal processing of a large
amount of stored data can be performed quickly.
[0075] It can also be possible to perform some sort of treatment of
the stored data in order to investigate a special characteristic or
to get out a result. In such a case one is perhaps not at all
interested in being able to output an inputted vector and then the
output buffers shown in dashed lines are not needed. These are
therefore not at all necessary in accordance with the
invention.
[0076] Every memory block, for example #m, has a processing buffer
mB.sub.m connected to it to which the control logic #mL can send
the contents in a memory plane, memory field by memory field, in
the same way as to its output buffer. The contents of the buffer
#m,B.sub.m is then transferred to a local signal processing unit
#m,LS.sub.m in which the special signal processing is performed.
Subsequently the processed data can either, as mentioned above and
shown dashed in the figure, be transferred back to the memory field
or memory fields from which it was taken or transferred to a signal
processing unit GS common for all the blocks which extracts a
result and outputs it, or both of these. It should be noted that
this extraction of a result can be done on separate memory planes,
memory fields in a memory plane or in the whole memory block
depending on what it is that is stored in the different memory
blocks. Because the type of signal treatment which is used is of no
concern for the inventive concept then below there is only given
one example of it, namely that of whole memory blocks or memory
planes in memory blocks.
[0077] It is also possible to perform the processing in all the
memory planes in the same memory block in the above mentioned
manner. A situation where this could happen is the storage of video
signals for picture production wherein each line in a picture can
be stored in different memory planes in the memory blocks. The
invention makes it possible to get quick and easy access to and
perform picture processing on portions of the picture where the
lines are collected in a special memory block or in several
adjacent memory blocks. This makes it possible to perform quick
picture processing on any type of picture.
APPLICATION ADVANTAGES
[0078] Examples of vectors which are specially suitable to be
stored by the method according to the invention are volumes of text
from a word processor. The volume of text can be defined as the
start point for a vector and its length. But one does not actually
have to mention where it is. An advantage with using the invention
is that the computer speed is considerably increased.
[0079] Traditionally volumes of text are stored divided up on
different places on, for example, a hard disc. In order to get hold
of stored information one first addresses one sector, takes out the
information there, addresses another one, gets out the information
there and so on. There is therefore then much addressing and
waiting for information.
[0080] Traditionally it is also such that taking information from a
nearby position is relatively fast. The more memory one has to look
through then the longer time it takes. In this way the data speed
reduces in proportion to how big the memory is and how more spread
out the information is.
[0081] In the invention the start point for the information is in a
vector at the in/output of the memory and is like a string, i.e. in
the different planes #mi,Qj, where j is any number between 1 and N,
which string extends from the in/output deeper into the memory. A
new vector can be inputted into the memory without a break to look
for suitable positions. Similarly a stored vector can be outputted
without break in the embodiments where outputting is necessary.
This means that one can make the quantity of information infinitely
large without in any way impairing the access time. The end point
for a vector is marked for the memory field in the last memory
blocks where the vector is written and is readable by the control
logic in the memory block which stores this information in its
internal memory. Simultaneous reading and writing of the memory can
take place. This control logic consequently always knows the end
point for both inputting and outputting and signals this to the
other control logics especially during the outputting of the end of
the vector through the respective output buffers.
[0082] Each control logic iS comprises therefore a list for each
information vector which states which information entity it is and
the start and the stop for the vector part which can be written in
its associated memory block and links. This part of the control
logic is suitably performed in hardware which is more efficient
than in a dynamic memory. An embodiment of the control logic for
the embodiments in FIGS. 1-5 can be performed like that in FIG. 6
without delay 16. The memory will look like a normal memory from
outside. The only limitation which applies to the memory according
to the invention is that it is only efficient during the treatment
of vectors. The memory can be included as part of the ordinary
memory of a computer.
[0083] In the new system can both information be quickly found and
data transfer take place quickly. A memory block can be a part of a
chip, i.e. several memory blocks can be on the same chip or the
memory blocks can also be in separate chips. Alternatively, each
memory block can be formed of several chips or be built of standard
components. All these possibilities can be on the market together
which implies flexible use with a combination of different
units.
[0084] If it appears that the vectors for an application tend to be
so long that they must be divided up into several vectors in order
to be able to be stored in the memory, then there is for example
the possibility to couple extra memory blocks (chips) after the
last one in a simple manner in order in this way to be able to
extend the storage space for vectors which can be stored.
[0085] Another area of use is telephone traffic where data can
arrive serial bit form in the case that there are suitable
converter units 5 for information coming to the first input buffer
for converting from bit to byte.
[0086] The input buffers can also be organized so that they are
serial shift registers (special case). One can also have serial
shift registers on the input buffers and parallel on the output
buffers or vice versa. It is a question of implementation in the
event one chooses to first perform up-parallelling of data. This is
very probable if one considers a future telecommunication
application. There the incoming information is serial. Then a first
parallel conversion is performed in the component 5 external to the
memory.
[0087] Each control logic 4 and mS can be in the form of a simple
data chip with a fixed program. Alternatively the control logic mS
can be integrated together with the memory planes. FIGS. 4 and 5
show a design of a flow diagram for the control logic. The
functions which are achieved with the flow diagrams have been
described above which is why the flow diagrams do not in themselves
require any extra description but can be directly understood by the
man skilled in the art.
[0088] Many conceivable modifications within the scope of the
invention are given in the appended claims.
* * * * *