U.S. patent application number 09/823073 was filed with the patent office on 2001-08-16 for programmable integrated passive devices.
Invention is credited to Richiuso, Dominick L..
Application Number | 20010013632 09/823073 |
Document ID | / |
Family ID | 25493857 |
Filed Date | 2001-08-16 |
United States Patent
Application |
20010013632 |
Kind Code |
A1 |
Richiuso, Dominick L. |
August 16, 2001 |
Programmable integrated passive devices
Abstract
An integrated passive device array structure with a value that
is programmable during manufacturing. The device structure includes
a substantially conductive first layer having a plurality of
passive device array elements of the integrated passive device
array structure disposed above the substantially conductive first
layer. The device further includes an insulating layer formed above
the plurality of passive device array elements. One or more vias
are selectively formed in the insulating layer. The vias facilitate
electrical connections between selected ones of the plurality of
passive device array elements with a substantially conductive
second layer subsequently deposited above the insulating layer.
Inventors: |
Richiuso, Dominick L.;
(Saratoga, CA) |
Correspondence
Address: |
BEYER WEAVER & THOMAS LLP
P.O. BOX 778
BERKELEY
CA
94704-0778
US
|
Family ID: |
25493857 |
Appl. No.: |
09/823073 |
Filed: |
March 29, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09823073 |
Mar 29, 2001 |
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09437587 |
Nov 9, 1999 |
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09437587 |
Nov 9, 1999 |
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08953350 |
Oct 17, 1997 |
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5998275 |
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60028778 |
Oct 18, 1996 |
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Current U.S.
Class: |
257/528 ;
257/209; 257/529; 257/532; 257/535; 257/E27.048; 257/E27.071 |
Current CPC
Class: |
H01L 27/101 20130101;
H01L 27/0805 20130101 |
Class at
Publication: |
257/528 ;
257/209; 257/529; 257/532; 257/535 |
International
Class: |
H01L 027/10; H01L
029/00 |
Claims
What is claimed is:
1. An integrated programmable passive device array structure,
comprising: a first node; a plurality of passive device array
elements electrically coupled to said first node; and a second
node, said second node being electrically coupled, in a selective
manner, to selected ones of said plurality of passive device array
elements, said selected ones of said plurality of passive device
array elements representing a subset of said plurality of passive
device array elements, wherein a value of said programmable passive
device array structure is substantially determined by an aggregate
of values of said selected ones of said plurality of passive device
array elements.
2. The integrated programmable passive device array structure of
claim 1 wherein said selected ones of said plurality of passive
device array elements are configured to be electrically coupled in
parallel between said first node and said second node.
3. The integrated programmable passive device array structure of
claim 1 wherein values of individual passive device array elements
of said selected ones of said plurality of passive device array
elements are related in a binary manner.
4. The integrated programmable passive device array structure of
claim 1 wherein said plurality of passive array elements represent
capacitors.
5. The integrated programmable passive device array structure of
claim 4 wherein said first node is implemented in a substantially
conductive first layer, said second node being implemented in a
substantially conductive second layer above said substantially
conductive first layer.
6. The integrated programmable passive device array structure of
claim 5 wherein each of said plurality of passive device array
elements includes a dielectric portion formed of a layer of
dielectric material, said layer of dielectric material being
disposed between said substantially conductive first layer and said
substantially conductive second layer.
7. The integrated programmable passive device array structure of
claim 6 wherein said layer of dielectric material is separated from
said substantially conductive second layer by an insulating layer,
each of said selected ones of said plurality of passive device
array elements being furnished with a via through said insulating
layer to permit said second node to form an electrical contact with
said each of said selected ones of said plurality of passive device
array elements through said insulating layer.
8. The integrated programmable passive device array structure of
claim 1 wherein at least one of said plurality of passive device
array elements is selected to be electrically decoupled from said
second node.
9. An integrated programmable passive device array structure,
comprising: a first node; a plurality of passive device array
elements electrically coupled to said first node, each of said
plurality of passive device array elements having a value; and a
second node, said second node being electrically coupled, in a
selective manner, to selected ones of said plurality of passive
device array elements, said selected ones of said plurality of
passive device array elements representing a subset of said
plurality of passive device array elements, wherein a value of said
programmable passive device array structure is substantially
determined by an aggregate of said values of said selected ones of
said plurality of passive device array elements.
10. The integrated programmable passive device array structure of
claim 9 wherein said selected ones of said plurality of passive
device array elements are configured to be electrically coupled in
parallel between said first node and said second node.
11. The integrated programmable passive device array structure of
claim 9 wherein the values of said plurality of passive device
array elements are related by a predetermined relationship.
12. The integrated programmable passive device array structure of
claim 11 wherein said predetermined relationship is selected from
the group consisting of: binary, linear, geometric, logarithmic,
exponential, and arbitrary.
13. The integrated programmable passive device array structure of
claim 9 wherein at least one of said plurality of passive device
array elements is selected from the group consisting of: capacitor,
resistor, and inductor.
14. An integrated circuit device incorporating a programmable
capacitor array including a plurality of capacitors, the array
comprising: a substrate; a plurality of bottom capacitor plates
disposed on an upper surface of said substrate; a corresponding
plurality of top capacitor plates disposed over said plurality of
bottom capacitor plates; a dielectric disposed between said
plurality of bottom capacitor plates and said corresponding
plurality of top capacitor plates; electrical separation means
disposed on at least a portion of said corresponding plurality of
top capacitor plates, said electrical separation means for
electrically separating individual ones of said capacitors; and a
conductive layer applied over said electrical separation means.
15. The integrated circuit device of claim 14 wherein said array
further comprises an epitaxial layer disposed between said
substrate and at least a portion of said plurality of bottom
capacitor plates.
16. The integrated circuit device of claim 14 wherein said array
further comprises a passivation layer deposited on at least a
portion of an upper surface of said conductive layer.
17. The integrated circuit device of claim 14 further comprising:
said electrical separation means formed as a layer of intermediate
oxide defining at least one contact hole therethrough, said contact
hole being disposed over a selected one of said plurality of top
plates; and said conductive layer further defines an electrical
path through said contact hole and to said selected one of said
plurality of top plates.
18. The integrated circuit device of claim 17 wherein said layer of
intermediate oxide defining at least one contact hole therethrough
is formed by a process comprising the steps of: masking at least a
portion of said layer of intermediate oxide; and etching at least
another portion of said layer of intermediate oxide.
19. The integrated circuit device of claim 18 wherein said masking
step is performed utilizing a process selected from the group
consisting of: contact masking, metal masking, via masking, poly
masking, and active masking.
20. The integrated circuit device of claim 14 further comprising at
least one field oxide element disposed between and separating
adjacent ones of said plurality of bottom capacitor plates.
21. The integrated circuit device of claim 20 wherein at least one
of said field oxide element and said plurality of bottom plates is
formed by the process consisting of the steps of: masking at least
a portion of said at least one of said field oxide and said
plurality of bottom plates; and etching at least another portion of
said field oxide and said plurality of bottom plates.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] Filed under Rule 1.53(b), this is a divisional patent
application of allowed co-pending application Ser. No. 08/953,350
entitled "Programmable Integrated Passive Devices and Methods
Therefor", which parent application was filed on Oct. 17, 1997.
BACKGROUND OF THE INVENTION
[0002] The present invention relates generally to the manufacture
of integrated circuits (IC's). More particularly, the present
invention relates to programmable capacitors, and methods therefor,
that render the value of the capacitor selectable during
manufacturing.
[0003] Integrated circuits integrate many discrete functions and
components into one "integrated" circuit. One of the reasons
integrated circuits presently predominate over discrete component
solutions is because of the costs involved in manufacturing,
assembling, and testing discrete based circuits. For example,
present day microprocessors incorporate more than one million
transistors into a square package less than 5 cm on each side. The
same number of transistors, discretely and separately placed on a
printed circuit board, would require several orders of magnitude
more space. Other advantages of integrated circuit technology,
which are well known to those skilled in the art, include
reliability and cost.
[0004] The miniaturization that present day integrated circuit
technology, and the benefits that such technology bestows, are
applicable to passive component integration as well. When passive
devices, e.g., capacitors, resistors, inductors, and the like, are
integrated, they are referred to herein as passive component
integrated circuits.
[0005] In the design of passive thin film integrated circuits, for
example, capacitors of different values are needed. By way of
example, in the design of a family of filters or terminators,
resistors and capacitors are combined in different configurations
and values to provide different functionality and performance. In
prior art, this is typically accomplished by a custom design and
integrated circuit layout configuration for each type of circuit
and for each value. This process is time consuming, more prone to
errors and less economical.
[0006] In the description that follows, an integrated capacitor is
selected for discussion. It should be borne in mind, however, that
the inventive concepts herein also apply to other types of passive
devices, e.g., resistors, inductors, and the like. In the prior
art, when an application requires an integrated capacitor having a
value that is previously unavailable, a new custom design is
necessitated to create an integrated circuit having a capacitor
with the desired value. This custom design approach requires a
substantial amount of time, effort, and expense since a custom
design with specific capacitance values and characteristics must be
laid out and verified, the required masks must be created, and
manufacturing steps must be tailored to fabricate the required
integrated circuit. As can be appreciated from the foregoing, the
custom design approach is disadvantageous in view of the great
variety of device values required by modern electronic
equipment.
[0007] In view of the foregoing, what is desired are passive
component integrated circuit structures and methods therefor, which
can implement a wide range of values in a given single design. This
alleviates all the above mentioned limitations of prior art custom
design approaches, thereby providing quicker design turnaround
time, fewer design errors and a lower manufacturing cost.
SUMMARY OF THE INVENTION
[0008] The present invention relates, in one embodiment, to a
method for endowing an integrated passive device array structure
with a programmable value during manufacturing. The method includes
forming a substantially conductive first layer and forming a
plurality of passive device array elements of the integrated
passive device array structure above the substantially conductive
first layer. The method further includes forming an insulating
layer above the plurality of passive device array elements. There
is further included selectively forming vias in the insulating
layer. The vias facilitate electrical connections between selected
ones of the plurality of passive device array elements with a
substantially conductive second layer subsequently deposited above
the insulating layer.
[0009] In another embodiment, the invention relates to a method for
forming an integrated passive device array structure having a
programmable value. The method includes forming a substantially
conductive first layer, and electrically coupling the substantially
conductive first layer with a plurality of passive device array
elements of the integrated passive device array structure. The
plurality of passive device array elements is disposed above the
substantially conductive first layer. There is also included
electrically coupling selected ones of the plurality of passive
device array elements with a substantially conductive second layer
to form the integrated passive device array structure. The selected
ones of the plurality of passive device array elements represent a
subset of the plurality of passive device array elements.
[0010] In yet another embodiment, the invention relates to an
integrated programmable passive device array structure, which
includes a first node, and a plurality of passive device array
elements electrically coupled to the first node. The integrated
programmable passive device array structure further includes a
second node electrically coupled, in a selective manner, to
selected ones of the plurality of passive device array elements.
The selected ones of the plurality of passive device array elements
represent a subset of the plurality of passive device array
elements, wherein a value of the programmable passive device array
structure is substantially determined by an aggregate of values of
the selected ones of the plurality of passive device array
elements.
[0011] In another embodiment, the invention relates to a capacitor
array structure having multiple capacitor array elements. During
production, the individual capacitor array elements are selected
for inclusion into or exclusion out of the final capacitor
structure. An included capacitor array element contributes its
capacitance value to the capacitance value of the final capacitor
structure. In contrast, the capacitance value of an excluded
capacitor array element makes no contribution to the capacitance
value of the final capacitor structure.
[0012] In another embodiment, the capacitor array elements are
binary related. In accordance with this embodiment, a given array
element has twice the capacitance value of its smaller counterpart.
For example, the cell surface area of a successive capacitor array
element increases by a factor of 2 relative to its immediately
smaller counterpart. Because capacitance is proportional to the
surface area of the plates forming the capacitor, by providing n
distinct cells in the array structure, 2n different capacitance
values may be available for each such array structure.
[0013] In accordance with yet another embodiment of the present
invention, a given capacitor array element is selected for
inclusion by providing it with a contact, thereby permitting an
electrical path to exist between its plates and the nodes of the
final capacitor structure through the provided contact. On the
other hand, another given capacitor array element is excluded from
the final capacitor structure when no contact is provided for it,
thereby inhibiting the formation of an electrical path between its
plates and the nodes of the final capacitor structure. In this
manner, individual capacitor array elements of a capacitor array
structure may be programmably selected for inclusion or exclusion
by appropriately designing the contact mask.
[0014] These and other advantages of the present invention will
become apparent upon reading the following detailed descriptions
and studying the various figures of the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIGS. 1(a) and 1(b) are a schematics illustrating, in
accordance with one aspect of the present invention, capacitor
array structures having capacitors coupled in parallel for
implementing the programmable capacitors of the present
invention.
[0016] FIG. 1(c) is a symbolic circuit diagram illustrating the
contribution made by selected and non-selected capacitor array
members to the capacitance value of the final capacitor
structure.
[0017] FIG. 2 shows, in accordance with one embodiment of the
present invention, a top plane view of a capacitor array
layout.
[0018] FIGS. 3a-j illustrate, in accordance with one embodiment of
the present invention, the relevant steps involved in the
fabrication and programming of a capacitor array structure.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0019] In accordance with one aspect of the present invention, the
value of the inventive programmable capacitor may be rendered
selectable during manufacturing by fabricating the capacitor as a
programmable capacitor array structure. The value of the capacitor
that results may be programmably determined during manufacturing by
the selective inclusion of individual capacitor array members.
Capacitor array members which are incorporated into the final
programmable capacitor array structure contribute to the
capacitance value of the resulting capacitor. On the other hand,
capacitor array members which are not incorporated into the final
programmable array structure do not contribute to the capacitance
value of that resulting capacitor. The above concept may be better
understood with reference to the Figures below.
[0020] FIGS. 1(a) through 1(c) illustrate the concept that
underlies the programmable capacitor array in accordance with one
aspect of the present invention. FIGS 1a illustrates a programmable
capacitor C, which comprises a plurality of programmably related
capacitor array members, C.sub.1, C.sub.2, C.sub.3 . . . C.sub.n.
The programmably related capacitor array members C.sub.1 . . .
C.sub.n are arranged such that each, if selected, may be coupled in
parallel with others in the programmable capacitor array. As is
readily recognizable by those skilled in the art, the effective
capacitance value of the programmable capacitor array of FIG. 1a
equals the cumulative capacitance value of the capacitor array
members that are coupled to nodes 100 and 102 in parallel. In other
words, the value of programmable capacitor C between nodes 100 and
102 is determined by which of capacitor array members C.sub.1 . . .
C.sub.n are incorporated into the final capacitor structure.
[0021] In one embodiment, the capacitor array members C.sub.1
through C.sub.n are related to one another in a binary manner. In
other words, the values of the capacitor array members are
successively increased by a factor of 2. In FIG. 1b, for example,
there are shown a programmable capacitor array comprising six
capacitor array members C.sub.1 . . . C.sub.6. When the capacitor
array members C.sub.1 . . . C.sub.6 are binary related, capacitor
array member C.sub.2 has twice the capacitance value of capacitor
array member C.sub.1; capacitor array member C.sub.3 has twice the
capacitance value of capacitor array member C.sub.2; and so on. It
should be recognized that the capacitance value of a capacitor
array member C.sub.m equals 2.sup.(m-1) times the capacitance value
of the smallest capacitor array member C.sub.1 (m being an
arbitrary integer between 1 and n, the total number of capacitor
array members in the programmable capacitor array).
[0022] It should be noted that although binary related capacitor
array members are discussed herein to facilitate ease of
understanding, the capacitance values of the capacitor array
members may be related to one another via any predetermined
relationship. For example, the capacitance values among the
capacitor array members may be related in accordance to a linear,
geometric, logarithmic, or exponential relationship. Of course,
they may also relate to one another in any other arbitrary,
predefined manner.
[0023] In FIG. 1b, capacitor array members C.sub.2 and C.sub.3 are
not incorporated into the final capacitor structure. As such, the
capacitance value of the capacitor structure of FIG. 1b
substantially equals to the sum of the capacitance values of
capacitor array members C.sub.1, C.sub.4, C.sub.5, and C.sub.6 (or
C.sub.1+8 C.sub.1+16 C.sub.1+32 C.sub.1=57 C.sub.1). Other
capacitance values may be obtained, as can be appreciated from the
foregoing, by selectively incorporating or removing the individual
capacitor array members from the final capacitor structure.
[0024] Depending on the particular fabrication technology employed,
the layout of the integrated circuit may, in some cases, give rise
to parasitic capacitance between the layers in some structures. The
parasitic capacitance associated with a given capacitor array
member may contribute to the capacitance value of the final
capacitor structure even if that particular capacitor array member
is not incorporated into the final capacitor structure. To
illustrate this concept, FIG. 1c symbolically illustrates the
contribution of each included and excluded capacitor array member
to the capacitance value of the final capacitor structure of FIG.
1b.
[0025] Referring to FIG. 1c, capacitor array member C1 is selected
for incorporation. Accordingly, its capacitance value contributes
to the resultant capacitance value of the final capacitor structure
of FIG. 1b. In the context of FIG. 1c, the incorporation of
capacitor array member C1 is illustrated symbolically by the
connection of capacitor C1 to nodes 100 and 102.
[0026] Capacitor array member C.sub.2 is not selected for
incorporation. Accordingly, its capacitance value does not
contribute to the resultant capacitance value of the final
capacitor structure of FIG. 1b. As shown in FIG. 1c, however, the
parasitic capacitance value associated with capacitor array member
C.sub.2 still contributes to the capacitance value of the final
capacitor structure. As a result, a parasitic capacitor C.sub.2p
(where p denotes parasitic capacitance) is symbolically coupled to
node 100 in FIG. 1c. Likewise, capacitor array member C.sub.3 is
not selected. As shown in FIG. 1c, the parasitic capacitor
C.sub.3p, which is associated with capacitor array member C.sub.3,
still makes its contribution to the capacitance value of the
resultant capacitor structure.
[0027] Finally, capacitor array members C.sub.4 and C.sub.5 are
selected for incorporation. As a result, their capacitance values
contribute to the value of the capacitor structure that results, as
shown in FIG. 1c. FIG. 1c is also useful for visualizing the
programmable aspect of the inventive capacitor array structure.
When a given capacitor array member is selected for incorporation
into the final capacitor structure, its capacitor may be thought of
as being coupled to a capacitor node (node 100 in the case of FIG.
1c) by a switch. When a given capacitor array member is not
selected for incorporation into the final capacitor structure, its
capacitor is not coupled to the capacitor nodes. Instead, the
parasitic capacitor associated with the non-selected capacitor
array member may then be thought of as being coupled to the
capacitor nodes.
[0028] FIG. 2 illustrates, in accordance with one embodiment of the
present invention, the layout of a programmable capacitor array.
For ease of discussion, the capacitor array members of FIG. 2 are
binary related although, as noted earlier, other relationships may
well be employed.
[0029] As is well known, a capacitor is created by placing a
dielectric medium of a certain thickness between two conductive
regions, or plates, with the capacitance being directly
proportional to the surface area of the plates in contact with the
dielectric; directly proportional to the dielectric constant and
inversely proportional to the dielectric thickness. In this manner,
for a given dielectric constant and thickness, if the surface area
is doubled, the capacitance is also doubled. In FIG. 2, the surface
area of capacitor C.sub.2 is twice that of capacitor C.sub.1.
Similarly, the capacitance of capacitor C.sub.3 is twice that of
capacitor C.sub.2, and that of C.sub.4 is twice that of capacitor
C.sub.3, and so on.
[0030] In accordance with one aspect of the present invention,
every capacitor array member of a programmable capacitor array is
fabricated, complete with its plates and dielectric layer
irrespective of whether that capacitor array member is incorporated
into the final capacitor structure. To select a capacitor array
member for incorporation, a contact is created with a capacitor
plate (typically but not necessarily the upper plate) to facilitate
the formation of a conduction path between a common conductor and
that capacitor plate. The common conductor represents a node of the
final capacitor structure, e.g., node 100 of FIGS. 1a, 1b, and 1e.
Consequently, the provision of a contact permits the selected
capacitor array member to be coupled to the common conductor, and
to the remainder of the resultant capacitor structure, in a
parallel fashion with other selected capacitor array members.
[0031] If a capacitor array member is not selected for
incorporation into the final capacitor array structure, no contact
is provided for that capacitor array member. Consequently, there is
no conduction path between the plate of that non-selected capacitor
and the common conductor, and the capacitor array member is
essentially "decoupled," electrically speaking, from the remainder
of the resultant capacitor structure.
[0032] The above concept may be better understood with reference to
FIGS. 3a-3j below. FIG. 3a-3j illustrate, in accordance with one
embodiment of the present invention, a manufacturing method whereby
a programmable capacitor array is created and selected ones of the
array's members are programmably incorporated into the final
capacitor structure. FIG. 3a shows the process starting with an
n.sup.+ type substrate 30. FIG. 3b shows a p- type epitaxial layer
32, which is grown on n.sup.+ type substrate 30 using a
conventional semiconductor manufacturing technique.
[0033] In FIG. 3c, a deep n.sup.+ diffusion through a selected
portion of p- type epitaxial layer 32, through to substrate 30, is
performed using conventional masking and diffusion techniques. This
n.sup.+ region 34 serves as the bottom plate of the capacitor array
members to be subsequently formed. The region to be diffused is
selected so that it lies underneath the entirety of the capacitor
array. In addition, the n.sup.+ region serves as a low resistance
path to the bottom of the wafer where physical contact is
eventually made to the bottom capacitor plate and to insure that
the capacitor structure that results does not vary with applied
voltage (in the manner expected of a standard MOS gate
transistor).
[0034] Referring to FIG. 1(c), for example, the bottom plate of
capacitors C.sub.1 through C.sub.6 are electrically connected. For
this reason and as will be shown herein, the selective
incorporation of the capacitor array members is performed using the
top plates of the capacitor array members.
[0035] In FIG. 3d, field oxidation is selectively performed to
separate the individual capacitor array members from one another.
This field oxidation is performed using conventional masking and
deposition techniques. As shown next in FIG. 3e, a selective gate
oxidation is performed. Gate oxide regions 38a and 38b are grown on
the portions of the n.sup.+ region 34 that are not covered by the
field oxide regions 36. These gate oxide regions 38(a) and 38(b)
form the dielectric of the capacitor array elements of the
programmable capacitor array. In the preferred embodiment, the
dielectric is silicon dioxide (SiO.sub.2). However, the dielectric
may represent a layer of silicon nitride, a silicon dioxide/silicon
nitride sandwich combination, or any other dielectric material.
[0036] Next, a polysilicon layer is deposited and masked, as shown
in FIG. 3f. These polysilicon regions 40a and 40b form the top
plates of the capacitor array elements associated with dielectric
regions 38a and 38b.
[0037] Next, an intermediate oxide layer 42 is then applied as
shown in FIG. 3g. This intermediate oxide layer 42 electrically
separates the individual capacitor array elements from a
subsequently deposited conductive layer.
[0038] In FIGS. 3g, the capacitor array is essentially
"unprogrammed." At this stage, the wafer prepared in accordance
with this invention may be stored until a customer's specification
for a product is received. To program the capacitor of FIG. 3g to a
particular desired value, the particular combination of capacitor
array elements C1 . . . Cn to be incorporated into the final
capacitor structure is first ascertained. For example, the desired
capacitance value may be compared against a predefined table which
lists the possible combinations of incorporated capacitor array
elements and the capacitance values that result thereby.
[0039] To select a given capacitor array element for incorporation
into the final capacitor array structure, a contact mask is
employed to perform a contact etch. If a capacitor array element
site is provided with a contact hole (through intermediate oxide
layer 42) to facilitate electrical contact with a subsequently
deposited conductive layer, that capacitor array element is
selected for incorporation. On the other hand, if a capacitor array
element is not provided with a contact hole through the
intermediate oxide layer 42 that overlies it, no electrical contact
may be formed between that capacitor array element and the
subsequently deposited conductive layer. Consequently, the latter
capacitor array element may be thought of as being non-selected,
i.e., makes no contribution (except for its parasitic capacitance)
to the capacitance value of the final capacitor structure.
[0040] As shown in FIG. 3h, a contact hole 44 is created by etching
through the intermediate oxide 42 to expose polysilicon top plate
40b. FIG. 3i shows the deposition of a metal layer 46, which makes
contact with polysilicon top plate 40b through contact hole 44.
This metal layer acts as a continuous top plate connected to all
selected capacitor array elements, advantageously minimizing the
parasitic effects of resistance and inductance.
[0041] As can be seen in FIG. 3h, the capacitor array element
associated with polysilicon top plate 40(b) is selected for
incorporation into the final capacitor structure. In contrast, no
contact hole is made with polysilicon top plate 40a, and the
capacitor array element associated therewith is left decoupled from
the final capacitor structure. However, there exists a parasitic
capacitor consisting of two capacitors in series. The first
capacitor is formed with the metal acting as the top plate, the
intermediate oxide acting as the primary dielectric, and the
polysilicon layer acting as the bottom plate. The second capacitor
is formed with the polysilicon layer acting as the top plate, the
gate oxide acting as the dielectric, and the n.sup.+ layer acting
as the bottom plate. This parasitic capacitor, which is associated
with the site of the non-selected capacitor array member, still
contributes to the capacitance value of the final capacitor
structure in the manner discussed in connection with FIG. 1c. In
practice, the parasitic capacitance value is much smaller than the
capacitance value of the normal capacitor array element, typically
one twentieth to one fortieth of the non-selected capacitor array
member. Following the metal deposition step of FIGS. 3i, a
passivation layer 50 is deposited in a conventional manner to
protect the entire structure, as shown in FIG. 3j.
[0042] It should be emphasized that in the above discussed
embodiment, the separate capacitor array elements are always
present. Whether a given capacitor array element is selected for
incorporation or left out of the final capacitor structure depends
on whether a contact hole is provided in the intermediate oxide
layer above that capacitor array element to create an electrical
path to its top plate. Thus, the value of the capacitor structure
that results is determined by appropriately programming the
presence or absence of selected contact holes on the contact
mask.
[0043] While this invention has been described in terms of several
preferred embodiments, there are alterations, permutations, and
equivalents which fall within the scope of this invention. By way
of example, although the inventive concept has been discussed, for
ease of illustration, with reference to n.sup.+ type substrates, n
type or p type materials could be reversed in a given process
implementation. Further, the present inventive concepts also apply
equally well to capacitor arrays employing different types of
dielectric materials, doping concentrations, as well as those not
having an epitaxial layer. Additionally, although the
programmability feature is facilitated through the use of a contact
mask in this discussion, it should be borne in mind that a
programmable passive device may be facilitated through the use of
the metal mask, the via mask between metal 1 and metal 2 layers,
poly mask, active mask, and the like. As a further example, the
inventive concepts discussed herein are also applicable to passive
devices (such as capacitors, resistors, inductors, and the like)
which are integrated with active components (such as transistors,
diodes, and the like) on the same integrated circuit. It should
also be noted that there are many other alternative ways of
implementing the methods and apparatuses of the present invention.
It is therefore intended that the specification herein be
interpreted as including all such alterations, permutations, and
equivalents as fall within the true spirit and scope of the present
invention.
* * * * *