Method of manufacturing thin film transistor

Abstract

The present invention discloses a method of manufacturing a thin film transistor, including: preparing a process chamber having a stage; providing a substrate on the stage of the process chamber; injecting a first mixed gas of NH.sub.3, N.sub.2 and SiH.sub.4 into the process chamber; forming a plasma in the process chamber and forming a silicon nitride film (SiNx) on the substrate; injecting a second mixed gas of H.sub.2 and SiH.sub.4 into the process chamber while removing the first mixed gas in the plasma state; forming a pure amorphous silicon film (a-Si:H) on the silicon nitride film using the second mixed gas; injecting a third mixed gas of H.sub.2, SiH.sub.4 and PH.sub.3 into the process chamber while removing the second mixed gas in the plasma state; and forming a doped amorphous silicon film (n.sup.+a-Si:H) on the silicon nitride film using the second mixed gas.

Description

CROSS REFERENCE

[0001] This application claims the benefit of Korean Patent Application No. 1999-67845, filed on Dec. 31, 2000, under 35 U.S.C. .sctn. 119, the entirety of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor for use in a liquid crystal display (LCD) device.

[0004] 2. Description of Related Art

[0005] Liquid crystal display (LCD) devices are in wide use as display devices capable of being reduced in weight, size and thickness. Of these, active matrix LCD devices, where thin film transistors (TFTs) and pixel electrodes are arranged in the form of a matrix, have been widely used due to a high resolution and an excellent performance of implementing moving images.

[0006] FIG. 1 is a cross-sectional view illustrating a liquid crystal panel of a typical active matrix LCD device. As shown in FIG. 1, the liquid crystal panel 20 includes lower and upper substrates 2 and 4 with a liquid crystal layer 10 interposed therebetween. The lower substrate 2, referred to as an array substrate, is divided into two regions: a region S; and a region P. TFTs are arranged on the region S as a switching element, and pixel electrodes 14 are arranged on the pixel region P. The upper substrate 4 includes a color filter 8 and a common electrode 12. Through the pixel electrode 14 and the common electrode 12, voltages are applied to the liquid crystal layer 10. In order to prevent a leakage of the liquid crystal, edge portions of the two substrate 2 and 4 are sealed by a sealant 6. The TFT receives signals from external drive integrated circuit (IC) to drive the pixel electrode 14.

[0007] An inverted staggered type TFT is used for a general LCD device because its simple structure and a high performance. The inverted staggered type TFT is divided into a back channel etch type and an etch stopper type. Hereinafter, the back channel etch type TFT is explained.

[0008] FIG. 2 is a cross-section view illustrating the typical back channel etch type TFT. As shown in FIG. 2, a gate electrode 30 is formed on a substrate 1. A gate insulating layer 32 is formed over the whole surface of the substrate 1 while covering the gate electrode 30. An active layer 34 and an ohmic contact layer 36 are sequentially formed on the gate insulating layer 32. Source and drain electrodes 38 and 40 overlap both end portions of the ohmic contact layer 36.

[0009] The gate electrode 30 is made of a low resistive material such as aluminum in order to reduce a RC delay. The gate insulating layer 34 is deposited at a low temperature of less than 350 and is made of SiNx or SiO.sub.2. The active layer 34 is made of an hydrogenated amorphous silicon (a-Si:H). The ohmic contact layer 36 is formed in such a way that a gas containing a boron (B) of a boron group or a phosphorous (P) of a nitrogen group is ion-doped into the amorphous silicon layer. The ohmic contact layer 36 is generally is made of n.sup.+-type hydrogenated amorphous silicon (n.sup.+ a-Si:H) doped with PH.sub.3 containing a phosphorous (P). The source and drain electrodes 42 and 44 are made of Cr or Mo.

[0010] In order to form the TFT, a deposition process is repeated several times, for example, using a plasma-enhanced chemical vapor deposition (PECVD) technique. The gate insulating layer 32, the active layer 34 and the ohmic contact layer 36 undergo a deposition process in the same process chamber.

[0011] FIG. 3 is a graph illustrating a relationship between a power and each of the layers when the gate insulating layer 32, the active layer 34 and the ohmic contact layer 36 are deposited.

[0012] In order to form the gate insulating layer 32, a mixed gas of NH.sub.3, N.sub.2 and SiH.sub.4 is injected into the process chamber and is decomposed by plasma, so that a silicon nitride film (SiNx) is formed on the substrate.

[0013] In order to form the active layer 34, NH.sub.3 and N.sub.2 that are used to deposit the gate insulating layer 32 are pumped, and H.sub.2 are added. The pure amorphous silicon (a-Si:H) is formed using SiH.sub.4 and H.sub.2.

[0014] Then, in order to form the ohmic contact layer 36, a small amount of PH.sub.3 is added to the mixed gas of SiH.sub.4 and H.sub.2 to form an n.sup.+ type amorphous silicon layer (a-Si:H).

[0015] The active layer 34 generally contains a hydrogen (H). Electrical characteristics of the amorphous silicon TFTs depend on a density of state (DOS). The silicon atoms of the active layer 34 have 4 outmost electrons, among them uncombined electrons cause a dangling bond problem. The dangling bond problem can be solved by the hydrogen.

[0016] As described above, in order to remove the mixed gases used to deposit the gate insulating layer, the active layer and the ohmic contact layer, plasma condition should be released first. After a predetermined time passes, the mixed gas in the process chamber is pumped.

[0017] FIG. 4 is a graph illustrating a relationship between an internal pressure variation of the process chamber and each of the layers when the gate insulating layer 32, the active layer 34 and the ohmic contact layer 36 are deposited. After a deposition of the gate insulating layer 32, if the mixed gas is removed in the state that the plasma condition is released, an internal pressure of the process chamber varies suddenly. When the internal pressure of the process chamber varies, the polymer generated during the deposition process may fall onto a surface of the gate insulating layer, leading to inferiority in subsequent process.

[0018] Further, when the active layer is formed, a predetermined time is required to maintain an initial plasma state. At this time, the active layer deposited has defects such as a dangling bond. As a result, an interface between the insulating layer and the active layer becomes inferior, and therefore current-voltage characteristics of the TFT are lowered.

[0019] Furthermore, an interface (see a portion "A" of FIG. 2) between the gate insulating layer and the active layer may have defects due to a lattice mismatch because of the difference of the atoms of the insulating layer and the active layer when the thin films are formed, thereby lowering electrical characteristics of the TFT. In other words, a threshold voltage of the TFT may increase, and a switching operation may become impossible, and there may come the problem in stability. For example, charges are accumulated on the interface between the gate insulating layer 32 and the active layer 34, lowering an ON current.

SUMMARY OF THE INVENTION

[0020] To overcome the problems described above, preferred embodiments of the present invention provide a method of manufacturing a thin film transistor minimizing defects generated when thin films of the thin film transistor are formed.

[0021] It is another object of the invention to provide a method of forming thin films for the thin film transistor, which can lower the manufacturing time.

[0022] In order to achieve the above object, the preferred embodiments of the present invention provide a method of manufacturing a thin film transistor, including: preparing a process chamber having a stage; providing a substrate on the stage of the process chamber; injecting a first mixed gas of NH.sub.3, N.sub.2 and SiH.sub.4 into the process chamber; forming a silicon nitride film (SiNx) on the substrate with the first mixed gas by creating a plasma state in the process chamber; injecting a second mixed gas of H.sub.2 and SiH.sub.4 into the process chamber while removing the first mixed gas in the plasma state; forming a pure amorphous silicon film (a-Si:H) on the silicon nitride film using the second mixed gas in the plasma state; injecting a third mixed gas of H.sub.2, SiH.sub.4 and PH.sub.3 into the process chamber while removing the second mixed gas in the plasma state; and forming a doped amorphous silicon film (n.sup.+ a-Si:H) on the silicon nitride film using the third mixed gas in the plasma state.

[0023] The method further includes forming a gate electrode before the step of forming the silicon nitride film; and forming source and drain electrodes on the doped amorphous silicon film. The method further includes performing a hydrogen plasma treatment on a surface of the silicon nitride film before the step of forming the pure amorphous silicon film. The method further includes performing a hydrogen plasma treatment on a surface of the pure amorphous silicon film before the step of forming the doped amorphous silicon film.

[0024] The method of manufacturing the TFT according to the preferred embodiment of the present invention has the following advantages. Firstly, since each of the thin films is deposited in the plasma state, variation of an internal atmosphere of the process chamber is minimized, whereupon a processing time becomes shorten. Secondly, since the thin films deposited are hydrogen plasma-treated, the hydrogen plasma etches detects on the interface between the thin films, whereupon defects can be prevented. Thirdly, since each of the thin films is deposited under the same pressure, an occurrence of a polymer in the process chamber can be prevented, and interface characteristics of the thin films can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which:

[0026] FIG. 1 is a cross-sectional view illustrating a liquid crystal panel of a conventional active matrix liquid crystal display device;

[0027] FIG. 2 is a cross-sectional view illustrating a conventional back channel etch type thin film transistor;

[0028] FIG. 3 is a graph illustrating a relationship between a RF-power and thin film depositions;

[0029] FIG. 4 is a graph illustrating a relationship between an internal pressure variation of a process chamber and thin film depositions;

[0030] FIG. 5 is a graph illustrating a relationship between a RF-power and a thin film deposition according to a preferred embodiment of the present invention; and

[0031] FIG. 6 is a graph illustrating a variation of an internal pressure of the process chamber during deposition processes of the thin films.

DETAILED DESCRIPTION OF PREFFERED EMBODIMENTS

[0032] Reference will now be made in detail to a preferred embodiment of the present invention, example of which is illustrated in the accompanying drawings.

[0033] FIG. 5 is a graph illustrating a relationship between a RF-power and thin film depositions according to a preferred embodiment of the present invention. As shown in FIG. 5, except for a process of injecting a first mixed gas of NH.sub.3, N.sub.2 and SiH.sub.4 into the process chamber in order to deposit a gate insulating layer, the power maintains ON state through the whole deposition processes.

[0034] First, the first mixed gas stabilized under a predetermined pressure is maintained in a first plasma state "A.sub.0" by a predetermined RF power intensity, and then the gate insulating layer is deposited. At this point, a deposition temperature of the thin films is one of the most important parameters to control a surface reaction of a semiconductor layer during a deposition process. In other words, since precursors actively react on hydrogen at a temperature of about 300.degree. C. and also the number of the silicon dangling bond is decreased at that temperature, to control a deposition temperature is very important.

[0035] Subsequently, after depositing the gate insulating layer using the first mixed gas, the first mixed gas is removed while the plasma state is maintained (i.e., without OFF of a power). At the same time, a H.sub.2 gas is injected into the process chamber. That is, in a second plasma state "A.sub.1", a remove of the first mixed gas (NH.sub.3+N.sub.2+SiH.su- b.4) and an injection of the H.sub.2 gas are simultaneously carried out. At this time, there is little variation of the pressure, but the pressure may vary in a range of less than 200 mTorr.

[0036] At this point, in the second plasma state "A.sub.1", a hydrogen (H.sub.2) plasma treatment is performed by adjusting radio frequency energy within the chamber during a predetermined time period. The hydrogen plasma terminates the dangling bond that may occur on a surface of the gate insulating layer. In other words, the hydrogen plasma functions to etch defects that exist on the surface of the gate insulating layer.

[0037] Subsequently, in the hydrogen plasma state "A.sub.2", a SiH.sub.4 gas is injected into the process chamber to create a second mixed gas, so that an active layer is formed using the second mixed gas (H.sub.2+SiH.sub.4).

[0038] After forming the active layer, the SiH.sub.4 gas is removed from the second mixed gas, and the active layer is hydrogen plasma-treated in the third plasma state "A.sub.2".

[0039] Next, the SiH.sub.4 gas and a PH.sub.3 gas are added to the H.sub.2 gas to create a third mixed gas (SiH.sub.4+PH.sub.3+H.sub.2), and an ohmic contact layer (n.sup.+ a-Si:H) is formed on the active layer using the third mixed gas.

[0040] As described above, a method of forming the thin films according to the preferred embodiment of the present invention does not turn off a power while depositing the gate insulating layer, the active layer and the ohmic contact layer, whereby defects due to a lattice mismatch can be prevented. As a result, since defects on the interface of each of the thin films are decreased, charges that are trapped due to defects are decreased, and therefore trapped charges do not prevent a flow of the charges. This leads to high electrical characteristics of the TFT.

[0041] FIG. 6 is a graph illustrating a variation of an internal pressure of the process chamber during a deposition process of the thin films. As shown in FIG. 6, there is little variation of the internal pressure during a deposition process of the thin films (the gate insulating layer, the active layer and the ohmic contact layer). Therefore, defects that may occur on a surface of the thin films due to a variation of the internal pressure can be prevented.

[0042] A method of forming other components such as a gate electrode, a source electrode and a drain electrode shown in FIG. 2 is same as the conventional art and thus its explanation is omitted.

[0043] As described herein before, the method of manufacturing the TFT according to the preferred embodiment of the present invention has the following advantages. Firstly, since each of the thin films is deposited in the plasma state, variation of an internal atmosphere of the process chamber is minimized, whereupon a processing time becomes shorten. Secondly, since the thin films deposited are hydrogen plasma-treated, the hydrogen plasma etches detects on the interface between the thin films, whereupon defects can be prevented. Thirdly, since each of the thin films is deposited under the same or similar pressure, an occurrence of a polymer in the process chamber can be prevented, and interface characteristics of the thin films can be improved.

[0044] While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

What is claimed is:

1. A method of manufacturing a thin film transistor, comprising: preparing a process chamber having a stage; providing a substrate on the stage of the process chamber; injecting a first mixed gas of NH.sub.3, N.sub.2 and SiH.sub.4 into the process chamber; forming a silicon nitride film (SiNx) on the substrate using the first mixed gas by creating a plasma in the process chamber; injecting a second mixed gas of H.sub.2 and SiH.sub.4 into the process chamber while removing the first mixed gas in the plasma state; forming a pure amorphous silicon film (a-Si:H) on the silicon nitride film using the second mixed gas; injecting a third mixed gas of H.sub.2, SiH.sub.4 and PH.sub.3 into the process chamber while removing the second mixed gas in the plasma state; and forming a doped amorphous silicon film (n.sup.+ a-Si:H) on the silicon nitride film using the second mixed gas.

2. The method of claim 1, further comprising, forming a gate electrode before the step of forming the silicon nitride film; and forming source and drain electrodes on the doped amorphous silicon film.

3. The method of claim 1, further comprising, performing a hydrogen plasma treatment on an interface of the silicon nitride film before the step of forming the pure amorphous silicon film.

4. The method of claim 1, further comprising, performing a hydrogen plasma treatment on an interface of the pure amorphous silicon film before the step of forming the doped amorphous silicon film.