U.S. patent application number 09/203295 was filed with the patent office on 2001-08-09 for system and method for detecting defects within an electrical circuit by analyzing quiescent current.
This patent application is currently assigned to AGILENT TECHNOLOGIES. Invention is credited to JOHANSEN, VICTOR, MAXWELL, PETER, O'NEILL, PETER M..
Application Number | 20010011903 09/203295 |
Document ID | / |
Family ID | 22753355 |
Filed Date | 2001-08-09 |
United States Patent
Application |
20010011903 |
Kind Code |
A1 |
O'NEILL, PETER M. ; et
al. |
August 9, 2001 |
SYSTEM AND METHOD FOR DETECTING DEFECTS WITHIN AN ELECTRICAL
CIRCUIT BY ANALYZING QUIESCENT CURRENT
Abstract
The present invention, in general, provides for a testing system
and method for detecting defects within a circuit. A current
signature of the quiescent current of the circuit is determined,
and certain constant values are calculated based on the current
signature using a linear iterative regression. A defect free state
for the circuit associated with a minimum quiescent current
(I.sub.DDQ) is then determined. The I.sub.DDQ of the circuit for
this state is measured, and a signal indicating the I.sub.DDQ at
this state is used along with the aforementioned constant values to
create upper and lower threshold values. Thereafter, signals
indicating the value of I.sub.DDQ for a plurality of other states
are compared to the upper and lower threshold values. The circuit
is determined to be defective if the values of any of the signals
is greater than the upper threshold value or is less than the lower
threshold value.
Inventors: |
O'NEILL, PETER M.; (FT
COLLINS, CO) ; JOHANSEN, VICTOR; (SANTA CLARA,
CA) ; MAXWELL, PETER; (SUNNYVALE, CA) |
Correspondence
Address: |
AGILENT TECHNOLOGIES, INC.
INTELLECTUAL PROPERTY ADMINISTRATION, LEGAL DEPT.
P.O. BOX 7599
M/S DL429
LOVELAND
CO
80537-0599
US
|
Assignee: |
AGILENT TECHNOLOGIES
|
Family ID: |
22753355 |
Appl. No.: |
09/203295 |
Filed: |
December 1, 1998 |
Current U.S.
Class: |
324/762.02 |
Current CPC
Class: |
G06F 2201/81 20130101;
G01R 31/3004 20130101; G01R 31/3008 20130101 |
Class at
Publication: |
324/763 |
International
Class: |
G01R 031/02 |
Claims
Now, therefore, the following is claimed:
1. A system for detecting defects within circuits, the system
comprising: a circuit; a power supply unit, said power supply unit
configured to transmit supply current to said circuit; a current
meter configured to receive said supply current and to transmit a
first signal and a second signal respectively indicating a first
value and a second value of said supply current; and an analyzer
configured to receive said first and second signals, to determine a
threshold value based on said first signal, to compare said second
signal to said threshold value, and to determine whether said
circuit is defective based on a comparison of said second signal to
said threshold value.
2. The system of claim 1, wherein said threshold value is unique to
said circuit.
3. The system of claim 1, wherein said analyzer is further
configured to detect a defect in said circuit when said second
signal is greater than said threshold value, to determine a lower
threshold value based on said first signal, to compare said second
signal to said lower threshold value, and to determine that said
circuit is defective when said second signal is less than said
lower threshold value.
4. The system of claim 1, wherein said analyzer is further
configured to detect a defect in said circuit when said second
signal is less than said threshold value, to determine an upper
threshold value based on said first signal, to compare said second
signal to said upper threshold value, and to determine that said
circuit is defective when said second signal is greater than said
upper threshold value.
5. The system of claim 1, wherein said first signal indicates a
minimum value of said supply current when said circuit is in defect
free states.
6. The system of claim 5, wherein said analyzer is further
configured to determine, based on said first signal, a signal value
indicating a maximum value of said supply current when said circuit
is in said defect free states.
7. A method for detecting defects within circuits, the method
comprising the steps of: providing a circuit; measuring a value of
a supply current associated with said circuit when said circuit is
in a first state; determining a threshold value based on said value
of said supply current measured in said measuring step; receiving a
signal indicating another value of said supply current when said
circuit is in a second state; comparing said signal to said
threshold value; and detecting a defect in said circuit based on
said comparing step.
8. The method of claim 7, further comprising the steps of:
determining a second threshold value based on said value of said
supply current measured in said measuring step; and comparing said
signal to said second threshold value.
9. The method of claim 7, further comprising the step of refraining
from determining a value of said signal.
10. The method of claim 7, further comprising the steps of:
receiving signals indicating values of said supply current when
said circuit is in a plurality of states; analyzing values of said
received signals; determining which of said values analyzed in said
analyzing step is a minimum value; and selecting said first state
in response to a determination that said first state is associated
with said minimum value.
11. The method of claim 7, further comprising the steps of:
providing a plurality of circuits; receiving signals indicating
values of supply currents associated with said plurality of
circuits for a plurality of states; selecting ones of said received
signals; determining constant values based on values of said
selected ones; and utilizing said constant values to determine said
threshold value in said determining step.
12. The method of claim 7, further comprising the steps of:
receiving signals indicating values of supply currents for a
plurality of circuits at a plurality of states; selecting a
respective first signal and a respective second signal for each of
said circuits; and determining said threshold value based on values
of said signals selected in said selecting step.
13. The method of claim 11, further comprising the steps of:
determining a new respective threshold value for each of said
plurality of circuits; and utilizing said constant values to
determine said new respective threshold values.
14. The method of claim 11, further comprising the step of:
removing outliers of said values of said selected ones via
regression techniques.
15. The method of claim 11, further comprising the steps of:
plotting said values of said selected ones; and fitting a curve to
said values plotted in said plotting step.
16. The method of claim 12, wherein said first signal is associated
with a maximum supply current value for a respective one of said
circuits and said second signal is associated with a minimum supply
current value for said respective one of said circuits.
17. The method of claim 12, further comprising the steps of:
plotting a value of said first respective signal versus a value of
said second respective signal for each of said circuits in a graph;
performing a regression of said graph; and removing outliers from
said graph.
18. A method for detecting defects within circuits, the method
comprising the steps of: providing a plurality of circuits;
producing signals indicating values of supply currents associated
with said circuits; analyzing values of said signals; determining a
constant value based on said analyzing step; selecting a circuit;
placing said circuit into a first state subsequent to said
determining step; producing a first signal indicating a first value
of a supply current of said circuit when said circuit is in said
first state; determining a threshold value based on said constant
value and said first signal; placing said first circuit into
another state; producing a second signal indicating a second value
of said supply current when said circuit is in said other state;
and determining whether a value of said second signal exceeds said
first threshold value.
19. The method of claim 18, further comprising the steps of:
determining a second threshold value for said circuit based on said
first signal; and determining whether said value of said second
signal exceeds said second threshold value.
20. The method of claim 18, further comprising the steps of:
selecting a first respective value and a second respective value of
said signals analyzed in said analyzing step for each of said
plurality of circuits; plotting said first respective value versus
said second respective value; and performing a regression of said
values plotted in said plotting step.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention generally relates to quiescent current
testing and, more particularly, to a system and method for
detecting defects within a complementary metal oxide silicon (CMOS)
circuit by measuring and characterizing the power supply current
conducted by the circuit in multiple quiescent states.
[0003] 2. Related Art
[0004] An ideal complementary metal oxide silicon (CMOS) integrated
circuit conducts a negligible amount of current when the circuit is
in standby or a quiescent state. Therefore, when a CMOS circuit is
not switching states, only a small amount of quiescent current
should be conducted by the circuit. The quiescent current, commonly
referred to as "I.sub.DDQ," is composed primarily of leakage
current. A defective circuit may draw a significantly larger amount
of quiescent current than a non-defective circuit.
[0005] Typical I.sub.DDQ testing includes setting a threshold value
of I.sub.DDQ in which the circuit being tested is failed if the
I.sub.DDQ conducted by the circuit exceeds the threshold value. In
this regard, input vectors drive the circuit's nodes to
predetermined states, and the I.sub.DDQ is measured while the
circuit's nodes are held in the predetermined states. I.sub.DDQ
testing may be done at a single state or it may include stepping
through many different input test vectors to test various states.
The test vectors can be generated by automatic test pattern
generation (ATPG) software tools or by integrated circuit
designers.
[0006] One of the difficulties of I.sub.DDQ testing is setting the
threshold value. A circuit that draws more current than the
threshold value of I.sub.DDQ for any input test vector is declared
defective. A circuit that draws less current than the threshold
value of I.sub.DDQ is considered non-defective. If the threshold
value is set too high, then circuits that contain defects may be
considered non-defective. If the threshold value is too low, then
circuits that are free of defects may fail the I.sub.DDQ test. This
increases the cost of the circuits considered non-defective.
Therefore, the determination of the threshold value for I.sub.DDQ
testing usually involves a tradeoff between the quality and the
cost of the circuits which pass I.sub.DDQ testing.
[0007] As the scale of CMOS circuits is increasingly reduced to
increase speed and density and to decrease cost, the background
current drawn by the CMOS circuits is increased. As known in the
art, I.sub.DDQ consists of two components (1) defect current, which
is the current drawn by a circuit due to defects within the circuit
and (2) background current, which is I.sub.DDQ minus the defect
current. The scale of CMOS circuitry has reached levels where the
magnitude of the background current is comparable to or even
exceeds the defect current. Therefore, it has become more difficult
to determine whether a variation in I.sub.DDQ is due to a variation
in background current or is due to a defect, thereby frustrating
the process of identifying which circuits are defective.
[0008] Process variations of the fabrication of electrical circuits
further complicate the determination of the I.sub.DDQ threshold
value. Process variations are differences that exist between
individual circuits of the same circuit design. Process variations
can affect the quiescent current drawn by the circuits. For
example, two integrated circuits of the same design can draw
different I.sub.DDQ values for the same set of input test vectors
due to process variations between the two circuits.
[0009] Gattiker and Maly (A. E. Gattiker and W. Maly, "Current
Signatures", Proc. VLSI Test Symposium, pp. 112-117, 1996) have
proposed a method which eliminates some of the threshold selection
problems. Traditionally, testing of a circuit ends as soon as the
circuit fails the I.sub.DDQ test. Gattiker and Maly propose that
I.sub.DDQ values be measured for a complete set of input test
vectors. A complete set of input test vectors include enough test
vectors to completely exercise the functionality of the circuitry
within the circuit being tested. From the measured values of
I.sub.DDQ, a current signature is generated. The current signature
includes an ordering of the I.sub.DDQ measurements from the
smallest value to the largest value. Gattiker and Maly claim that
the magnitude of the measurements is not as important as the shape
of a plot of the current signature. If there are no large jumps in
the plot of the current signature, then the circuit is designated
as non-defective. If the plot of the current signature includes any
significant jumps or discontinuities, then the circuit is
designated as defective.
[0010] The I.sub.DDQ signature concepts proposed by Gattiker and
Maly represent important findings in I.sub.DDQ testing analysis.
However, these concepts cannot be directly implemented into
present-day integrated circuit manufacturing environments. Testing
methods using the Gattiker and Maly I.sub.DDQ signature concepts
require a complete set of input vector test settings to be applied
to the integrated circuit under test and the resultant measured
values of I.sub.DDQ for each input vector setting to be analyzed.
Determination of the values of I.sub.DDQ for a complete set of
input vector settings takes too long to implement in circuit
manufacturing environment at a reasonable cost.
[0011] It is desirable to provide a system and method for I.sub.DDQ
testing which overcomes the limitations of present I.sub.DDQ
testing methods using a single threshold test. Furthermore, it is
desirable that the method of I.sub.DDQ testing be easily
implemented into existing circuit manufacturing environments by not
requiring excessive storage and analysis of measured values of
I.sub.DDQ.
SUMMARY OF THE INVENTION
[0012] The present invention overcomes the inadequacies and
deficiencies of the prior art as discussed herein. The present
invention provides a system and method for detecting defects in
electrical circuits by analyzing quiescent current.
[0013] In general, the present invention utilizes a circuit, a
power supply unit, a current meter, and a analyzer. The power
supply unit is connected to the circuit and transmits supply
current to the circuit. The current meter measures the supply
current and transmits a first signal and a second signal
respectively indicating a first value and a second value of the
supply current. The analyzer receives the first parameter and
determines a threshold value based on the first parameter value.
The analyzer then receives the second signal and compares the
second signal to the threshold value. The analyzer determines
whether a defect is detected based on the comparison of the second
signal to the threshold value.
[0014] In accordance with another feature of the present invention,
the analyzer also determines a second threshold value based on the
first signal. The analyzer can then determine whether a defect is
detected by comparing the second signal to the second threshold
value.
[0015] In accordance with another feature of the present invention,
the analyzer calculates the threshold values based on predetermined
constants. To determine the predetermined constants, the values of
signals indicating the supply current values for a plurality of
states and a plurality of circuits are measured. Then, selected
values of the signals are then plotted to create a current
signature of the circuits. A regression is then used to remove
outliers from the plot and to fit a curve or line to the plotted
points. The predetermined constants are then determined from the
fitted curve or line, and the predetermined constants are used by
the analyzer to determine the threshold values for each of the
circuits tested.
[0016] The present invention can also be viewed as providing a
method for detecting defects within circuits. Briefly described,
the method can be broadly conceptualized by the following steps:
providing a circuit; measuring a value of a supply current
associated with the circuit when the circuit is in a first state;
determining a threshold value based on the value of the supply
current measured in the measuring step; receiving a signal
indicating another value of the supply current when the circuit is
in a second state; comparing the signal to the threshold value; and
detecting a defect in the circuit based on the comparing step.
[0017] The present invention has many advantages, a few of which
are delineated hereafter, as mere examples.
[0018] An advantage of the present invention is that defects in
circuits can be detected by comparing the quiescent current
associated with circuit to threshold values. These comparisons can
be achieved without determining the value of the quiescent current,
thereby making the comparisons relatively fast.
[0019] Another advantage of the present invention is that the cost
associated with quiescent current testing can be significantly
reduced.
[0020] Another advantage of the present invention is that quiescent
current testing can be achieved by comparing the quiescent current
of a circuit to thresholds that are uniquely calculated for each
circuit. Therefore, the effects of fluctuations in background
current are reduced.
[0021] Other features and advantages of the present invention will
become apparent to one skilled in the art upon examination of the
following detailed description, when read in conjunction with the
accompanying drawings. It is intended that all such features and
advantages be included herein within the scope of the present
invention, as is defined by the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The invention can be better understood with reference to the
following drawings. The elements of the drawings are not
necessarily to scale relative to each other, emphasis instead being
placed upon clearly illustrating the principles of the invention.
Furthermore, like reference numerals designate corresponding parts
throughout the several views.
[0023] FIG. 1 depicts a block diagram illustrating a testing system
in accordance with the present invention.
[0024] FIG. 2 depicts a block diagram illustrating a computer
system employing the analyzer of FIG. 1.
[0025] FIGS. 3A and 3B depict a flow chart illustrating the
architecture, functionality, and operation of the testing system of
FIG. 1.
[0026] FIG. 4 depicts a graph of the test signal value versus state
for a circuit being tested by the testing system of FIG. 1.
[0027] FIG. 5 depicts a graph of the maximum test signal value
versus the minimum test signal value for each circuit being
measured to derive the outlier margin value and the values of m and
b.
[0028] FIG. 6 depicts the graph of FIG. 5 after linear
regression.
DETAILED DESCRIPTION OF THE INVENTION
[0029] In general, the present invention provides a testing system
and method for detecting defects within an electrical circuit. In
this regard, upper and lower threshold values for the quiescent
current (I.sub.DDQ) of the circuit are determined, and a signal
indicating the I.sub.DDQ value for the circuit at a plurality of
states is compared to the upper and lower threshold values. A
defect is detected when the signal corresponds to a value greater
than the upper threshold value or less than the lower threshold
value.
[0030] FIG. 1 depicts a testing system 10 in accordance with the
preferred embodiment of the present invention. The system 10
includes a circuit 14, such as a complementary metal oxide silicon
(CMOS) integrated circuit, that is to be tested for defects. The
state of the circuit 14 is controlled by a state generator 15,
which transmits input signals via connections 16 to the circuit 14.
As known in the art, the values of the input signals can be
adjusted to transition the circuit 14 into different states. The
number of connections 16 may vary depending on the number of states
that are to be tested.
[0031] A power supply unit 17 is designed to transmit supply
current to a current meter 18 via connection 19. The current meter
18 is designed to pass the supply current to circuit 14 via
connection 21 and to provide a test signal to an analyzer 22 via
connection 25. The current meter 18 may be included in the power
supply unit 17 or may be in a stand alone configuration. The test
signal transmitted to the analyzer 22 by the current meter 18
indicates the value of I.sub.DDQ (which is the supply current being
provided to the circuit 14 via connection 25 when the circuit 14 is
in a quiescent state). For example, in the preferred embodiment,
the current meter 18 is designed to produce a voltage signal on
connection 25 proportional to the supply current being transmitted
to the circuit 14 via connections 19 and 21. However, the test
signal may be other types of signals as long as it indicates the
value of I.sub.DDQ. For example, it is possible for the test signal
to be a current signal with a current value matching or
corresponding with the current value of I.sub.DDQ. It is also
possible for the test signal to be a digital signal having a
digital value corresponding with the current value of
I.sub.DDQ.
[0032] The analyzer 22 is designed to receive the test signal and
to detect defects in the circuit 14 based on the test signal. The
analyzer 22 can be implemented in software, hardware, or a
combination thereof. In the preferred embodiment, as illustrated by
way of example in FIG. 2, the analyzer 22 is implemented in
software and stored in memory 30 of a computer system 31.
[0033] Note that the analyzer 22 can be stored and transported on
any computer-readable medium for use by or in connection with an
instruction execution system, apparatus, or device, such as a
computer-based system, processor-containing system, or other system
that can fetch the instructions from the instruction execution
system, apparatus, or device and execute the instructions. In the
context of this document, a "computer-readable medium" can be any
means that can contain, store, communicate, propagate, or transport
the program for use by or in connection with the instruction
execution system, apparatus, or device. The computer readable
medium can be, for example but not limited to, an electronic,
magnetic, optical, electromagnetic, infrared, or semiconductor
system, apparatus, device, or propagation medium. More specific
examples (a non-exhaustive list) of the computer-readable medium
would include the following: an electrical connection (electronic)
having one or more wires, a portable computer diskette (magnetic),
a random access memory (RAM) (magnetic), a read-only memory (ROM)
(magnetic), an erasable programmable read-only memory (EPROM or
Flash memory) (magnetic), an optical fiber (optical), and a
portable compact disc read-only memory (CDROM) (optical). Note that
the computer-readable medium could even be paper or another
suitable medium upon which the program is printed, as the program
can be electronically captured, via for instance optical scanning
of the paper or other medium, then compiled, interpreted or
otherwise processed in a suitable manner if necessary, and then
stored in a computer memory. As an example, the analyzer 22 may be
magnetically stored and transported on a conventional portable
computer diskette.
[0034] The preferred embodiment of the computer system 31 of FIG. 2
comprises one or more conventional processing elements 32, such as
a digital signal processor (DSP), that communicate to and drive the
other elements within the computer system 31 via a local interface
33, which can include one or more buses. Furthermore, an input
device 34, for example, a keyboard or a mouse, can be used to input
data from a user of the computer system 31, and screen display 35
or a printer 36 can be used to output data to the user. A disk
storage mechanism 37 can be connected to the local interface 33 to
transfer data to and from a nonvolatile disk (e.g., magnetic,
optical, etc.). Furthermore, an test signal interface 39 receives
the test signal from connection 25 (FIG. 1) and interfaces the test
signal with the local interface 33. It should be noted that input
device 34, display 35, printer 36, and disk 37 are optional and are
not a part of the preferred embodiment, although other embodiments
may include these features.
[0035] The analyzer 22, which will be discussed in further detail
hereinafter, is configured to calculate or otherwise determine
upper and lower threshold values for the test signal. The analyzer
22 is then designed to compare the test signal to the upper and
lower threshold values and to determine that the circuit 22 is
defective when the test signal is greater than the upper threshold
value or is less than the lower threshold value.
[0036] The analyzer 22 preferably utilizes a predetermined formula
to calculate the upper and lower threshold values. In the preferred
embodiment, this predetermined formula is modeled from the equation
of a line. In this regard, the formula used by the analyzer 22
is:
I.sub.DDQ,max=m.times.I.sub.DDQ,min+b Equation (1)
[0037] where I.sub.DDQ,max is the maximum measured test signal
value for the circuit 14 in a defect free state, I.sub.DDQ,min is
the minimum measured test signal value for the circuit 14 in a
defect free state, m is a predetermined constant, and b is a
predetermined constant. These values are predetermined in that they
are determined before the first circuit 14 is tested. Determination
of these values will be discussed in further detail hereinafter in
the Operation section.
[0038] The upper threshold value is preferably defined as the value
of I.sub.DDQ,max plus an outlier margin value, and the lower
threshold value is preferably defined as I.sub.DDQ,min minus the
outlier margin value. The addition and subtraction of the outlier
margin value in calculating the threshold values allows small
variations in I.sub.DDQ to exist without incorrectly declaring the
circuit 14 as defective when the small variations do not result
from a defect. In other words, the addition and subtraction of the
outlier margin value allows for small variations to occur which are
attributable to measurement inaccuracies and/or process variations
instead of circuit defects. The outlier margin value in the
preferred embodiment is three times the standard of deviation of
the residuals of the regression, although the outlier margin value
can be set to other values. Calculation of the outlier margin value
and performance of the regression will be discussed in further
detail hereinafter.
[0039] Once I.sub.DDQ,max, I.sub.DDQ,min, and the outlier margin
value have been determined, the analyzer 22 is configured to
calculate the upper and lower threshold values. The analyzer 22 is
designed to then compare the upper and lower threshold values to
the test signal transmitted on connection 25 to detect defects
within the circuit 14.
Operation
[0040] The preferred use and operation of the testing system 10 and
associated methodology are described hereafter.
[0041] Before the circuit 14 is tested, the behavior of the circuit
14 is modeled to determine the outlier margin value and the values
of m and b of Equation (1). In this regard, the test signal value
of a plurality of circuits 14 (each circuit 14 having the same
design) is measured at a plurality of states for each circuit 14,
as shown by blocks 52 and 55 of FIG. 3A. FIG. 4 depicts the current
signature for one of the circuits 14. Generally, the current
signature is the shape of the curve representing the current versus
state of a circuit 14 or is any set of parameters that represent
the shape of the curve. Measuring and plotting in FIG. 4 test
signals from a plurality of circuits 14 characterizes the behavior
of I.sub.DDQ over a range of manufacturing (i.e., process)
variation. The number of states measured for each circuit 14 can
vary.
[0042] The maximum test signal value measured for each circuit 14
at any one of the measured states is preferably plotted versus the
minimum test signal value measured for each circuit 14 at any one
of the measured states, as shown by FIG. 5 and blocks 57 and 61 of
FIG. 3A. In other words, each dot of FIG. 5 represents the maximum
test signal value measured at any state for a single circuit 14
versus the minimum test signal value measured at any state for the
single circuit 14. For example, using the data shown in FIG. 4, the
value of the test signal at state 9 versus the value of the test
signal at state 14 would comprise one dot in FIG. 5.
[0043] The graph of FIG. 5 is preferably used to determine the
outlier margin value in block 64. The outlier margin value is
preferably three times the standard deviation of the regression
residuals of the points plotted in FIG. 5. The standard deviation
can be calculated through techniques well known in the art. In the
preferred embodiment, the standard deviation is calculated by
performing an iterative linear regression (removing outliers at
each iteration), although non-linear regression may also be used.
As known in the art, an outlier is defined as points outside of the
distribution of a population. The iterations of the regression
terminate or stop when all remaining residuals are determined to be
from a single population. Such regression techniques are well known
in the art.
[0044] For illustrative purposes, assume that points 41 of FIG. 5
are determined to be outliers because of their respective position
from the other points in the graph. It is likely that points 41 are
located significantly far from the line established by the majority
of the points on the graph due to defects and/or errors in
measurement of the I.sub.DDQ values drawn by the circuits 14
associated with the points 41. Points 41 are identified as outliers
and are, therefore, removed during the regression such that the
graph of FIG. 6 is produced. Once all of the outliers have been
removed and the linear regression is complete, the values of m and
b that best represent the circuit's defect free behavior can be
determined. In this regard, m is the slope (i.e.,
.DELTA.Y/.DELTA.X) of the fitted line, and b is the y-intercept of
the fitted line. It should be noted that other techniques may be
utilized for removing outliers and for fitting a curve or line to
the sample points of FIG. 6.
[0045] After calculating the outlier margin value and the values of
m and b, these values are stored in memory 30 of the computer
system 31 (FIG. 2). Then, the inputs to the circuit 14 shown in
FIG. 1 are set by the state generator 16 to put the circuit 14 into
a minimum I.sub.DDQ state. The minimum I.sub.DDQ state is selected
at block 67 of FIG. 3A and is the state where the plurality of
circuits 14 measured to derive FIG. 6 draw the smallest I.sub.DDQ
value, as determined at block 69. The smallest I.sub.DDQ value may
change from circuit 14 to circuit 14, but the state at which the
smallest I.sub.DDQ values occur should be constant. This state is
the minimum I.sub.DDQ state. For example, in FIG. 4, the minimum
I.sub.DDQ state is state 14 since state 14 corresponds with the
lowest measured value of I.sub.DDQ.
[0046] It should be noted that due to process variations and/or
other factors, it is possible that the same state for each circuit
14 does not produce a minimum I.sub.DDQ for the circuit 14. It is
sufficient for the purposes of the present invention that only a
significant number of circuits 14 produce a minimum I.sub.DDQ at
the state selected as the minimum I.sub.DDQ state. Furthermore, it
is possible that multiple states may produce the minimum I.sub.DDQ
value. In this situation, any one of the states producing the
minimum I.sub.DDQ value or a value close to the minimum I.sub.DDQ
value may be selected as the I.sub.DDQ minimum state.
[0047] When a particular circuit 14 is to be tested, the state
generator 15 produces values on connections 16 that place the
circuit in the minimum I.sub.DDQ state. The analyzer 22 then reads
the test signal on connection 25 and determines the value of the
test signal at the minimum I.sub.DDQ state, as shown by blocks 72
and 75 of FIG. 3B. This value of the test signal is I.sub.DDQ,min
of Equation (1). Then, the analyzer 22 calculates the upper and
lower threshold values for the circuit 14 at block 77. In this
regard, the analyzer 22 subtracts the outlier margin value from
I.sub.DDQ,min to determine the lower threshold. The analyzer 22
then determines I.sub.DDQ,max via Equation (1) where I.sub.DDQ,min,
b and m are now known values. The analyzer 22 adds the outlier
margin value to I.sub.DDQ,max to determine the upper threshold.
[0048] The state of the circuit 14 is then changed in block 81 of
FIG. 3B via the inputs from signal generator 15 to any desirable
testing state. The analyzer 22 compares the test signal currently
generated by the current meter 18 to the upper and lower threshold
values, as shown by blocks 83 and 85. The analyzer 22 detects a
defect at block 88 if the test signal is greater than the upper
threshold value or if the test signal is less than the lower
threshold value. No defect is detected if the test signal is less
than the upper threshold value and greater than the lower threshold
value. If a defect is detected, then the analyzer 22 preferably
indicates via display 35 or printer 36 (FIG. 2) that a defect has
been discovered, as shown by block 91 of FIG. 3B. Furthermore,
pursuant to conventional manufacturing techniques, the defective
circuit is preferably marked as defective or separated from the
other circuits that have not been determined to be defective.
[0049] It should be noted that many hardware comparators exist in
the art for determining whether one signal is greater than another
signal. If desired, the analyzer 22 may include or employ such a
comparator to determine whether the test signal exceeds the
threshold values. In this regard, the analyzer 22 preferably
transmits an analog signal to the comparator. The analog signal
preferably has a voltage or current value proportional to the value
of one of the threshold values. The comparator, through techniques
known in the art, can then determine whether the signal
corresponding with the threshold value is greater than the test
signal without knowing or discovering the actual values of either
the test signal or the threshold value. It should be noted,
however, that it is also possible to perform the comparisons in
software or a combination of hardware and software.
[0050] After determining whether a defect is detected at the
current state, the state of the circuit 14 is changed by the state
generator 15, and the test signal at this new state is again tested
for defects. As shown by block 94 of FIG. 3B, this process is
continued until a desired number of states have been tested or
until a defect is detected. If no defects have been detected at any
of the states, then the analyzer 22 determines that the circuit is
non-defective. However, if a defect is detected at any of the
states (or, in the alternative, if a defect is detected at a
predetermined number of states), then the analyzer 22 determines
that the circuit 14 is defective.
[0051] Note that the value of the test signal does not actually
have to be determined in comparing the test signal to the upper and
lower threshold values. Only a determination as to whether the test
signal is greater than or less than the threshold values needs to
be made. Making such a determination is much faster than
determining the value of the test signal. Therefore, a large number
of states can be tested by the analyzer 22 in a relatively short
time, thereby making I.sub.DDQ testing for a large number of states
feasible.
[0052] After the circuit 14 has been tested by the analyzer 22, the
circuit 14 is then replaced by a new circuit 14, as shown by blocks
97 and 72 of FIG. 3B. The new circuit 14 is then tested according
to the techniques described hereinabove. As long as the new circuit
14 has the same design as the original circuit 14, the same values
of the outlier margin value and of m and b can be used in testing
the new circuit 14. However, new values of I.sub.DDQ,min and
I.sub.DDQ,max should be calculated based on the value of the test
signal for the new circuit 14 at the minimum I.sub.DDQ state.
Therefore, new threshold values for the new circuit 14 should also
be calculated based on the new values of I.sub.DDQ,min and
I.sub.DDQ,max, as shown by blocks 72, 75, and 77 of FIG. 3B.
[0053] It should be noted that the present invention assumes that
each of the circuits 14 described hereinabove have the same design.
In this regard, the values calculated for the outlier margin value
and the values of m and b are unique to a specific circuit design.
In deriving these values, only circuits 14 of the same design
should be used.
[0054] It should also be noted that since a defect tends to
increase I.sub.DDQ, it may be possible to adequately test circuit
14 by comparing the test signal value to the upper threshold value
only. However, when computing the upper threshold value, the
present invention assumes that no defects exist at the minimum
I.sub.DDQ state and if there is a defect at this state, it is
possible that the defect will not be detected when only the upper
threshold value is compared to the test signal. However, the defect
at the minimum I.sub.DDQ state can be detected if the test signal
is compared to the lower threshold value, as described hereinabove.
Therefore, although it is possible to only compare the test signal
value to either of the threshold values, it is preferable to
compare the test signal value to both the upper and lower threshold
values so that the probability of detecting a defect is
maximized.
[0055] In addition, it is well known that most circuits 14 have an
absolute maximum value for I.sub.DDQ that is established by the
circuit's design and specifications of the process in which it is
manufactured. Therefore, the calculated maximum threshold value
should not correspond with an I.sub.DDQ value that exceeds the
absolute maximum value for the circuit 14. If the calculated
maximum threshold value corresponds to an I.sub.DDQ value that
exceeds the absolute maximum value for the circuit 14, then a
threshold value corresponding to the absolute maximum value for the
circuit 14 should be used as the calculated maximum threshold
value. Furthermore, current meters 18 can only provide accurate
measurements at an absolute minimum I.sub.DDQ value or greater due
to noise and other measurement inaccuracies. Therefore, the
calculated minimum threshold value should not correspond to an
I.sub.DDQ value that is less than this absolute minimum value. If
the calculated minimum threshold value corresponds to an I.sub.DDQ
value that is less than the absolute maximum value for the circuit
14, then a threshold value corresponding to the absolute minimum
value for the circuit 14 should be used as the calculated minimum
threshold value.
[0056] Finally, it should be noted that either the current being
provided to the circuit 14 by the power supply unit 17 or the
current being returned to the power supply unit 17 from the circuit
14 while the circuit 14 is in a quiescent state may be utilized to
determine the test signal. As known in the art, a circuit must be
complete before current can flow. Therefore, if the power supply
unit 17 is providing current to circuit 14 via connections 19 and
21, there must be another connection 99 allowing current to flow
into the power supply unit 17. Connection 99 is often referred to
as the "ground" connection. Both the current flowing out of the
power supply unit 17 via connection 19 and the current flowing into
the power supply unit 17 via connection 99 indicates the value of
the supply current being provided to the circuit 14, and the
current flowing on either of the connections 19 and 99 may be used
to define the test signal. Therefore, although FIG. 1 shows the
current meter 18 connected between connections 19 and 21, it could
be inserted into connection 99 instead.
[0057] In concluding the detailed description, it should be noted
that it will be obvious to those skilled in the art that many
variations and modifications may be made to the preferred
embodiment without substantially departing from the principles of
the present invention. All such variations and modifications are
intended to be included herein within the scope of the present
invention, as set forth in the following claims.
* * * * *