U.S. patent application number 08/870654 was filed with the patent office on 2001-08-09 for semiconductor device with flip-chip structure and method of manufacturing the same.
This patent application is currently assigned to KABUSHIKI KAISHA TOSHIBA. Invention is credited to YOSHIDA, AKITO.
Application Number | 20010011771 08/870654 |
Document ID | / |
Family ID | 15927419 |
Filed Date | 2001-08-09 |
United States Patent
Application |
20010011771 |
Kind Code |
A1 |
YOSHIDA, AKITO |
August 9, 2001 |
SEMICONDUCTOR DEVICE WITH FLIP-CHIP STRUCTURE AND METHOD OF
MANUFACTURING THE SAME
Abstract
A semiconductor device has a plurality of input/output terminals
formed on the inner region on a semiconductor substrate, and a
plurality of die testing terminals formed on the peripheral region
on the semiconductor substrate, and the input/output terminals and
the die testing terminals are connected to each other by a metal
wiring layer. Die testing is performed by bringing probes
projecting from a probe card into contact with the plurality of die
testing terminals.
Inventors: |
YOSHIDA, AKITO;
(KANAGAWA-KEN, JP) |
Correspondence
Address: |
FINNEGAN HENDERSON FARABOW
GARRETT AND DUNNER
1300 I STREET NW
WASHINGTON
DC
200053315
|
Assignee: |
KABUSHIKI KAISHA TOSHIBA
|
Family ID: |
15927419 |
Appl. No.: |
08/870654 |
Filed: |
June 6, 1997 |
Current U.S.
Class: |
257/734 ;
257/691; 257/693; 257/786; 438/617 |
Current CPC
Class: |
H01L 2224/05164
20130101; H01L 2224/05124 20130101; H01L 2224/13024 20130101; Y10T
29/49004 20150115; H01L 24/02 20130101; H01L 2224/05666 20130101;
H01L 2924/0001 20130101; H01L 22/32 20130101; H01L 24/03 20130101;
H01L 24/05 20130101; H01L 24/11 20130101; H01L 2224/05155 20130101;
H01L 2224/02377 20130101; H01L 24/13 20130101; H01L 2924/14
20130101; H01L 2224/06131 20130101; H01L 2224/05166 20130101; H01L
2224/05569 20130101; H01L 2924/14 20130101; H01L 2924/00 20130101;
H01L 2224/05666 20130101; H01L 2924/00014 20130101; H01L 2224/05124
20130101; H01L 2924/00014 20130101; H01L 2224/05155 20130101; H01L
2924/00014 20130101; H01L 2224/05164 20130101; H01L 2924/00014
20130101; H01L 2224/05166 20130101; H01L 2924/00014 20130101; H01L
2224/05666 20130101; H01L 2924/01074 20130101; H01L 2924/013
20130101; H01L 2924/0001 20130101; H01L 2224/02 20130101 |
Class at
Publication: |
257/734 ;
257/691; 257/693; 257/786; 438/617 |
International
Class: |
H01L 023/48; H01L
023/52; H01L 029/40; H01L 021/44 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 12, 1996 |
JP |
8-171664 |
Claims
1. A semiconductor device comprising: a semiconductor substrate; an
input/output terminal portion formed on said semiconductor
substrate, said input/output terminal portion having a plurality of
input/output terminals formed on an inner region on said
semiconductor substrate, and a plurality of die testing terminals
formed on a peripheral region on said semiconductor substrate; and
a metal wiring layer for connecting said input/output terminals and
said die testing terminals.
2. A device according to claim 1, wherein input/output circuits are
arranged along sides of said semiconductor substrate on the
peripheral region of said semiconductor substrate, and said
plurality of die testing terminals are respectively arranged
between said input/output circuits and the sides of said
semiconductor substrate.
3. A device according to claim 1, wherein said plurality of
input/output terminals formed on the inner region on said
semiconductor substrate are arranged at substantially equal
intervals.
4. A device according to claim 1, wherein each of said plurality of
input/output terminals has a substantially square distal end, and a
central line parallel to two opposing sides of the distal end is
inclined at about 45.degree. with respect to an arbitrary side of
said semiconductor substrate.
5. A device according to claim 1, wherein a multilayered wiring
structure is formed on said semiconductor substrate, said metal
wiring layer for electrically connecting said input/output
terminals and said die testing terminals uses an arbitrary wiring
layer of said multilayered wiring structure, and said input/output
terminals and said die testing terminals use wiring layers above
the arbitrary wiring layer.
6. A device according to claim 1, wherein said input/output
terminal portion formed on said semiconductor substrate further has
a portion consisting of only input/output terminals excluding said
die testing terminals.
7. A device according to claim 1, wherein said die testing
terminals include a metal wiring layer coated with a conductive
anti-etching protection film.
8. A device according to claim 1, wherein each of said input/output
terminals is made up of an uppermost metal wiring layer of a
multilayered wiring structure on said semiconductor substrate, a
conductive anti-etching protection film that covers said metal
wiring layer, a barrier metal formed on said anti-etching
protection film, and a bump formed on said barrier metal.
9. A device according to claim 8, wherein said anti-etching
protection film has an anti-etching property higher than said
barrier metal with respect to an etchant that etches said barrier
metal.
10. A method of manufacturing a semiconductor device, comprising
the steps of: forming a multilayered wiring structure on a
semiconductor substrate; forming a plurality of pads by patterning
an uppermost metal wiring layer of said multilayered wiring
structure by lithography and etching; coating said uppermost metal
wiring layer with a protection insulating film while leaving
opening portions from which surfaces of said pads are exposed;
forming a conductive anti-etching protection film on the exposed
pads by lithography and etching; forming a barrier metal formation
metal film on said protection insulating film including said
anti-etching protection film; forming bumps on said pads on an
inner region on said semiconductor substrate via said anti-etching
protection film and said barrier metal formation metal film;
forming input/output terminals on the inner region on said
semiconductor substrate by forming barrier metals between said
bumps and said anti-etching protection film by patterning said
barrier metal formation metal film; and forming die testing
terminals by removing said barrier metal formation metal film after
the step of forming said barrier metal formation metal film on said
pads on an external region on said semiconductor substrate and said
anti-etching protection film.
11. A method of manufacturing a semiconductor device, comprising
the steps of: forming a multilayered wiring structure on a
semiconductor substrate; forming a conductive anti-etching
protection film on an uppermost metal layer of said multilayered
wiring structure; forming a plurality of pads coated with said
anti-etching protection film by simultaneously patterning said
metal wiring layer and said anti-etching protection film by
lithography and etching; coating said uppermost metal wiring layer
with a protection insulating film while leaving opening portions
from which the anti-etching protection film portions on said pads
are exposed; forming a barrier metal formation metal film on said
protection insulating film including said anti-etching protection
film; forming bumps on said pads on an inner region on said
semiconductor substrate via said anti-etching protection film and
said barrier metal formation metal film; forming input/output
terminals on the inner region on said semiconductor substrate by
forming barrier metals between said bumps and said anti-etching
protection film by patterning said barrier metal formation metal
film; and forming die testing terminals by removing said barrier
metal formation metal film after the step of forming said barrier
metal formation metal film on said pads on an external region on
said semiconductor substrate and said anti-etching protection film.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to a semiconductor device with
a flip-chip structure, in which semiconductor elements (chips) are
connected to a circuit board via protruding electrodes such as
solder bumps, and a method of manufacturing the same.
[0002] Conventionally, in order to mount semiconductor elements on
a circuit board, the following methods are used. That is, the
distal ends of a plurality of lead lines extending from each
semiconductor element (to be referred to as a chip hereinafter) are
electrically connected to a wiring or interconnect pattern on a
circuit board, or a chip is mounted on a circuit board and is
electrically connected thereto by wire bonding, TAB (Tape Automated
Bonding), or the like.
[0003] However, in the former method in which lead lines are
extended from the chip and are connected to the circuit board, the
interval between adjacent bumps is limited, thus posing a serious
bottleneck against realization of high packaging density of
semiconductor devices.
[0004] Especially, in recent years, semiconductor devices are used
in a variety of applications, and their packaging densities are
increasing. For example, a low-profile circuit board such as a
memory card is often used, and the number of memory elements to be
mounted is on the rise.
[0005] Under such circumstances, packaging chips using lead lines
has limitations.
[0006] In view of this problem, a flip-chip structure has received
a lot of attention. In this structure, bumps are attached to a
plurality of connection electrodes (pads) formed on a chip, and are
directly connected to the wiring pattern on the circuit board.
[0007] FIG. 1 is a sectional view of a conventional semiconductor
device in which a chip consisting of a silicon semiconductor is
mounted on a circuit board by flip-chip bonding. FIG. 2 is a plan
view showing the major surface of a semiconductor substrate, that
has bumps, and FIG. 3 is a sectional view showing the structure of
input/output terminals having bumps.
[0008] A semiconductor substrate 1 comprises pad electrodes 7 and
bumps 3. Each pad electrode 7 is used as a pad electrically
connected to an internal integrated circuit on the major surface of
the semiconductor substrate 1, and consists of, e.g., aluminum.
[0009] Each bump 3 is connected on the pad electrode 7, is made up
of a low-melting point metal solder bump containing lead (Pb), tin
(Sb), and the like as major components, and has a height of about
100 .mu.m.
[0010] Each input/output terminal 10 formed on the major surface of
the conventional semiconductor substrate 1 shown in FIG. 2
comprises a bump 3 and a pad electrode 7, as shown in FIG. 3 (to be
explained later) and a barrier metal 9 is normally interposed
between the bump 3 and the pad electrode 7.
[0011] At least one chip is mounted on a circuit board 2. A
plurality of bumps 3 on the semiconductor substrate 1 are
electrically connected to pad electrodes (to be referred to as
substrate pads hereinafter) 8 connected to a wiring pattern (not
shown) formed on the surface of the circuit board 2, thus mounting
the semiconductor substrate 1 on the circuit board 2.
[0012] Each bump 3 may use gold in addition to the low-melting
point metals, or may also use a structure prepared by forming a
conductive layer on the surface of a spherical insulating member.
As the low-melting metals, Pb--Sn solder, In--Sn solder, and the
like are known.
[0013] As the circuit board 2, a printed board prepared by stacking
glass base members impregnated with an epoxy resin, a ceramic
board, a silicon semiconductor board, and the like are used. Also,
an encapsulating resin may be filled between the semiconductor
substrate 1 and the circuit board 2.
[0014] The major surface of the semiconductor substrate 1 is
divided into an inner region 1a and a peripheral region 1b. On the
inner region 1a, an integrated circuit 20 as an internal circuit
formed inside the semiconductor substrate 1 is formed. An
input/output circuit 11 is formed on that region of the peripheral
region 1b, which is in the vicinity of the inner region 1a, and the
input/output terminals 10 are electrically connected to the
integrated circuit 20 via the input/output circuit 11.
[0015] The bump structure on the semiconductor substrate is as
shown in FIG. 3. That is, a pad 7 of, e.g., aluminum, which is
electrically connected to the integrated circuit formed inside the
semiconductor substrate, is formed on an insulating film 4 formed
on the surface of the semiconductor substrate 1. The surrounding
portion of the pad 7 is protected by an insulating film 5 of, e.g.,
SiO.sub.2.
[0016] An opening portion or via hole 5a of the insulating film 5
is formed on the surface of the pad 7 to expose the pad 7
therefrom. This opening portion 5a is covered by a barrier metal 9,
which is electrically connected to the pad 7. A bump 3 is attached
on the barrier metal 9. The barrier metal 9 consists of, e.g.,
Pd/Ni/Ti, TiW, Ti/Ti/W, or the like.
[0017] As described above, the input/output terminals of the
conventional semiconductor device with the TAB or flip-chip
structure are formed on the peripheral region along the outer edge
of the semiconductor substrate.
[0018] Defect discrimination of an integrated circuit in the chip
or wafer state (to be referred to as die testing hereinafter) is
done by electrical tests by bringing probes 6 projecting from a
probe card 12 into contact with the bumps 3 on the input/output
terminals 10, as shown in FIG. 4.
[0019] However, in recent years, semiconductor devices having the
same functions as those of conventional ones can be realized in
smaller sizes along with advance of the micropatterning techniques
of elements, while it has become harder to decrease the pitch of
input/output terminals due to limitations traced to the
interconnection techniques.
[0020] As a consequence, the number of input/output terminals
formed on the outer peripheral portion of the semiconductor
substrate is insufficient, and a structure in which a plurality of
input/output terminals are arranged on the entire major surface of
the semiconductor substrate 1 is proposed, as shown in FIG. 5. The
input/output terminals of a chip are arranged on the inner region
where the integrated circuit is formed, and the peripheral region
of the major surface of the semiconductor substrate 1.
[0021] However, the chip with such structure suffers the following
problem.
[0022] That is, die testing is conducted using the probes
projecting from the conventional probe card, but the probes cannot
be simultaneously in contact with all the plurality of input/output
terminals on the entire major surface.
[0023] In order to solve this problem, a probe card that can set a
plurality of probes on the entire major surface of the
semiconductor substrate is required. When a probe card with such
structure is used, it is very hard to attain alignment between a
plurality of bumps on the input/output terminals of the
semiconductor substrate and the plurality of probes, thus posing
another problem.
BRIEF SUMMARY OF THE INVENTION
[0024] The present invention has been made in consideration of the
above situation, and has as its object to provide a semiconductor
device which comprises die testing terminals and input/output
terminals with a structure that allow easy die testing even by a
conventional probe card using probes, and a method of manufacturing
the same.
[0025] In order to achieve the above object, a semiconductor device
according to the present invention comprises:
[0026] a semiconductor substrate;
[0027] an input/output terminal portion formed on the semiconductor
substrate, the input/output terminal portion having a plurality of
input/output terminals formed on an inner region on the
semiconductor substrate, and a plurality of die testing terminals
formed on a peripheral region on the semiconductor substrate;
and
[0028] a metal wiring layer for connecting the input/output
terminals and the die testing terminals.
[0029] Also, a method of manufacturing a semiconductor device
according to the present invention, comprises the steps of:
[0030] forming a multilayered wiring structure on a semiconductor
substrate;
[0031] forming a plurality of pads by patterning an uppermost metal
wiring layer of the multilayered wiring structure by lithography
and etching;
[0032] coating the uppermost metal wiring layer with a protection
insulating film while leaving opening portions from which surfaces
of the pads are exposed;
[0033] forming a conductive anti-etching protection film on the
exposed pads by lithography and etching;
[0034] forming a barrier metal formation metal film on the
protection insulating film including the anti-etching protection
film;
[0035] forming bumps on the pads on an inner region on the
semiconductor substrate via the anti-etching protection film and
the barrier metal formation metal film;
[0036] forming input/output terminals on the inner region on the
semiconductor substrate by forming barrier metals between the bumps
and the anti-etching protection film by patterning the barrier
metal formation metal film; and
[0037] forming die testing terminals by removing the barrier metal
formation metal film after the step of forming the barrier metal
formation metal film on the pads on an external region on the
semiconductor substrate and the anti-etching protection film.
[0038] Furthermore, a method of manufacturing a semiconductor
device according to the present invention, comprises the steps
of:
[0039] forming a multilayered wiring structure on a semiconductor
substrate;
[0040] forming a conductive anti-etching protection film on an
uppermost metal layer of the multilayered wiring structure;
[0041] forming a plurality of pads coated with the anti-etching
protection film by simultaneously patterning the metal wiring layer
and the anti-etching protection film by lithography and
etching;
[0042] coating the uppermost metal wiring layer with a protection
insulating film while leaving opening portions from which the
anti-etching protection film portions on the pads are exposed;
[0043] forming a barrier metal formation metal film on the
protection insulating film including the anti-etching protection
film;
[0044] forming bumps on the pads on an inner region on the
semiconductor substrate via the anti-etching protection film and
the barrier metal formation metal film;
[0045] forming input/output terminals on the inner region on the
semiconductor substrate by forming barrier metals between the bumps
and the anti-etching protection film by patterning the barrier
metal formation metal film; and
[0046] forming die testing terminals by removing the barrier metal
formation metal film after the step of forming the barrier metal
formation metal film on the pads on an external region on the
semiconductor substrate and the anti-etching protection film.
[0047] With this arrangement, according to the semiconductor device
and its manufacturing method of the present invention, easy die
testing can be attained even using a conventional probe card.
[0048] On the semiconductor substrate, both the die testing
terminals having no bumps and the connection input/output terminals
formed with bumps are present. Since the input/output terminal
portion is made up of wiring lines consisting of, e.g., aluminum,
and bumps formed thereon, the barrier metal for preventing metals
from diffusing is interposed between the bump and the aluminum
wiring line.
[0049] The anti-etching protection film protects aluminum wiring
lines of the die testing terminal portion from dissolving upon
removal of the barrier metal by etching. Also, the anti-etching
protection film protects metal wiring lines from mechanical damage
upon die testing.
[0050] The above-mentioned problem upon alignment between the
plurality of bumps on the input/output terminals of the
semiconductor substrate and the plurality of probes can be
solved.
[0051] Additional object and advantages of the invention will be
set forth in the description which follows, and in part will be
obvious from the description, or may be learned by practice of the
invention. The object and advantages of the invention may be
realized and obtained by means of the instrumentalities and
combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0052] The accompanying drawings, which are incorporated in and
constitute a part of the specification, illustrate presently
preferred embodiments of the invention, and together with the
general description given above and the detailed description of the
preferred embodiments given below, serve to explain the principles
of the invention.
[0053] FIG. 1 is a sectional view showing the structure of a
conventional semiconductor device mounted on a circuit board;
[0054] FIG. 2 is a plan view of the conventional semiconductor
device mounted on the circuit board;
[0055] FIG. 3 is a sectional view of the input/output terminals of
the conventional semiconductor device;
[0056] FIG. 4 is a sectional view showing the manner die testing is
conducted for the input/output terminals of the conventional
semiconductor device;
[0057] FIG. 5 is a plan view of a semiconductor substrate with a
plurality of input/output terminals of a conventional semiconductor
device;
[0058] FIG. 6 is a plan view of a semiconductor device according to
the first embodiment of the present invention;
[0059] FIG. 7 is a sectional view showing the structure of die
testing terminals and input/output terminals of the input/output
terminal portion of the semiconductor device shown in FIG. 6;
[0060] FIG. 8 is a sectional view showing one manufacturing process
of the semiconductor device shown in FIG. 6;
[0061] FIG. 9 is a sectional view showing one manufacturing process
of the semiconductor device that follows FIG. 8;
[0062] FIG. 10 is a sectional view showing one manufacturing
process of the semiconductor device that follows FIG. 9;
[0063] FIG. 11 is a sectional view showing one manufacturing
process of the semiconductor device that follows FIG. 10;
[0064] FIG. 12 is a sectional view showing one manufacturing
process of a semiconductor device according to the second
embodiment of the present invention;
[0065] FIG. 13 is a sectional view showing one manufacturing
process of the semiconductor device that follows FIG. 12;
[0066] FIG. 14 is a sectional view showing one manufacturing
process of the semiconductor device that follows FIG. 13;
[0067] FIG. 15 is a sectional view showing one manufacturing
process of the semiconductor device that follows FIG. 14;
[0068] FIG. 16 is a sectional view showing the structure of die
testing terminals and input/output terminals of the input/output
terminal portion of a semiconductor device according to still
another embodiment of the present invention having a multilayered
wiring structure;
[0069] FIG. 17 is a plan view of a semiconductor device according
to the third embodiment of the present invention; and
[0070] FIG. 18 is a plan view of a semiconductor device according
to the fourth embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0071] FIG. 6 is a plan view of a semiconductor device according to
the first embodiment of the present invention, and FIG. 7 shows the
sectional structure of die testing terminals 101 and input/output
terminals 102 of the semiconductor device shown in FIG. 6.
[0072] The major surface of a semiconductor substrate 1 is divided
into an inner region 1a which includes an integrated circuit, and
is formed with the input/output terminals 102, and a peripheral
region 1b formed with input/output circuits 11 and the die testing
terminals 101.
[0073] The input/output circuits 11 are arranged between the die
testing terminals 101 and the input/output terminals 102.
[0074] The die testing terminals 101 and the input/output terminals
102 consist of a plurality of metal wiring lines, and are
electrically connected to each other via a connection wiring layer
below these metal wiring lines.
[0075] Bumps 3 have a thickness of 100 .mu.m, and are made up of
low-melting point solder containing lead, tin, and the like.
[0076] FIG. 7 is a sectional view of the semiconductor substrate
showing the internal structure of the input/output terminals 102.
The major surface of, e.g., an n-type silicon semiconductor
substrate 1 is coated with an insulating film 14 such as a thermal
oxide film.
[0077] For example, a second aluminum wiring layer 15 is formed on
the insulating film 14. The aluminum wiring layer 15 is
electrically connected to, e.g., a p-type impurity doped region 13
formed in an element region of the surface region of the
semiconductor substrate 1 via an opening portion or window formed
in the insulating film 14.
[0078] The second aluminum wiring layer 15 is coated with an
insulating interlayer 4 of, e.g., CVD SiO.sub.2. A third aluminum
wiring layer that serves as pads 7 is formed on the insulating
interlayer 4. A conductive anti-etching protection film 16 is
formed on the entire surface of the third aluminum wiring layer.
The pads 7 of both the die testing terminals 101 and input/output
terminals 102 are electrically connected to the second aluminum
wiring layer 15 via opening portions 4a and 4b formed in the
insulating interlayer 4.
[0079] Accordingly, the die testing terminals 101 and the
input/output terminals 102 are electrically connected to each
other. The pads 7 made up of the third aluminum wiring layer are
coated with an SiO.sub.2 protection insulating film 5 via the
anti-etching protection film 16.
[0080] Opening portions 5a and 5b are formed in the protection
insulating film 5 in correspondence with the die testing terminals
101 and input/output terminals 102. In each die testing terminal
101, the anti-etching protection film 16 is exposed. In each
input/output terminal 102, a barrier metal 9 is formed on the
anti-etching protection film 16, and a bump 3 is formed on the
barrier metal 9.
[0081] As described above, no bump is attached to the die testing
terminal 101, and a bump is attached to the input/output terminal
102.
[0082] In this manner, the die testing terminals 101 having no
bumps for tests, and the input/output terminals 102 formed with
bumps for connection are present on the semiconductor substrate,
and they constitute a single input/output terminal portion.
[0083] Since each input/output terminal 102 is made up of a wiring
line of, e.g., aluminum, and the bump 3 formed thereon, the barrier
metal 9 for preventing metals from diffusing is interposed between
the bump and the aluminum wiring line.
[0084] On the other hand, each die testing terminal 101 consists of
an aluminum wiring line alone, and the barrier metal 9 formed on
the entire major surface of the semiconductor substrate must be
removed by a barrier metal etching solution. Therefore, the
anti-etching protection film 16 protects the aluminum wiring lines
of the die testing terminals 101 from dissolving upon removal of
the barrier metal by etching.
[0085] Also, the anti-etching protection film 16 protects the
aluminum wiring lines from mechanical damage upon die testing.
[0086] Since the die testing terminals 101 are arranged on the
peripheral region of the semiconductor substrate 1, a conventional
probe card can be effectively used upon die testing.
[0087] An embodiment of a method of manufacturing a semiconductor
device according to the present invention will be explained below
with reference to FIGS. 8 to 12.
[0088] FIG. 8 does not illustrate metal wiring lines (second
aluminum wiring layer) for electrically connecting the die testing
terminals 101 and the input/output terminals 102 for the sake of
simplicity.
[0089] An aluminum metal film having a thickness of about 500 nm
formed on an insulating film 4 of, e.g., SiO.sub.2 that covers a
semiconductor substrate 1 is patterned to form, e.g., a third
aluminum wiring layer.
[0090] Predetermined portions of this aluminum wiring layer are
used as pads 7 having a nearly square shape.
[0091] The insulating film 4 and the third aluminum wiring layer
serving as the pads 7 are coated with a protection insulating film
5 of, e.g., SiO.sub.2. The protection insulating film 5 is
patterned to form opening portions 5a from which the pads 7 are
exposed.
[0092] Subsequently, as shown in FIG. 9, an anti-etching protection
film 16 is formed on the exposed pads 17. The anti-etching
protection film 16 consists of, e.g., titanium nitride (TiN), and
has a thickness of about 50 nm.
[0093] The thickness of the anti-etching protection film 16 must be
larger than 30 nm, and is effective within the range from about 30
nm to 50 nm in terms of mechanical strength. The anti-etching
protection film may properly use other nitrides such as TiSiN and
the like in addition to TiN.
[0094] As shown in FIG. 10, a barrier metal formation metal film 9
is formed on the insulating film 5 including the anti-etching
protection film 16. As the input/output terminals 102 formed on the
inner region of the semiconductor substrate 1, bumps 3 are formed
on the pads 7 via the anti-etching protection film 16 and the
barrier metal formation metal film 9.
[0095] Subsequently, as shown in FIG. 11, the barrier metal
formation metal film is patterned to form a barrier metal 9 between
the bump 3 and the anti-etching protection film 16 of each
input/output terminal 102. On the other hand, the barrier metal
formation metal film on the die testing terminals 101 is removed.
In this manner, the die testing terminals 101 having no bumps are
formed on a peripheral region 1b of the semiconductor substrate 1,
and the input/output terminals 102 with the bumps 3 are formed on
an inner region 1a of the substrate 1.
[0096] The barrier metal formation metal film consists of, e.g.,
Ti/TiW; the thickness of Ti is 100 nm, and the thickness of TiW,
500 nm. A barrier metal etching solution (etchant) used for
patterning this metal film includes, e.g., a mixed acid of
HCl--HNO.sub.3--CH.sub.3COOH, diluted HF, and the like. As the
barrier metal, Pd/Ni/Ti, TiW, and the like may be used in addition
to the above-mentioned material. The anti-etching protection film
made up of a metal nitride film such as TiN, TiSiN, or the like has
a high resistance against such barrier metal etching solutions. If
the barrier metal consists of Pd/Ni/Ti, it is etched by a mixed
acid of HCl--HNO.sub.3--CH.sub.3COOH, Ti by diluted HF, and TiW by
diluted HF.
[0097] Since each Die testing terminal 101 is made up of an
aluminum wiring layer alone that serves as the pad 7 and is coated
with the anti-etching protection film 16, and has no bump, the
barrier metal formation metal film formed on the entire major
surface of the semiconductor substrate is removed by the barrier
metal etching solution. In this case, the anti-etching protection
film 16 protects the aluminum wiring layer of the die testing
terminals 101 from dissolving upon removal of the barrier metal 9
by etching.
[0098] A method of manufacturing a semiconductor device according
to the second embodiment of the present invention will be described
below with reference to FIGS. 12 to 15.
[0099] FIG. 12 does not illustrate metal wiring lines (second
aluminum wiring layer) for electrically connecting the die testing
terminals 101 and the input/output terminals 102 for the sake of
simplicity.
[0100] An aluminum metal film having a thickness of about 800 nm
and a TiN film formed on an insulating film 4 of, e.g., SiO.sub.2
that covers a semiconductor substrate 1 are patterned to form,
e.g., a third aluminum wiring layer coated with an anti-etching
protection film 16 having a thickness of about 100 nm.
[0101] Predetermined portions of this aluminum wiring layer are
used as pads 7 each having a nearly square shape.
[0102] Subsequently, as shown in FIG. 13, the insulating film 4 and
the third aluminum wiring layer thereon are coated with a
protection insulating film 5 of, e.g., SiO.sub.2. The insulating
film 5 is patterned to form opening portions 5a from which the
anti-etching protection film portions 16 on the pads 7 are
exposed.
[0103] As shown in FIG. 14, a barrier metal formation metal film
serving as a barrier metal 9 is formed on the anti-etching
protection film 16 and the insulating film 5. On the pad 7 of each
input/output terminal 102 formed on the inner region 1a of the
semiconductor substrate 1, a bump 3 is formed via the anti-etching
protection film 16 and the barrier metal formation metal film.
[0104] The barrier metal formation metal film is patterned to form
a barrier metal 9 between the bump 3 of each input/output terminal
102 and the anti-etching protection film 16, and the barrier metal
formation metal film on the die testing terminals 101 is
removed.
[0105] In this manner, the die testing terminals 101 having no
bumps are formed on a peripheral region 1b of the semiconductor
substrate 1, and the input/output terminals 102 with the bumps 3
are formed on an inner region 1a of the substrate 1.
[0106] The barrier metal formation metal film consists of, e.g.,
Ti/TiW; the thickness of Ti is 100 nm and the thickness of TiW, 500
nm. As a barrier metal etching solution (etchant) used for
patterning this metal film, diluted HF is used.
[0107] Since each Die testing terminal 101 is made up of an
aluminum wiring layer alone which is coated with the anti-etching
protection film 16, and has no bump, the barrier metal formation
metal film formed on the entire major surface of the semiconductor
substrate must be removed by the barrier metal etching
solution.
[0108] The anti-etching protection film 16 protects the aluminum
wiring layer of the die testing terminals 101 from dissolving upon
removal of the barrier metal 9 by etching.
[0109] The above-mentioned arrangement of the semiconductor device
according to the first embodiment of the present invention shown in
FIG. 7 uses the first aluminum wiring layer 15 on the substrate 1
as a first metal wiring layer, and the third aluminum wiring layer
serving as the pads 7 as a second metal wiring layer. However, the
present invention is not limited to this. For example, in another
multilevel interconnect architecture, as shown in FIG. 16, an
aluminum wiring layer 21 to be connected to a p-type impurity doped
region 13 formed in an element region of the surface region of the
substrate 1, may be additionally formed and may be used as a third
metal wiring layer.
[0110] The third embodiment of the present invention will be
described below with reference to FIG. 17.
[0111] FIG. 17 is a plan view showing the arrangement in which a
plurality of input/output terminals 102 are arranged on the major
surface of a semiconductor substrate 1 formed with a semiconductor
device.
[0112] Die testing terminals 101 and input/output circuits 11 are
formed on the semiconductor substrate 1. The major surface of the
semiconductor substrate 1 is divided into an inner region 1a formed
with an integrated circuit, and a peripheral region 1b formed with
the input/output circuits 11.
[0113] The input/output circuits 11 are arranged between the die
testing terminals 101 and input/output terminals 102. An
input/output terminal portion includes the die testing terminals
101 for testing, which are formed on the peripheral region 1b and
have no bumps, and the input/output terminals 102 for connection,
which are formed on the inner region 1a and have bumps. The die
testing terminals 101 and the input/output terminals 102 are
electrically connected to each other by a metal wiring layer 103
below the metal wiring layers that make up these terminals.
[0114] The semiconductor substrate 1 has a substantially square
shape. Also, the shape of each input/output terminal 102 is
square.
[0115] In the first embodiment shown in FIG. 6, the input/output
terminals 102 are arranged so that their arbitrary sides extend
parallel to the sides of the semiconductor substrate 1. However, in
the embodiment shown in FIG. 17, the input/output terminals 102 are
arranged so that a central line parallel to two opposing sides of
each input/output terminal 102 extends parallel to one diagonal
line of the semiconductor substrate 1.
[0116] When the input/output terminals 102 are arranged in this
manner, wiring of a connection means that connects the die testing
terminals 101 and the input/output terminals 102 can be easily
attained.
[0117] The fourth embodiment of the present invention will be
explained below with reference to FIG. 18.
[0118] FIG. 18 is a plan view showing the structure of input/output
terminals on the major surface of a semiconductor substrate formed
with a semiconductor device.
[0119] The major surface of a semiconductor substrate 1 is divided
into an inner region 1a which is formed with an integrated circuit
and a plurality of input/output terminals 102 are arranged, and a
peripheral region 1b which is formed with input/output circuits 11
and die testing terminals 101.
[0120] The input/output circuits 11 are arranged between the die
testing terminals 101 and the input/output terminals 102.
[0121] An input/output terminal portion includes the die testing
terminals 101 for testing, which are formed on the peripheral
region 1b and have no bumps, and the input/output terminals 102 for
connection, which are formed on the inner region 1a and have
bumps.
[0122] The die testing terminals 101 and the input/output terminals
102 are electrically connected to each other by a metal wiring
layer 103 below the metal wiring layers that make up these
terminals.
[0123] The semiconductor substrate 1 has a substantially square
shape. Also, the shape of each input/output terminal 102 is square.
In this embodiment, the input/output terminals 102 are arranged so
that a central line parallel to two opposing sides of each
input/output terminal 102 extends parallel to one diagonal line of
the semiconductor substrate 1. With this arrangement, wiring of a
connection means that connects the die testing terminals 101 and
the input/output terminals 102 can be easily attained.
[0124] This embodiment exemplifies a case wherein some of the die
testing terminals 101 on the peripheral region 1b to be connected
in correspondence with the connection input/output terminals 102
which are arranged on the inner region 1a and are formed with bumps
are omitted.
[0125] This semiconductor substrate 1 incorporates a scan circuit,
and specific die testing terminals 101 alone need only be subjected
to die testing using a shift register. For this reason, probes need
not be brought into contact with all the die testing terminals.
[0126] With the above-mentioned arrangement, die testing can be
easily performed even using a conventional probe card.
[0127] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalent.
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