U.S. patent application number 08/954426 was filed with the patent office on 2001-08-09 for chip scale package using large ductile solder balls.
Invention is credited to ELENIUS, PETER, HOLLACK, HARRY.
Application Number | 20010011764 08/954426 |
Document ID | / |
Family ID | 25495408 |
Filed Date | 2001-08-09 |
United States Patent
Application |
20010011764 |
Kind Code |
A1 |
ELENIUS, PETER ; et
al. |
August 9, 2001 |
CHIP SCALE PACKAGE USING LARGE DUCTILE SOLDER BALLS
Abstract
A chip scale package design for a flip chip integrated circuit
includes a redistribution metal layer upon the upper surface of a
semiconductor wafer for simultaneously forming solder bump pads as
well as the metal redistribution traces that electrically couple
such solder bump pads with the conductive bond pads of the
underlying integrated circuit. A patterned passivation layer is
applied over the redistribution metal layer. Relatively large,
ductile solder balls are placed on the solder bump pads for
mounting the chip scale package to a circuit board or other
substrate without the need for an underfill material. The back side
of the semiconductor wafer can be protected by a coating for
mechanical strength during handling. A method of forming such a
chip scale package at the wafer processing level is also
disclosed.
Inventors: |
ELENIUS, PETER; (SCOTTSDALE,
AZ) ; HOLLACK, HARRY; (SCOTTSDALE, AZ) |
Correspondence
Address: |
CAHILL SUTTON & THOMAS
ATTN MARVIN A GLAZER
155 PARK ONE
2141 EAST HIGHLAND AVENUE
PHOENIX
AZ
85016
|
Family ID: |
25495408 |
Appl. No.: |
08/954426 |
Filed: |
October 20, 1997 |
Current U.S.
Class: |
257/679 ;
257/678; 257/690; 257/E21.508 |
Current CPC
Class: |
H01L 2224/05155
20130101; H01L 2924/01006 20130101; H01L 2924/014 20130101; H01L
2924/01049 20130101; H01L 2924/351 20130101; G06F 1/1601 20130101;
H01L 2924/0001 20130101; H01L 2224/02381 20130101; H01L 23/3114
20130101; H01L 2924/01082 20130101; H01L 2224/10 20130101; H01L
2924/01029 20130101; H01L 2924/01013 20130101; H01L 2924/01322
20130101; H01L 2224/0235 20130101; H01L 24/05 20130101; H01L
2924/14 20130101; H01L 2224/0231 20130101; G06F 2200/1612 20130101;
H01L 2224/0401 20130101; H01L 2924/01033 20130101; H01L 24/13
20130101; H01L 2224/13017 20130101; H01L 2224/131 20130101; H01L
2224/13099 20130101; H01L 2224/02377 20130101; H01L 2224/05572
20130101; H01L 2924/01057 20130101; H01L 2924/01023 20130101; H01L
2924/01051 20130101; H01L 2224/05647 20130101; H01L 2224/13024
20130101; H01L 2924/01078 20130101; H01L 2924/01022 20130101; H01L
24/11 20130101; H01L 2224/05166 20130101; H01L 2224/06131 20130101;
H01L 2224/05548 20130101; H01L 2224/05124 20130101; H01L 24/12
20130101; H01L 2924/01005 20130101; H01L 24/02 20130101; H01L
2224/13007 20130101; H01L 2224/13022 20130101; H01L 2924/351
20130101; H01L 2924/00 20130101; H01L 2224/05647 20130101; H01L
2924/00014 20130101; H01L 2224/05124 20130101; H01L 2924/00014
20130101; H01L 2224/05155 20130101; H01L 2924/00014 20130101; H01L
2224/05166 20130101; H01L 2924/00014 20130101; H01L 2224/05155
20130101; H01L 2924/01023 20130101; H01L 2924/013 20130101; H01L
2924/0001 20130101; H01L 2224/02 20130101; H01L 2224/131 20130101;
H01L 2924/014 20130101 |
Class at
Publication: |
257/679 ;
257/678; 257/690 |
International
Class: |
H01L 023/02; H01L
023/48; H01L 023/52 |
Claims
We claim:
1. A chip scale package comprising in combination: a. an integrated
circuit formed upon a semiconductor die, said semiconductor die
having a front surface and an opposing rear surface, said
semiconductor die including a plurality of conductive bond pads
formed upon the front surface thereof for making electrical
interconnections to said integrated circuit; b. a patterned metal
layer formed over the front surface of said semiconductor die, said
patterned metal layer providing a plurality of solder bump pads
upon the front surface of said semiconductor die, and said
patterned metal layer electrically coupling said conductive bond
pads to said plurality of solder bump pads; c. a plurality of
ductile solder balls, each of said ductile solder balls being
secured to a corresponding one of said solder bump pads, each of
said ductile solder balls having a generally spherical shape and
measuring at least 9 mils (0.009 inch) in diameter.
2. The chip scale package recited by claim 1 wherein each of said
plurality of solder balls consists of at least 80 percent lead (Pb)
by weight.
3. The chip scale package recited by claim 1 wherein each of said
plurality of solder balls consists of an alloy of Indium (In).
4. The chip scale package recited by claim 1 wherein each of said
plurality of solder balls consists of eutectic tin/lead (63
Sb/Pb).
5. The chip scale package recited by claim 1 wherein said
integrated circuit has a center and an outer perimeter, said
integrated circuit having at least one peripheral conductive bond
pad formed proximate the outer perimeter of said integrated
circuit, and wherein at least one solder bump pad of said
integrated circuit is disposed upon the front surface of said
semiconductor die closer to the center of said integrated circuit
than the corresponding peripheral conductive bond pad to which such
solder bump pad is electrically coupled.
6. The chip scale package recited by claim 1 including a
passivation layer extending over the front surface of said
semiconductor die and above said patterned metal layer, said
passivation layer having openings formed therein above said solder
bump pads.
7. The chip scale package recited by claim 6 wherein said
passivation layer is a polymer layer.
8. The chip scale package recited by claim 6 wherein said
passivation layer is Benzocyclobutene.
9. The chip scale package recited by claim 1 wherein said patterned
metal layer provides a plurality of redistribution traces for
electrically coupling the plurality of solder bump pads to said
plurality of conductive bond pads, and wherein said patterned metal
layer consists of a single metal layer that provides both said
plurality of solder bump pads as well as said plurality of
redistribution traces.
10. The chip scale package recited by claim 1 including a
protective coating formed over the rear surface of said
semiconductor die.
11. A solder-bumped semiconductor wafer construction comprising: a.
a semiconductor wafer containing a plurality of like integrated
circuits, said semiconductor wafer having a front surface and an
opposing rear surface, each of said integrated circuits including a
plurality of conductive bond pads formed upon the front surface of
said semiconductor wafer for making electrical interconnections to
each such integrated circuit, each of such integrated circuits
having an outer perimeter, and each of said integrated circuits
having its plurality of conductive bond pads being formed proximate
the outer perimeter of each such integrated circuit; b. each of
said integrated circuits including a patterned metal layer formed
over the front surface of said semiconductor wafer, each of said
patterned metal layers providing a plurality of solder bump pads
upon the front surface of each such integrated circuit, and each
such patterned metal layer electrically coupling said conductive
bond pads of each such integrated circuit to said plurality of
solder bump pads of each such integrated circuit; c. a passivation
layer extending over the front surface of said semiconductor wafer
and above each of said patterned metal layers, said passivation
layer having openings formed therein above each of said solder bump
pads; and d. a plurality of ductile solder balls, each of said
ductile solder balls being secured to a corresponding one of said
solder bump pads on each of said plurality of integrated circuits,
each of said ductile solder balls having a generally spherical
shape and measuring at least 9 mils (0.009 inch) in diameter.
12. The solder-bumped semiconductor wafer construction recited by
claim 11 wherein each of said plurality of solder balls consists of
at least 80 percent lead (Pb) by weight.
13. The solder-bumped semiconductor wafer construction recited by
claim 11 wherein each of said plurality of solder balls consists of
an alloy of Indium (In).
14. The solder-bumped semiconductor wafer construction recited by
claim 11 wherein each of said plurality of solder balls consists of
eutectic tin/lead (63 Sb/Pb).
15. The solder-bumped semiconductor wafer construction recited by
claim 11 wherein each of said integrated circuits has a center, and
wherein the plurality of solder bump pads of each such integrated
circuit is disposed upon the front surface of said semiconductor
wafer closer to the center of each such integrated circuit than the
corresponding conductive bond pad to which each such solder bump
pad is electrically coupled.
16. The solder-bumped semiconductor wafer construction recited by
claim 11 wherein said passivation layer is a polymer layer.
17. The solder-bumped semiconductor wafer construction recited by
claim 11 wherein said passivation layer is Benzocyclobutene.
18. The solder-bumped semiconductor wafer construction recited by
claim 11 wherein each of said patterned metal layers provides a
plurality of redistribution traces for electrically coupling the
plurality of solder bump pads of each integrated circuit to the
corresponding plurality of conductive bond pads of each integrated
circuit, and wherein each such patterned metal layer consists of a
single metal layer that provides both said plurality of solder bump
pads as well as said plurality of redistribution traces.
19. The solder-bumped semiconductor wafer construction recited by
claim 11 including a protective coating formed over the rear
surface of said semiconductor die.
20. A method of forming a flip chip package for an integrated
circuit, including the steps of: a. providing a semiconductor wafer
containing a plurality of like integrated circuits, the
semiconductor wafer having a front surface and an opposing rear
surface, each of said integrated circuits including a plurality of
conductive bond pads formed upon the front surface of the
semiconductor wafer for making electrical interconnections to each
such integrated circuit; b. applying a layer of metal over the
front surface of the semiconductor wafer; c. selectively removing
portions of the applied metal layer over each of said integrated
circuits to provide a patterned metal layer over each integrated
circuit, each of such patterned metal layers providing a plurality
of solder bump pads upon the front surface of each such integrated
circuit, and each such patterned metal layer electrically coupling
the conductive bond pads of each such integrated circuit to the
solder bump pads of each such integrated circuit; d. applying a
passivation layer over the front surface of the semiconductor wafer
and above each of the patterned metal layers; e. forming openings
in the applied passivation layer above each of the solder bump
pads; f. applying a ductile solder ball to each solder bump pad,
each of said ductile solder balls having a generally spherical
shape and measuring at least 9 mils (0.009 inch) in diameter; and
g. dicing the semiconductor wafer to provide the plurality of
integrated circuits in chip scale packaged form.
21. The method recited by claim 20 wherein the ductile solder balls
applied in step f) each consist of at least 80 percent lead (Pb) by
weight.
22. The method recited by claim 20 wherein the ductile solder balls
applied in step f) each consist of an alloy of Indium (In).
23. The method recited by claim 20 wherein the ductile solder balls
applied in step f) each consist of eutectic tin/lead (63
Sb/Pb).
24. The method recited by claim 20 wherein each of such integrated
circuits has a center and an outer perimeter, and each of such
integrated circuits has at least one peripheral conductive bond pad
formed proximate the outer perimeter of each such integrated
circuit, and wherein step c) includes the step of disposing at
least one solder bump pad of each such integrated circuit upon the
front surface of the semiconductor wafer closer to the center of
each such integrated circuit than the corresponding peripheral
conductive bond pad to which such solder bump pad is electrically
coupled.
25. The method recited by claim 20 wherein the passivation layer
applied in step d) is a polymer layer.
26. The method recited by claim 20 wherein the passivation layer
applied in step d) is Benzocyclobutene.
27. The method recited by claim 20 wherein the step of selectively
removing portions of the applied metal layer over each of said
integrated circuits includes the step of providing a plurality of
redistribution traces for electrically coupling the plurality of
solder bump pads of each integrated circuit to the corresponding
plurality of conductive bond pads of each integrated circuit, and
wherein steps b) and c) form both the solder bump pads and the
redistribution traces as a single patterned metal layer.
28. The method recited by claim 20 wherein the ductile solder balls
have a characteristic reflow temperature at which they become
molten, and wherein said method further includes the steps of
applying solder flux to the solder bump pads prior to application
of the ductile solder balls, and thereafter heating the
semiconductor wafer to the reflow temperature of such solder balls
after application of the ductile solder balls to permanently secure
such ductile solder balls to the solder bump pads.
29. The method recited by claim 20 wherein the step of applying a
ductile solder ball to each solder bump pad includes the step of
mechanically placing a pre-formed solder ball on each such solder
bump pad.
30. The method recited by claim 20 further including the step of
applying a protective coating over the rear surface of the
semiconductor wafer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to flip chip
mounting of integrated circuits to circuit boards or other mounting
substrates via solder bumps, and more particularly, to a chip scale
package and related method for allowing integrated circuits to be
directly connected to an underlying circuit board or other
substrate.
[0003] 2. Description of the Related Art
[0004] Flip chips are conventionally understood by those skilled in
the art to designate unpackaged integrated circuit chips that have
contact pads bearing solder bumps for attachment to a patterned
substrate. Such flip chips are formed from integrated circuit die
that are scribed from a semiconductor wafer. During processing,
such semiconductor wafer has an upper active surface through which
impurities are introduced, by chemical diffusion and/or
implantation, to form individual transistors and other electronic
components. Metallization layers are also patterned upon the upper,
or active, surface of such semiconductor wafer to electrically
interconnect the electrodes of the various devices formed in such
semiconductor wafer. For flip chips, the upper active surface of
scribed integrated circuit die are inverted, or flipped, in order
to be solder connected to an underlying patterned substrate.
Heating of the solder bumps to their "reflow" temperature melts the
solder, and the "reflow" of the solder joins the flip chip
electrically and mechanically with the underlying patterned support
substrate. The use of solder bumps to interconnect such flip chips
to underlying support substrates is disclosed, for example, within
U.S. Pat. No. 5,261,593 to Casson, et al.; within U.S. Pat. No.
5,220,200 to Blanton; within U.S. Pat. No. 5,547,740 to Higdon, et
al.; and within U.S. Pat. No. 5,564,617 to Degani, et al.
[0005] Unpackaged integrated circuits are essentially bare
semiconductor die, and are subject to damage if mishandled during
assembly. Accordingly, many manufacturers of electronic equipment
are reluctant to directly attach unpackaged flip chips to circuit
boards, and many of such manufacturers desire devices that are
"packaged". Consequently, many integrated circuit suppliers have
elected to "package" integrated circuits in a so-called "chip scale
packages" to overcome customer concerns about handling bare die. A
"chip scale package" typically designates a package that is no more
than 20 percent larger than the integrated circuit die itself. Such
chip scale packages provide a minimal degree of mechanical
protection to the integrated circuit die and allow it to be handled
more easily; customers tend to derive a sense of security knowing
that they are not handling bare die. Such chip scale packages
typically join the active surface of the integrated circuit to a
somewhat larger substrate; electrical contacts provided on the
substrate are then used to interconnect the chip scale package to
the circuit board.
[0006] Often, the supporting substrate of a flip chip assembly and
the associated integrated circuit will have different coefficients
of thermal expansion. Such thermal stresses can fracture the solder
bumps used to join the flip chip integrated circuit to the
supporting substrate, causing the circuitry to fail. It is known to
those in the flip chip packaging field to utilize an underfill
material around the solder bumps, and between the integrated
circuit and the supporting substrate, to constrain thermal
expansion differences between the chip and the substrate. While the
use of such underfill material serves to improves the fatigue life
of the solder joints, the application of this underfill is often
perceived as an expensive process that is not consistent with
standard surface mount technology manufacturing processes.
[0007] Standard flip chip solder joints are typically very small
(i.e., 100 micron diameter with a joined height of 70-85 microns).
To be compatible with standard surface mount technology processes,
the typical solder joint is composed of a 63 Sn/Pb solder, i.e.,
the solder bump is composed of 63% tin and 37% lead. In one known
technology, 63 Sn/Pb solder is deposited onto a substrate's solder
contact pads, and high percentage Pb solder bumps are evaporated or
plated onto the flip chip bond pads of the integrated circuit;
however, the size of such solder bumps was typically less than 7
mils (0.007 inch). The small solder joint, and the fatigue
characteristics of these flip chip solder joints, mandate the use
of an underfill to minimize the strain on the solder bumps.
[0008] Many known chip scale package processes use solder bumps to
join the bonding pads of the integrated circuit to the supporting
substrate. These bonding pads are typically located at the outer
perimeter of the integrated circuit chip. Complex integrated
circuits often require in excess of one-hundred separate bonding
pads in order to make the necessary power, input, and output
connections between the integrated circuit and the outside world.
Consequently, such bonding pads are typically disposed close to
each other and place physical limitations upon the size and height
of solder bumps overlying such bonding pads. While U.S. Pat. No.
5,547,740 to Higdon, et al. discloses that some of the solder bump
contact pads can be redistributed internally, away from the outer
perimeter of the integrated circuit, the size of such solder bumps
is unchanged.
[0009] Moreover, most of the known techniques for forming chip
scale packaging of integrated circuits must be practiced at the
individual die level; i.e., the semiconductor wafer from which the
integrated circuits are taken must first be scribed and cut into
individual die before such chip scale packaging processes can be
performed. These die level packaging techniques do not obtain the
cost benefits of the wafer scale processing techniques. Moreover,
certain integrated circuit markets, such as memory chips, are
largely driven by form factor (i.e., the physical size of the
packaged integrated circuit) and the cost of packaging. Yet, many
of the known chip scale package techniques involve significant
added cost and increase the dimensions of the packaged integrated
circuit.
[0010] One of the known wafer level processing technologies used to
form chip scale packages is the Mitsubishi PMEB (Plastic Molded,
Extended Bump) technique; the PMEB package from Mitsubishi utilizes
a redistribution technology to move solder bump pads away from the
bond pads of the integrated circuit, and also performs initial
solder bumping at the wafer level; however, following these steps,
the Mitsubishi PMEB technique dices the components from the
semiconductor wafer, encapsulates them, and then places a eutectic
"extended bump" onto the surface of the package. The resulting chip
scale package construction is sensitive to moisture ingress and has
a relatively high cost at low lead counts. In addition, the
Mitsubishi PMEB package uses a 63 Sn/Pb extended solder bump (the
plastic encapsulant precludes a higher solder reflow temperature)
which limits the fatigue life of the extended solder bumps.
[0011] Another known wafer level technology used to form chip scale
packages is the Sandia Mini Ball Grid Array technique redistributes
the locations of the solder bump locations on the integrated
circuit, but requires multiple metal layers because a plating
process is used for solder deposition. The redistribution wiring is
provided by a first layer of deposited metal that is patterned and
passivated. A second layer of metal is then sputtered over the
wafer to form the solder bump pads, and standard electroplating
processes are used for forming standard-sized solder bumps.
[0012] Accordingly, it is an object of the present invention to
provide an improved chip scale package, and a method of forming
such an improved chip scale package, for flip chip integrated
circuits which is consistent with standard surface mount technology
manufacturing processes, and which avoids the need to add an
underfill material between the integrated circuit and a supporting
substrate in order to protect the solder bumps from fatigue induced
by thermal coefficient differentials.
[0013] It is another object of the present invention to provide an
improved chip scale package, and method for forming the same, which
can be carried out at the wafer processing level, as opposed to the
discrete integrated circuit die level.
[0014] Still another object of the present invention is to provide
an improved chip scale package for an integrated circuit, and
method for forming the same, which is relatively inexpensive to
implement, and which results in a small form factor, i.e., the
resulting chip scale package is not larger than the size of the
original integrated circuit.
[0015] A further object of the present invention is to provide a
wafer scale chip scale package which can be directly surface
mounted, yet which are better protected, and easier to handle, than
bare flip chip integrated circuit die.
[0016] A still further object of the present invention is to
provide a wafer scale chip scale package that can be directly
surface mounted to supporting substrates via solder bumping and
wherein the susceptibility of such solder bumps to fatigue is
reduced.
[0017] Yet another object of the present invention is to provide
such a wafer scale chip scale package which minimizes the number of
metallization layers applied over the integrated circuit die to
facilitate solder bumping, and which permits the formation of
solder bumps by processes other than plating.
[0018] These and other objects of the present invention will become
more apparent to those skilled in the art as the description of the
present invention proceeds.
SUMMARY OF THE INVENTION
[0019] Briefly described, and in accordance with a preferred
embodiment thereof, the present invention relates to a chip scale
package that includes an integrated circuit formed upon a
semiconductor die having a front surface and an opposing rear
surface. A group of conductive bond pads are formed upon the front
surface of the integrated circuit die proximate the outer periphery
thereof for making electrical interconnections to the devices
formed within the integrated circuit. A patterned metal layer is
formed over the front surface of the semiconductor die, defining a
number of solder bump pads that are electrically coupled to the
conductive bond pads of the integrated circuit die but laterally
displaced from the outer periphery of the integrated circuit die. A
passivation layer extends over the front surface of the
semiconductor die and above the patterned metal layer; openings
formed within such passivation layer expose the solder bump pads. A
protective coating can extend over the rear surface of the
semiconductor die for mechanical protection. Ductile solder balls,
each being generally spherical and measuring at least 9 mils (0.009
inch) in diameter, are formed upon each such solder pad for
allowing the resulting structure to be directly surface mounted to
a circuit board or other substrate.
[0020] In the preferred embodiment of the present invention, the
aforementioned ductile solder balls consist of at least 80 percent
lead (Pb) by weight. While such solder balls have a higher reflow
temperature, they are also less subject to mechanical fatigue.
Other ductile solder ball compositions may be used, including
alloys of Indium (In).
[0021] Preferably, each of the solder bump pads is disposed upon
the front surface of the semiconductor die closer to the center
thereof than the corresponding conductive bond pad to which each
such solder bump pad is electrically coupled. This arrangement
permits the solder balls to be of larger diameter without risking
that such solder balls will extend over the peripheral edge of the
semiconductor die, and without risking that such solder balls will
abut each other. The patterned metal layer provides a plurality of
redistribution traces for electrically coupling the solder bump
pads to their corresponding conductive bond pads; this patterned
metal layer ideally consists of a single layer of metal that
simultaneously provides both the solder bump pads as well as the
redistribution traces. The aforementioned passivation layer is
preferably a polymer, the compound Benzocyclobutene being
preferred.
[0022] Another aspect of the present invention relates to a
solder-bumped semiconductor wafer construction including a
semiconductor wafer containing a plurality of like integrated
circuits, each of the integrated circuits including a series of
conductive bond pads formed about the outer periphery thereof upon
the front surface of the semiconductor wafer for making electrical
interconnections to each such integrated circuit. A patterned metal
layer is formed over the front surface of the semiconductor wafer
above each such integrated circuit for providing a series of solder
bump pads and electrically coupling the conductive bond pads of
each such integrated circuit to its corresponding series of solder
bump pads. The front surface of the semiconductor wafer is
protected by a passivation layer that extends over the front
surface of the semiconductor wafer and above each of the patterned
metal layers; openings are formed in the passivation layer above
each of the solder bump pads. The rear surface of the semiconductor
wafer can be protected by a protective coating formed thereupon.
Ductile solder balls, each having a generally spherical shape and
measuring at least 9 mils (0.009 inch) in diameter, are secured to
each solder bump pad on each of the integrated circuits. The
resulting semiconductor wafer can then be scribed and diced to
provide a number of such integrated circuits in the form of chip
scale integrated circuit packages.
[0023] The present invention also relates to a method of forming a
chip scale package for a flip chip integrated circuit. According to
such method, a semiconductor wafer is provided containing a number
of like integrated circuits, each of such integrated circuits
including a series of conductive bond pads formed upon the front
surface of the semiconductor wafer and arranged about the periphery
of each such integrated circuit for making electrical
interconnections thereto. A protective coating can be applied over
the rear surface of the semiconductor wafer. A layer of metal is
applied over the front surface of the semiconductor wafer, and
portions of such metal layer are then selectively removed to leave
a patterned metal layer over each integrated circuit. Each of the
patterned metal layers provides a series of solder bump pads upon
the front surface of each such integrated circuit, each such solder
bump pad being electrically coupled by such patterned metal layer
to a corresponding one of the solder bump pads. A passivation layer
is then applied over the front surface of the semiconductor wafer
and above each of the patterned metal layers to seal the front
surface of each of the integrated circuits, while leaving openings
in the applied passivation layer above each of the solder bump
pads. Ductile solder balls are then applied to each solder bump
pad, each of the ductile solder balls having a generally spherical
shape and measuring at least 9 mils (0.009 inch) in diameter. The
resulting semiconductor wafer is then diced to provide a number of
integrated circuits in chip scale packaged form.
[0024] The passivation layer applied in the present method is
preferably a polymer layer; the product Benzocyclobutene has been
found to be particularly advantageous as such a polymer passivation
layer.
[0025] In practicing the method of the present invention, the
solder balls are caused to be highly ductile, preferably by
selecting a solder ball composition consisting of at least 80
percent lead (Pb) by weight. Alternatively, a solder ball
composition consisting of an alloy of Indium (In) may also be used.
In the preferred embodiment of the present method, a ductile solder
ball is provided above each solder bump pad by mechanically placing
a pre-formed solder ball on each such solder bump pad. Solder flux
is preferably applied to the solder bump pads prior to application
of the ductile solder balls; the semiconductor wafer is then heated
to the reflow temperature of the solder balls following application
of the ductile solder balls to permanently secure the solder balls
to the underlying solder bump pad.
[0026] In view of the relatively large size of such solder balls,
the present method contemplates the redistribution of the solder
pads away from the periphery of the integrated circuit to points
located closer to the center of each integrated circuit, as
compared with the original locations of the corresponding
conductive bond pads of the integrated circuit. This relocation of
the solder bump pads is accomplished by providing a series of
redistribution traces during the step of selectively removing
portions of the applied metal layer in order to electrically couple
each solder bump pad to its corresponding conductive bond pad. In
practicing this method, it is preferred that the same applied metal
layer is patterned to form both the solder bump pads as well as the
aforementioned redistribution traces.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIG. 1 is a top view of a chip scale packaged integrated
circuit constructed in accordance with a preferred embodiment of
the present invention.
[0028] FIG. 2 is a cross-sectional view of a portion of a
semiconductor wafer used to form the chip scale packaged integrated
circuit shown in FIG. 1.
[0029] FIG. 3 is a cross-sectional view of a ductile solder ball
following heating of the semiconductor wafer to permanently secure
the ductile solder ball to an underlying solder bond pad.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0030] FIGS. 1 and 2 illustrate a chip scale package, designated
generally by reference numeral 8, for a flip chip integrated
circuit constructed in accordance with the present invention.
Within FIG. 1, an integrated circuit 10 has been formed upon a
semiconductor die in a conventional manner, and incorporates an
interconnected network of transistors and other electrical
components (not shown). Referring to FIG. 2, integrated circuit 10
is formed upon the front surface 12 of a semiconductor wafer 14,
which also includes an opposing rear surface 16. Chemical
impurities are diffused, implanted, or otherwise introduced into
semiconductor wafer 14 through front surface 12 thereof during the
processing of integrated circuit 10 to form various transistors and
other electrical components within integrated circuit 10. Such
electrical components are interconnected with each other by one or
more metallization layers (not shown) formed upon front surface 12
of semiconductor wafer 14.
[0031] Integrated circuit 10 includes a series of input, output,
and power terminals which must be electrically connected to the
outside world in order to make practical use of integrated circuit
10. For this purpose, most integrated circuits are provided with a
series of conductive bond pads, such as those designated by
reference numerals 18 and 20 within FIGS. 1 and 2, formed upon the
front surface of semiconductor wafer 14 for making electrical
interconnections to integrated circuit 10. As indicated within FIG.
1, these conductive bond pads 18 and 20 are typically formed and
disposed proximate the outer perimeter 22 of the semiconductor die
containing integrated circuit 10. Integrated circuit 10 also
typically includes a wafer passivation layer 22 applied over the
front surface of semiconductor wafer 14, as shown in FIG. 2, in
order to protect the upper metal interconnect layer of integrated
circuit 10. As indicated in FIG. 2, openings are typically provided
in wafer passivation layer above conductive bond pads 18/20 to
allow access thereto. The structure and steps described thus far
are typical of common integrated circuits, whether such integrated
circuits are ultimately wire bonded to a package or solder
bumped.
[0032] As indicated above, the present invention uses ductile
solder balls to interconnect chip scale package 8 with external
circuitry. In preparation for solder bumping, a first passivation
layer 24 is optionally applied over the front surface of
semiconductor wafer 14 immediately above wafer passivation layer
22. This first passivation layer 24 is a dielectric and serves to
passivate and planarize the wafer surface, and may be omitted in
some instances, depending upon the characteristics of existing
wafer passivation layer 22. In the preferred embodiment of the
present invention, first passivation layer 24 is formed of
Benzocyclobutene commercially available from Dow Chemical Company
of Midland, Michigan under the commercial designation "Cyclotene".
However, other compositions may be used to form first passivation
layer 24, including polyimides, polyolefins and other organic and
inorganic passivations. First passivation layer 24 is preferably
applied over semiconductor wafer 14 by spin coating to form a layer
approximately 4-5 .mu.m thick. Conventional photolithography
techniques are used to form patterned openings within first
passivation layer 24 above each of the conductive bond pads 18/20
and at those locations at which solder bump pads will ultimately be
formed; alternatively, such openings can be limited to the areas
above each of the conductive bond pads 18/20, in which case the
solder bump pads will ultimately lie above first passivation layer
24.
[0033] As indicated above, chip scale package 8 utilizes ductile
solder balls that are of somewhat larger dimension than have been
used in the past. In order to accommodate such larger solder balls,
it is required to relocate, or redistribute, the solder bump pads
relative to their corresponding conductive bond pads. As shown in
FIGS. 1 and 2, solder bump pad 26, to which ductile solder ball 28
is attached, is laterally displaced from conductive bond pad 18. As
further indicated in FIGS. 1 and 2, solder bump pad 26 and
conductive bond pad 18 are electrically interconnected by
redistribution trace 30.
[0034] Redistribution trace 30 and solder bump pad 26 are provided
as a patterned metal layer formed over the wafer passivation layer
22 and over first passivation layer 24, above the front surface of
semiconductor wafer 14. This patterned metal layer is preferably
formed by first blanketing the front surface of semiconductor wafer
14 with a so-called Under Bump Metallurgy (or UBM) layer.
Preferably, this UBM layer is a triple-metal stack structure of
Aluminum (Al), Nickel Vanadium (NiV), and Copper (Cu);
alternatively, the UBM layer could be a triple-metal stack
structure of Titanium (Ti), Nickel Vanadium (NiV), and Copper (Cu)
or other suitable metal structure. The UBM layer can be applied
over semiconductor wafer 14 by known metal sputtering techniques.
Preferably, the thickness of such applied UBM layer is
approximately 2 microns. The UBM layer serves several purposes;
first, it adheres to the underlying surfaces. Secondly, it acts as
a solder diffusion barrier for preventing molten solder from
passing into the front surface of semiconductor wafer 14. The UBM
layer also serves as a "wettable" layer for solderability purposes;
finally, the UBM layer serves to minimize electrical contact
resistance between the ductile solder ball 28 and the conductive
bond pad 18. Following application of such UBM layer, it is etched
in accordance with known photolithographic techniques to provide
the desired patterned metal layer, thereby providing solder bump
pad 26, redistribution trace 30, as well as the electrical contact
32 to conductive bond pad 18.
[0035] Those skilled in the art will appreciate that UBM layer
described above accomplishes a redistribution of the typical
conductive bond pads to a new pattern, such as the array
redistribution pattern shown in FIG. 1. The redistribution process
described above for relocating the solder bump pads utilizes the
same metallurgy for both the redistribution traces (30) as well as
the UBM interface (26) to the solder ball 28. The redistributed
solder bump pads 26 can be located virtually anywhere on the
surface of the device. Typically, the solder bump pads (26) are
disposed at a point closer to the center of integrated circuit 10
than the corresponding conductive bond pads (18) to which each such
solder bump pad is electrically coupled.
[0036] After the UBM layer is applied and patterned in the manner
described above, a second passivation layer 32 is applied over such
patterned metal layer, as illustrated in FIG. 2. This second
passivation layer is also preferably formed of Benzocyclobutene as
described above, though polyimides, polyolefins and other organic
and inorganic passivations may also be used. Second passivation
layer 32 is preferably applied over semiconductor wafer 14 by spin
coating to form a layer approximately 4 microns thick. Conventional
photolithography techniques are used to form patterned openings
within second passivation layer 32 at the site of each of the
solder bump pads (26).
[0037] Once the second passivation layer 32 is patterned, a ductile
solder ball, like solder ball 28 in FIG. 2, is formed upon each of
the exposed solder pads 22. Each of such ductile solder balls has a
generally spherical shape and measures at least 9 mils (0.009
inch), or at least 229 microns, in diameter. Conventional solder
bumping forms solder bumps from 63 Sn/Pb solder or 95 Pb/Sn, but of
a size that is less than 0.007 inch in diameter due to process
limitations. In contrast, solder ball 28 is formed of a more
ductile composition. The preferred composition of solder ball 28 is
at least 80 percent lead (Pb) by weight, with the remainder
consisting of tin. Alternatively, solder ball 28 can be formed of
an alloy of Indium (In) or other Pb alloys having at least 80
percent Pb by weight for increased ductility. The larger diameter
and increased ductility of such solder balls makes such solder
balls more resistant to fatigue imposed by differing rates of
thermal expansion as between the chip scale package 8 and the
substrate to which it is ultimately mounted, thereby eliminating
the need for the addition of any underfill material. In practicing
the preferred embodiment of the present invention, solder ball 28
is pre-formed and is mechanically placed upon solder pad 26. Prior
to such mechanical placement, solder flux is applied over the
solder bump pads to enhance the joint ultimately formed between
solder ball 28 and solder bump pad 26. The mechanical placement of
the solder balls upon their respective solder bump pads is
accomplished by a mechanical mask through which the solder balls
are located. However, the ductile solder balls can be formed by a
variety of other methods, including plating, solder paste,
evaporation, ball bumping, and solder jetting. Once the solder
balls are formed upon the solder bump pads, semiconductor wafer
chip scale package 8 is heated to the reflow temperature of solder
ball 28, thereby forming a secure attachment of solder ball 28 to
solder bump pad 26.
[0038] Referring to FIG. 2, the back side, or rear surface, of
semiconductor wafer 14 is designated by reference numeral 16. In
practicing the preferred embodiment of the present invention, an
organic protective coating 34 is coated onto rear surface 16 of
semiconductor wafer 14. This protective coating 34 can be spun onto
the back side of semiconductor wafer 14 using known spin coat wafer
processing equipment, and thereafter cured. Organic protective
coating 34 is preferably an epoxy or other suitable organic
protective coating that provides mechanical protection to the back
side of the die during handling. Protective coating 34 is normally
diced through as part of the wafer dicing process; alternatively,
protective coating 34 can be photoimaged to provide a kerf to dice
through. In either case, the final dimensions of protective coating
34 are the same as the final dimensions of the die, thereby
providing a chip scale packaged device with a minimal form factor.
While protective coating 34 can be applied at different stages in
the formation of the chip scale package, protective coating 34 is
preferably applied before first passivation layer 24 is applied to
the front surface of semiconductor wafer 14.
[0039] FIG. 3 is a cross-sectional representation, obtained via an
electron scanning microscope, of the solder bump structure
following heating of ductile solder ball 28 to its reflow
temperature. While solder ball 28 flattens somewhat during reflow,
the height of ductile solder ball 28 is still 9.5 mils (0.0095)
inch or greater. This increased height and ductility, when compared
with standard solder bump processing, avoids the need for underfill
operations, yet resists cracking due to the stresses imposed by
differing rates of thermal expansion as between the chip scale
package and the substrate to which it is mounted.
[0040] As noted above, the present invention also relates to the
method of forming the above-described flip chip package for an
integrated circuit. In practicing such method, a semiconductor
wafer 14 is provided containing a plurality of like integrated
circuits (10). Each integrated circuit 10 includes a series of
conductive bond pads (18/20) formed upon the front surface 12, at
least some of which lie proximate the outer perimeter of the
semiconductor wafer, for making electrical interconnections
thereto. A protective coating 34 is applied over the rear surface
16 of the semiconductor wafer. A layer of metal (26/30/32) is
applied over the front surface 12 of the semiconductor wafer, and
portions of such metal layer are thereafter selectively removed to
provide a patterned metal layer providing a series of solder bump
pads (26) upon the front surface 12 of each such integrated circuit
(10). The patterned metal layer (30) electrically couples the
conductive bond pads (18/20) of each integrated circuit (10) to
their associated solder bump pads (22). Typically, the majority of
the conductive bond pads (18/20) are disposed near the outer
periphery of the integrated circuit 10, and the step of patterning
the metal layer preferably includes the step of disposing the
plurality of solder bump pads (26) closer to the center of
integrated circuit 10 than the corresponding conductive bond pad
(18) to which each such solder bump pad is electrically coupled.
Thus, the step of selectively removing portions of the applied
metal layer preferably includes the step of forming a series of
redistribution traces (30) for electrically coupling each solder
bump pad (26) to the corresponding conductive bond pad (18).
Ideally, the solder bump pads (26) and the redistribution traces
(30) are formed as a single patterned metal layer.
[0041] A passivation layer 24 is then applied over the front
surface (12/22) of the semiconductor wafer 14 and above each of the
patterned metal layers (26/30/32). This passivation layer is a
polymer layer, preferably consisting of the polymer
Benzocyclobutene. Openings are then formed in the applied
passivation layer 24 above each of the solder bump pads 26.
[0042] A ductile solder ball 28 is formed upon each solder bump pad
26; each such ductile solder ball has a generally spherical shape
and measures approximately 0.009 inch in diameter or greater. In
the preferred embodiment of the process, the ductile solder balls
consist of at least 80 percent lead (Pb) by weight to provide the
desired degree of ductility. Alternatively, such ductile solder
balls may consist of an alloy of Indium (In). Preferably, such
ductile solder balls are formed upon each solder bump pad by
mechanical placement of a pre-formed solder ball on each such
solder bump pad. The ductile solder balls (28) have a
characteristic reflow temperature at which they become molten. The
preferred process includes the step of applying solder flux to the
solder bump pads (26) prior to application of the ductile solder
balls (28), and thereafter heating semiconductor wafer 14 to the
reflow temperature of such solder balls after application of the
ductile solder balls to permanently secure such ductile solder
balls to their respective solder bump pads.
[0043] All of the processing steps used to practice the present
invention are performed at the wafer level, i.e., before the
semiconductor wafer is diced to form individual integrated
circuits/chip scale packages. At this stage, semiconductor wafer 14
is then diced in accordance with conventional scribing/breaking
methods to provide a number of chip scale packaged integrated
circuits ready to be mounted to a circuit board or other patterned
substrate.
[0044] Those skilled in the art will now appreciate that an
improved chip scale package for a flip chip integrated circuit, and
method for providing such a chip scale package, has been described.
The flip chip scale package method described herein is a
wafer-level process that can be performed before individual
integrated circuits are scribed and cut from a semiconductor wafer,
thereby reducing cost. No bare die handling is required at any step
in the process, which is a significant advantage over the
above-described PMEB package from Mitsubishi. The large ductile
solder bumps greatly reduce the likelihood of fatigue induced by
differing coefficients of thermal expansion as between the flip
chip integrated circuit and the substrate to which it is soldered,
thereby eliminating the need for, and associated expense of,
including an underfill operation. The process of coating the
backside of the wafer makes the integrated circuit easier to handle
and provides additional mechanical protection. In contrast, the
Mini BGA process by Sandia does not provide any additional
packaging to the integrated circuit.
[0045] In addition, the ability to use the same patterned metal
layer to form both the solder bump pads as well as the
redistribution traces that relocate such solder bump pads minimizes
the number of processing steps and reduces the cost of manufacture.
In contrast, the aforementioned Mini BGA solder bump technology
from Sandia requires that a plating process be used to apply solder
bumps, and therefore requires the use of two metallization layers
to accomplish redistribution of the solder bump pad locations.
Moreover, the size of the solder bumps provided using the Mini BGA
technology is not as large as can be obtained by mechanically
placing solder balls on their respective solder pads.
[0046] While the present invention has been described with respect
to a preferred embodiment thereof, such description is for
illustrative purposes only, and is not to be construed as limiting
the scope of the invention. For example, while the preferred
embodiment of the present invention uses highly ductile solder
balls having a high lead content, it is possible to use solder
balls of conventional eutectic tin/lead (63 Sn/Pb); the larger
diameter of the solder balls made in accordance with the present
invention increases the resistance of such solder balls to fatigue
and may be sufficient to avoid the need for underfill even though
such solder balls are made of conventional eutectic tin/lead.
Various modifications and changes may be made to the described
embodiments by those skilled in the art without departing from the
true spirit and scope of the invention as defined by the appended
claims.
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